clk: imx: Finish converting clock-osc-24 back to osc_24
authorAdam Ford <aford173@gmail.com>
Wed, 16 Apr 2025 21:55:24 +0000 (16:55 -0500)
committerFabio Estevam <festevam@denx.de>
Fri, 25 Apr 2025 11:50:23 +0000 (08:50 -0300)
The UART clocks were added around the same time some other clock
updates were happening, so converting clock-osc-24 back to osc_24
was missed on the UART clocks for imx8mm and imx8mn, so update
them here.

Fixes: b4734c9c333b ("clk: imx: Convert clock-osc-* back to osc_*")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reported-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
drivers/clk/imx/clk-imx8mm.c
drivers/clk/imx/clk-imx8mn.c

index b81db51..7eb0518 100644 (file)
@@ -81,19 +81,19 @@ static const char * const imx8mm_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys
                                                "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
                                                "audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mm_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mm_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
                                          "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4",
                                          "audio_pll2_out", };
 
-static const char * const imx8mm_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mm_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
                                          "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3",
                                          "audio_pll2_out", };
 
-static const char * const imx8mm_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mm_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
                                          "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4",
                                          "audio_pll2_out", };
 
-static const char * const imx8mm_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mm_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
                                          "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3",
                                          "audio_pll2_out", };
 
index be5b793..2dfa860 100644 (file)
@@ -97,19 +97,19 @@ static const char * const imx8mn_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys
                                                "sys_pll3_out", "audio_pll1_out", "video_pll_out",
                                                "audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mn_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mn_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
                                                 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
                                                 "clk_ext4", "audio_pll2_out", };
 
-static const char * const imx8mn_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mn_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
                                                 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
                                                 "clk_ext3", "audio_pll2_out", };
 
-static const char * const imx8mn_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mn_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
                                                 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
                                                 "clk_ext4", "audio_pll2_out", };
 
-static const char * const imx8mn_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mn_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
                                                 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
                                                 "clk_ext3", "audio_pll2_out", };