#include <spl.h>
+char __data_start[0] __section(".__data_start");
char __data_save_start[0] __section(".__data_save_start");
char __data_save_end[0] __section(".__data_save_end");
u32 cold_reboot_flag = 1;
+u32 __weak reset_flag(void)
+{
+ return 1;
+}
+
void spl_save_restore_data(void)
{
u32 data_size = __data_save_end - __data_save_start;
+ cold_reboot_flag = reset_flag();
if (cold_reboot_flag == 1) {
/* Save data section to data_save section */
- memcpy(__data_save_start, __data_save_start - data_size,
- data_size);
+ memcpy(__data_save_start, __data_start, data_size);
} else {
/* Restore the data_save section to data section */
- memcpy(__data_save_start - data_size, __data_save_start,
- data_size);
+ memcpy(__data_start, __data_save_start, data_size);
}
cold_reboot_flag++;
DECLARE_GLOBAL_DATA_PTR;
+u32 reset_flag(void)
+{
+ /* Check rstmgr.stat for warm reset status */
+ u32 status = readl(SOCFPGA_RSTMGR_ADDRESS);
+
+ /* Check whether any L4 watchdogs or SDM had triggered warm reset */
+ u32 warm_reset_mask = RSTMGR_L4WD_MPU_WARMRESET_MASK;
+
+ if (status & warm_reset_mask)
+ return 0;
+
+ return 1;
+}
+
void board_init_f(ulong dummy)
{
int ret;
struct udevice *dev;
+ /* Enable Async */
+ asm volatile("msr daifclr, #4");
+
+#ifdef CONFIG_SPL_BUILD
+ spl_save_restore_data();
+#endif
+
ret = spl_early_init();
if (ret)
hang();