"pll2_pfd2", "pll2_pfd0", "pll1_div5", "pll_arm"};
static const char * const semc_sels[] = {"rcosc48M_div2", "osc", "rcosc400M", "rcosc16M",
"pll1_div5", "pll2_sys", "pll2_pfd2", "pll3_pfd0"};
+static const char * const flexspi1_sels[] = {"rcosc48M_div2", "osc", "rcosc400M", "rcosc16M",
+"pll3_pdf0", "pll2_clk", "pll2_pfd2", "pll3_clk"};
static int imxrt1170_clk_probe(struct udevice *dev)
{
imx_clk_divider(dev, "lpuart1", "lpuart1_sel",
base + (25 * 0x80), 0, 8));
+ clk_dm(IMXRT1170_CLK_FLEXSPI1_SEL,
+ imx_clk_mux(dev, "flexspi1_sel", base + (20 * 0x80), 8, 3,
+ flexspi1_sels, ARRAY_SIZE(flexspi1_sels)));
+ clk_dm(IMXRT1170_CLK_FLEXSPI1,
+ imx_clk_divider(dev, "flexspi1", "flexspi1_sel",
+ base + (20 * 0x80), 0, 8));
+
clk_dm(IMXRT1170_CLK_USDHC1_SEL,
imx_clk_mux(dev, "usdhc1_sel", base + (58 * 0x80), 8, 3,
usdhc1_sels, ARRAY_SIZE(usdhc1_sels)));
.little_endian = true, /* little-endian */
};
+static struct nxp_fspi_devtype_data imxrt1170_data = {
+ .rxfifo = SZ_256,
+ .txfifo = SZ_256,
+ .ahb_buf_size = SZ_4K,
+ .quirks = 0,
+ .lut_num = 16,
+ .little_endian = true,
+};
+
struct nxp_fspi {
struct udevice *dev;
void __iomem *iobase;
{ .compatible = "nxp,lx2160a-fspi", .data = (ulong)&lx2160a_data, },
{ .compatible = "nxp,imx8mm-fspi", .data = (ulong)&imx8mm_data, },
{ .compatible = "nxp,imx8mp-fspi", .data = (ulong)&imx8mm_data, },
+ { .compatible = "nxp,imxrt1170-fspi", .data = (ulong)&imxrt1170_data, },
{ }
};