drm/nvc0/pm: restrict pll mode to clocks that can actually use it
authorBen Skeggs <bskeggs@redhat.com>
Mon, 6 Feb 2012 23:59:54 +0000 (09:59 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Tue, 13 Mar 2012 07:14:58 +0000 (17:14 +1000)
Fixes reclocking failure on some chips where we attempted to set PDAEMON
to PLL mode.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

No differences found