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drm/radeon: rework crtc pll setup to better support PPLL sharing
authorAlex Deucher <alexander.deucher@amd.com>
Thu, 13 Sep 2012 14:56:16 +0000 (10:56 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 20 Sep 2012 17:10:44 +0000 (13:10 -0400)
We need the calculate the pixel clock before allocating a PPLL
in order to insure the clocks really match.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

No differences found
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