gcc-4.5.inc: Disable Optimize load 0.0 for NEON patch

* fixes the cairo regression and has been reported to malfunction
  see https://bugs.launchpad.net/gcc-linaro/+bug/667490

Signed-off-by: Khem Raj <raj.khem@gmail.com>

diff --git a/recipes/gcc/gcc-4.5.inc b/recipes/gcc/gcc-4.5.inc
index b35ee92..14c281c 100644 (file)
--- a/recipes/gcc/gcc-4.5.inc
+++ b/recipes/gcc/gcc-4.5.inc
@@ -8,7 +8,7 @@ DEPENDS = "mpfr gmp libmpc libelf"
 NATIVEDEPS = "mpfr-native gmp-native libmpc-native"
 
 
-INC_PR = "r15"
+INC_PR = "r16"
 
 SRCREV = "165931"
 PV = "4.5"
@@ -75,7 +75,7 @@ SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH} \
           file://linaro/gcc-4.5-linaro-r99347.patch \
           file://linaro/gcc-4.5-linaro-r99348.patch \
           file://linaro/gcc-4.5-linaro-r99349.patch \
-          file://linaro/gcc-4.5-linaro-r99350.patch \
+#         file://linaro/gcc-4.5-linaro-r99350.patch \
           file://linaro/gcc-4.5-linaro-r99351.patch \
           file://linaro/gcc-4.5-linaro-r99352.patch \
           file://linaro/gcc-4.5-linaro-r99353.patch \

diff --git a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99368.patch b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99368.patch
index fa13e0e..0705e41 100644 (file)
--- a/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99368.patch
+++ b/recipes/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99368.patch
@@ -16,20 +16,22 @@
        Backport from mainline:
 
 === modified file 'gcc/config/arm/constraints.md'
---- old/gcc/config/arm/constraints.md  2010-08-13 10:59:06 +0000
-+++ new/gcc/config/arm/constraints.md  2010-08-23 14:29:45 +0000
+Index: gcc-4.5/gcc/config/arm/constraints.md
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/constraints.md
++++ gcc-4.5/gcc/config/arm/constraints.md
 @@ -29,7 +29,7 @@
  ;; in Thumb-1 state: I, J, K, L, M, N, O
  
  ;; The following multi-letter normal constraints have been used:
--;; in ARM/Thumb-2 state: D0, Da, Db, Dc, Di, Dn, Dl, DL, Dv, Dy
-+;; in ARM/Thumb-2 state: D0, Da, Db, Dc, Di, Dn, Dl, DL, Dv, Dy, Dz
+-;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di
++;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dz
  ;; in Thumb-1 state: Pa, Pb
  ;; in Thumb-2 state: Ps, Pt, Pv
  
-@@ -180,6 +180,12 @@
+@@ -173,6 +173,12 @@
   (and (match_code "const_double")
-       (match_test "TARGET_NEON && op == CONST0_RTX (mode)")))
+       (match_test "TARGET_32BIT && neg_const_double_rtx_ok_for_fpa (op)")))
  
 +(define_constraint "Dz"
 + "@internal
@@ -40,10 +42,10 @@
  (define_constraint "Da"
   "@internal
    In ARM/Thumb-2 state a const_int, const_double or const_vector that can
-
-=== modified file 'gcc/config/arm/neon.md'
---- old/gcc/config/arm/neon.md 2010-08-20 16:21:01 +0000
-+++ new/gcc/config/arm/neon.md 2010-08-23 14:29:45 +0000
+Index: gcc-4.5/gcc/config/arm/neon.md
+===================================================================
+--- gcc-4.5.orig/gcc/config/arm/neon.md
++++ gcc-4.5/gcc/config/arm/neon.md
 @@ -141,7 +141,9 @@
     (UNSPEC_VUZP2              202)
     (UNSPEC_VZIP1              203)
@@ -338,4 +340,3 @@
  (define_insn "neon_vcage<mode>"
    [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
          (unspec:<V_cmp_result> [(match_operand:VCVTF 1 "s_register_operand" "w")
-