pinctrl: sunxi: add Allwinner A100/A133 pinctrl description
authorAndre Przywara <andre.przywara@arm.com>
Wed, 25 Oct 2023 23:38:59 +0000 (00:38 +0100)
committerAndre Przywara <andre.przywara@arm.com>
Thu, 27 Mar 2025 00:26:35 +0000 (00:26 +0000)
The Allwinner A100 SoC has been around for a while, and has now seemingly
been replaced with its close sibling A133.

Add the required mapping between the pinmux group strings and their
respective mux value, as far as used by U-Boot proper. Linux has some
basic (clock and pinctrl) support for a while, so we can build on the
names already used there.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
drivers/pinctrl/sunxi/Kconfig
drivers/pinctrl/sunxi/pinctrl-sunxi.c

index cbd6179..65e8192 100644 (file)
@@ -124,6 +124,16 @@ config PINCTRL_SUN50I_H616_R
        default MACH_SUN50I_H616
        select PINCTRL_SUNXI
 
+config PINCTRL_SUN50I_A100
+       bool "Support for the Allwinner A100/A133 PIO"
+       default MACH_SUN50I_A133
+       select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_A100_R
+       bool "Support for the Allwinner A100/A133 R-PIO"
+       default MACH_SUN50I_A133
+       select PINCTRL_SUNXI
+
 config PINCTRL_SUN20I_D1
        bool "Support for the Allwinner D1/R528 PIO"
        default MACH_SUN8I_R528
index 37ea937..c38edf7 100644 (file)
@@ -774,6 +774,41 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_r_pinctrl_desc
        .num_banks      = 1,
 };
 
+static const struct sunxi_pinctrl_function sun50i_a100_pinctrl_functions[] = {
+       { "emac0",      5 },    /* PH0-PH16 */
+       { "gpio_in",    0 },
+       { "gpio_out",   1 },
+       { "mmc0",       2 },    /* PF0-PF5 */
+       { "mmc1",       2 },    /* PG0-PG5 */
+       { "mmc2",       3 },    /* PC0-PC16 */
+       { "spi0",       4 },    /* PC2-PC4, PC7, PC12, PC15-PC16 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+       { "uart0",      3 },    /* PF2-PF4 */
+#else
+       { "uart0",      2 },    /* PB9-PB10 */
+#endif
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a100_pinctrl_desc = {
+       .functions      = sun50i_a100_pinctrl_functions,
+       .num_functions  = ARRAY_SIZE(sun50i_a100_pinctrl_functions),
+       .first_bank     = SUNXI_GPIO_A,
+       .num_banks      = 8,
+};
+
+static const struct sunxi_pinctrl_function sun50i_a100_r_pinctrl_functions[] = {
+       { "gpio_in",    0 },
+       { "gpio_out",   1 },
+       { "s_i2c0",     2 },
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a100_r_pinctrl_desc = {
+       .functions      = sun50i_a100_r_pinctrl_functions,
+       .num_functions  = ARRAY_SIZE(sun50i_a100_r_pinctrl_functions),
+       .first_bank     = SUNXI_GPIO_L,
+       .num_banks      = 1,
+};
+
 static const struct udevice_id sunxi_pinctrl_ids[] = {
 #ifdef CONFIG_PINCTRL_SUNIV_F1C100S
        {
@@ -936,6 +971,18 @@ static const struct udevice_id sunxi_pinctrl_ids[] = {
                .compatible = "allwinner,sun50i-h616-r-pinctrl",
                .data = (ulong)&sun50i_h616_r_pinctrl_desc,
        },
+#endif
+#ifdef CONFIG_PINCTRL_SUN50I_A100
+       {
+               .compatible = "allwinner,sun50i-a100-pinctrl",
+               .data = (ulong)&sun50i_a100_pinctrl_desc,
+       },
+#endif
+#ifdef CONFIG_PINCTRL_SUN50I_A100_R
+       {
+               .compatible = "allwinner,sun50i-a100-r-pinctrl",
+               .data = (ulong)&sun50i_a100_r_pinctrl_desc,
+       },
 #endif
        {}
 };