clk: imx93: support i.MX91

i.MX91 is a derived from i.MX93, and most clocks could be reused from
i.MX93. Also Update imx93-clock.h to sync with linux next.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c
index ede36c4..b31e57a 100644 (file)
--- a/drivers/clk/imx/clk-imx93.c
+++ b/drivers/clk/imx/clk-imx93.c
@@ -13,6 +13,11 @@
 
 #include "clk.h"
 
+#define IMX93_CLK_END 207
+
+#define PLAT_IMX93 BIT(0)
+#define PLAT_IMX91 BIT(1)
+
 enum clk_sel {
        LOW_SPEED_IO_SEL,
        NON_IO_SEL,
@@ -50,6 +55,7 @@ static const struct imx93_clk_root {
        u32 off;
        enum clk_sel sel;
        unsigned long flags;
+       unsigned long plat;
 } root_array[] = {
        /* a55/m33/bus critical clk for system run */
        { IMX93_CLK_A55_PERIPH,         "a55_periph_root",      0x0000, FAST_SEL, CLK_IS_CRITICAL },
@@ -60,7 +66,7 @@ static const struct imx93_clk_root {
        { IMX93_CLK_BUS_AON,            "bus_aon_root",         0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
        { IMX93_CLK_WAKEUP_AXI,         "wakeup_axi_root",      0x0380, FAST_SEL, CLK_IS_CRITICAL },
        { IMX93_CLK_SWO_TRACE,          "swo_trace_root",       0x0400, LOW_SPEED_IO_SEL, },
-       { IMX93_CLK_M33_SYSTICK,        "m33_systick_root",     0x0480, LOW_SPEED_IO_SEL, },
+       { IMX93_CLK_M33_SYSTICK,        "m33_systick_root",     0x0480, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
        { IMX93_CLK_FLEXIO1,            "flexio1_root",         0x0500, LOW_SPEED_IO_SEL, },
        { IMX93_CLK_FLEXIO2,            "flexio2_root",         0x0580, LOW_SPEED_IO_SEL, },
        { IMX93_CLK_LPTMR1,             "lptmr1_root",          0x0700, LOW_SPEED_IO_SEL, },
@@ -117,15 +123,15 @@ static const struct imx93_clk_root {
        { IMX93_CLK_HSIO_ACSCAN_80M,    "hsio_acscan_80m_root", 0x1f80, LOW_SPEED_IO_SEL, },
        { IMX93_CLK_HSIO_ACSCAN_480M,   "hsio_acscan_480m_root", 0x2000, MISC_SEL, },
        { IMX93_CLK_NIC_AXI,            "nic_axi_root",         0x2080, FAST_SEL, CLK_IS_CRITICAL, },
-       { IMX93_CLK_ML_APB,             "ml_apb_root",          0x2180, LOW_SPEED_IO_SEL, },
-       { IMX93_CLK_ML,                 "ml_root",              0x2200, FAST_SEL, },
+       { IMX93_CLK_ML_APB,             "ml_apb_root",          0x2180, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
+       { IMX93_CLK_ML,                 "ml_root",              0x2200, FAST_SEL, 0, PLAT_IMX93, },
        { IMX93_CLK_MEDIA_AXI,          "media_axi_root",       0x2280, FAST_SEL, },
        { IMX93_CLK_MEDIA_APB,          "media_apb_root",       0x2300, LOW_SPEED_IO_SEL, },
-       { IMX93_CLK_MEDIA_LDB,          "media_ldb_root",       0x2380, VIDEO_SEL, },
+       { IMX93_CLK_MEDIA_LDB,          "media_ldb_root",       0x2380, VIDEO_SEL, 0, PLAT_IMX93, },
        { IMX93_CLK_MEDIA_DISP_PIX,     "media_disp_pix_root",  0x2400, VIDEO_SEL, },
        { IMX93_CLK_CAM_PIX,            "cam_pix_root",         0x2480, VIDEO_SEL, },
-       { IMX93_CLK_MIPI_TEST_BYTE,     "mipi_test_byte_root",  0x2500, VIDEO_SEL, },
-       { IMX93_CLK_MIPI_PHY_CFG,       "mipi_phy_cfg_root",    0x2580, VIDEO_SEL, },
+       { IMX93_CLK_MIPI_TEST_BYTE,     "mipi_test_byte_root",  0x2500, VIDEO_SEL, 0, PLAT_IMX93, },
+       { IMX93_CLK_MIPI_PHY_CFG,       "mipi_phy_cfg_root",    0x2580, VIDEO_SEL, 0, PLAT_IMX93, },
        { IMX93_CLK_ADC,                "adc_root",             0x2700, LOW_SPEED_IO_SEL, },
        { IMX93_CLK_PDM,                "pdm_root",             0x2780, AUDIO_SEL, },
        { IMX93_CLK_TSTMR1,             "tstmr1_root",          0x2800, LOW_SPEED_IO_SEL, },
@@ -134,13 +140,16 @@ static const struct imx93_clk_root {
        { IMX93_CLK_MQS2,               "mqs2_root",            0x2980, AUDIO_SEL, },
        { IMX93_CLK_AUDIO_XCVR,         "audio_xcvr_root",      0x2a00, NON_IO_SEL, },
        { IMX93_CLK_SPDIF,              "spdif_root",           0x2a80, AUDIO_SEL, },
-       { IMX93_CLK_ENET,               "enet_root",            0x2b00, NON_IO_SEL, },
-       { IMX93_CLK_ENET_TIMER1,        "enet_timer1_root",     0x2b80, LOW_SPEED_IO_SEL, },
-       { IMX93_CLK_ENET_TIMER2,        "enet_timer2_root",     0x2c00, LOW_SPEED_IO_SEL, },
-       { IMX93_CLK_ENET_REF,           "enet_ref_root",        0x2c80, NON_IO_SEL, },
-       { IMX93_CLK_ENET_REF_PHY,       "enet_ref_phy_root",    0x2d00, LOW_SPEED_IO_SEL, },
-       { IMX93_CLK_I3C1_SLOW,          "i3c1_slow_root",       0x2d80, LOW_SPEED_IO_SEL, },
-       { IMX93_CLK_I3C2_SLOW,          "i3c2_slow_root",       0x2e00, LOW_SPEED_IO_SEL, },
+       { IMX93_CLK_ENET,               "enet_root",            0x2b00, NON_IO_SEL, 0, PLAT_IMX93, },
+       { IMX93_CLK_ENET_TIMER1,        "enet_timer1_root",     0x2b80, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
+       { IMX93_CLK_ENET_TIMER2,        "enet_timer2_root",     0x2c00, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
+       { IMX93_CLK_ENET_REF,           "enet_ref_root",        0x2c80, NON_IO_SEL, 0, PLAT_IMX93, },
+       { IMX93_CLK_ENET_REF_PHY,       "enet_ref_phy_root",    0x2d00, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
+       { IMX91_CLK_ENET1_QOS_TSN,      "enet1_qos_tsn_root",   0x2b00, NON_IO_SEL, 0, PLAT_IMX91, },
+       { IMX91_CLK_ENET_TIMER,         "enet_timer_root",      0x2b80, LOW_SPEED_IO_SEL, 0, PLAT_IMX91, },
+       { IMX91_CLK_ENET2_REGULAR,      "enet2_regular_root",   0x2c80, NON_IO_SEL, 0, PLAT_IMX91, },
+       { IMX93_CLK_I3C1_SLOW,          "i3c1_slow_root",       0x2d80, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
+       { IMX93_CLK_I3C2_SLOW,          "i3c2_slow_root",       0x2e00, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
        { IMX93_CLK_USB_PHY_BURUNIN,    "usb_phy_root",         0x2e80, LOW_SPEED_IO_SEL, },
        { IMX93_CLK_PAL_CAME_SCAN,      "pal_came_scan_root",   0x2f00, MISC_SEL, }
 };
@@ -152,6 +161,7 @@ static const struct imx93_clk_ccgr {
        u32 off;
        unsigned long flags;
        u32 *shared_count;
+       unsigned long plat;
 } ccgr_array[] = {
        { IMX93_CLK_A55_GATE,           "a55_alt",      "a55_alt_root",         0x8000, },
        /* M33 critical clk for system run */
@@ -226,7 +236,7 @@ static const struct imx93_clk_ccgr {
        { IMX93_CLK_SAI3_IPG,           "sai3_ipg_clk", "bus_wakeup_root",      0x94c0, 0, &share_count_sai3},
        { IMX93_CLK_MIPI_CSI_GATE,      "mipi_csi",     "media_apb_root",       0x9580, },
        { IMX93_CLK_MIPI_DSI_GATE,      "mipi_dsi",     "media_apb_root",       0x95c0, },
-       { IMX93_CLK_LVDS_GATE,          "lvds",         "media_ldb_root",       0x9600, },
+       { IMX93_CLK_LVDS_GATE,          "lvds",         "media_ldb_root",       0x9600, 0, NULL, PLAT_IMX93, },
        { IMX93_CLK_LCDIF_GATE,         "lcdif",        "media_apb_root",       0x9640, },
        { IMX93_CLK_PXP_GATE,           "pxp",          "media_apb_root",       0x9680, },
        { IMX93_CLK_ISI_GATE,           "isi",          "media_apb_root",       0x96c0, },
@@ -240,8 +250,10 @@ static const struct imx93_clk_ccgr {
        { IMX93_CLK_AUD_XCVR_GATE,      "aud_xcvr",     "audio_xcvr_root",      0x9b80, },
        { IMX93_CLK_SPDIF_GATE,         "spdif",        "spdif_root",           0x9c00, },
        { IMX93_CLK_HSIO_32K_GATE,      "hsio_32k",     "clock-osc-24m",        0x9dc0, },
-       { IMX93_CLK_ENET1_GATE,         "enet1",        "wakeup_axi_root",      0x9e00, },
-       { IMX93_CLK_ENET_QOS_GATE,      "enet_qos",     "wakeup_axi_root",      0x9e40, },
+       { IMX93_CLK_ENET1_GATE,         "enet1",        "wakeup_axi_root",      0x9e00, 0, NULL, PLAT_IMX93, },
+       { IMX93_CLK_ENET_QOS_GATE,      "enet_qos",     "wakeup_axi_root",      0x9e40, 0, NULL, PLAT_IMX93, },
+       { IMX91_CLK_ENET2_REGULAR_GATE, "enet2_regular",        "wakeup_axi_root",      0x9e00, 0, NULL, PLAT_IMX91, },
+       { IMX91_CLK_ENET1_QOS_TSN_GATE,     "enet1_qos_tsn",        "wakeup_axi_root",      0x9e40, 0, NULL, PLAT_IMX91, },
        /* Critical because clk accessed during CPU idle */
        { IMX93_CLK_SYS_CNT_GATE,       "sys_cnt",      "clock-osc-24m",        0x9e80, CLK_IS_CRITICAL},
        { IMX93_CLK_TSTMR1_GATE,        "tstmr1",       "bus_aon_root",         0x9ec0, },
@@ -257,6 +269,7 @@ static int imx93_clk_probe(struct udevice *dev)
        struct clk osc_24m_clk, osc_32k_clk, ext1_clk;
        void __iomem *base, *anatop_base;
        int i, ret;
+       const unsigned long plat = (unsigned long)dev_get_driver_data(dev);
 
        clk_dm(IMX93_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0UL));
 
@@ -307,6 +320,8 @@ static int imx93_clk_probe(struct udevice *dev)
 
        for (i = 0; i < ARRAY_SIZE(root_array); i++) {
                root = &root_array[i];
+               if (root->plat && !(root->plat & plat))
+                       continue;
                clk_dm(root->clk, imx93_clk_composite_flags(root->name,
                                                            parent_names[root->sel],
                                                            4, base + root->off, 3,
@@ -315,6 +330,8 @@ static int imx93_clk_probe(struct udevice *dev)
 
        for (i = 0; i < ARRAY_SIZE(ccgr_array); i++) {
                ccgr = &ccgr_array[i];
+               if (ccgr->plat && !(ccgr->plat & plat))
+                       continue;
                clk_dm(ccgr->clk, imx93_clk_gate(NULL, ccgr->name, ccgr->parent_name,
                                                 ccgr->flags, base + ccgr->off, 0, 1, 1, 3,
                                                 ccgr->shared_count));
@@ -328,7 +345,8 @@ static int imx93_clk_probe(struct udevice *dev)
 }
 
 static const struct udevice_id imx93_clk_ids[] = {
-       { .compatible = "fsl,imx93-ccm" },
+       { .compatible = "fsl,imx93-ccm", .data = (unsigned long)PLAT_IMX93 },
+       { .compatible = "fsl,imx91-ccm", .data = (unsigned long)PLAT_IMX91 },
        { /* Sentinel */ },
 };
 

diff --git a/dts/upstream/include/dt-bindings/clock/imx93-clock.h b/dts/upstream/include/dt-bindings/clock/imx93-clock.h
index 787c9e7..6c68506 100644 (file)
--- a/dts/upstream/include/dt-bindings/clock/imx93-clock.h
+++ b/dts/upstream/include/dt-bindings/clock/imx93-clock.h
@@ -204,6 +204,10 @@
 #define IMX93_CLK_A55_SEL              199
 #define IMX93_CLK_A55_CORE             200
 #define IMX93_CLK_PDM_IPG              201
-#define IMX93_CLK_END                  202
+#define IMX91_CLK_ENET1_QOS_TSN     202
+#define IMX91_CLK_ENET_TIMER        203
+#define IMX91_CLK_ENET2_REGULAR     204
+#define IMX91_CLK_ENET2_REGULAR_GATE           205
+#define IMX91_CLK_ENET1_QOS_TSN_GATE           206
 
 #endif