pci: pcie_dw_rockchip: Use dw_pcie_link_set_max_link_width()

Use dw_pcie_link_set_max_link_width() instead of local implementation
of the same functionality. This does change the behavior slightly, as
the dw_pcie_link_set_max_link_width() implementation also programs the
LNKCAP register MLW, this should however be correct and is now aligned
with Linux kernel behavior.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index ac7faa4..208aa30 100644 (file)
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -158,8 +158,6 @@ static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg,
  */
 static void rk_pcie_configure(struct rk_pcie *pci)
 {
-       u32 val;
-
        dw_pcie_dbi_write_enable(&pci->dw, true);
 
        /* Disable BAR 0 and BAR 1 */
@@ -175,43 +173,8 @@ static void rk_pcie_configure(struct rk_pcie *pci)
                        TARGET_LINK_SPEED_MASK, pci->gen);
 
        /* Set the number of lanes */
-       val = readl(pci->dw.dbi_base + PCIE_PORT_LINK_CONTROL);
-       val &= ~PORT_LINK_FAST_LINK_MODE;
-       val |= PORT_LINK_DLL_LINK_EN;
-       val &= ~PORT_LINK_MODE_MASK;
-       switch (pci->num_lanes) {
-       case 1:
-               val |= PORT_LINK_MODE_1_LANES;
-               break;
-       case 2:
-               val |= PORT_LINK_MODE_2_LANES;
-               break;
-       case 4:
-               val |= PORT_LINK_MODE_4_LANES;
-               break;
-       default:
-               dev_err(pci->dw.dev, "num-lanes %u: invalid value\n", pci->num_lanes);
-               goto out;
-       }
-       writel(val, pci->dw.dbi_base + PCIE_PORT_LINK_CONTROL);
-
-       /* Set link width speed control register */
-       val = readl(pci->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
-       val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
-       switch (pci->num_lanes) {
-       case 1:
-               val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
-               break;
-       case 2:
-               val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
-               break;
-       case 4:
-               val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
-               break;
-       }
-       writel(val, pci->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
+       dw_pcie_link_set_max_link_width(&pci->dw, pci->num_lanes);
 
-out:
        dw_pcie_dbi_write_enable(&pci->dw, false);
 }