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microblaze: Clear all MSR flags on the first kernel instruction
authorMichal Simek <monstr@monstr.eu>
Wed, 9 Nov 2011 14:39:58 +0000 (15:39 +0100)
committerMichal Simek <monstr@monstr.eu>
Fri, 23 Mar 2012 08:28:16 +0000 (09:28 +0100)
The main reason is bug because of dynamic TLB allocation.
U-BOOT didn't disable dcache and then writing to physical address
from ASM wan't visible for reading through MMU.
Disabling caches and clearing all flags from previous code
is good to do so.

Signed-off-by: Michal Simek <monstr@monstr.eu>
arch/microblaze/kernel/head.S patch | blob | history

diff --cc arch/microblaze/kernel/head.S
Simple merge
Pandora Kernel Repository