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agp/intel: fix cache control for sandybridge
authorZhenyu Wang <zhenyuw@linux.intel.com>
Tue, 2 Nov 2010 09:30:46 +0000 (17:30 +0800)
committerChris Wilson <chris@chris-wilson.co.uk>
Thu, 4 Nov 2010 09:39:50 +0000 (09:39 +0000)
This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3.
Let's set the correct bit for LLC+MLC and LLC only.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

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