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ath9k_hw: Update the PCI WAR register
authorSujith <Sujith.Manoharan@atheros.com>
Tue, 1 Jun 2010 09:44:09 +0000 (15:14 +0530)
committerJohn W. Linville <linville@tuxdriver.com>
Thu, 3 Jun 2010 18:10:46 +0000 (14:10 -0400)
This patch updates the PCI power save handling
code, fixing ASPM hangs and handling device state D3
properly.

The WAR register is programmed with the correct
values now.

Signed-off-by: Sujith <Sujith.Manoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

No differences found
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