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MIPS: lantiq: fix bootselect bits on XRX200 SoC
authorJohn Crispin <blogic@openwrt.org>
Fri, 9 Nov 2012 12:31:51 +0000 (13:31 +0100)
committerJohn Crispin <blogic@openwrt.org>
Sun, 11 Nov 2012 17:47:20 +0000 (18:47 +0100)
The XRX200 SoC family has a different register layout for reading the boot
selection bits.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4519


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