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RDMA/cxgb4: Zero out ISGL padding
authorSteve Wise <swise@opengridcomputing.com>
Fri, 10 Sep 2010 16:14:53 +0000 (11:14 -0500)
committerRoland Dreier <rolandd@cisco.com>
Tue, 28 Sep 2010 17:46:30 +0000 (10:46 -0700)
The HW design requires zeroing any pad in SGLs.

Signed-off-by: Steve Wise <swise@opengridcomputing.com>
Signed-off-by: Roland Dreier <rolandd@cisco.com>

No differences found
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