+++ /dev/null
-From 26abf45ac80be4c54a63fecf1c3c1e1efb416e0a Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Wed, 1 Apr 2009 18:27:09 +0300
-Subject: [PATCH 01/69] Revert "gro: Fix legacy path napi_complete crash"
-
-This reverts commit 303c6a0251852ecbdc5c15e466dcaff5971f7517.
-
-Fixes USB network problems
----
- net/core/dev.c | 5 ++---
- 1 files changed, 2 insertions(+), 3 deletions(-)
-
-diff --git a/net/core/dev.c b/net/core/dev.c
-index e3fe5c7..c1e9dc0 100644
---- a/net/core/dev.c
-+++ b/net/core/dev.c
-@@ -2588,9 +2588,9 @@ static int process_backlog(struct napi_struct *napi, int quota)
- local_irq_disable();
- skb = __skb_dequeue(&queue->input_pkt_queue);
- if (!skb) {
-+ __napi_complete(napi);
- local_irq_enable();
-- napi_complete(napi);
-- goto out;
-+ break;
- }
- local_irq_enable();
-
-@@ -2599,7 +2599,6 @@ static int process_backlog(struct napi_struct *napi, int quota)
-
- napi_gro_flush(napi);
-
--out:
- return work;
- }
-
---
-1.6.2.4
-
+++ /dev/null
-From 02243f13eec816e11d16676a131bc04b8a0666ab Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Wed, 11 Feb 2009 16:33:02 +0200
-Subject: [PATCH] OMAPFB: move omapfb.h to include/linux/
-
-This is needed so that omapfb.h is automatically exported to user space.
-
-omapfb.h should be cleaned up later. Some stuff can probably be moved
-to omapfb's private include file.
-
-Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
----
- arch/arm/mach-omap1/board-nokia770.c | 2 +-
- arch/arm/mach-omap2/board-n800.c | 2 +-
- arch/arm/mach-omap2/io.c | 2 +-
- arch/arm/plat-omap/fb.c | 2 +-
- arch/arm/plat-omap/include/mach/omapfb.h | 398 ------------------------------
- drivers/video/omap/blizzard.c | 2 +-
- drivers/video/omap/dispc.c | 2 +-
- drivers/video/omap/hwa742.c | 2 +-
- drivers/video/omap/lcd_2430sdp.c | 2 +-
- drivers/video/omap/lcd_ams_delta.c | 2 +-
- drivers/video/omap/lcd_apollon.c | 2 +-
- drivers/video/omap/lcd_h3.c | 2 +-
- drivers/video/omap/lcd_h4.c | 3 +-
- drivers/video/omap/lcd_inn1510.c | 2 +-
- drivers/video/omap/lcd_inn1610.c | 2 +-
- drivers/video/omap/lcd_ldp.c | 2 +-
- drivers/video/omap/lcd_mipid.c | 2 +-
- drivers/video/omap/lcd_omap2evm.c | 2 +-
- drivers/video/omap/lcd_omap3beagle.c | 2 +-
- drivers/video/omap/lcd_omap3evm.c | 2 +-
- drivers/video/omap/lcd_osk.c | 2 +-
- drivers/video/omap/lcd_overo.c | 2 +-
- drivers/video/omap/lcd_p2.c | 2 +-
- drivers/video/omap/lcd_palmte.c | 2 +-
- drivers/video/omap/lcd_palmtt.c | 2 +-
- drivers/video/omap/lcd_palmz71.c | 3 +-
- drivers/video/omap/lcdc.c | 2 +-
- drivers/video/omap/omapfb_main.c | 2 +-
- drivers/video/omap/rfbi.c | 3 +-
- drivers/video/omap/sossi.c | 2 +-
- include/linux/omapfb.h | 398 ++++++++++++++++++++++++++++++
- 31 files changed, 427 insertions(+), 430 deletions(-)
- delete mode 100644 arch/arm/plat-omap/include/mach/omapfb.h
- create mode 100644 include/linux/omapfb.h
-
-diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
-index 8780ca6..ca4680a 100644
---- a/arch/arm/mach-omap1/board-nokia770.c
-+++ b/arch/arm/mach-omap1/board-nokia770.c
-@@ -18,6 +18,7 @@
- #include <linux/spi/spi.h>
- #include <linux/spi/ads7846.h>
- #include <linux/workqueue.h>
-+#include <linux/omapfb.h>
- #include <linux/delay.h>
-
- #include <mach/hardware.h>
-@@ -32,7 +33,6 @@
- #include <mach/keypad.h>
- #include <mach/common.h>
- #include <mach/dsp_common.h>
--#include <mach/omapfb.h>
- #include <mach/lcd_mipid.h>
- #include <mach/mmc.h>
- #include <mach/usb.h>
-diff --git a/arch/arm/mach-omap2/board-n800.c b/arch/arm/mach-omap2/board-n800.c
-index cb32b61..f6f6571 100644
---- a/arch/arm/mach-omap2/board-n800.c
-+++ b/arch/arm/mach-omap2/board-n800.c
-@@ -27,6 +27,7 @@
- #include <linux/i2c/lm8323.h>
- #include <linux/i2c/menelaus.h>
- #include <linux/i2c/lp5521.h>
-+#include <linux/omapfb.h>
- #include <mach/hardware.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
-@@ -39,7 +40,6 @@
- #include <mach/lcd_mipid.h>
- #include <mach/clock.h>
- #include <mach/gpio-switch.h>
--#include <mach/omapfb.h>
- #include <mach/blizzard.h>
-
- #include <../drivers/cbus/tahvo.h>
-diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
-index 3746222..40615a6 100644
---- a/arch/arm/plat-omap/fb.c
-+++ b/arch/arm/plat-omap/fb.c
-@@ -28,13 +28,13 @@
- #include <linux/platform_device.h>
- #include <linux/bootmem.h>
- #include <linux/io.h>
-+#include <linux/omapfb.h>
-
- #include <mach/hardware.h>
- #include <asm/mach/map.h>
-
- #include <mach/board.h>
- #include <mach/sram.h>
--#include <mach/omapfb.h>
-
- #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
-
-diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/mach/omapfb.h
-deleted file mode 100644
-index b226bdf..0000000
---- a/arch/arm/plat-omap/include/mach/omapfb.h
-+++ /dev/null
-@@ -1,398 +0,0 @@
--/*
-- * File: arch/arm/plat-omap/include/mach/omapfb.h
-- *
-- * Framebuffer driver for TI OMAP boards
-- *
-- * Copyright (C) 2004 Nokia Corporation
-- * Author: Imre Deak <imre.deak@nokia.com>
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License as published by the
-- * Free Software Foundation; either version 2 of the License, or (at your
-- * option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful, but
-- * WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- * General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License along
-- * with this program; if not, write to the Free Software Foundation, Inc.,
-- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- */
--
--#ifndef __OMAPFB_H
--#define __OMAPFB_H
--
--#include <asm/ioctl.h>
--#include <asm/types.h>
--
--/* IOCTL commands. */
--
--#define OMAP_IOW(num, dtype) _IOW('O', num, dtype)
--#define OMAP_IOR(num, dtype) _IOR('O', num, dtype)
--#define OMAP_IOWR(num, dtype) _IOWR('O', num, dtype)
--#define OMAP_IO(num) _IO('O', num)
--
--#define OMAPFB_MIRROR OMAP_IOW(31, int)
--#define OMAPFB_SYNC_GFX OMAP_IO(37)
--#define OMAPFB_VSYNC OMAP_IO(38)
--#define OMAPFB_SET_UPDATE_MODE OMAP_IOW(40, int)
--#define OMAPFB_GET_CAPS OMAP_IOR(42, struct omapfb_caps)
--#define OMAPFB_GET_UPDATE_MODE OMAP_IOW(43, int)
--#define OMAPFB_LCD_TEST OMAP_IOW(45, int)
--#define OMAPFB_CTRL_TEST OMAP_IOW(46, int)
--#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old)
--#define OMAPFB_SET_COLOR_KEY OMAP_IOW(50, struct omapfb_color_key)
--#define OMAPFB_GET_COLOR_KEY OMAP_IOW(51, struct omapfb_color_key)
--#define OMAPFB_SETUP_PLANE OMAP_IOW(52, struct omapfb_plane_info)
--#define OMAPFB_QUERY_PLANE OMAP_IOW(53, struct omapfb_plane_info)
--#define OMAPFB_UPDATE_WINDOW OMAP_IOW(54, struct omapfb_update_window)
--#define OMAPFB_SETUP_MEM OMAP_IOW(55, struct omapfb_mem_info)
--#define OMAPFB_QUERY_MEM OMAP_IOW(56, struct omapfb_mem_info)
--
--#define OMAPFB_CAPS_GENERIC_MASK 0x00000fff
--#define OMAPFB_CAPS_LCDC_MASK 0x00fff000
--#define OMAPFB_CAPS_PANEL_MASK 0xff000000
--
--#define OMAPFB_CAPS_MANUAL_UPDATE 0x00001000
--#define OMAPFB_CAPS_TEARSYNC 0x00002000
--#define OMAPFB_CAPS_PLANE_RELOCATE_MEM 0x00004000
--#define OMAPFB_CAPS_PLANE_SCALE 0x00008000
--#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000
--#define OMAPFB_CAPS_WINDOW_SCALE 0x00020000
--#define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000
--#define OMAPFB_CAPS_WINDOW_ROTATE 0x00080000
--#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000
--
--/* Values from DSP must map to lower 16-bits */
--#define OMAPFB_FORMAT_MASK 0x00ff
--#define OMAPFB_FORMAT_FLAG_DOUBLE 0x0100
--#define OMAPFB_FORMAT_FLAG_TEARSYNC 0x0200
--#define OMAPFB_FORMAT_FLAG_FORCE_VSYNC 0x0400
--#define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY 0x0800
--#define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY 0x1000
--
--#define OMAPFB_EVENT_READY 1
--#define OMAPFB_EVENT_DISABLED 2
--
--#define OMAPFB_MEMTYPE_SDRAM 0
--#define OMAPFB_MEMTYPE_SRAM 1
--#define OMAPFB_MEMTYPE_MAX 1
--
--enum omapfb_color_format {
-- OMAPFB_COLOR_RGB565 = 0,
-- OMAPFB_COLOR_YUV422,
-- OMAPFB_COLOR_YUV420,
-- OMAPFB_COLOR_CLUT_8BPP,
-- OMAPFB_COLOR_CLUT_4BPP,
-- OMAPFB_COLOR_CLUT_2BPP,
-- OMAPFB_COLOR_CLUT_1BPP,
-- OMAPFB_COLOR_RGB444,
-- OMAPFB_COLOR_YUY422,
--};
--
--struct omapfb_update_window {
-- __u32 x, y;
-- __u32 width, height;
-- __u32 format;
-- __u32 out_x, out_y;
-- __u32 out_width, out_height;
-- __u32 reserved[8];
--};
--
--struct omapfb_update_window_old {
-- __u32 x, y;
-- __u32 width, height;
-- __u32 format;
--};
--
--enum omapfb_plane {
-- OMAPFB_PLANE_GFX = 0,
-- OMAPFB_PLANE_VID1,
-- OMAPFB_PLANE_VID2,
--};
--
--enum omapfb_channel_out {
-- OMAPFB_CHANNEL_OUT_LCD = 0,
-- OMAPFB_CHANNEL_OUT_DIGIT,
--};
--
--struct omapfb_plane_info {
-- __u32 pos_x;
-- __u32 pos_y;
-- __u8 enabled;
-- __u8 channel_out;
-- __u8 mirror;
-- __u8 reserved1;
-- __u32 out_width;
-- __u32 out_height;
-- __u32 reserved2[12];
--};
--
--struct omapfb_mem_info {
-- __u32 size;
-- __u8 type;
-- __u8 reserved[3];
--};
--
--struct omapfb_caps {
-- __u32 ctrl;
-- __u32 plane_color;
-- __u32 wnd_color;
--};
--
--enum omapfb_color_key_type {
-- OMAPFB_COLOR_KEY_DISABLED = 0,
-- OMAPFB_COLOR_KEY_GFX_DST,
-- OMAPFB_COLOR_KEY_VID_SRC,
--};
--
--struct omapfb_color_key {
-- __u8 channel_out;
-- __u32 background;
-- __u32 trans_key;
-- __u8 key_type;
--};
--
--enum omapfb_update_mode {
-- OMAPFB_UPDATE_DISABLED = 0,
-- OMAPFB_AUTO_UPDATE,
-- OMAPFB_MANUAL_UPDATE
--};
--
--#ifdef __KERNEL__
--
--#include <linux/completion.h>
--#include <linux/interrupt.h>
--#include <linux/fb.h>
--#include <linux/mutex.h>
--
--#include <mach/board.h>
--
--#define OMAP_LCDC_INV_VSYNC 0x0001
--#define OMAP_LCDC_INV_HSYNC 0x0002
--#define OMAP_LCDC_INV_PIX_CLOCK 0x0004
--#define OMAP_LCDC_INV_OUTPUT_EN 0x0008
--#define OMAP_LCDC_HSVS_RISING_EDGE 0x0010
--#define OMAP_LCDC_HSVS_OPPOSITE 0x0020
--
--#define OMAP_LCDC_SIGNAL_MASK 0x003f
--
--#define OMAP_LCDC_PANEL_TFT 0x0100
--
--#define OMAPFB_PLANE_XRES_MIN 8
--#define OMAPFB_PLANE_YRES_MIN 8
--
--#ifdef CONFIG_ARCH_OMAP1
--#define OMAPFB_PLANE_NUM 1
--#else
--#define OMAPFB_PLANE_NUM 3
--#endif
--
--struct omapfb_device;
--
--struct lcd_panel {
-- const char *name;
-- int config; /* TFT/STN, signal inversion */
-- int bpp; /* Pixel format in fb mem */
-- int data_lines; /* Lines on LCD HW interface */
--
-- int x_res, y_res;
-- int pixel_clock; /* In kHz */
-- int hsw; /* Horizontal synchronization
-- pulse width */
-- int hfp; /* Horizontal front porch */
-- int hbp; /* Horizontal back porch */
-- int vsw; /* Vertical synchronization
-- pulse width */
-- int vfp; /* Vertical front porch */
-- int vbp; /* Vertical back porch */
-- int acb; /* ac-bias pin frequency */
-- int pcd; /* pixel clock divider.
-- Obsolete use pixel_clock instead */
--
-- int (*init) (struct lcd_panel *panel,
-- struct omapfb_device *fbdev);
-- void (*cleanup) (struct lcd_panel *panel);
-- int (*enable) (struct lcd_panel *panel);
-- void (*disable) (struct lcd_panel *panel);
-- unsigned long (*get_caps) (struct lcd_panel *panel);
-- int (*set_bklight_level)(struct lcd_panel *panel,
-- unsigned int level);
-- unsigned int (*get_bklight_level)(struct lcd_panel *panel);
-- unsigned int (*get_bklight_max) (struct lcd_panel *panel);
-- int (*run_test) (struct lcd_panel *panel, int test_num);
--};
--
--struct extif_timings {
-- int cs_on_time;
-- int cs_off_time;
-- int we_on_time;
-- int we_off_time;
-- int re_on_time;
-- int re_off_time;
-- int we_cycle_time;
-- int re_cycle_time;
-- int cs_pulse_width;
-- int access_time;
--
-- int clk_div;
--
-- u32 tim[5]; /* set by extif->convert_timings */
--
-- int converted;
--};
--
--struct lcd_ctrl_extif {
-- int (*init) (struct omapfb_device *fbdev);
-- void (*cleanup) (void);
-- void (*get_clk_info) (u32 *clk_period, u32 *max_clk_div);
-- unsigned long (*get_max_tx_rate)(void);
-- int (*convert_timings) (struct extif_timings *timings);
-- void (*set_timings) (const struct extif_timings *timings);
-- void (*set_bits_per_cycle)(int bpc);
-- void (*write_command) (const void *buf, unsigned int len);
-- void (*read_data) (void *buf, unsigned int len);
-- void (*write_data) (const void *buf, unsigned int len);
-- void (*transfer_area) (int width, int height,
-- void (callback)(void * data), void *data);
-- int (*setup_tearsync) (unsigned pin_cnt,
-- unsigned hs_pulse_time, unsigned vs_pulse_time,
-- int hs_pol_inv, int vs_pol_inv, int div);
-- int (*enable_tearsync) (int enable, unsigned line);
--
-- unsigned long max_transmit_size;
--};
--
--struct omapfb_notifier_block {
-- struct notifier_block nb;
-- void *data;
-- int plane_idx;
--};
--
--typedef int (*omapfb_notifier_callback_t)(struct notifier_block *,
-- unsigned long event,
-- void *fbi);
--
--struct omapfb_mem_region {
-- u32 paddr;
-- void __iomem *vaddr;
-- unsigned long size;
-- u8 type; /* OMAPFB_PLANE_MEM_* */
-- unsigned alloc:1; /* allocated by the driver */
-- unsigned map:1; /* kernel mapped by the driver */
--};
--
--struct omapfb_mem_desc {
-- int region_cnt;
-- struct omapfb_mem_region region[OMAPFB_PLANE_NUM];
--};
--
--struct lcd_ctrl {
-- const char *name;
-- void *data;
--
-- int (*init) (struct omapfb_device *fbdev,
-- int ext_mode,
-- struct omapfb_mem_desc *req_md);
-- void (*cleanup) (void);
-- void (*bind_client) (struct omapfb_notifier_block *nb);
-- void (*get_caps) (int plane, struct omapfb_caps *caps);
-- int (*set_update_mode)(enum omapfb_update_mode mode);
-- enum omapfb_update_mode (*get_update_mode)(void);
-- int (*setup_plane) (int plane, int channel_out,
-- unsigned long offset,
-- int screen_width,
-- int pos_x, int pos_y, int width,
-- int height, int color_mode);
-- int (*set_rotate) (int angle);
-- int (*setup_mem) (int plane, size_t size,
-- int mem_type, unsigned long *paddr);
-- int (*mmap) (struct fb_info *info,
-- struct vm_area_struct *vma);
-- int (*set_scale) (int plane,
-- int orig_width, int orig_height,
-- int out_width, int out_height);
-- int (*enable_plane) (int plane, int enable);
-- int (*update_window) (struct fb_info *fbi,
-- struct omapfb_update_window *win,
-- void (*callback)(void *),
-- void *callback_data);
-- void (*sync) (void);
-- void (*suspend) (void);
-- void (*resume) (void);
-- int (*run_test) (int test_num);
-- int (*setcolreg) (u_int regno, u16 red, u16 green,
-- u16 blue, u16 transp,
-- int update_hw_mem);
-- int (*set_color_key) (struct omapfb_color_key *ck);
-- int (*get_color_key) (struct omapfb_color_key *ck);
--};
--
--enum omapfb_state {
-- OMAPFB_DISABLED = 0,
-- OMAPFB_SUSPENDED= 99,
-- OMAPFB_ACTIVE = 100
--};
--
--struct omapfb_plane_struct {
-- int idx;
-- struct omapfb_plane_info info;
-- enum omapfb_color_format color_mode;
-- struct omapfb_device *fbdev;
--};
--
--struct omapfb_device {
-- int state;
-- int ext_lcdc; /* Using external
-- LCD controller */
-- struct mutex rqueue_mutex;
--
-- int palette_size;
-- u32 pseudo_palette[17];
--
-- struct lcd_panel *panel; /* LCD panel */
-- const struct lcd_ctrl *ctrl; /* LCD controller */
-- const struct lcd_ctrl *int_ctrl; /* internal LCD ctrl */
-- struct lcd_ctrl_extif *ext_if; /* LCD ctrl external
-- interface */
-- struct device *dev;
-- struct fb_var_screeninfo new_var; /* for mode changes */
--
-- struct omapfb_mem_desc mem_desc;
-- struct fb_info *fb_info[OMAPFB_PLANE_NUM];
--};
--
--struct omapfb_platform_data {
-- struct omap_lcd_config lcd;
-- struct omapfb_mem_desc mem_desc;
-- void *ctrl_platform_data;
--};
--
--#ifdef CONFIG_ARCH_OMAP1
--extern struct lcd_ctrl omap1_lcd_ctrl;
--#else
--extern struct lcd_ctrl omap2_disp_ctrl;
--#endif
--
--extern void omapfb_reserve_sdram(void);
--extern void omapfb_register_panel(struct lcd_panel *panel);
--extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
--extern void omapfb_notify_clients(struct omapfb_device *fbdev,
-- unsigned long event);
--extern int omapfb_register_client(struct omapfb_notifier_block *nb,
-- omapfb_notifier_callback_t callback,
-- void *callback_data);
--extern int omapfb_unregister_client(struct omapfb_notifier_block *nb);
--extern int omapfb_update_window_async(struct fb_info *fbi,
-- struct omapfb_update_window *win,
-- void (*callback)(void *),
-- void *callback_data);
--
--/* in arch/arm/plat-omap/fb.c */
--extern void omapfb_set_ctrl_platform_data(void *pdata);
--
--#endif /* __KERNEL__ */
--
--#endif /* __OMAPFB_H */
-diff --git a/drivers/video/omap/blizzard.c b/drivers/video/omap/blizzard.c
-index f60a233..8121c09 100644
---- a/drivers/video/omap/blizzard.c
-+++ b/drivers/video/omap/blizzard.c
-@@ -25,9 +25,9 @@
- #include <linux/fb.h>
- #include <linux/delay.h>
- #include <linux/clk.h>
-+#include <linux/omapfb.h>
-
- #include <mach/dma.h>
--#include <mach/omapfb.h>
- #include <mach/blizzard.h>
-
- #include "dispc.h"
-diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
-index c140c21..1915af5 100644
---- a/drivers/video/omap/dispc.c
-+++ b/drivers/video/omap/dispc.c
-@@ -24,9 +24,9 @@
- #include <linux/vmalloc.h>
- #include <linux/clk.h>
- #include <linux/io.h>
-+#include <linux/omapfb.h>
-
- #include <mach/sram.h>
--#include <mach/omapfb.h>
- #include <mach/board.h>
-
- #include "dispc.h"
-diff --git a/drivers/video/omap/hwa742.c b/drivers/video/omap/hwa742.c
-index f24df0b..9b4c506 100644
---- a/drivers/video/omap/hwa742.c
-+++ b/drivers/video/omap/hwa742.c
-@@ -25,9 +25,9 @@
- #include <linux/fb.h>
- #include <linux/delay.h>
- #include <linux/clk.h>
-+#include <linux/omapfb.h>
-
- #include <mach/dma.h>
--#include <mach/omapfb.h>
- #include <mach/hwa742.h>
-
- #define HWA742_REV_CODE_REG 0x0
-diff --git a/drivers/video/omap/lcd_2430sdp.c b/drivers/video/omap/lcd_2430sdp.c
-index a22b452..1252cc3 100644
---- a/drivers/video/omap/lcd_2430sdp.c
-+++ b/drivers/video/omap/lcd_2430sdp.c
-@@ -26,9 +26,9 @@
- #include <linux/delay.h>
- #include <linux/gpio.h>
- #include <linux/i2c/twl4030.h>
-+#include <linux/omapfb.h>
-
- #include <mach/mux.h>
--#include <mach/omapfb.h>
- #include <asm/mach-types.h>
-
- #define SDP2430_LCD_PANEL_BACKLIGHT_GPIO 91
-diff --git a/drivers/video/omap/lcd_ams_delta.c b/drivers/video/omap/lcd_ams_delta.c
-index 3fd5342..4d54725 100644
---- a/drivers/video/omap/lcd_ams_delta.c
-+++ b/drivers/video/omap/lcd_ams_delta.c
-@@ -24,13 +24,13 @@
-
- #include <linux/module.h>
- #include <linux/platform_device.h>
-+#include <linux/omapfb.h>
-
- #include <asm/delay.h>
- #include <asm/io.h>
-
- #include <mach/board-ams-delta.h>
- #include <mach/hardware.h>
--#include <mach/omapfb.h>
-
- #define AMS_DELTA_DEFAULT_CONTRAST 112
-
-diff --git a/drivers/video/omap/lcd_apollon.c b/drivers/video/omap/lcd_apollon.c
-index beae5d9..e3b2224 100644
---- a/drivers/video/omap/lcd_apollon.c
-+++ b/drivers/video/omap/lcd_apollon.c
-@@ -23,10 +23,10 @@
-
- #include <linux/module.h>
- #include <linux/platform_device.h>
-+#include <linux/omapfb.h>
-
- #include <mach/gpio.h>
- #include <mach/mux.h>
--#include <mach/omapfb.h>
-
- /* #define USE_35INCH_LCD 1 */
-
-diff --git a/drivers/video/omap/lcd_h3.c b/drivers/video/omap/lcd_h3.c
-index 2486237..f7264ea 100644
---- a/drivers/video/omap/lcd_h3.c
-+++ b/drivers/video/omap/lcd_h3.c
-@@ -22,9 +22,9 @@
- #include <linux/module.h>
- #include <linux/platform_device.h>
- #include <linux/i2c/tps65010.h>
-+#include <linux/omapfb.h>
-
- #include <mach/gpio.h>
--#include <mach/omapfb.h>
-
- #define MODULE_NAME "omapfb-lcd_h3"
-
-diff --git a/drivers/video/omap/lcd_h4.c b/drivers/video/omap/lcd_h4.c
-index 6ff5643..d72df0c 100644
---- a/drivers/video/omap/lcd_h4.c
-+++ b/drivers/video/omap/lcd_h4.c
-@@ -21,8 +21,7 @@
-
- #include <linux/module.h>
- #include <linux/platform_device.h>
--
--#include <mach/omapfb.h>
-+#include <linux/omapfb.h>
-
- static int h4_panel_init(struct lcd_panel *panel, struct omapfb_device *fbdev)
- {
-diff --git a/drivers/video/omap/lcd_inn1510.c b/drivers/video/omap/lcd_inn1510.c
-index 6953ed4..f6e05d7 100644
---- a/drivers/video/omap/lcd_inn1510.c
-+++ b/drivers/video/omap/lcd_inn1510.c
-@@ -22,9 +22,9 @@
- #include <linux/module.h>
- #include <linux/platform_device.h>
- #include <linux/io.h>
-+#include <linux/omapfb.h>
-
- #include <mach/fpga.h>
--#include <mach/omapfb.h>
-
- static int innovator1510_panel_init(struct lcd_panel *panel,
- struct omapfb_device *fbdev)
-diff --git a/drivers/video/omap/lcd_inn1610.c b/drivers/video/omap/lcd_inn1610.c
-index 4c4f7ee..c599e41 100644
---- a/drivers/video/omap/lcd_inn1610.c
-+++ b/drivers/video/omap/lcd_inn1610.c
-@@ -21,9 +21,9 @@
-
- #include <linux/module.h>
- #include <linux/platform_device.h>
-+#include <linux/omapfb.h>
-
- #include <mach/gpio.h>
--#include <mach/omapfb.h>
-
- #define MODULE_NAME "omapfb-lcd_h3"
-
-diff --git a/drivers/video/omap/lcd_ldp.c b/drivers/video/omap/lcd_ldp.c
-index 8925230..1c25186 100644
---- a/drivers/video/omap/lcd_ldp.c
-+++ b/drivers/video/omap/lcd_ldp.c
-@@ -25,10 +25,10 @@
- #include <linux/platform_device.h>
- #include <linux/delay.h>
- #include <linux/i2c/twl4030.h>
-+#include <linux/omapfb.h>
-
- #include <mach/gpio.h>
- #include <mach/mux.h>
--#include <mach/omapfb.h>
- #include <asm/mach-types.h>
-
- #define LCD_PANEL_BACKLIGHT_GPIO (15 + OMAP_MAX_GPIO_LINES)
-diff --git a/drivers/video/omap/lcd_mipid.c b/drivers/video/omap/lcd_mipid.c
-index 1895997..4b28005 100644
---- a/drivers/video/omap/lcd_mipid.c
-+++ b/drivers/video/omap/lcd_mipid.c
-@@ -22,8 +22,8 @@
- #include <linux/delay.h>
- #include <linux/workqueue.h>
- #include <linux/spi/spi.h>
-+#include <linux/omapfb.h>
-
--#include <mach/omapfb.h>
- #include <mach/lcd_mipid.h>
-
- #include "../../cbus/tahvo.h"
-diff --git a/drivers/video/omap/lcd_omap2evm.c b/drivers/video/omap/lcd_omap2evm.c
-index 2fc46c2..1908a2b 100644
---- a/drivers/video/omap/lcd_omap2evm.c
-+++ b/drivers/video/omap/lcd_omap2evm.c
-@@ -25,9 +25,9 @@
- #include <linux/platform_device.h>
- #include <linux/gpio.h>
- #include <linux/i2c/twl4030.h>
-+#include <linux/omapfb.h>
-
- #include <mach/mux.h>
--#include <mach/omapfb.h>
- #include <asm/mach-types.h>
-
- #define LCD_PANEL_ENABLE_GPIO 154
-diff --git a/drivers/video/omap/lcd_omap3beagle.c b/drivers/video/omap/lcd_omap3beagle.c
-index eae43e4..6be117e 100644
---- a/drivers/video/omap/lcd_omap3beagle.c
-+++ b/drivers/video/omap/lcd_omap3beagle.c
-@@ -24,9 +24,9 @@
- #include <linux/platform_device.h>
- #include <linux/gpio.h>
- #include <linux/i2c/twl4030.h>
-+#include <linux/omapfb.h>
-
- #include <mach/mux.h>
--#include <mach/omapfb.h>
- #include <asm/mach-types.h>
-
- #define LCD_PANEL_ENABLE_GPIO 170
-diff --git a/drivers/video/omap/lcd_omap3evm.c b/drivers/video/omap/lcd_omap3evm.c
-index 1c3d814..10ba48c 100644
---- a/drivers/video/omap/lcd_omap3evm.c
-+++ b/drivers/video/omap/lcd_omap3evm.c
-@@ -24,9 +24,9 @@
- #include <linux/platform_device.h>
- #include <linux/gpio.h>
- #include <linux/i2c/twl4030.h>
-+#include <linux/omapfb.h>
-
- #include <mach/mux.h>
--#include <mach/omapfb.h>
- #include <asm/mach-types.h>
-
- #define LCD_PANEL_ENABLE_GPIO 153
-diff --git a/drivers/video/omap/lcd_osk.c b/drivers/video/omap/lcd_osk.c
-index 379c96d..d6b193e 100644
---- a/drivers/video/omap/lcd_osk.c
-+++ b/drivers/video/omap/lcd_osk.c
-@@ -22,10 +22,10 @@
-
- #include <linux/module.h>
- #include <linux/platform_device.h>
-+#include <linux/omapfb.h>
-
- #include <mach/gpio.h>
- #include <mach/mux.h>
--#include <mach/omapfb.h>
-
- static int osk_panel_init(struct lcd_panel *panel, struct omapfb_device *fbdev)
- {
-diff --git a/drivers/video/omap/lcd_overo.c b/drivers/video/omap/lcd_overo.c
-index 2bc5c92..40c2026 100644
---- a/drivers/video/omap/lcd_overo.c
-+++ b/drivers/video/omap/lcd_overo.c
-@@ -22,10 +22,10 @@
- #include <linux/module.h>
- #include <linux/platform_device.h>
- #include <linux/i2c/twl4030.h>
-+#include <linux/omapfb.h>
-
- #include <mach/gpio.h>
- #include <mach/mux.h>
--#include <mach/omapfb.h>
- #include <asm/mach-types.h>
-
- #define LCD_ENABLE 144
-diff --git a/drivers/video/omap/lcd_p2.c b/drivers/video/omap/lcd_p2.c
-index dd40fd7..bc5abef 100644
---- a/drivers/video/omap/lcd_p2.c
-+++ b/drivers/video/omap/lcd_p2.c
-@@ -24,10 +24,10 @@
- #include <linux/module.h>
- #include <linux/delay.h>
- #include <linux/platform_device.h>
-+#include <linux/omapfb.h>
-
- #include <mach/mux.h>
- #include <mach/gpio.h>
--#include <mach/omapfb.h>
-
- /*
- * File: epson-md-tft.h
-diff --git a/drivers/video/omap/lcd_palmte.c b/drivers/video/omap/lcd_palmte.c
-index 2183173..dcb456c 100644
---- a/drivers/video/omap/lcd_palmte.c
-+++ b/drivers/video/omap/lcd_palmte.c
-@@ -22,9 +22,9 @@
- #include <linux/module.h>
- #include <linux/platform_device.h>
- #include <linux/io.h>
-+#include <linux/omapfb.h>
-
- #include <mach/fpga.h>
--#include <mach/omapfb.h>
-
- static int palmte_panel_init(struct lcd_panel *panel,
- struct omapfb_device *fbdev)
-diff --git a/drivers/video/omap/lcd_palmtt.c b/drivers/video/omap/lcd_palmtt.c
-index 57b0f6c..e8adab8 100644
---- a/drivers/video/omap/lcd_palmtt.c
-+++ b/drivers/video/omap/lcd_palmtt.c
-@@ -28,9 +28,9 @@ GPIO13 - screen blanking
- #include <linux/platform_device.h>
- #include <linux/module.h>
- #include <linux/io.h>
-+#include <linux/omapfb.h>
-
- #include <mach/gpio.h>
--#include <mach/omapfb.h>
-
- static int palmtt_panel_init(struct lcd_panel *panel,
- struct omapfb_device *fbdev)
-diff --git a/drivers/video/omap/lcd_palmz71.c b/drivers/video/omap/lcd_palmz71.c
-index d33d78b..d5b3f82 100644
---- a/drivers/video/omap/lcd_palmz71.c
-+++ b/drivers/video/omap/lcd_palmz71.c
-@@ -23,8 +23,7 @@
- #include <linux/module.h>
- #include <linux/platform_device.h>
- #include <linux/io.h>
--
--#include <mach/omapfb.h>
-+#include <linux/omapfb.h>
-
- static int palmz71_panel_init(struct lcd_panel *panel,
- struct omapfb_device *fbdev)
-diff --git a/drivers/video/omap/lcdc.c b/drivers/video/omap/lcdc.c
-index ab39492..633e33c 100644
---- a/drivers/video/omap/lcdc.c
-+++ b/drivers/video/omap/lcdc.c
-@@ -28,9 +28,9 @@
- #include <linux/dma-mapping.h>
- #include <linux/vmalloc.h>
- #include <linux/clk.h>
-+#include <linux/omapfb.h>
-
- #include <mach/dma.h>
--#include <mach/omapfb.h>
-
- #include <asm/mach-types.h>
-
-diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c
-index 3bb4247..c6306af 100644
---- a/drivers/video/omap/omapfb_main.c
-+++ b/drivers/video/omap/omapfb_main.c
-@@ -27,9 +27,9 @@
- #include <linux/platform_device.h>
- #include <linux/mm.h>
- #include <linux/uaccess.h>
-+#include <linux/omapfb.h>
-
- #include <mach/dma.h>
--#include <mach/omapfb.h>
-
- #include "lcdc.h"
- #include "dispc.h"
-diff --git a/drivers/video/omap/rfbi.c b/drivers/video/omap/rfbi.c
-index 29fa368..118cfa9 100644
---- a/drivers/video/omap/rfbi.c
-+++ b/drivers/video/omap/rfbi.c
-@@ -26,8 +26,7 @@
- #include <linux/interrupt.h>
- #include <linux/clk.h>
- #include <linux/io.h>
--
--#include <mach/omapfb.h>
-+#include <linux/omapfb.h>
-
- #include "dispc.h"
-
-diff --git a/drivers/video/omap/sossi.c b/drivers/video/omap/sossi.c
-index cc697cc..ff9dd71 100644
---- a/drivers/video/omap/sossi.c
-+++ b/drivers/video/omap/sossi.c
-@@ -23,9 +23,9 @@
- #include <linux/clk.h>
- #include <linux/irq.h>
- #include <linux/io.h>
-+#include <linux/omapfb.h>
-
- #include <mach/dma.h>
--#include <mach/omapfb.h>
-
- #include "lcdc.h"
-
-diff --git a/include/linux/omapfb.h b/include/linux/omapfb.h
-new file mode 100644
-index 0000000..b226bdf
---- /dev/null
-+++ b/include/linux/omapfb.h
-@@ -0,0 +1,398 @@
-+/*
-+ * File: arch/arm/plat-omap/include/mach/omapfb.h
-+ *
-+ * Framebuffer driver for TI OMAP boards
-+ *
-+ * Copyright (C) 2004 Nokia Corporation
-+ * Author: Imre Deak <imre.deak@nokia.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-+ */
-+
-+#ifndef __OMAPFB_H
-+#define __OMAPFB_H
-+
-+#include <asm/ioctl.h>
-+#include <asm/types.h>
-+
-+/* IOCTL commands. */
-+
-+#define OMAP_IOW(num, dtype) _IOW('O', num, dtype)
-+#define OMAP_IOR(num, dtype) _IOR('O', num, dtype)
-+#define OMAP_IOWR(num, dtype) _IOWR('O', num, dtype)
-+#define OMAP_IO(num) _IO('O', num)
-+
-+#define OMAPFB_MIRROR OMAP_IOW(31, int)
-+#define OMAPFB_SYNC_GFX OMAP_IO(37)
-+#define OMAPFB_VSYNC OMAP_IO(38)
-+#define OMAPFB_SET_UPDATE_MODE OMAP_IOW(40, int)
-+#define OMAPFB_GET_CAPS OMAP_IOR(42, struct omapfb_caps)
-+#define OMAPFB_GET_UPDATE_MODE OMAP_IOW(43, int)
-+#define OMAPFB_LCD_TEST OMAP_IOW(45, int)
-+#define OMAPFB_CTRL_TEST OMAP_IOW(46, int)
-+#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old)
-+#define OMAPFB_SET_COLOR_KEY OMAP_IOW(50, struct omapfb_color_key)
-+#define OMAPFB_GET_COLOR_KEY OMAP_IOW(51, struct omapfb_color_key)
-+#define OMAPFB_SETUP_PLANE OMAP_IOW(52, struct omapfb_plane_info)
-+#define OMAPFB_QUERY_PLANE OMAP_IOW(53, struct omapfb_plane_info)
-+#define OMAPFB_UPDATE_WINDOW OMAP_IOW(54, struct omapfb_update_window)
-+#define OMAPFB_SETUP_MEM OMAP_IOW(55, struct omapfb_mem_info)
-+#define OMAPFB_QUERY_MEM OMAP_IOW(56, struct omapfb_mem_info)
-+
-+#define OMAPFB_CAPS_GENERIC_MASK 0x00000fff
-+#define OMAPFB_CAPS_LCDC_MASK 0x00fff000
-+#define OMAPFB_CAPS_PANEL_MASK 0xff000000
-+
-+#define OMAPFB_CAPS_MANUAL_UPDATE 0x00001000
-+#define OMAPFB_CAPS_TEARSYNC 0x00002000
-+#define OMAPFB_CAPS_PLANE_RELOCATE_MEM 0x00004000
-+#define OMAPFB_CAPS_PLANE_SCALE 0x00008000
-+#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000
-+#define OMAPFB_CAPS_WINDOW_SCALE 0x00020000
-+#define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000
-+#define OMAPFB_CAPS_WINDOW_ROTATE 0x00080000
-+#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000
-+
-+/* Values from DSP must map to lower 16-bits */
-+#define OMAPFB_FORMAT_MASK 0x00ff
-+#define OMAPFB_FORMAT_FLAG_DOUBLE 0x0100
-+#define OMAPFB_FORMAT_FLAG_TEARSYNC 0x0200
-+#define OMAPFB_FORMAT_FLAG_FORCE_VSYNC 0x0400
-+#define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY 0x0800
-+#define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY 0x1000
-+
-+#define OMAPFB_EVENT_READY 1
-+#define OMAPFB_EVENT_DISABLED 2
-+
-+#define OMAPFB_MEMTYPE_SDRAM 0
-+#define OMAPFB_MEMTYPE_SRAM 1
-+#define OMAPFB_MEMTYPE_MAX 1
-+
-+enum omapfb_color_format {
-+ OMAPFB_COLOR_RGB565 = 0,
-+ OMAPFB_COLOR_YUV422,
-+ OMAPFB_COLOR_YUV420,
-+ OMAPFB_COLOR_CLUT_8BPP,
-+ OMAPFB_COLOR_CLUT_4BPP,
-+ OMAPFB_COLOR_CLUT_2BPP,
-+ OMAPFB_COLOR_CLUT_1BPP,
-+ OMAPFB_COLOR_RGB444,
-+ OMAPFB_COLOR_YUY422,
-+};
-+
-+struct omapfb_update_window {
-+ __u32 x, y;
-+ __u32 width, height;
-+ __u32 format;
-+ __u32 out_x, out_y;
-+ __u32 out_width, out_height;
-+ __u32 reserved[8];
-+};
-+
-+struct omapfb_update_window_old {
-+ __u32 x, y;
-+ __u32 width, height;
-+ __u32 format;
-+};
-+
-+enum omapfb_plane {
-+ OMAPFB_PLANE_GFX = 0,
-+ OMAPFB_PLANE_VID1,
-+ OMAPFB_PLANE_VID2,
-+};
-+
-+enum omapfb_channel_out {
-+ OMAPFB_CHANNEL_OUT_LCD = 0,
-+ OMAPFB_CHANNEL_OUT_DIGIT,
-+};
-+
-+struct omapfb_plane_info {
-+ __u32 pos_x;
-+ __u32 pos_y;
-+ __u8 enabled;
-+ __u8 channel_out;
-+ __u8 mirror;
-+ __u8 reserved1;
-+ __u32 out_width;
-+ __u32 out_height;
-+ __u32 reserved2[12];
-+};
-+
-+struct omapfb_mem_info {
-+ __u32 size;
-+ __u8 type;
-+ __u8 reserved[3];
-+};
-+
-+struct omapfb_caps {
-+ __u32 ctrl;
-+ __u32 plane_color;
-+ __u32 wnd_color;
-+};
-+
-+enum omapfb_color_key_type {
-+ OMAPFB_COLOR_KEY_DISABLED = 0,
-+ OMAPFB_COLOR_KEY_GFX_DST,
-+ OMAPFB_COLOR_KEY_VID_SRC,
-+};
-+
-+struct omapfb_color_key {
-+ __u8 channel_out;
-+ __u32 background;
-+ __u32 trans_key;
-+ __u8 key_type;
-+};
-+
-+enum omapfb_update_mode {
-+ OMAPFB_UPDATE_DISABLED = 0,
-+ OMAPFB_AUTO_UPDATE,
-+ OMAPFB_MANUAL_UPDATE
-+};
-+
-+#ifdef __KERNEL__
-+
-+#include <linux/completion.h>
-+#include <linux/interrupt.h>
-+#include <linux/fb.h>
-+#include <linux/mutex.h>
-+
-+#include <mach/board.h>
-+
-+#define OMAP_LCDC_INV_VSYNC 0x0001
-+#define OMAP_LCDC_INV_HSYNC 0x0002
-+#define OMAP_LCDC_INV_PIX_CLOCK 0x0004
-+#define OMAP_LCDC_INV_OUTPUT_EN 0x0008
-+#define OMAP_LCDC_HSVS_RISING_EDGE 0x0010
-+#define OMAP_LCDC_HSVS_OPPOSITE 0x0020
-+
-+#define OMAP_LCDC_SIGNAL_MASK 0x003f
-+
-+#define OMAP_LCDC_PANEL_TFT 0x0100
-+
-+#define OMAPFB_PLANE_XRES_MIN 8
-+#define OMAPFB_PLANE_YRES_MIN 8
-+
-+#ifdef CONFIG_ARCH_OMAP1
-+#define OMAPFB_PLANE_NUM 1
-+#else
-+#define OMAPFB_PLANE_NUM 3
-+#endif
-+
-+struct omapfb_device;
-+
-+struct lcd_panel {
-+ const char *name;
-+ int config; /* TFT/STN, signal inversion */
-+ int bpp; /* Pixel format in fb mem */
-+ int data_lines; /* Lines on LCD HW interface */
-+
-+ int x_res, y_res;
-+ int pixel_clock; /* In kHz */
-+ int hsw; /* Horizontal synchronization
-+ pulse width */
-+ int hfp; /* Horizontal front porch */
-+ int hbp; /* Horizontal back porch */
-+ int vsw; /* Vertical synchronization
-+ pulse width */
-+ int vfp; /* Vertical front porch */
-+ int vbp; /* Vertical back porch */
-+ int acb; /* ac-bias pin frequency */
-+ int pcd; /* pixel clock divider.
-+ Obsolete use pixel_clock instead */
-+
-+ int (*init) (struct lcd_panel *panel,
-+ struct omapfb_device *fbdev);
-+ void (*cleanup) (struct lcd_panel *panel);
-+ int (*enable) (struct lcd_panel *panel);
-+ void (*disable) (struct lcd_panel *panel);
-+ unsigned long (*get_caps) (struct lcd_panel *panel);
-+ int (*set_bklight_level)(struct lcd_panel *panel,
-+ unsigned int level);
-+ unsigned int (*get_bklight_level)(struct lcd_panel *panel);
-+ unsigned int (*get_bklight_max) (struct lcd_panel *panel);
-+ int (*run_test) (struct lcd_panel *panel, int test_num);
-+};
-+
-+struct extif_timings {
-+ int cs_on_time;
-+ int cs_off_time;
-+ int we_on_time;
-+ int we_off_time;
-+ int re_on_time;
-+ int re_off_time;
-+ int we_cycle_time;
-+ int re_cycle_time;
-+ int cs_pulse_width;
-+ int access_time;
-+
-+ int clk_div;
-+
-+ u32 tim[5]; /* set by extif->convert_timings */
-+
-+ int converted;
-+};
-+
-+struct lcd_ctrl_extif {
-+ int (*init) (struct omapfb_device *fbdev);
-+ void (*cleanup) (void);
-+ void (*get_clk_info) (u32 *clk_period, u32 *max_clk_div);
-+ unsigned long (*get_max_tx_rate)(void);
-+ int (*convert_timings) (struct extif_timings *timings);
-+ void (*set_timings) (const struct extif_timings *timings);
-+ void (*set_bits_per_cycle)(int bpc);
-+ void (*write_command) (const void *buf, unsigned int len);
-+ void (*read_data) (void *buf, unsigned int len);
-+ void (*write_data) (const void *buf, unsigned int len);
-+ void (*transfer_area) (int width, int height,
-+ void (callback)(void * data), void *data);
-+ int (*setup_tearsync) (unsigned pin_cnt,
-+ unsigned hs_pulse_time, unsigned vs_pulse_time,
-+ int hs_pol_inv, int vs_pol_inv, int div);
-+ int (*enable_tearsync) (int enable, unsigned line);
-+
-+ unsigned long max_transmit_size;
-+};
-+
-+struct omapfb_notifier_block {
-+ struct notifier_block nb;
-+ void *data;
-+ int plane_idx;
-+};
-+
-+typedef int (*omapfb_notifier_callback_t)(struct notifier_block *,
-+ unsigned long event,
-+ void *fbi);
-+
-+struct omapfb_mem_region {
-+ u32 paddr;
-+ void __iomem *vaddr;
-+ unsigned long size;
-+ u8 type; /* OMAPFB_PLANE_MEM_* */
-+ unsigned alloc:1; /* allocated by the driver */
-+ unsigned map:1; /* kernel mapped by the driver */
-+};
-+
-+struct omapfb_mem_desc {
-+ int region_cnt;
-+ struct omapfb_mem_region region[OMAPFB_PLANE_NUM];
-+};
-+
-+struct lcd_ctrl {
-+ const char *name;
-+ void *data;
-+
-+ int (*init) (struct omapfb_device *fbdev,
-+ int ext_mode,
-+ struct omapfb_mem_desc *req_md);
-+ void (*cleanup) (void);
-+ void (*bind_client) (struct omapfb_notifier_block *nb);
-+ void (*get_caps) (int plane, struct omapfb_caps *caps);
-+ int (*set_update_mode)(enum omapfb_update_mode mode);
-+ enum omapfb_update_mode (*get_update_mode)(void);
-+ int (*setup_plane) (int plane, int channel_out,
-+ unsigned long offset,
-+ int screen_width,
-+ int pos_x, int pos_y, int width,
-+ int height, int color_mode);
-+ int (*set_rotate) (int angle);
-+ int (*setup_mem) (int plane, size_t size,
-+ int mem_type, unsigned long *paddr);
-+ int (*mmap) (struct fb_info *info,
-+ struct vm_area_struct *vma);
-+ int (*set_scale) (int plane,
-+ int orig_width, int orig_height,
-+ int out_width, int out_height);
-+ int (*enable_plane) (int plane, int enable);
-+ int (*update_window) (struct fb_info *fbi,
-+ struct omapfb_update_window *win,
-+ void (*callback)(void *),
-+ void *callback_data);
-+ void (*sync) (void);
-+ void (*suspend) (void);
-+ void (*resume) (void);
-+ int (*run_test) (int test_num);
-+ int (*setcolreg) (u_int regno, u16 red, u16 green,
-+ u16 blue, u16 transp,
-+ int update_hw_mem);
-+ int (*set_color_key) (struct omapfb_color_key *ck);
-+ int (*get_color_key) (struct omapfb_color_key *ck);
-+};
-+
-+enum omapfb_state {
-+ OMAPFB_DISABLED = 0,
-+ OMAPFB_SUSPENDED= 99,
-+ OMAPFB_ACTIVE = 100
-+};
-+
-+struct omapfb_plane_struct {
-+ int idx;
-+ struct omapfb_plane_info info;
-+ enum omapfb_color_format color_mode;
-+ struct omapfb_device *fbdev;
-+};
-+
-+struct omapfb_device {
-+ int state;
-+ int ext_lcdc; /* Using external
-+ LCD controller */
-+ struct mutex rqueue_mutex;
-+
-+ int palette_size;
-+ u32 pseudo_palette[17];
-+
-+ struct lcd_panel *panel; /* LCD panel */
-+ const struct lcd_ctrl *ctrl; /* LCD controller */
-+ const struct lcd_ctrl *int_ctrl; /* internal LCD ctrl */
-+ struct lcd_ctrl_extif *ext_if; /* LCD ctrl external
-+ interface */
-+ struct device *dev;
-+ struct fb_var_screeninfo new_var; /* for mode changes */
-+
-+ struct omapfb_mem_desc mem_desc;
-+ struct fb_info *fb_info[OMAPFB_PLANE_NUM];
-+};
-+
-+struct omapfb_platform_data {
-+ struct omap_lcd_config lcd;
-+ struct omapfb_mem_desc mem_desc;
-+ void *ctrl_platform_data;
-+};
-+
-+#ifdef CONFIG_ARCH_OMAP1
-+extern struct lcd_ctrl omap1_lcd_ctrl;
-+#else
-+extern struct lcd_ctrl omap2_disp_ctrl;
-+#endif
-+
-+extern void omapfb_reserve_sdram(void);
-+extern void omapfb_register_panel(struct lcd_panel *panel);
-+extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
-+extern void omapfb_notify_clients(struct omapfb_device *fbdev,
-+ unsigned long event);
-+extern int omapfb_register_client(struct omapfb_notifier_block *nb,
-+ omapfb_notifier_callback_t callback,
-+ void *callback_data);
-+extern int omapfb_unregister_client(struct omapfb_notifier_block *nb);
-+extern int omapfb_update_window_async(struct fb_info *fbi,
-+ struct omapfb_update_window *win,
-+ void (*callback)(void *),
-+ void *callback_data);
-+
-+/* in arch/arm/plat-omap/fb.c */
-+extern void omapfb_set_ctrl_platform_data(void *pdata);
-+
-+#endif /* __KERNEL__ */
-+
-+#endif /* __OMAPFB_H */
---
-1.5.6.5
-
+++ /dev/null
-From 284deec412f9c6f15c971d8eaf4d0156a51a2f3b Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Thu, 2 Apr 2009 10:23:42 +0300
-Subject: [PATCH 03/69] DSS2: OMAP2/3 Display Subsystem driver
-
-Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
----
- Documentation/arm/OMAP/DSS | 311 +++
- arch/arm/plat-omap/Makefile | 2 +-
- arch/arm/plat-omap/include/mach/display.h | 520 ++++
- arch/arm/plat-omap/include/mach/vram.h | 33 +
- arch/arm/plat-omap/include/mach/vrfb.h | 47 +
- arch/arm/plat-omap/vram.c | 615 +++++
- arch/arm/plat-omap/vrfb.c | 159 ++
- drivers/video/Kconfig | 1 +
- drivers/video/Makefile | 1 +
- drivers/video/omap2/Kconfig | 3 +
- drivers/video/omap2/Makefile | 4 +
- drivers/video/omap2/dss/Kconfig | 89 +
- drivers/video/omap2/dss/Makefile | 6 +
- drivers/video/omap2/dss/core.c | 641 +++++
- drivers/video/omap2/dss/dispc.c | 2968 +++++++++++++++++++++++
- drivers/video/omap2/dss/display.c | 693 ++++++
- drivers/video/omap2/dss/dpi.c | 393 +++
- drivers/video/omap2/dss/dsi.c | 3752 +++++++++++++++++++++++++++++
- drivers/video/omap2/dss/dss.c | 345 +++
- drivers/video/omap2/dss/dss.h | 331 +++
- drivers/video/omap2/dss/manager.c | 576 +++++
- drivers/video/omap2/dss/overlay.c | 587 +++++
- drivers/video/omap2/dss/rfbi.c | 1304 ++++++++++
- drivers/video/omap2/dss/sdi.c | 245 ++
- drivers/video/omap2/dss/venc.c | 600 +++++
- 25 files changed, 14225 insertions(+), 1 deletions(-)
- create mode 100644 Documentation/arm/OMAP/DSS
- create mode 100644 arch/arm/plat-omap/include/mach/display.h
- create mode 100644 arch/arm/plat-omap/include/mach/vram.h
- create mode 100644 arch/arm/plat-omap/include/mach/vrfb.h
- create mode 100644 arch/arm/plat-omap/vram.c
- create mode 100644 arch/arm/plat-omap/vrfb.c
- create mode 100644 drivers/video/omap2/Kconfig
- create mode 100644 drivers/video/omap2/Makefile
- create mode 100644 drivers/video/omap2/dss/Kconfig
- create mode 100644 drivers/video/omap2/dss/Makefile
- create mode 100644 drivers/video/omap2/dss/core.c
- create mode 100644 drivers/video/omap2/dss/dispc.c
- create mode 100644 drivers/video/omap2/dss/display.c
- create mode 100644 drivers/video/omap2/dss/dpi.c
- create mode 100644 drivers/video/omap2/dss/dsi.c
- create mode 100644 drivers/video/omap2/dss/dss.c
- create mode 100644 drivers/video/omap2/dss/dss.h
- create mode 100644 drivers/video/omap2/dss/manager.c
- create mode 100644 drivers/video/omap2/dss/overlay.c
- create mode 100644 drivers/video/omap2/dss/rfbi.c
- create mode 100644 drivers/video/omap2/dss/sdi.c
- create mode 100644 drivers/video/omap2/dss/venc.c
-
-diff --git a/Documentation/arm/OMAP/DSS b/Documentation/arm/OMAP/DSS
-new file mode 100644
-index 0000000..9e902a2
---- /dev/null
-+++ b/Documentation/arm/OMAP/DSS
-@@ -0,0 +1,311 @@
-+OMAP2/3 Display Subsystem
-+-------------------------
-+
-+This is an almost total rewrite of the OMAP FB driver in drivers/video/omap
-+(let's call it DSS1). The main differences between DSS1 and DSS2 are DSI,
-+TV-out and multiple display support, but there are lots of small improvements
-+also.
-+
-+The DSS2 driver (omapdss module) is in arch/arm/plat-omap/dss/, and the FB,
-+panel and controller drivers are in drivers/video/omap2/. DSS1 and DSS2 live
-+currently side by side, you can choose which one to use.
-+
-+Features
-+--------
-+
-+Working and tested features include:
-+
-+- MIPI DPI (parallel) output
-+- MIPI DSI output in command mode
-+- MIPI DBI (RFBI) output
-+- SDI output
-+- TV output
-+- All pieces can be compiled as a module or inside kernel
-+- Use DISPC to update any of the outputs
-+- Use CPU to update RFBI or DSI output
-+- OMAP DISPC planes
-+- RGB16, RGB24 packed, RGB24 unpacked
-+- YUV2, UYVY
-+- Scaling
-+- Adjusting DSS FCK to find a good pixel clock
-+- Use DSI DPLL to create DSS FCK
-+
-+Tested boards include:
-+- OMAP3 SDP board
-+- Beagle board
-+- N810
-+
-+omapdss driver
-+--------------
-+
-+The DSS driver does not itself have any support for Linux framebuffer, V4L or
-+such like the current ones, but it has an internal kernel API that upper level
-+drivers can use.
-+
-+The DSS driver models OMAP's overlays, overlay managers and displays in a
-+flexible way to enable non-common multi-display configuration. In addition to
-+modelling the hardware overlays, omapdss supports virtual overlays and overlay
-+managers. These can be used when updating a display with CPU or system DMA.
-+
-+Panel and controller drivers
-+----------------------------
-+
-+The drivers implement panel or controller specific functionality and are not
-+usually visible to users except through omapfb driver. They register
-+themselves to the DSS driver.
-+
-+omapfb driver
-+-------------
-+
-+The omapfb driver implements arbitrary number of standard linux framebuffers.
-+These framebuffers can be routed flexibly to any overlays, thus allowing very
-+dynamic display architecture.
-+
-+The driver exports some omapfb specific ioctls, which are compatible with the
-+ioctls in the old driver.
-+
-+The rest of the non standard features are exported via sysfs. Whether the final
-+implementation will use sysfs, or ioctls, is still open.
-+
-+V4L2 drivers
-+------------
-+
-+V4L2 is being implemented in TI.
-+
-+From omapdss point of view the V4L2 drivers should be similar to framebuffer
-+driver.
-+
-+Architecture
-+--------------------
-+
-+Some clarification what the different components do:
-+
-+ - Framebuffer is a memory area inside OMAP's SRAM/SDRAM that contains the
-+ pixel data for the image. Framebuffer has width and height and color
-+ depth.
-+ - Overlay defines where the pixels are read from and where they go on the
-+ screen. The overlay may be smaller than framebuffer, thus displaying only
-+ part of the framebuffer. The position of the overlay may be changed if
-+ the overlay is smaller than the display.
-+ - Overlay manager combines the overlays in to one image and feeds them to
-+ display.
-+ - Display is the actual physical display device.
-+
-+A framebuffer can be connected to multiple overlays to show the same pixel data
-+on all of the overlays. Note that in this case the overlay input sizes must be
-+the same, but, in case of video overlays, the output size can be different. Any
-+framebuffer can be connected to any overlay.
-+
-+An overlay can be connected to one overlay manager. Also DISPC overlays can be
-+connected only to DISPC overlay managers, and virtual overlays can be only
-+connected to virtual overlays.
-+
-+An overlay manager can be connected to one display. There are certain
-+restrictions which kinds of displays an overlay manager can be connected:
-+
-+ - DISPC TV overlay manager can be only connected to TV display.
-+ - Virtual overlay managers can only be connected to DBI or DSI displays.
-+ - DISPC LCD overlay manager can be connected to all displays, except TV
-+ display.
-+
-+Sysfs
-+-----
-+The sysfs interface is mainly used for testing. I don't think sysfs
-+interface is the best for this in the final version, but I don't quite know
-+what would be the best interfaces for these things.
-+
-+The sysfs interface is divided to two parts: DSS and FB.
-+
-+/sys/class/graphics/fb? directory:
-+mirror 0=off, 1=on
-+rotate Rotation 0-3 for 0, 90, 180, 270 degrees
-+rotate_type 0 = DMA rotation, 1 = VRFB rotation
-+overlays List of overlay numbers to which framebuffer pixels go
-+phys_addr Physical address of the framebuffer
-+virt_addr Virtual address of the framebuffer
-+size Size of the framebuffer
-+
-+/sys/devices/platform/omapdss/overlay? directory:
-+enabled 0=off, 1=on
-+input_size width,height (ie. the framebuffer size)
-+manager Destination overlay manager name
-+name
-+output_size width,height
-+position x,y
-+screen_width width
-+
-+/sys/devices/platform/omapdss/manager? directory:
-+display Destination display
-+name
-+
-+/sys/devices/platform/omapdss/display? directory:
-+ctrl_name Controller name
-+mirror 0=off, 1=on
-+update_mode 0=off, 1=auto, 2=manual
-+enabled 0=off, 1=on
-+name
-+rotate Rotation 0-3 for 0, 90, 180, 270 degrees
-+timings Display timings (pixclock,xres/hfp/hbp/hsw,yres/vfp/vbp/vsw)
-+ When writing, two special timings are accepted for tv-out:
-+ "pal" and "ntsc"
-+panel_name
-+tear_elim Tearing elimination 0=off, 1=on
-+
-+There are also some debugfs files at <debugfs>/omapdss/ which show information
-+about clocks and registers.
-+
-+Examples
-+--------
-+
-+The following definitions have been made for the examples below:
-+
-+ovl0=/sys/devices/platform/omapdss/overlay0
-+ovl1=/sys/devices/platform/omapdss/overlay1
-+ovl2=/sys/devices/platform/omapdss/overlay2
-+
-+mgr0=/sys/devices/platform/omapdss/manager0
-+mgr1=/sys/devices/platform/omapdss/manager1
-+
-+lcd=/sys/devices/platform/omapdss/display0
-+dvi=/sys/devices/platform/omapdss/display1
-+tv=/sys/devices/platform/omapdss/display2
-+
-+fb0=/sys/class/graphics/fb0
-+fb1=/sys/class/graphics/fb1
-+fb2=/sys/class/graphics/fb2
-+
-+Default setup on OMAP3 SDP
-+--------------------------
-+
-+Here's the default setup on OMAP3 SDP board. All planes go to LCD. DVI
-+and TV-out are not in use. The columns from left to right are:
-+framebuffers, overlays, overlay managers, displays. Framebuffers are
-+handled by omapfb, and the rest by the DSS.
-+
-+FB0 --- GFX -\ DVI
-+FB1 --- VID1 --+- LCD ---- LCD
-+FB2 --- VID2 -/ TV ----- TV
-+
-+Example: Switch from LCD to DVI
-+----------------------
-+
-+w=`cat $dvi/horizontal | cut -d "," -f 1`
-+h=`cat $dvi/vertical | cut -d "," -f 1`
-+
-+echo "0" > $lcd/enabled
-+echo "" > $mgr0/display
-+fbset -fb /dev/fb0 -xres $w -yres $h -vxres $w -vyres $h
-+# at this point you have to switch the dvi/lcd dip-switch from the omap board
-+echo "dvi" > $mgr0/display
-+echo "1" > $dvi/enabled
-+
-+After this the configuration looks like:
-+
-+FB0 --- GFX -\ -- DVI
-+FB1 --- VID1 --+- LCD -/ LCD
-+FB2 --- VID2 -/ TV ----- TV
-+
-+Example: Clone GFX overlay to LCD and TV
-+-------------------------------
-+
-+w=`cat $tv/horizontal | cut -d "," -f 1`
-+h=`cat $tv/vertical | cut -d "," -f 1`
-+
-+echo "0" > $ovl0/enabled
-+echo "0" > $ovl1/enabled
-+
-+echo "" > $fb1/overlays
-+echo "0,1" > $fb0/overlays
-+
-+echo "$w,$h" > $ovl1/output_size
-+echo "tv" > $ovl1/manager
-+
-+echo "1" > $ovl0/enabled
-+echo "1" > $ovl1/enabled
-+
-+echo "1" > $tv/enabled
-+
-+After this the configuration looks like (only relevant parts shown):
-+
-+FB0 +-- GFX ---- LCD ---- LCD
-+ \- VID1 ---- TV ---- TV
-+
-+Misc notes
-+----------
-+
-+OMAP FB allocates the framebuffer memory using the OMAP VRAM allocator.
-+
-+Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
-+of 86.5MHz (max possible), and with that you get 1280x1024@57 output from DVI.
-+
-+Rotation and mirroring currently only supports RGB565 and RGB8888 modes. VRFB
-+does not support mirroring.
-+
-+VRFB rotation requires much more memory than non-rotated framebuffer, so you
-+probably need to increase your vram setting before using VRFB rotation. Also,
-+many applications may not work with VRFB if they do not pay attention to all
-+framebuffer parameters.
-+
-+Kernel boot arguments
-+---------------------
-+
-+vram=<size>
-+ - Amount of total VRAM to preallocate. For example, "10M". omapfb
-+ allocates memory for framebuffers from VRAM.
-+
-+omapfb.mode=<display>:<mode>[,...]
-+ - Default video mode for specified displays. For example,
-+ "dvi:800x400MR-24@60". See drivers/video/modedb.c.
-+ There are also two special modes: "pal" and "ntsc" that
-+ can be used to tv out.
-+
-+omapfb.vram=<fbnum>:<size>[@<physaddr>][,...]
-+ - VRAM allocated for a framebuffer. Normally omapfb allocates vram
-+ depending on the display size. With this you can manually allocate
-+ more or define the physical address of each framebuffer. For example,
-+ "1:4M" to allocate 4M for fb1.
-+
-+omapfb.debug=<y|n>
-+ - Enable debug printing. You have to have OMAPFB debug support enabled
-+ in kernel config.
-+
-+omapfb.test=<y|n>
-+ - Draw test pattern to framebuffer whenever framebuffer settings change.
-+ You need to have OMAPFB debug support enabled in kernel config.
-+
-+omapfb.vrfb=<y|n>
-+ - Use VRFB rotation for all framebuffers.
-+
-+omapfb.rotate=<angle>
-+ - Default rotation applied to all framebuffers.
-+ 0 - 0 degree rotation
-+ 1 - 90 degree rotation
-+ 2 - 180 degree rotation
-+ 3 - 270 degree rotation
-+
-+omapfb.mirror=<y|n>
-+ - Default mirror for all framebuffers. Only works with DMA rotation.
-+
-+omapdss.def_disp=<display>
-+ - Name of default display, to which all overlays will be connected.
-+ Common examples are "lcd" or "tv".
-+
-+omapdss.debug=<y|n>
-+ - Enable debug printing. You have to have DSS debug support enabled in
-+ kernel config.
-+
-+TODO
-+----
-+
-+DSS locking
-+
-+Error checking
-+- Lots of checks are missing or implemented just as BUG()
-+
-+System DMA update for DSI
-+- Can be used for RGB16 and RGB24P modes. Probably not for RGB24U (how
-+ to skip the empty byte?)
-+
-+OMAP1 support
-+- Not sure if needed
-+
-diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
-index 3ebc09e..e6146b2 100644
---- a/arch/arm/plat-omap/Makefile
-+++ b/arch/arm/plat-omap/Makefile
-@@ -4,7 +4,7 @@
-
- # Common support
- obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \
-- usb.o fb.o io.o
-+ usb.o fb.o vram.o vrfb.o io.o
- obj-m :=
- obj-n :=
- obj- :=
-diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
-new file mode 100644
-index 0000000..6288353
---- /dev/null
-+++ b/arch/arm/plat-omap/include/mach/display.h
-@@ -0,0 +1,520 @@
-+/*
-+ * linux/include/asm-arm/arch-omap/display.h
-+ *
-+ * Copyright (C) 2008 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#ifndef __ASM_ARCH_OMAP_DISPLAY_H
-+#define __ASM_ARCH_OMAP_DISPLAY_H
-+
-+#include <linux/list.h>
-+#include <linux/kobject.h>
-+#include <asm/atomic.h>
-+
-+#define DISPC_IRQ_FRAMEDONE (1 << 0)
-+#define DISPC_IRQ_VSYNC (1 << 1)
-+#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
-+#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
-+#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
-+#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
-+#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
-+#define DISPC_IRQ_GFX_END_WIN (1 << 7)
-+#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
-+#define DISPC_IRQ_OCP_ERR (1 << 9)
-+#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
-+#define DISPC_IRQ_VID1_END_WIN (1 << 11)
-+#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
-+#define DISPC_IRQ_VID2_END_WIN (1 << 13)
-+#define DISPC_IRQ_SYNC_LOST (1 << 14)
-+#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
-+#define DISPC_IRQ_WAKEUP (1 << 16)
-+
-+enum omap_display_type {
-+ OMAP_DISPLAY_TYPE_NONE = 0,
-+ OMAP_DISPLAY_TYPE_DPI = 1 << 0,
-+ OMAP_DISPLAY_TYPE_DBI = 1 << 1,
-+ OMAP_DISPLAY_TYPE_SDI = 1 << 2,
-+ OMAP_DISPLAY_TYPE_DSI = 1 << 3,
-+ OMAP_DISPLAY_TYPE_VENC = 1 << 4,
-+};
-+
-+enum omap_plane {
-+ OMAP_DSS_GFX = 0,
-+ OMAP_DSS_VIDEO1 = 1,
-+ OMAP_DSS_VIDEO2 = 2
-+};
-+
-+enum omap_channel {
-+ OMAP_DSS_CHANNEL_LCD = 0,
-+ OMAP_DSS_CHANNEL_DIGIT = 1,
-+};
-+
-+enum omap_color_mode {
-+ OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
-+ OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
-+ OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
-+ OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
-+ OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
-+ OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
-+ OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
-+ OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
-+ OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
-+ OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
-+ OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
-+ OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
-+ OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
-+ OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
-+
-+ OMAP_DSS_COLOR_GFX_OMAP3 =
-+ OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
-+ OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
-+ OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
-+ OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
-+ OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
-+ OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
-+
-+ OMAP_DSS_COLOR_VID_OMAP3 =
-+ OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
-+ OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
-+ OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
-+ OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
-+ OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
-+};
-+
-+enum omap_lcd_display_type {
-+ OMAP_DSS_LCD_DISPLAY_STN,
-+ OMAP_DSS_LCD_DISPLAY_TFT,
-+};
-+
-+enum omap_dss_load_mode {
-+ OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
-+ OMAP_DSS_LOAD_CLUT_ONLY = 1,
-+ OMAP_DSS_LOAD_FRAME_ONLY = 2,
-+ OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
-+};
-+
-+enum omap_dss_color_key_type {
-+ OMAP_DSS_COLOR_KEY_GFX_DST = 0,
-+ OMAP_DSS_COLOR_KEY_VID_SRC = 1,
-+};
-+
-+enum omap_rfbi_te_mode {
-+ OMAP_DSS_RFBI_TE_MODE_1 = 1,
-+ OMAP_DSS_RFBI_TE_MODE_2 = 2,
-+};
-+
-+enum omap_panel_config {
-+ OMAP_DSS_LCD_IVS = 1<<0,
-+ OMAP_DSS_LCD_IHS = 1<<1,
-+ OMAP_DSS_LCD_IPC = 1<<2,
-+ OMAP_DSS_LCD_IEO = 1<<3,
-+ OMAP_DSS_LCD_RF = 1<<4,
-+ OMAP_DSS_LCD_ONOFF = 1<<5,
-+
-+ OMAP_DSS_LCD_TFT = 1<<20,
-+};
-+
-+enum omap_dss_venc_type {
-+ OMAP_DSS_VENC_TYPE_COMPOSITE,
-+ OMAP_DSS_VENC_TYPE_SVIDEO,
-+};
-+
-+struct omap_display;
-+struct omap_panel;
-+struct omap_ctrl;
-+
-+/* RFBI */
-+
-+struct rfbi_timings {
-+ int cs_on_time;
-+ int cs_off_time;
-+ int we_on_time;
-+ int we_off_time;
-+ int re_on_time;
-+ int re_off_time;
-+ int we_cycle_time;
-+ int re_cycle_time;
-+ int cs_pulse_width;
-+ int access_time;
-+
-+ int clk_div;
-+
-+ u32 tim[5]; /* set by rfbi_convert_timings() */
-+
-+ int converted;
-+};
-+
-+void omap_rfbi_write_command(const void *buf, u32 len);
-+void omap_rfbi_read_data(void *buf, u32 len);
-+void omap_rfbi_write_data(const void *buf, u32 len);
-+void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
-+ u16 x, u16 y,
-+ u16 w, u16 h);
-+int omap_rfbi_enable_te(bool enable, unsigned line);
-+int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
-+ unsigned hs_pulse_time, unsigned vs_pulse_time,
-+ int hs_pol_inv, int vs_pol_inv, int extif_div);
-+
-+/* DSI */
-+int dsi_vc_dcs_write(int channel, u8 *data, int len);
-+int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
-+int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
-+int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
-+int dsi_vc_send_null(int channel);
-+
-+/* Board specific data */
-+struct omap_dss_display_config {
-+ enum omap_display_type type;
-+
-+ union {
-+ struct {
-+ u8 data_lines;
-+ } dpi;
-+
-+ struct {
-+ u8 channel;
-+ u8 data_lines;
-+ } rfbi;
-+
-+ struct {
-+ u8 datapairs;
-+ } sdi;
-+
-+ struct {
-+ u8 clk_lane;
-+ u8 clk_pol;
-+ u8 data1_lane;
-+ u8 data1_pol;
-+ u8 data2_lane;
-+ u8 data2_pol;
-+ unsigned long ddr_clk_hz;
-+ } dsi;
-+
-+ struct {
-+ enum omap_dss_venc_type type;
-+ } venc;
-+ } u;
-+
-+ int panel_reset_gpio;
-+ int ctrl_reset_gpio;
-+
-+ const char *name; /* for debug */
-+ const char *ctrl_name;
-+ const char *panel_name;
-+
-+ void *panel_data;
-+ void *ctrl_data;
-+
-+ /* platform specific enable/disable */
-+ int (*panel_enable)(struct omap_display *display);
-+ void (*panel_disable)(struct omap_display *display);
-+ int (*ctrl_enable)(struct omap_display *display);
-+ void (*ctrl_disable)(struct omap_display *display);
-+ int (*set_backlight)(struct omap_display *display,
-+ int level);
-+};
-+
-+struct device;
-+
-+/* Board specific data */
-+struct omap_dss_board_info {
-+ unsigned (*get_last_off_on_transaction_id)(struct device *dev);
-+ int (*dsi_power_up)(void);
-+ void (*dsi_power_down)(void);
-+ int num_displays;
-+ struct omap_dss_display_config *displays[];
-+};
-+
-+struct omap_ctrl {
-+ struct module *owner;
-+
-+ const char *name;
-+
-+ int (*init)(struct omap_display *display);
-+ void (*cleanup)(struct omap_display *display);
-+ int (*enable)(struct omap_display *display);
-+ void (*disable)(struct omap_display *display);
-+ int (*suspend)(struct omap_display *display);
-+ int (*resume)(struct omap_display *display);
-+ void (*setup_update)(struct omap_display *display,
-+ u16 x, u16 y, u16 w, u16 h);
-+
-+ int (*enable_te)(struct omap_display *display, bool enable);
-+
-+ u8 (*get_rotate)(struct omap_display *display);
-+ int (*set_rotate)(struct omap_display *display, u8 rotate);
-+
-+ bool (*get_mirror)(struct omap_display *display);
-+ int (*set_mirror)(struct omap_display *display, bool enable);
-+
-+ int (*run_test)(struct omap_display *display, int test);
-+ int (*memory_read)(struct omap_display *display,
-+ void *buf, size_t size,
-+ u16 x, u16 y, u16 w, u16 h);
-+
-+ u8 pixel_size;
-+
-+ struct rfbi_timings timings;
-+
-+ void *priv;
-+};
-+
-+struct omap_video_timings {
-+ /* Unit: pixels */
-+ u16 x_res;
-+ /* Unit: pixels */
-+ u16 y_res;
-+ /* Unit: KHz */
-+ u32 pixel_clock;
-+ /* Unit: pixel clocks */
-+ u16 hsw; /* Horizontal synchronization pulse width */
-+ /* Unit: pixel clocks */
-+ u16 hfp; /* Horizontal front porch */
-+ /* Unit: pixel clocks */
-+ u16 hbp; /* Horizontal back porch */
-+ /* Unit: line clocks */
-+ u16 vsw; /* Vertical synchronization pulse width */
-+ /* Unit: line clocks */
-+ u16 vfp; /* Vertical front porch */
-+ /* Unit: line clocks */
-+ u16 vbp; /* Vertical back porch */
-+
-+};
-+
-+#ifdef CONFIG_OMAP2_DSS_VENC
-+/* Hardcoded timings for tv modes. Venc only uses these to
-+ * identify the mode, and does not actually use the configs
-+ * itself. However, the configs should be something that
-+ * a normal monitor can also show */
-+const extern struct omap_video_timings omap_dss_pal_timings;
-+const extern struct omap_video_timings omap_dss_ntsc_timings;
-+#endif
-+
-+struct omap_panel {
-+ struct module *owner;
-+
-+ const char *name;
-+
-+ int (*init)(struct omap_display *display);
-+ void (*cleanup)(struct omap_display *display);
-+ int (*remove)(struct omap_display *display);
-+ int (*enable)(struct omap_display *display);
-+ void (*disable)(struct omap_display *display);
-+ int (*suspend)(struct omap_display *display);
-+ int (*resume)(struct omap_display *display);
-+ int (*run_test)(struct omap_display *display, int test);
-+
-+ struct omap_video_timings timings;
-+
-+ int acbi; /* ac-bias pin transitions per interrupt */
-+ /* Unit: line clocks */
-+ int acb; /* ac-bias pin frequency */
-+
-+ enum omap_panel_config config;
-+
-+ u8 recommended_bpp;
-+
-+ void *priv;
-+};
-+
-+/* XXX perhaps this should be removed */
-+enum omap_dss_overlay_managers {
-+ OMAP_DSS_OVL_MGR_LCD,
-+ OMAP_DSS_OVL_MGR_TV,
-+};
-+
-+struct omap_overlay_manager;
-+
-+struct omap_overlay_info {
-+ bool enabled;
-+
-+ u32 paddr;
-+ void __iomem *vaddr;
-+ u16 screen_width;
-+ u16 width;
-+ u16 height;
-+ enum omap_color_mode color_mode;
-+ u8 rotation;
-+ bool mirror;
-+
-+ u16 pos_x;
-+ u16 pos_y;
-+ u16 out_width; /* if 0, out_width == width */
-+ u16 out_height; /* if 0, out_height == height */
-+};
-+
-+enum omap_overlay_caps {
-+ OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
-+ OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
-+};
-+
-+struct omap_overlay {
-+ struct kobject kobj;
-+ struct list_head list;
-+
-+ const char *name;
-+ int id;
-+ struct omap_overlay_manager *manager;
-+ enum omap_color_mode supported_modes;
-+ struct omap_overlay_info info;
-+ enum omap_overlay_caps caps;
-+
-+ int (*set_manager)(struct omap_overlay *ovl,
-+ struct omap_overlay_manager *mgr);
-+ int (*unset_manager)(struct omap_overlay *ovl);
-+
-+ int (*set_overlay_info)(struct omap_overlay *ovl,
-+ struct omap_overlay_info *info);
-+ void (*get_overlay_info)(struct omap_overlay *ovl,
-+ struct omap_overlay_info *info);
-+};
-+
-+enum omap_overlay_manager_caps {
-+ OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
-+};
-+
-+struct omap_overlay_manager {
-+ struct kobject kobj;
-+ struct list_head list;
-+
-+ const char *name;
-+ int id;
-+ enum omap_overlay_manager_caps caps;
-+ struct omap_display *display;
-+ int num_overlays;
-+ struct omap_overlay **overlays;
-+ enum omap_display_type supported_displays;
-+
-+ int (*set_display)(struct omap_overlay_manager *mgr,
-+ struct omap_display *display);
-+ int (*unset_display)(struct omap_overlay_manager *mgr);
-+
-+ int (*apply)(struct omap_overlay_manager *mgr);
-+
-+ void (*set_default_color)(struct omap_overlay_manager *mgr, u32 color);
-+ void (*set_trans_key)(struct omap_overlay_manager *mgr,
-+ enum omap_dss_color_key_type type,
-+ u32 trans_key);
-+ void (*enable_trans_key)(struct omap_overlay_manager *mgr,
-+ bool enable);
-+};
-+
-+enum omap_display_caps {
-+ OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
-+};
-+
-+enum omap_dss_update_mode {
-+ OMAP_DSS_UPDATE_DISABLED = 0,
-+ OMAP_DSS_UPDATE_AUTO,
-+ OMAP_DSS_UPDATE_MANUAL,
-+};
-+
-+enum omap_dss_display_state {
-+ OMAP_DSS_DISPLAY_DISABLED = 0,
-+ OMAP_DSS_DISPLAY_ACTIVE,
-+ OMAP_DSS_DISPLAY_SUSPENDED,
-+};
-+
-+struct omap_display {
-+ struct kobject kobj;
-+ struct list_head list;
-+
-+ /*atomic_t ref_count;*/
-+ int ref_count;
-+ /* helper variable for driver suspend/resume */
-+ int activate_after_resume;
-+
-+ enum omap_display_type type;
-+ const char *name;
-+
-+ enum omap_display_caps caps;
-+
-+ struct omap_overlay_manager *manager;
-+
-+ enum omap_dss_display_state state;
-+
-+ struct omap_dss_display_config hw_config; /* board specific data */
-+ struct omap_ctrl *ctrl; /* static common data */
-+ struct omap_panel *panel; /* static common data */
-+
-+ int (*enable)(struct omap_display *display);
-+ void (*disable)(struct omap_display *display);
-+
-+ int (*suspend)(struct omap_display *display);
-+ int (*resume)(struct omap_display *display);
-+
-+ void (*get_resolution)(struct omap_display *display,
-+ u16 *xres, u16 *yres);
-+ int (*get_recommended_bpp)(struct omap_display *display);
-+
-+ int (*check_timings)(struct omap_display *display,
-+ struct omap_video_timings *timings);
-+ void (*set_timings)(struct omap_display *display,
-+ struct omap_video_timings *timings);
-+ void (*get_timings)(struct omap_display *display,
-+ struct omap_video_timings *timings);
-+ int (*update)(struct omap_display *display,
-+ u16 x, u16 y, u16 w, u16 h);
-+ int (*sync)(struct omap_display *display);
-+ int (*wait_vsync)(struct omap_display *display);
-+
-+ int (*set_update_mode)(struct omap_display *display,
-+ enum omap_dss_update_mode);
-+ enum omap_dss_update_mode (*get_update_mode)
-+ (struct omap_display *display);
-+
-+ int (*enable_te)(struct omap_display *display, bool enable);
-+ int (*get_te)(struct omap_display *display);
-+
-+ u8 (*get_rotate)(struct omap_display *display);
-+ int (*set_rotate)(struct omap_display *display, u8 rotate);
-+
-+ bool (*get_mirror)(struct omap_display *display);
-+ int (*set_mirror)(struct omap_display *display, bool enable);
-+
-+ int (*run_test)(struct omap_display *display, int test);
-+ int (*memory_read)(struct omap_display *display,
-+ void *buf, size_t size,
-+ u16 x, u16 y, u16 w, u16 h);
-+
-+ void (*configure_overlay)(struct omap_overlay *overlay);
-+};
-+
-+int omap_dss_get_num_displays(void);
-+struct omap_display *omap_dss_get_display(int no);
-+void omap_dss_put_display(struct omap_display *display);
-+
-+void omap_dss_register_ctrl(struct omap_ctrl *ctrl);
-+void omap_dss_unregister_ctrl(struct omap_ctrl *ctrl);
-+
-+void omap_dss_register_panel(struct omap_panel *panel);
-+void omap_dss_unregister_panel(struct omap_panel *panel);
-+
-+int omap_dss_get_num_overlay_managers(void);
-+struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
-+
-+int omap_dss_get_num_overlays(void);
-+struct omap_overlay *omap_dss_get_overlay(int num);
-+
-+typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
-+int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
-+int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
-+
-+int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
-+int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
-+ unsigned long timeout);
-+
-+#endif
-diff --git a/arch/arm/plat-omap/include/mach/vram.h b/arch/arm/plat-omap/include/mach/vram.h
-new file mode 100644
-index 0000000..f176562
---- /dev/null
-+++ b/arch/arm/plat-omap/include/mach/vram.h
-@@ -0,0 +1,33 @@
-+/*
-+ * File: arch/arm/plat-omap/include/mach/vram.h
-+ *
-+ * Copyright (C) 2009 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-+ */
-+
-+#ifndef __OMAPVRAM_H
-+#define __OMAPVRAM_H
-+
-+#include <asm/types.h>
-+
-+extern int omap_vram_free(unsigned long paddr, size_t size);
-+extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr);
-+extern int omap_vram_reserve(unsigned long paddr, size_t size);
-+extern void omap2_set_sdram_vram(u32 size, u32 start);
-+extern void omap2_set_sram_vram(u32 size, u32 start);
-+
-+#endif
-diff --git a/arch/arm/plat-omap/include/mach/vrfb.h b/arch/arm/plat-omap/include/mach/vrfb.h
-new file mode 100644
-index 0000000..2047862
---- /dev/null
-+++ b/arch/arm/plat-omap/include/mach/vrfb.h
-@@ -0,0 +1,47 @@
-+/*
-+ * File: arch/arm/plat-omap/include/mach/vrfb.h
-+ *
-+ * VRFB
-+ *
-+ * Copyright (C) 2009 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-+ */
-+
-+#ifndef __VRFB_H
-+#define __VRFB_H
-+
-+#define OMAP_VRFB_LINE_LEN 2048
-+
-+struct vrfb
-+{
-+ u8 context;
-+ void __iomem *vaddr[4];
-+ unsigned long paddr[4];
-+ u16 xoffset;
-+ u16 yoffset;
-+ u8 bytespp;
-+};
-+
-+extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
-+extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
-+extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
-+ u8 bytespp);
-+extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
-+ u16 width, u16 height,
-+ u8 bytespp);
-+
-+#endif /* __VRFB_H */
-diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
-new file mode 100644
-index 0000000..f24a110
---- /dev/null
-+++ b/arch/arm/plat-omap/vram.c
-@@ -0,0 +1,615 @@
-+/*
-+ * linux/arch/arm/plat-omap/vram.c
-+ *
-+ * Copyright (C) 2008 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * Some code and ideas taken from drivers/video/omap/ driver
-+ * by Imre Deak.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+/*#define DEBUG*/
-+
-+#include <linux/vmalloc.h>
-+#include <linux/kernel.h>
-+#include <linux/mm.h>
-+#include <linux/list.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/proc_fs.h>
-+#include <linux/seq_file.h>
-+#include <linux/bootmem.h>
-+#include <linux/omapfb.h>
-+
-+#include <asm/setup.h>
-+
-+#include <mach/sram.h>
-+#include <mach/vram.h>
-+
-+#ifdef DEBUG
-+#define DBG(format, ...) printk(KERN_DEBUG "VRAM: " format, ## __VA_ARGS__)
-+#else
-+#define DBG(format, ...)
-+#endif
-+
-+#define OMAP2_SRAM_START 0x40200000
-+/* Maximum size, in reality this is smaller if SRAM is partially locked. */
-+#define OMAP2_SRAM_SIZE 0xa0000 /* 640k */
-+
-+#define REG_MAP_SIZE(_page_cnt) \
-+ ((_page_cnt + (sizeof(unsigned long) * 8) - 1) / 8)
-+#define REG_MAP_PTR(_rg, _page_nr) \
-+ (((_rg)->map) + (_page_nr) / (sizeof(unsigned long) * 8))
-+#define REG_MAP_MASK(_page_nr) \
-+ (1 << ((_page_nr) & (sizeof(unsigned long) * 8 - 1)))
-+
-+#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
-+
-+/* postponed regions are used to temporarily store region information at boot
-+ * time when we cannot yet allocate the region list */
-+#define MAX_POSTPONED_REGIONS 10
-+
-+static int postponed_cnt __initdata;
-+static struct {
-+ unsigned long paddr;
-+ size_t size;
-+} postponed_regions[MAX_POSTPONED_REGIONS] __initdata;
-+
-+struct vram_alloc {
-+ struct list_head list;
-+ unsigned long paddr;
-+ unsigned pages;
-+};
-+
-+struct vram_region {
-+ struct list_head list;
-+ struct list_head alloc_list;
-+ unsigned long paddr;
-+ unsigned pages;
-+};
-+
-+static DEFINE_MUTEX(region_mutex);
-+static LIST_HEAD(region_list);
-+
-+static inline int region_mem_type(unsigned long paddr)
-+{
-+ if (paddr >= OMAP2_SRAM_START &&
-+ paddr < OMAP2_SRAM_START + OMAP2_SRAM_SIZE)
-+ return OMAPFB_MEMTYPE_SRAM;
-+ else
-+ return OMAPFB_MEMTYPE_SDRAM;
-+}
-+
-+static struct vram_region *omap_vram_create_region(unsigned long paddr,
-+ unsigned pages)
-+{
-+ struct vram_region *rm;
-+
-+ rm = kzalloc(sizeof(*rm), GFP_KERNEL);
-+
-+ if (rm) {
-+ INIT_LIST_HEAD(&rm->alloc_list);
-+ rm->paddr = paddr;
-+ rm->pages = pages;
-+ }
-+
-+ return rm;
-+}
-+
-+#if 0
-+static void omap_vram_free_region(struct vram_region *vr)
-+{
-+ list_del(&vr->list);
-+ kfree(vr);
-+}
-+#endif
-+
-+static struct vram_alloc *omap_vram_create_allocation(struct vram_region *vr,
-+ unsigned long paddr, unsigned pages)
-+{
-+ struct vram_alloc *va;
-+ struct vram_alloc *new;
-+
-+ new = kzalloc(sizeof(*va), GFP_KERNEL);
-+
-+ if (!new)
-+ return NULL;
-+
-+ new->paddr = paddr;
-+ new->pages = pages;
-+
-+ list_for_each_entry(va, &vr->alloc_list, list) {
-+ if (va->paddr > new->paddr)
-+ break;
-+ }
-+
-+ list_add_tail(&new->list, &va->list);
-+
-+ return new;
-+}
-+
-+static void omap_vram_free_allocation(struct vram_alloc *va)
-+{
-+ list_del(&va->list);
-+ kfree(va);
-+}
-+
-+static __init int omap_vram_add_region_postponed(unsigned long paddr,
-+ size_t size)
-+{
-+ if (postponed_cnt == MAX_POSTPONED_REGIONS)
-+ return -ENOMEM;
-+
-+ postponed_regions[postponed_cnt].paddr = paddr;
-+ postponed_regions[postponed_cnt].size = size;
-+
-+ ++postponed_cnt;
-+
-+ return 0;
-+}
-+
-+/* add/remove_region can be exported if there's need to add/remove regions
-+ * runtime */
-+static int omap_vram_add_region(unsigned long paddr, size_t size)
-+{
-+ struct vram_region *rm;
-+ unsigned pages;
-+
-+ DBG("adding region paddr %08lx size %d\n",
-+ paddr, size);
-+
-+ size &= PAGE_MASK;
-+ pages = size >> PAGE_SHIFT;
-+
-+ rm = omap_vram_create_region(paddr, pages);
-+ if (rm == NULL)
-+ return -ENOMEM;
-+
-+ list_add(&rm->list, ®ion_list);
-+
-+ return 0;
-+}
-+
-+int omap_vram_free(unsigned long paddr, size_t size)
-+{
-+ struct vram_region *rm;
-+ struct vram_alloc *alloc;
-+ unsigned start, end;
-+
-+ DBG("free mem paddr %08lx size %d\n", paddr, size);
-+
-+ size = PAGE_ALIGN(size);
-+
-+ mutex_lock(®ion_mutex);
-+
-+ list_for_each_entry(rm, ®ion_list, list) {
-+ list_for_each_entry(alloc, &rm->alloc_list, list) {
-+ start = alloc->paddr;
-+ end = alloc->paddr + (alloc->pages >> PAGE_SHIFT);
-+
-+ if (start >= paddr && end < paddr + size)
-+ goto found;
-+ }
-+ }
-+
-+ mutex_unlock(®ion_mutex);
-+ return -EINVAL;
-+
-+found:
-+ omap_vram_free_allocation(alloc);
-+
-+ mutex_unlock(®ion_mutex);
-+ return 0;
-+}
-+EXPORT_SYMBOL(omap_vram_free);
-+
-+static int _omap_vram_reserve(unsigned long paddr, unsigned pages)
-+{
-+ struct vram_region *rm;
-+ struct vram_alloc *alloc;
-+ size_t size;
-+
-+ size = pages << PAGE_SHIFT;
-+
-+ list_for_each_entry(rm, ®ion_list, list) {
-+ unsigned long start, end;
-+
-+ DBG("checking region %lx %d\n", rm->paddr, rm->pages);
-+
-+ if (region_mem_type(rm->paddr) != region_mem_type(paddr))
-+ continue;
-+
-+ start = rm->paddr;
-+ end = start + (rm->pages << PAGE_SHIFT) - 1;
-+ if (start > paddr || end < paddr + size - 1)
-+ continue;
-+
-+ DBG("block ok, checking allocs\n");
-+
-+ list_for_each_entry(alloc, &rm->alloc_list, list) {
-+ end = alloc->paddr - 1;
-+
-+ if (start <= paddr && end >= paddr + size - 1)
-+ goto found;
-+
-+ start = alloc->paddr + (alloc->pages << PAGE_SHIFT);
-+ }
-+
-+ end = rm->paddr + (rm->pages << PAGE_SHIFT) - 1;
-+
-+ if (!(start <= paddr && end >= paddr + size - 1))
-+ continue;
-+found:
-+ DBG("FOUND area start %lx, end %lx\n", start, end);
-+
-+ if (omap_vram_create_allocation(rm, paddr, pages) == NULL)
-+ return -ENOMEM;
-+
-+ return 0;
-+ }
-+
-+ return -ENOMEM;
-+}
-+
-+int omap_vram_reserve(unsigned long paddr, size_t size)
-+{
-+ unsigned pages;
-+ int r;
-+
-+ DBG("reserve mem paddr %08lx size %d\n", paddr, size);
-+
-+ size = PAGE_ALIGN(size);
-+ pages = size >> PAGE_SHIFT;
-+
-+ mutex_lock(®ion_mutex);
-+
-+ r = _omap_vram_reserve(paddr, pages);
-+
-+ mutex_unlock(®ion_mutex);
-+
-+ return r;
-+}
-+EXPORT_SYMBOL(omap_vram_reserve);
-+
-+static int _omap_vram_alloc(int mtype, unsigned pages, unsigned long *paddr)
-+{
-+ struct vram_region *rm;
-+ struct vram_alloc *alloc;
-+
-+ list_for_each_entry(rm, ®ion_list, list) {
-+ unsigned long start, end;
-+
-+ DBG("checking region %lx %d\n", rm->paddr, rm->pages);
-+
-+ if (region_mem_type(rm->paddr) != mtype)
-+ continue;
-+
-+ start = rm->paddr;
-+
-+ list_for_each_entry(alloc, &rm->alloc_list, list) {
-+ end = alloc->paddr;
-+
-+ if (end - start >= pages << PAGE_SHIFT)
-+ goto found;
-+
-+ start = alloc->paddr + (alloc->pages << PAGE_SHIFT);
-+ }
-+
-+ end = rm->paddr + (rm->pages << PAGE_SHIFT);
-+found:
-+ if (end - start < pages << PAGE_SHIFT)
-+ continue;
-+
-+ DBG("FOUND %lx, end %lx\n", start, end);
-+
-+ alloc = omap_vram_create_allocation(rm, start, pages);
-+ if (alloc == NULL)
-+ return -ENOMEM;
-+
-+ *paddr = start;
-+
-+ return 0;
-+ }
-+
-+ return -ENOMEM;
-+}
-+
-+int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr)
-+{
-+ unsigned pages;
-+ int r;
-+
-+ BUG_ON(mtype > OMAPFB_MEMTYPE_MAX || !size);
-+
-+ DBG("alloc mem type %d size %d\n", mtype, size);
-+
-+ size = PAGE_ALIGN(size);
-+ pages = size >> PAGE_SHIFT;
-+
-+ mutex_lock(®ion_mutex);
-+
-+ r = _omap_vram_alloc(mtype, pages, paddr);
-+
-+ mutex_unlock(®ion_mutex);
-+
-+ return r;
-+}
-+EXPORT_SYMBOL(omap_vram_alloc);
-+
-+#ifdef CONFIG_PROC_FS
-+static void *r_next(struct seq_file *m, void *v, loff_t *pos)
-+{
-+ struct list_head *l = v;
-+
-+ (*pos)++;
-+
-+ if (list_is_last(l, ®ion_list))
-+ return NULL;
-+
-+ return l->next;
-+}
-+
-+static void *r_start(struct seq_file *m, loff_t *pos)
-+{
-+ loff_t p = *pos;
-+ struct list_head *l = ®ion_list;
-+
-+ mutex_lock(®ion_mutex);
-+
-+ do {
-+ l = l->next;
-+ if (l == ®ion_list)
-+ return NULL;
-+ } while (p--);
-+
-+ return l;
-+}
-+
-+static void r_stop(struct seq_file *m, void *v)
-+{
-+ mutex_unlock(®ion_mutex);
-+}
-+
-+static int r_show(struct seq_file *m, void *v)
-+{
-+ struct vram_region *vr;
-+ struct vram_alloc *va;
-+ unsigned size;
-+
-+ vr = list_entry(v, struct vram_region, list);
-+
-+ size = vr->pages << PAGE_SHIFT;
-+
-+ seq_printf(m, "%08lx-%08lx (%d bytes)\n",
-+ vr->paddr, vr->paddr + size - 1,
-+ size);
-+
-+ list_for_each_entry(va, &vr->alloc_list, list) {
-+ size = va->pages << PAGE_SHIFT;
-+ seq_printf(m, " %08lx-%08lx (%d bytes)\n",
-+ va->paddr, va->paddr + size - 1,
-+ size);
-+ }
-+
-+
-+
-+ return 0;
-+}
-+
-+static const struct seq_operations resource_op = {
-+ .start = r_start,
-+ .next = r_next,
-+ .stop = r_stop,
-+ .show = r_show,
-+};
-+
-+static int vram_open(struct inode *inode, struct file *file)
-+{
-+ return seq_open(file, &resource_op);
-+}
-+
-+static const struct file_operations proc_vram_operations = {
-+ .open = vram_open,
-+ .read = seq_read,
-+ .llseek = seq_lseek,
-+ .release = seq_release,
-+};
-+
-+static int __init omap_vram_create_proc(void)
-+{
-+ proc_create("omap-vram", 0, NULL, &proc_vram_operations);
-+
-+ return 0;
-+}
-+#endif
-+
-+static __init int omap_vram_init(void)
-+{
-+ int i, r;
-+
-+ for (i = 0; i < postponed_cnt; i++)
-+ omap_vram_add_region(postponed_regions[i].paddr,
-+ postponed_regions[i].size);
-+
-+#ifdef CONFIG_PROC_FS
-+ r = omap_vram_create_proc();
-+ if (r)
-+ return -ENOMEM;
-+#endif
-+
-+ return 0;
-+}
-+
-+arch_initcall(omap_vram_init);
-+
-+/* boottime vram alloc stuff */
-+
-+/* set from board file */
-+static u32 omapfb_sram_vram_start __initdata;
-+static u32 omapfb_sram_vram_size __initdata;
-+
-+/* set from board file */
-+static u32 omapfb_sdram_vram_start __initdata;
-+static u32 omapfb_sdram_vram_size __initdata;
-+
-+/* set from kernel cmdline */
-+static u32 omapfb_def_sdram_vram_size __initdata;
-+static u32 omapfb_def_sdram_vram_start __initdata;
-+
-+static void __init omapfb_early_vram(char **p)
-+{
-+ omapfb_def_sdram_vram_size = memparse(*p, p);
-+ if (**p == ',')
-+ omapfb_def_sdram_vram_start = simple_strtoul((*p) + 1, p, 16);
-+
-+ printk("omapfb_early_vram, %d, 0x%x\n",
-+ omapfb_def_sdram_vram_size,
-+ omapfb_def_sdram_vram_start);
-+}
-+__early_param("vram=", omapfb_early_vram);
-+
-+/*
-+ * Called from map_io. We need to call to this early enough so that we
-+ * can reserve the fixed SDRAM regions before VM could get hold of them.
-+ */
-+void __init omapfb_reserve_sdram(void)
-+{
-+ struct bootmem_data *bdata;
-+ unsigned long sdram_start, sdram_size;
-+ u32 paddr;
-+ u32 size = 0;
-+
-+ /* cmdline arg overrides the board file definition */
-+ if (omapfb_def_sdram_vram_size) {
-+ size = omapfb_def_sdram_vram_size;
-+ paddr = omapfb_def_sdram_vram_start;
-+ }
-+
-+ if (!size) {
-+ size = omapfb_sdram_vram_size;
-+ paddr = omapfb_sdram_vram_start;
-+ }
-+
-+#ifdef CONFIG_OMAP2_DSS_VRAM_SIZE
-+ if (!size) {
-+ size = CONFIG_OMAP2_DSS_VRAM_SIZE * 1024 * 1024;
-+ paddr = 0;
-+ }
-+#endif
-+
-+ if (!size)
-+ return;
-+
-+ size = PAGE_ALIGN(size);
-+
-+ bdata = NODE_DATA(0)->bdata;
-+ sdram_start = bdata->node_min_pfn << PAGE_SHIFT;
-+ sdram_size = (bdata->node_low_pfn << PAGE_SHIFT) - sdram_start;
-+
-+ if (paddr) {
-+ if ((paddr & ~PAGE_MASK) || paddr < sdram_start ||
-+ paddr + size > sdram_start + sdram_size) {
-+ printk(KERN_ERR "Illegal SDRAM region for VRAM\n");
-+ return;
-+ }
-+
-+ reserve_bootmem(paddr, size, BOOTMEM_DEFAULT);
-+ } else {
-+ if (size > sdram_size) {
-+ printk(KERN_ERR "Illegal SDRAM size for VRAM\n");
-+ return;
-+ }
-+
-+ paddr = virt_to_phys(alloc_bootmem_pages(size));
-+ BUG_ON(paddr & ~PAGE_MASK);
-+ }
-+
-+ omap_vram_add_region_postponed(paddr, size);
-+
-+ pr_info("Reserving %u bytes SDRAM for VRAM\n", size);
-+}
-+
-+/*
-+ * Called at sram init time, before anything is pushed to the SRAM stack.
-+ * Because of the stack scheme, we will allocate everything from the
-+ * start of the lowest address region to the end of SRAM. This will also
-+ * include padding for page alignment and possible holes between regions.
-+ *
-+ * As opposed to the SDRAM case, we'll also do any dynamic allocations at
-+ * this point, since the driver built as a module would have problem with
-+ * freeing / reallocating the regions.
-+ */
-+unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
-+ unsigned long sram_vstart,
-+ unsigned long sram_size,
-+ unsigned long pstart_avail,
-+ unsigned long size_avail)
-+{
-+ unsigned long pend_avail;
-+ unsigned long reserved;
-+ u32 paddr;
-+ u32 size;
-+
-+ paddr = omapfb_sram_vram_start;
-+ size = omapfb_sram_vram_size;
-+
-+ if (!size)
-+ return 0;
-+
-+ reserved = 0;
-+ pend_avail = pstart_avail + size_avail;
-+
-+ if (!paddr) {
-+ /* Dynamic allocation */
-+ if ((size_avail & PAGE_MASK) < size) {
-+ printk(KERN_ERR "Not enough SRAM for VRAM\n");
-+ return 0;
-+ }
-+ size_avail = (size_avail - size) & PAGE_MASK;
-+ paddr = pstart_avail + size_avail;
-+ }
-+
-+ if (paddr < sram_pstart ||
-+ paddr + size > sram_pstart + sram_size) {
-+ printk(KERN_ERR "Illegal SRAM region for VRAM\n");
-+ return 0;
-+ }
-+
-+ /* Reserve everything above the start of the region. */
-+ if (pend_avail - paddr > reserved)
-+ reserved = pend_avail - paddr;
-+ size_avail = pend_avail - reserved - pstart_avail;
-+
-+ omap_vram_add_region_postponed(paddr, size);
-+
-+ if (reserved)
-+ pr_info("Reserving %lu bytes SRAM for VRAM\n", reserved);
-+
-+ return reserved;
-+}
-+
-+void __init omap2_set_sdram_vram(u32 size, u32 start)
-+{
-+ omapfb_sdram_vram_start = start;
-+ omapfb_sdram_vram_size = size;
-+}
-+
-+void __init omap2_set_sram_vram(u32 size, u32 start)
-+{
-+ omapfb_sram_vram_start = start;
-+ omapfb_sram_vram_size = size;
-+}
-+
-+#endif
-+
-diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
-new file mode 100644
-index 0000000..7e0f8fc
---- /dev/null
-+++ b/arch/arm/plat-omap/vrfb.c
-@@ -0,0 +1,159 @@
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/ioport.h>
-+#include <asm/io.h>
-+
-+#include <mach/io.h>
-+#include <mach/vrfb.h>
-+
-+/*#define DEBUG*/
-+
-+#ifdef DEBUG
-+#define DBG(format, ...) printk(KERN_DEBUG "VRFB: " format, ## __VA_ARGS__)
-+#else
-+#define DBG(format, ...)
-+#endif
-+
-+#define SMS_ROT_VIRT_BASE(context, rot) \
-+ (((context >= 4) ? 0xD0000000 : 0x70000000) \
-+ | 0x4000000 * (context) \
-+ | 0x1000000 * (rot))
-+
-+#define OMAP_VRFB_SIZE (2048 * 2048 * 4)
-+
-+#define VRFB_PAGE_WIDTH_EXP 5 /* Assuming SDRAM pagesize= 1024 */
-+#define VRFB_PAGE_HEIGHT_EXP 5 /* 1024 = 2^5 * 2^5 */
-+#define VRFB_PAGE_WIDTH (1 << VRFB_PAGE_WIDTH_EXP)
-+#define VRFB_PAGE_HEIGHT (1 << VRFB_PAGE_HEIGHT_EXP)
-+#define SMS_IMAGEHEIGHT_OFFSET 16
-+#define SMS_IMAGEWIDTH_OFFSET 0
-+#define SMS_PH_OFFSET 8
-+#define SMS_PW_OFFSET 4
-+#define SMS_PS_OFFSET 0
-+
-+#define OMAP_SMS_BASE 0x6C000000
-+#define SMS_ROT_CONTROL(context) (OMAP_SMS_BASE + 0x180 + 0x10 * context)
-+#define SMS_ROT_SIZE(context) (OMAP_SMS_BASE + 0x184 + 0x10 * context)
-+#define SMS_ROT_PHYSICAL_BA(context) (OMAP_SMS_BASE + 0x188 + 0x10 * context)
-+
-+#define VRFB_NUM_CTXS 12
-+/* bitmap of reserved contexts */
-+static unsigned ctx_map;
-+
-+void omap_vrfb_adjust_size(u16 *width, u16 *height,
-+ u8 bytespp)
-+{
-+ *width = ALIGN(*width * bytespp, VRFB_PAGE_WIDTH) / bytespp;
-+ *height = ALIGN(*height, VRFB_PAGE_HEIGHT);
-+}
-+EXPORT_SYMBOL(omap_vrfb_adjust_size);
-+
-+void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
-+ u16 width, u16 height,
-+ u8 bytespp)
-+{
-+ unsigned pixel_size_exp;
-+ u16 vrfb_width;
-+ u16 vrfb_height;
-+ u8 ctx = vrfb->context;
-+
-+ DBG("omapfb_set_vrfb(%d, %lx, %dx%d, %d)\n", ctx, paddr,
-+ width, height, bytespp);
-+
-+ if (bytespp == 4)
-+ pixel_size_exp = 2;
-+ else if (bytespp == 2)
-+ pixel_size_exp = 1;
-+ else
-+ BUG();
-+
-+ vrfb_width = ALIGN(width * bytespp, VRFB_PAGE_WIDTH) / bytespp;
-+ vrfb_height = ALIGN(height, VRFB_PAGE_HEIGHT);
-+
-+ DBG("vrfb w %u, h %u\n", vrfb_width, vrfb_height);
-+
-+ omap_writel(paddr, SMS_ROT_PHYSICAL_BA(ctx));
-+ omap_writel((vrfb_width << SMS_IMAGEWIDTH_OFFSET) |
-+ (vrfb_height << SMS_IMAGEHEIGHT_OFFSET),
-+ SMS_ROT_SIZE(ctx));
-+
-+ omap_writel(pixel_size_exp << SMS_PS_OFFSET |
-+ VRFB_PAGE_WIDTH_EXP << SMS_PW_OFFSET |
-+ VRFB_PAGE_HEIGHT_EXP << SMS_PH_OFFSET,
-+ SMS_ROT_CONTROL(ctx));
-+
-+ DBG("vrfb offset pixels %d, %d\n",
-+ vrfb_width - width, vrfb_height - height);
-+
-+ vrfb->xoffset = vrfb_width - width;
-+ vrfb->yoffset = vrfb_height - height;
-+ vrfb->bytespp = bytespp;
-+}
-+EXPORT_SYMBOL(omap_vrfb_setup);
-+
-+void omap_vrfb_release_ctx(struct vrfb *vrfb)
-+{
-+ int rot;
-+
-+ if (vrfb->context == 0xff)
-+ return;
-+
-+ DBG("release ctx %d\n", vrfb->context);
-+
-+ ctx_map &= ~(1 << vrfb->context);
-+
-+ for (rot = 0; rot < 4; ++rot) {
-+ if(vrfb->paddr[rot]) {
-+ release_mem_region(vrfb->paddr[rot], OMAP_VRFB_SIZE);
-+ vrfb->paddr[rot] = 0;
-+ }
-+ }
-+
-+ vrfb->context = 0xff;
-+}
-+EXPORT_SYMBOL(omap_vrfb_release_ctx);
-+
-+int omap_vrfb_request_ctx(struct vrfb *vrfb)
-+{
-+ int rot;
-+ u32 paddr;
-+ u8 ctx;
-+
-+ DBG("request ctx\n");
-+
-+ for (ctx = 0; ctx < VRFB_NUM_CTXS; ++ctx)
-+ if ((ctx_map & (1 << ctx)) == 0)
-+ break;
-+
-+ if (ctx == VRFB_NUM_CTXS) {
-+ printk(KERN_ERR "vrfb: no free contexts\n");
-+ return -EBUSY;
-+ }
-+
-+ DBG("found free ctx %d\n", ctx);
-+
-+ ctx_map |= 1 << ctx;
-+
-+ memset(vrfb, 0, sizeof(*vrfb));
-+
-+ vrfb->context = ctx;
-+
-+ for (rot = 0; rot < 4; ++rot) {
-+ paddr = SMS_ROT_VIRT_BASE(ctx, rot);
-+ if (!request_mem_region(paddr, OMAP_VRFB_SIZE, "vrfb")) {
-+ printk(KERN_ERR "vrfb: failed to reserve VRFB "
-+ "area for ctx %d, rotation %d\n",
-+ ctx, rot * 90);
-+ omap_vrfb_release_ctx(vrfb);
-+ return -ENOMEM;
-+ }
-+
-+ vrfb->paddr[rot] = paddr;
-+
-+ DBG("VRFB %d/%d: %lx\n", ctx, rot*90, vrfb->paddr[rot]);
-+ }
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(omap_vrfb_request_ctx);
-+
-diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
-index fb19803..8b3752b 100644
---- a/drivers/video/Kconfig
-+++ b/drivers/video/Kconfig
-@@ -2132,6 +2132,7 @@ config FB_MX3
- an LCD display with your i.MX31 system, say Y here.
-
- source "drivers/video/omap/Kconfig"
-+source "drivers/video/omap2/Kconfig"
-
- source "drivers/video/backlight/Kconfig"
- source "drivers/video/display/Kconfig"
-diff --git a/drivers/video/Makefile b/drivers/video/Makefile
-index 2a998ca..1db8dd4 100644
---- a/drivers/video/Makefile
-+++ b/drivers/video/Makefile
-@@ -120,6 +120,7 @@ obj-$(CONFIG_FB_SM501) += sm501fb.o
- obj-$(CONFIG_FB_XILINX) += xilinxfb.o
- obj-$(CONFIG_FB_SH_MOBILE_LCDC) += sh_mobile_lcdcfb.o
- obj-$(CONFIG_FB_OMAP) += omap/
-+obj-$(CONFIG_OMAP2_DSS) += omap2/
- obj-$(CONFIG_XEN_FBDEV_FRONTEND) += xen-fbfront.o
- obj-$(CONFIG_FB_CARMINE) += carminefb.o
- obj-$(CONFIG_FB_MB862XX) += mb862xx/
-diff --git a/drivers/video/omap2/Kconfig b/drivers/video/omap2/Kconfig
-new file mode 100644
-index 0000000..89bf210
---- /dev/null
-+++ b/drivers/video/omap2/Kconfig
-@@ -0,0 +1,3 @@
-+source "drivers/video/omap2/dss/Kconfig"
-+source "drivers/video/omap2/displays/Kconfig"
-+source "drivers/video/omap2/omapfb/Kconfig"
-diff --git a/drivers/video/omap2/Makefile b/drivers/video/omap2/Makefile
-new file mode 100644
-index 0000000..72134db
---- /dev/null
-+++ b/drivers/video/omap2/Makefile
-@@ -0,0 +1,4 @@
-+# OMAP2/3 Display Subsystem
-+obj-y += dss/
-+obj-y += displays/
-+obj-y += omapfb/
-diff --git a/drivers/video/omap2/dss/Kconfig b/drivers/video/omap2/dss/Kconfig
-new file mode 100644
-index 0000000..f2ce068
---- /dev/null
-+++ b/drivers/video/omap2/dss/Kconfig
-@@ -0,0 +1,89 @@
-+menuconfig OMAP2_DSS
-+ tristate "OMAP2/3 Display Subsystem support (EXPERIMENTAL)"
-+ depends on ARCH_OMAP2 || ARCH_OMAP3
-+ help
-+ OMAP2/3 Display Subsystem support.
-+
-+if OMAP2_DSS
-+
-+config OMAP2_DSS_VRAM_SIZE
-+ int "VRAM size (MB)"
-+ range 0 32
-+ default 4
-+ help
-+ The amount of SDRAM to reserve at boot time for video RAM use.
-+ This VRAM will be used by omapfb and other drivers that need
-+ large continuous RAM area for video use.
-+
-+ You can also set this with "vram=<bytes>" kernel argument, or
-+ in the board file.
-+
-+config OMAP2_DSS_DEBUG_SUPPORT
-+ bool "Debug support"
-+ default y
-+ help
-+ This enables debug messages. You need to enable printing
-+ with 'debug' module parameter.
-+
-+config OMAP2_DSS_RFBI
-+ bool "RFBI support"
-+ default n
-+ help
-+ MIPI DBI, or RFBI (Remote Framebuffer Interface), support.
-+
-+config OMAP2_DSS_VENC
-+ bool "VENC support"
-+ default y
-+ help
-+ OMAP Video Encoder support.
-+
-+config OMAP2_DSS_SDI
-+ bool "SDI support"
-+ depends on ARCH_OMAP3
-+ default n
-+ help
-+ SDI (Serial Display Interface) support.
-+
-+config OMAP2_DSS_DSI
-+ bool "DSI support"
-+ depends on ARCH_OMAP3
-+ default n
-+ help
-+ MIPI DSI support.
-+
-+config OMAP2_DSS_USE_DSI_PLL
-+ bool "Use DSI PLL for PCLK (EXPERIMENTAL)"
-+ default n
-+ depends on OMAP2_DSS_DSI
-+ help
-+ Use DSI PLL to generate pixel clock. Currently only for DPI output.
-+ DSI PLL can be used to generate higher and more precise pixel clocks.
-+
-+config OMAP2_DSS_FAKE_VSYNC
-+ bool "Fake VSYNC irq from manual update displays"
-+ default n
-+ help
-+ If this is selected, DSI will generate a fake DISPC VSYNC interrupt
-+ when DSI has sent a frame. This is only needed with DSI or RFBI
-+ displays using manual mode, and you want VSYNC to, for example,
-+ time animation.
-+
-+config OMAP2_DSS_MIN_FCK_PER_PCK
-+ int "Minimum FCK/PCK ratio (for scaling)"
-+ range 0 32
-+ default 0
-+ help
-+ This can be used to adjust the minimum FCK/PCK ratio.
-+
-+ With this you can make sure that DISPC FCK is at least
-+ n x PCK. Video plane scaling requires higher FCK than
-+ normally.
-+
-+ If this is set to 0, there's no extra constraint on the
-+ DISPC FCK. However, the FCK will at minimum be
-+ 2xPCK (if active matrix) or 3xPCK (if passive matrix).
-+
-+ Max FCK is 173MHz, so this doesn't work if your PCK
-+ is very high.
-+
-+endif
-diff --git a/drivers/video/omap2/dss/Makefile b/drivers/video/omap2/dss/Makefile
-new file mode 100644
-index 0000000..980c72c
---- /dev/null
-+++ b/drivers/video/omap2/dss/Makefile
-@@ -0,0 +1,6 @@
-+obj-$(CONFIG_OMAP2_DSS) += omapdss.o
-+omapdss-y := core.o dss.o dispc.o dpi.o display.o manager.o overlay.o
-+omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o
-+omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o
-+omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o
-+omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o
-diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c
-new file mode 100644
-index 0000000..ae7cd06
---- /dev/null
-+++ b/drivers/video/omap2/dss/core.c
-@@ -0,0 +1,641 @@
-+/*
-+ * linux/drivers/video/omap2/dss/core.c
-+ *
-+ * Copyright (C) 2009 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * Some code and ideas taken from drivers/video/omap/ driver
-+ * by Imre Deak.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#define DSS_SUBSYS_NAME "CORE"
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/platform_device.h>
-+#include <linux/seq_file.h>
-+#include <linux/debugfs.h>
-+#include <linux/io.h>
-+
-+#include <mach/display.h>
-+#include <mach/clock.h>
-+
-+#include "dss.h"
-+
-+static struct {
-+ struct platform_device *pdev;
-+ unsigned ctx_id;
-+
-+ struct clk *dss_ick;
-+ struct clk *dss1_fck;
-+ struct clk *dss2_fck;
-+ struct clk *dss_54m_fck;
-+ struct clk *dss_96m_fck;
-+ unsigned num_clks_enabled;
-+} core;
-+
-+static void dss_clk_enable_all_no_ctx(void);
-+static void dss_clk_disable_all_no_ctx(void);
-+static void dss_clk_enable_no_ctx(enum dss_clock clks);
-+static void dss_clk_disable_no_ctx(enum dss_clock clks);
-+
-+static char *def_disp_name;
-+module_param_named(def_disp, def_disp_name, charp, 0);
-+MODULE_PARM_DESC(def_disp_name, "default display name");
-+
-+#ifdef DEBUG
-+unsigned int dss_debug;
-+module_param_named(debug, dss_debug, bool, 0644);
-+#endif
-+
-+/* CONTEXT */
-+static unsigned dss_get_ctx_id(void)
-+{
-+ struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
-+
-+ if (!pdata->get_last_off_on_transaction_id)
-+ return 0;
-+
-+ return pdata->get_last_off_on_transaction_id(&core.pdev->dev);
-+}
-+
-+int dss_need_ctx_restore(void)
-+{
-+ int id = dss_get_ctx_id();
-+
-+ if (id != core.ctx_id) {
-+ DSSDBG("ctx id %u -> id %u\n",
-+ core.ctx_id, id);
-+ core.ctx_id = id;
-+ return 1;
-+ } else {
-+ return 0;
-+ }
-+}
-+
-+static void save_all_ctx(void)
-+{
-+ DSSDBG("save context\n");
-+
-+ dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
-+
-+ dss_save_context();
-+ dispc_save_context();
-+#ifdef CONFIG_OMAP2_DSS_DSI
-+ dsi_save_context();
-+#endif
-+
-+ dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
-+}
-+
-+static void restore_all_ctx(void)
-+{
-+ DSSDBG("restore context\n");
-+
-+ dss_clk_enable_all_no_ctx();
-+
-+ dss_restore_context();
-+ dispc_restore_context();
-+#ifdef CONFIG_OMAP2_DSS_DSI
-+ dsi_restore_context();
-+#endif
-+
-+ dss_clk_disable_all_no_ctx();
-+}
-+
-+/* CLOCKS */
-+void dss_dump_clocks(struct seq_file *s)
-+{
-+ int i;
-+ struct clk *clocks[5] = {
-+ core.dss_ick,
-+ core.dss1_fck,
-+ core.dss2_fck,
-+ core.dss_54m_fck,
-+ core.dss_96m_fck
-+ };
-+
-+ seq_printf(s, "- dss -\n");
-+
-+ seq_printf(s, "internal clk count\t%u\n", core.num_clks_enabled);
-+
-+ for (i = 0; i < 5; i++) {
-+ if (!clocks[i])
-+ continue;
-+ seq_printf(s, "%-15s\t%lu\t%d\n",
-+ clocks[i]->name,
-+ clk_get_rate(clocks[i]),
-+ clocks[i]->usecount);
-+ }
-+}
-+
-+static int dss_get_clocks(void)
-+{
-+ const struct {
-+ struct clk **clock;
-+ char *omap2_name;
-+ char *omap3_name;
-+ } clocks[5] = {
-+ { &core.dss_ick, "dss_ick", "dss_ick" }, /* L3 & L4 ick */
-+ { &core.dss1_fck, "dss1_fck", "dss1_alwon_fck" },
-+ { &core.dss2_fck, "dss2_fck", "dss2_alwon_fck" },
-+ { &core.dss_54m_fck, "dss_54m_fck", "dss_tv_fck" },
-+ { &core.dss_96m_fck, NULL, "dss_96m_fck" },
-+ };
-+
-+ int r = 0;
-+ int i;
-+ const int num_clocks = 5;
-+
-+ for (i = 0; i < num_clocks; i++)
-+ *clocks[i].clock = NULL;
-+
-+ for (i = 0; i < num_clocks; i++) {
-+ struct clk *clk;
-+ const char *clk_name;
-+
-+ clk_name = cpu_is_omap34xx() ? clocks[i].omap3_name
-+ : clocks[i].omap2_name;
-+
-+ if (!clk_name)
-+ continue;
-+
-+ clk = clk_get(NULL, clk_name);
-+
-+ if (IS_ERR(clk)) {
-+ DSSERR("can't get clock %s", clk_name);
-+ r = PTR_ERR(clk);
-+ goto err;
-+ }
-+
-+ DSSDBG("clk %s, rate %ld\n",
-+ clk_name, clk_get_rate(clk));
-+
-+ *clocks[i].clock = clk;
-+ }
-+
-+ return 0;
-+
-+err:
-+ for (i = 0; i < num_clocks; i++) {
-+ if (!IS_ERR(*clocks[i].clock))
-+ clk_put(*clocks[i].clock);
-+ }
-+
-+ return r;
-+}
-+
-+static void dss_put_clocks(void)
-+{
-+ if (core.dss_96m_fck)
-+ clk_put(core.dss_96m_fck);
-+ clk_put(core.dss_54m_fck);
-+ clk_put(core.dss1_fck);
-+ clk_put(core.dss2_fck);
-+ clk_put(core.dss_ick);
-+}
-+
-+unsigned long dss_clk_get_rate(enum dss_clock clk)
-+{
-+ switch (clk) {
-+ case DSS_CLK_ICK:
-+ return clk_get_rate(core.dss_ick);
-+ case DSS_CLK_FCK1:
-+ return clk_get_rate(core.dss1_fck);
-+ case DSS_CLK_FCK2:
-+ return clk_get_rate(core.dss2_fck);
-+ case DSS_CLK_54M:
-+ return clk_get_rate(core.dss_54m_fck);
-+ case DSS_CLK_96M:
-+ return clk_get_rate(core.dss_96m_fck);
-+ }
-+
-+ BUG();
-+ return 0;
-+}
-+
-+static unsigned count_clk_bits(enum dss_clock clks)
-+{
-+ unsigned num_clks = 0;
-+
-+ if (clks & DSS_CLK_ICK)
-+ ++num_clks;
-+ if (clks & DSS_CLK_FCK1)
-+ ++num_clks;
-+ if (clks & DSS_CLK_FCK2)
-+ ++num_clks;
-+ if (clks & DSS_CLK_54M)
-+ ++num_clks;
-+ if (clks & DSS_CLK_96M)
-+ ++num_clks;
-+
-+ return num_clks;
-+}
-+
-+static void dss_clk_enable_no_ctx(enum dss_clock clks)
-+{
-+ unsigned num_clks = count_clk_bits(clks);
-+
-+ if (clks & DSS_CLK_ICK)
-+ clk_enable(core.dss_ick);
-+ if (clks & DSS_CLK_FCK1)
-+ clk_enable(core.dss1_fck);
-+ if (clks & DSS_CLK_FCK2)
-+ clk_enable(core.dss2_fck);
-+ if (clks & DSS_CLK_54M)
-+ clk_enable(core.dss_54m_fck);
-+ if (clks & DSS_CLK_96M)
-+ clk_enable(core.dss_96m_fck);
-+
-+ core.num_clks_enabled += num_clks;
-+}
-+
-+void dss_clk_enable(enum dss_clock clks)
-+{
-+ dss_clk_enable_no_ctx(clks);
-+
-+ if (cpu_is_omap34xx() && dss_need_ctx_restore())
-+ restore_all_ctx();
-+}
-+
-+static void dss_clk_disable_no_ctx(enum dss_clock clks)
-+{
-+ unsigned num_clks = count_clk_bits(clks);
-+
-+ if (clks & DSS_CLK_ICK)
-+ clk_disable(core.dss_ick);
-+ if (clks & DSS_CLK_FCK1)
-+ clk_disable(core.dss1_fck);
-+ if (clks & DSS_CLK_FCK2)
-+ clk_disable(core.dss2_fck);
-+ if (clks & DSS_CLK_54M)
-+ clk_disable(core.dss_54m_fck);
-+ if (clks & DSS_CLK_96M)
-+ clk_disable(core.dss_96m_fck);
-+
-+ core.num_clks_enabled -= num_clks;
-+}
-+
-+void dss_clk_disable(enum dss_clock clks)
-+{
-+ if (cpu_is_omap34xx()) {
-+ unsigned num_clks = count_clk_bits(clks);
-+
-+ BUG_ON(core.num_clks_enabled < num_clks);
-+
-+ if (core.num_clks_enabled == num_clks)
-+ save_all_ctx();
-+ }
-+
-+ dss_clk_disable_no_ctx(clks);
-+}
-+
-+static void dss_clk_enable_all_no_ctx(void)
-+{
-+ enum dss_clock clks;
-+
-+ clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
-+ if (cpu_is_omap34xx())
-+ clks |= DSS_CLK_96M;
-+ dss_clk_enable_no_ctx(clks);
-+}
-+
-+static void dss_clk_disable_all_no_ctx(void)
-+{
-+ enum dss_clock clks;
-+
-+ clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
-+ if (cpu_is_omap34xx())
-+ clks |= DSS_CLK_96M;
-+ dss_clk_disable_no_ctx(clks);
-+}
-+
-+static void dss_clk_disable_all(void)
-+{
-+ enum dss_clock clks;
-+
-+ clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
-+ if (cpu_is_omap34xx())
-+ clks |= DSS_CLK_96M;
-+ dss_clk_disable(clks);
-+}
-+
-+/* DEBUGFS */
-+#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
-+static void dss_debug_dump_clocks(struct seq_file *s)
-+{
-+ dss_dump_clocks(s);
-+ dispc_dump_clocks(s);
-+#ifdef CONFIG_OMAP2_DSS_DSI
-+ dsi_dump_clocks(s);
-+#endif
-+}
-+
-+static int dss_debug_show(struct seq_file *s, void *unused)
-+{
-+ void (*func)(struct seq_file *) = s->private;
-+ func(s);
-+ return 0;
-+}
-+
-+static int dss_debug_open(struct inode *inode, struct file *file)
-+{
-+ return single_open(file, dss_debug_show, inode->i_private);
-+}
-+
-+static const struct file_operations dss_debug_fops = {
-+ .open = dss_debug_open,
-+ .read = seq_read,
-+ .llseek = seq_lseek,
-+ .release = single_release,
-+};
-+
-+static struct dentry *dss_debugfs_dir;
-+
-+static int dss_initialize_debugfs(void)
-+{
-+ dss_debugfs_dir = debugfs_create_dir("omapdss", NULL);
-+ if (IS_ERR(dss_debugfs_dir)) {
-+ int err = PTR_ERR(dss_debugfs_dir);
-+ dss_debugfs_dir = NULL;
-+ return err;
-+ }
-+
-+ debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir,
-+ &dss_debug_dump_clocks, &dss_debug_fops);
-+
-+ debugfs_create_file("dss", S_IRUGO, dss_debugfs_dir,
-+ &dss_dump_regs, &dss_debug_fops);
-+ debugfs_create_file("dispc", S_IRUGO, dss_debugfs_dir,
-+ &dispc_dump_regs, &dss_debug_fops);
-+#ifdef CONFIG_OMAP2_DSS_RFBI
-+ debugfs_create_file("rfbi", S_IRUGO, dss_debugfs_dir,
-+ &rfbi_dump_regs, &dss_debug_fops);
-+#endif
-+#ifdef CONFIG_OMAP2_DSS_DSI
-+ debugfs_create_file("dsi", S_IRUGO, dss_debugfs_dir,
-+ &dsi_dump_regs, &dss_debug_fops);
-+#endif
-+ return 0;
-+}
-+
-+static void dss_uninitialize_debugfs(void)
-+{
-+ if (dss_debugfs_dir)
-+ debugfs_remove_recursive(dss_debugfs_dir);
-+}
-+#endif /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */
-+
-+
-+/* DSI powers */
-+int dss_dsi_power_up(void)
-+{
-+ struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
-+
-+ if (!pdata->dsi_power_up)
-+ return 0; /* presume power is always on then */
-+
-+ return pdata->dsi_power_up();
-+}
-+
-+void dss_dsi_power_down(void)
-+{
-+ struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
-+
-+ if (!pdata->dsi_power_down)
-+ return;
-+
-+ pdata->dsi_power_down();
-+}
-+
-+
-+
-+/* PLATFORM DEVICE */
-+static int omap_dss_probe(struct platform_device *pdev)
-+{
-+ int skip_init = 0;
-+ int r;
-+
-+ core.pdev = pdev;
-+
-+ r = dss_get_clocks();
-+ if (r)
-+ goto fail0;
-+
-+ dss_clk_enable_all_no_ctx();
-+
-+ core.ctx_id = dss_get_ctx_id();
-+ DSSDBG("initial ctx id %u\n", core.ctx_id);
-+
-+#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
-+ /* DISPC_CONTROL */
-+ if (omap_readl(0x48050440) & 1) /* LCD enabled? */
-+ skip_init = 1;
-+#endif
-+
-+ r = dss_init(skip_init);
-+ if (r) {
-+ DSSERR("Failed to initialize DSS\n");
-+ goto fail0;
-+ }
-+
-+#ifdef CONFIG_OMAP2_DSS_RFBI
-+ r = rfbi_init();
-+ if (r) {
-+ DSSERR("Failed to initialize rfbi\n");
-+ goto fail0;
-+ }
-+#endif
-+
-+ r = dpi_init();
-+ if (r) {
-+ DSSERR("Failed to initialize dpi\n");
-+ goto fail0;
-+ }
-+
-+ r = dispc_init();
-+ if (r) {
-+ DSSERR("Failed to initialize dispc\n");
-+ goto fail0;
-+ }
-+#ifdef CONFIG_OMAP2_DSS_VENC
-+ r = venc_init();
-+ if (r) {
-+ DSSERR("Failed to initialize venc\n");
-+ goto fail0;
-+ }
-+#endif
-+ if (cpu_is_omap34xx()) {
-+#ifdef CONFIG_OMAP2_DSS_SDI
-+ r = sdi_init(skip_init);
-+ if (r) {
-+ DSSERR("Failed to initialize SDI\n");
-+ goto fail0;
-+ }
-+#endif
-+#ifdef CONFIG_OMAP2_DSS_DSI
-+ r = dsi_init();
-+ if (r) {
-+ DSSERR("Failed to initialize DSI\n");
-+ goto fail0;
-+ }
-+#endif
-+ }
-+
-+#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
-+ r = dss_initialize_debugfs();
-+ if (r)
-+ goto fail0;
-+#endif
-+
-+ dss_init_displays(pdev);
-+ dss_init_overlay_managers(pdev);
-+ dss_init_overlays(pdev, def_disp_name);
-+
-+ dss_clk_disable_all();
-+
-+ return 0;
-+
-+ /* XXX fail correctly */
-+fail0:
-+ return r;
-+}
-+
-+static int omap_dss_remove(struct platform_device *pdev)
-+{
-+ int c;
-+
-+ dss_uninit_overlays(pdev);
-+ dss_uninit_overlay_managers(pdev);
-+ dss_uninit_displays(pdev);
-+
-+#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
-+ dss_uninitialize_debugfs();
-+#endif
-+
-+#ifdef CONFIG_OMAP2_DSS_VENC
-+ venc_exit();
-+#endif
-+ dispc_exit();
-+ dpi_exit();
-+#ifdef CONFIG_OMAP2_DSS_RFBI
-+ rfbi_exit();
-+#endif
-+ if (cpu_is_omap34xx()) {
-+#ifdef CONFIG_OMAP2_DSS_DSI
-+ dsi_exit();
-+#endif
-+#ifdef CONFIG_OMAP2_DSS_SDI
-+ sdi_exit();
-+#endif
-+ }
-+
-+ dss_exit();
-+
-+ /* these should be removed at some point */
-+ c = core.dss_ick->usecount;
-+ if (c > 0) {
-+ DSSERR("warning: dss_ick usecount %d, disabling\n", c);
-+ while (c-- > 0)
-+ clk_disable(core.dss_ick);
-+ }
-+
-+ c = core.dss1_fck->usecount;
-+ if (c > 0) {
-+ DSSERR("warning: dss1_fck usecount %d, disabling\n", c);
-+ while (c-- > 0)
-+ clk_disable(core.dss1_fck);
-+ }
-+
-+ c = core.dss2_fck->usecount;
-+ if (c > 0) {
-+ DSSERR("warning: dss2_fck usecount %d, disabling\n", c);
-+ while (c-- > 0)
-+ clk_disable(core.dss2_fck);
-+ }
-+
-+ c = core.dss_54m_fck->usecount;
-+ if (c > 0) {
-+ DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c);
-+ while (c-- > 0)
-+ clk_disable(core.dss_54m_fck);
-+ }
-+
-+ if (core.dss_96m_fck) {
-+ c = core.dss_96m_fck->usecount;
-+ if (c > 0) {
-+ DSSERR("warning: dss_96m_fck usecount %d, disabling\n",
-+ c);
-+ while (c-- > 0)
-+ clk_disable(core.dss_96m_fck);
-+ }
-+ }
-+
-+ dss_put_clocks();
-+
-+ return 0;
-+}
-+
-+static void omap_dss_shutdown(struct platform_device *pdev)
-+{
-+ DSSDBG("shutdown\n");
-+}
-+
-+static int omap_dss_suspend(struct platform_device *pdev, pm_message_t state)
-+{
-+ DSSDBG("suspend %d\n", state.event);
-+
-+ return dss_suspend_all_displays();
-+}
-+
-+static int omap_dss_resume(struct platform_device *pdev)
-+{
-+ DSSDBG("resume\n");
-+
-+ return dss_resume_all_displays();
-+}
-+
-+static struct platform_driver omap_dss_driver = {
-+ .probe = omap_dss_probe,
-+ .remove = omap_dss_remove,
-+ .shutdown = omap_dss_shutdown,
-+ .suspend = omap_dss_suspend,
-+ .resume = omap_dss_resume,
-+ .driver = {
-+ .name = "omapdss",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int __init omap_dss_init(void)
-+{
-+ return platform_driver_register(&omap_dss_driver);
-+}
-+
-+static void __exit omap_dss_exit(void)
-+{
-+ platform_driver_unregister(&omap_dss_driver);
-+}
-+
-+subsys_initcall(omap_dss_init);
-+module_exit(omap_dss_exit);
-+
-+
-+MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
-+MODULE_DESCRIPTION("OMAP2/3 Display Subsystem");
-+MODULE_LICENSE("GPL v2");
-+
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-new file mode 100644
-index 0000000..ffb5648
---- /dev/null
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -0,0 +1,2968 @@
-+/*
-+ * linux/drivers/video/omap2/dss/dispc.c
-+ *
-+ * Copyright (C) 2009 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * Some code and ideas taken from drivers/video/omap/ driver
-+ * by Imre Deak.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#define DSS_SUBSYS_NAME "DISPC"
-+
-+#include <linux/kernel.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/vmalloc.h>
-+#include <linux/clk.h>
-+#include <linux/io.h>
-+#include <linux/jiffies.h>
-+#include <linux/seq_file.h>
-+#include <linux/delay.h>
-+#include <linux/workqueue.h>
-+
-+#include <mach/sram.h>
-+#include <mach/board.h>
-+#include <mach/clock.h>
-+
-+#include <mach/display.h>
-+
-+#include "dss.h"
-+
-+/* DISPC */
-+#define DISPC_BASE 0x48050400
-+
-+#define DISPC_SZ_REGS SZ_1K
-+
-+struct dispc_reg { u16 idx; };
-+
-+#define DISPC_REG(idx) ((const struct dispc_reg) { idx })
-+
-+/* DISPC common */
-+#define DISPC_REVISION DISPC_REG(0x0000)
-+#define DISPC_SYSCONFIG DISPC_REG(0x0010)
-+#define DISPC_SYSSTATUS DISPC_REG(0x0014)
-+#define DISPC_IRQSTATUS DISPC_REG(0x0018)
-+#define DISPC_IRQENABLE DISPC_REG(0x001C)
-+#define DISPC_CONTROL DISPC_REG(0x0040)
-+#define DISPC_CONFIG DISPC_REG(0x0044)
-+#define DISPC_CAPABLE DISPC_REG(0x0048)
-+#define DISPC_DEFAULT_COLOR0 DISPC_REG(0x004C)
-+#define DISPC_DEFAULT_COLOR1 DISPC_REG(0x0050)
-+#define DISPC_TRANS_COLOR0 DISPC_REG(0x0054)
-+#define DISPC_TRANS_COLOR1 DISPC_REG(0x0058)
-+#define DISPC_LINE_STATUS DISPC_REG(0x005C)
-+#define DISPC_LINE_NUMBER DISPC_REG(0x0060)
-+#define DISPC_TIMING_H DISPC_REG(0x0064)
-+#define DISPC_TIMING_V DISPC_REG(0x0068)
-+#define DISPC_POL_FREQ DISPC_REG(0x006C)
-+#define DISPC_DIVISOR DISPC_REG(0x0070)
-+#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
-+#define DISPC_SIZE_DIG DISPC_REG(0x0078)
-+#define DISPC_SIZE_LCD DISPC_REG(0x007C)
-+
-+/* DISPC GFX plane */
-+#define DISPC_GFX_BA0 DISPC_REG(0x0080)
-+#define DISPC_GFX_BA1 DISPC_REG(0x0084)
-+#define DISPC_GFX_POSITION DISPC_REG(0x0088)
-+#define DISPC_GFX_SIZE DISPC_REG(0x008C)
-+#define DISPC_GFX_ATTRIBUTES DISPC_REG(0x00A0)
-+#define DISPC_GFX_FIFO_THRESHOLD DISPC_REG(0x00A4)
-+#define DISPC_GFX_FIFO_SIZE_STATUS DISPC_REG(0x00A8)
-+#define DISPC_GFX_ROW_INC DISPC_REG(0x00AC)
-+#define DISPC_GFX_PIXEL_INC DISPC_REG(0x00B0)
-+#define DISPC_GFX_WINDOW_SKIP DISPC_REG(0x00B4)
-+#define DISPC_GFX_TABLE_BA DISPC_REG(0x00B8)
-+
-+#define DISPC_DATA_CYCLE1 DISPC_REG(0x01D4)
-+#define DISPC_DATA_CYCLE2 DISPC_REG(0x01D8)
-+#define DISPC_DATA_CYCLE3 DISPC_REG(0x01DC)
-+
-+#define DISPC_CPR_COEF_R DISPC_REG(0x0220)
-+#define DISPC_CPR_COEF_G DISPC_REG(0x0224)
-+#define DISPC_CPR_COEF_B DISPC_REG(0x0228)
-+
-+#define DISPC_GFX_PRELOAD DISPC_REG(0x022C)
-+
-+/* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
-+#define DISPC_VID_REG(n, idx) DISPC_REG(0x00BC + (n)*0x90 + idx)
-+
-+#define DISPC_VID_BA0(n) DISPC_VID_REG(n, 0x0000)
-+#define DISPC_VID_BA1(n) DISPC_VID_REG(n, 0x0004)
-+#define DISPC_VID_POSITION(n) DISPC_VID_REG(n, 0x0008)
-+#define DISPC_VID_SIZE(n) DISPC_VID_REG(n, 0x000C)
-+#define DISPC_VID_ATTRIBUTES(n) DISPC_VID_REG(n, 0x0010)
-+#define DISPC_VID_FIFO_THRESHOLD(n) DISPC_VID_REG(n, 0x0014)
-+#define DISPC_VID_FIFO_SIZE_STATUS(n) DISPC_VID_REG(n, 0x0018)
-+#define DISPC_VID_ROW_INC(n) DISPC_VID_REG(n, 0x001C)
-+#define DISPC_VID_PIXEL_INC(n) DISPC_VID_REG(n, 0x0020)
-+#define DISPC_VID_FIR(n) DISPC_VID_REG(n, 0x0024)
-+#define DISPC_VID_PICTURE_SIZE(n) DISPC_VID_REG(n, 0x0028)
-+#define DISPC_VID_ACCU0(n) DISPC_VID_REG(n, 0x002C)
-+#define DISPC_VID_ACCU1(n) DISPC_VID_REG(n, 0x0030)
-+
-+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
-+#define DISPC_VID_FIR_COEF_H(n, i) DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
-+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
-+#define DISPC_VID_FIR_COEF_HV(n, i) DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
-+/* coef index i = {0, 1, 2, 3, 4} */
-+#define DISPC_VID_CONV_COEF(n, i) DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
-+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
-+#define DISPC_VID_FIR_COEF_V(n, i) DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
-+
-+#define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04)
-+
-+
-+#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
-+ DISPC_IRQ_OCP_ERR | \
-+ DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
-+ DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
-+ DISPC_IRQ_SYNC_LOST | \
-+ DISPC_IRQ_SYNC_LOST_DIGIT)
-+
-+#define DISPC_MAX_NR_ISRS 8
-+
-+struct omap_dispc_isr_data {
-+ omap_dispc_isr_t isr;
-+ void *arg;
-+ u32 mask;
-+};
-+
-+#define REG_GET(idx, start, end) \
-+ FLD_GET(dispc_read_reg(idx), start, end)
-+
-+#define REG_FLD_MOD(idx, val, start, end) \
-+ dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
-+
-+static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
-+ DISPC_VID_ATTRIBUTES(0),
-+ DISPC_VID_ATTRIBUTES(1) };
-+
-+static struct {
-+ void __iomem *base;
-+
-+ struct clk *dpll4_m4_ck;
-+
-+ spinlock_t irq_lock;
-+
-+ unsigned long cache_req_pck;
-+ unsigned long cache_prate;
-+ struct dispc_clock_info cache_cinfo;
-+
-+ u32 irq_error_mask;
-+ struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
-+
-+ spinlock_t error_lock;
-+ u32 error_irqs;
-+ struct work_struct error_work;
-+
-+ u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
-+} dispc;
-+
-+static void omap_dispc_set_irqs(void);
-+
-+static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
-+{
-+ __raw_writel(val, dispc.base + idx.idx);
-+}
-+
-+static inline u32 dispc_read_reg(const struct dispc_reg idx)
-+{
-+ return __raw_readl(dispc.base + idx.idx);
-+}
-+
-+#define SR(reg) \
-+ dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
-+#define RR(reg) \
-+ dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
-+
-+void dispc_save_context(void)
-+{
-+ if (cpu_is_omap24xx())
-+ return;
-+
-+ SR(SYSCONFIG);
-+ SR(IRQENABLE);
-+ SR(CONTROL);
-+ SR(CONFIG);
-+ SR(DEFAULT_COLOR0);
-+ SR(DEFAULT_COLOR1);
-+ SR(TRANS_COLOR0);
-+ SR(TRANS_COLOR1);
-+ SR(LINE_NUMBER);
-+ SR(TIMING_H);
-+ SR(TIMING_V);
-+ SR(POL_FREQ);
-+ SR(DIVISOR);
-+ SR(GLOBAL_ALPHA);
-+ SR(SIZE_DIG);
-+ SR(SIZE_LCD);
-+
-+ SR(GFX_BA0);
-+ SR(GFX_BA1);
-+ SR(GFX_POSITION);
-+ SR(GFX_SIZE);
-+ SR(GFX_ATTRIBUTES);
-+ SR(GFX_FIFO_THRESHOLD);
-+ SR(GFX_ROW_INC);
-+ SR(GFX_PIXEL_INC);
-+ SR(GFX_WINDOW_SKIP);
-+ SR(GFX_TABLE_BA);
-+
-+ SR(DATA_CYCLE1);
-+ SR(DATA_CYCLE2);
-+ SR(DATA_CYCLE3);
-+
-+ SR(CPR_COEF_R);
-+ SR(CPR_COEF_G);
-+ SR(CPR_COEF_B);
-+
-+ SR(GFX_PRELOAD);
-+
-+ /* VID1 */
-+ SR(VID_BA0(0));
-+ SR(VID_BA1(0));
-+ SR(VID_POSITION(0));
-+ SR(VID_SIZE(0));
-+ SR(VID_ATTRIBUTES(0));
-+ SR(VID_FIFO_THRESHOLD(0));
-+ SR(VID_ROW_INC(0));
-+ SR(VID_PIXEL_INC(0));
-+ SR(VID_FIR(0));
-+ SR(VID_PICTURE_SIZE(0));
-+ SR(VID_ACCU0(0));
-+ SR(VID_ACCU1(0));
-+
-+ SR(VID_FIR_COEF_H(0, 0));
-+ SR(VID_FIR_COEF_H(0, 1));
-+ SR(VID_FIR_COEF_H(0, 2));
-+ SR(VID_FIR_COEF_H(0, 3));
-+ SR(VID_FIR_COEF_H(0, 4));
-+ SR(VID_FIR_COEF_H(0, 5));
-+ SR(VID_FIR_COEF_H(0, 6));
-+ SR(VID_FIR_COEF_H(0, 7));
-+
-+ SR(VID_FIR_COEF_HV(0, 0));
-+ SR(VID_FIR_COEF_HV(0, 1));
-+ SR(VID_FIR_COEF_HV(0, 2));
-+ SR(VID_FIR_COEF_HV(0, 3));
-+ SR(VID_FIR_COEF_HV(0, 4));
-+ SR(VID_FIR_COEF_HV(0, 5));
-+ SR(VID_FIR_COEF_HV(0, 6));
-+ SR(VID_FIR_COEF_HV(0, 7));
-+
-+ SR(VID_CONV_COEF(0, 0));
-+ SR(VID_CONV_COEF(0, 1));
-+ SR(VID_CONV_COEF(0, 2));
-+ SR(VID_CONV_COEF(0, 3));
-+ SR(VID_CONV_COEF(0, 4));
-+
-+ SR(VID_FIR_COEF_V(0, 0));
-+ SR(VID_FIR_COEF_V(0, 1));
-+ SR(VID_FIR_COEF_V(0, 2));
-+ SR(VID_FIR_COEF_V(0, 3));
-+ SR(VID_FIR_COEF_V(0, 4));
-+ SR(VID_FIR_COEF_V(0, 5));
-+ SR(VID_FIR_COEF_V(0, 6));
-+ SR(VID_FIR_COEF_V(0, 7));
-+
-+ SR(VID_PRELOAD(0));
-+
-+ /* VID2 */
-+ SR(VID_BA0(1));
-+ SR(VID_BA1(1));
-+ SR(VID_POSITION(1));
-+ SR(VID_SIZE(1));
-+ SR(VID_ATTRIBUTES(1));
-+ SR(VID_FIFO_THRESHOLD(1));
-+ SR(VID_ROW_INC(1));
-+ SR(VID_PIXEL_INC(1));
-+ SR(VID_FIR(1));
-+ SR(VID_PICTURE_SIZE(1));
-+ SR(VID_ACCU0(1));
-+ SR(VID_ACCU1(1));
-+
-+ SR(VID_FIR_COEF_H(1, 0));
-+ SR(VID_FIR_COEF_H(1, 1));
-+ SR(VID_FIR_COEF_H(1, 2));
-+ SR(VID_FIR_COEF_H(1, 3));
-+ SR(VID_FIR_COEF_H(1, 4));
-+ SR(VID_FIR_COEF_H(1, 5));
-+ SR(VID_FIR_COEF_H(1, 6));
-+ SR(VID_FIR_COEF_H(1, 7));
-+
-+ SR(VID_FIR_COEF_HV(1, 0));
-+ SR(VID_FIR_COEF_HV(1, 1));
-+ SR(VID_FIR_COEF_HV(1, 2));
-+ SR(VID_FIR_COEF_HV(1, 3));
-+ SR(VID_FIR_COEF_HV(1, 4));
-+ SR(VID_FIR_COEF_HV(1, 5));
-+ SR(VID_FIR_COEF_HV(1, 6));
-+ SR(VID_FIR_COEF_HV(1, 7));
-+
-+ SR(VID_CONV_COEF(1, 0));
-+ SR(VID_CONV_COEF(1, 1));
-+ SR(VID_CONV_COEF(1, 2));
-+ SR(VID_CONV_COEF(1, 3));
-+ SR(VID_CONV_COEF(1, 4));
-+
-+ SR(VID_FIR_COEF_V(1, 0));
-+ SR(VID_FIR_COEF_V(1, 1));
-+ SR(VID_FIR_COEF_V(1, 2));
-+ SR(VID_FIR_COEF_V(1, 3));
-+ SR(VID_FIR_COEF_V(1, 4));
-+ SR(VID_FIR_COEF_V(1, 5));
-+ SR(VID_FIR_COEF_V(1, 6));
-+ SR(VID_FIR_COEF_V(1, 7));
-+
-+ SR(VID_PRELOAD(1));
-+}
-+
-+void dispc_restore_context(void)
-+{
-+ RR(SYSCONFIG);
-+ RR(IRQENABLE);
-+ /*RR(CONTROL);*/
-+ RR(CONFIG);
-+ RR(DEFAULT_COLOR0);
-+ RR(DEFAULT_COLOR1);
-+ RR(TRANS_COLOR0);
-+ RR(TRANS_COLOR1);
-+ RR(LINE_NUMBER);
-+ RR(TIMING_H);
-+ RR(TIMING_V);
-+ RR(POL_FREQ);
-+ RR(DIVISOR);
-+ RR(GLOBAL_ALPHA);
-+ RR(SIZE_DIG);
-+ RR(SIZE_LCD);
-+
-+ RR(GFX_BA0);
-+ RR(GFX_BA1);
-+ RR(GFX_POSITION);
-+ RR(GFX_SIZE);
-+ RR(GFX_ATTRIBUTES);
-+ RR(GFX_FIFO_THRESHOLD);
-+ RR(GFX_ROW_INC);
-+ RR(GFX_PIXEL_INC);
-+ RR(GFX_WINDOW_SKIP);
-+ RR(GFX_TABLE_BA);
-+
-+ RR(DATA_CYCLE1);
-+ RR(DATA_CYCLE2);
-+ RR(DATA_CYCLE3);
-+
-+ RR(CPR_COEF_R);
-+ RR(CPR_COEF_G);
-+ RR(CPR_COEF_B);
-+
-+ RR(GFX_PRELOAD);
-+
-+ /* VID1 */
-+ RR(VID_BA0(0));
-+ RR(VID_BA1(0));
-+ RR(VID_POSITION(0));
-+ RR(VID_SIZE(0));
-+ RR(VID_ATTRIBUTES(0));
-+ RR(VID_FIFO_THRESHOLD(0));
-+ RR(VID_ROW_INC(0));
-+ RR(VID_PIXEL_INC(0));
-+ RR(VID_FIR(0));
-+ RR(VID_PICTURE_SIZE(0));
-+ RR(VID_ACCU0(0));
-+ RR(VID_ACCU1(0));
-+
-+ RR(VID_FIR_COEF_H(0, 0));
-+ RR(VID_FIR_COEF_H(0, 1));
-+ RR(VID_FIR_COEF_H(0, 2));
-+ RR(VID_FIR_COEF_H(0, 3));
-+ RR(VID_FIR_COEF_H(0, 4));
-+ RR(VID_FIR_COEF_H(0, 5));
-+ RR(VID_FIR_COEF_H(0, 6));
-+ RR(VID_FIR_COEF_H(0, 7));
-+
-+ RR(VID_FIR_COEF_HV(0, 0));
-+ RR(VID_FIR_COEF_HV(0, 1));
-+ RR(VID_FIR_COEF_HV(0, 2));
-+ RR(VID_FIR_COEF_HV(0, 3));
-+ RR(VID_FIR_COEF_HV(0, 4));
-+ RR(VID_FIR_COEF_HV(0, 5));
-+ RR(VID_FIR_COEF_HV(0, 6));
-+ RR(VID_FIR_COEF_HV(0, 7));
-+
-+ RR(VID_CONV_COEF(0, 0));
-+ RR(VID_CONV_COEF(0, 1));
-+ RR(VID_CONV_COEF(0, 2));
-+ RR(VID_CONV_COEF(0, 3));
-+ RR(VID_CONV_COEF(0, 4));
-+
-+ RR(VID_FIR_COEF_V(0, 0));
-+ RR(VID_FIR_COEF_V(0, 1));
-+ RR(VID_FIR_COEF_V(0, 2));
-+ RR(VID_FIR_COEF_V(0, 3));
-+ RR(VID_FIR_COEF_V(0, 4));
-+ RR(VID_FIR_COEF_V(0, 5));
-+ RR(VID_FIR_COEF_V(0, 6));
-+ RR(VID_FIR_COEF_V(0, 7));
-+
-+ RR(VID_PRELOAD(0));
-+
-+ /* VID2 */
-+ RR(VID_BA0(1));
-+ RR(VID_BA1(1));
-+ RR(VID_POSITION(1));
-+ RR(VID_SIZE(1));
-+ RR(VID_ATTRIBUTES(1));
-+ RR(VID_FIFO_THRESHOLD(1));
-+ RR(VID_ROW_INC(1));
-+ RR(VID_PIXEL_INC(1));
-+ RR(VID_FIR(1));
-+ RR(VID_PICTURE_SIZE(1));
-+ RR(VID_ACCU0(1));
-+ RR(VID_ACCU1(1));
-+
-+ RR(VID_FIR_COEF_H(1, 0));
-+ RR(VID_FIR_COEF_H(1, 1));
-+ RR(VID_FIR_COEF_H(1, 2));
-+ RR(VID_FIR_COEF_H(1, 3));
-+ RR(VID_FIR_COEF_H(1, 4));
-+ RR(VID_FIR_COEF_H(1, 5));
-+ RR(VID_FIR_COEF_H(1, 6));
-+ RR(VID_FIR_COEF_H(1, 7));
-+
-+ RR(VID_FIR_COEF_HV(1, 0));
-+ RR(VID_FIR_COEF_HV(1, 1));
-+ RR(VID_FIR_COEF_HV(1, 2));
-+ RR(VID_FIR_COEF_HV(1, 3));
-+ RR(VID_FIR_COEF_HV(1, 4));
-+ RR(VID_FIR_COEF_HV(1, 5));
-+ RR(VID_FIR_COEF_HV(1, 6));
-+ RR(VID_FIR_COEF_HV(1, 7));
-+
-+ RR(VID_CONV_COEF(1, 0));
-+ RR(VID_CONV_COEF(1, 1));
-+ RR(VID_CONV_COEF(1, 2));
-+ RR(VID_CONV_COEF(1, 3));
-+ RR(VID_CONV_COEF(1, 4));
-+
-+ RR(VID_FIR_COEF_V(1, 0));
-+ RR(VID_FIR_COEF_V(1, 1));
-+ RR(VID_FIR_COEF_V(1, 2));
-+ RR(VID_FIR_COEF_V(1, 3));
-+ RR(VID_FIR_COEF_V(1, 4));
-+ RR(VID_FIR_COEF_V(1, 5));
-+ RR(VID_FIR_COEF_V(1, 6));
-+ RR(VID_FIR_COEF_V(1, 7));
-+
-+ RR(VID_PRELOAD(1));
-+
-+ /* enable last, because LCD & DIGIT enable are here */
-+ RR(CONTROL);
-+}
-+
-+#undef SR
-+#undef RR
-+
-+static inline void enable_clocks(bool enable)
-+{
-+ if (enable)
-+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+ else
-+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+}
-+
-+void dispc_go(enum omap_channel channel)
-+{
-+ int bit;
-+ unsigned long tmo;
-+
-+ enable_clocks(1);
-+
-+ if (channel == OMAP_DSS_CHANNEL_LCD)
-+ bit = 0; /* LCDENABLE */
-+ else
-+ bit = 1; /* DIGITALENABLE */
-+
-+ /* if the channel is not enabled, we don't need GO */
-+ if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
-+ goto end;
-+
-+ if (channel == OMAP_DSS_CHANNEL_LCD)
-+ bit = 5; /* GOLCD */
-+ else
-+ bit = 6; /* GODIGIT */
-+
-+ tmo = jiffies + msecs_to_jiffies(200);
-+ while (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
-+ if (time_after(jiffies, tmo)) {
-+ DSSERR("timeout waiting GO flag\n");
-+ goto end;
-+ }
-+ cpu_relax();
-+ }
-+
-+ DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
-+
-+ REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
-+end:
-+ enable_clocks(0);
-+}
-+
-+static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
-+{
-+ BUG_ON(plane == OMAP_DSS_GFX);
-+
-+ dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
-+}
-+
-+static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
-+{
-+ BUG_ON(plane == OMAP_DSS_GFX);
-+
-+ dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
-+}
-+
-+static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
-+{
-+ BUG_ON(plane == OMAP_DSS_GFX);
-+
-+ dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
-+}
-+
-+static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
-+ int vscaleup, int five_taps)
-+{
-+ /* Coefficients for horizontal up-sampling */
-+ static const u32 coef_hup[8] = {
-+ 0x00800000,
-+ 0x0D7CF800,
-+ 0x1E70F5FF,
-+ 0x335FF5FE,
-+ 0xF74949F7,
-+ 0xF55F33FB,
-+ 0xF5701EFE,
-+ 0xF87C0DFF,
-+ };
-+
-+ /* Coefficients for horizontal down-sampling */
-+ static const u32 coef_hdown[8] = {
-+ 0x24382400,
-+ 0x28371FFE,
-+ 0x2C361BFB,
-+ 0x303516F9,
-+ 0x11343311,
-+ 0x1635300C,
-+ 0x1B362C08,
-+ 0x1F372804,
-+ };
-+
-+ /* Coefficients for horizontal and vertical up-sampling */
-+ static const u32 coef_hvup[2][8] = {
-+ {
-+ 0x00800000,
-+ 0x037B02FF,
-+ 0x0C6F05FE,
-+ 0x205907FB,
-+ 0x00404000,
-+ 0x075920FE,
-+ 0x056F0CFF,
-+ 0x027B0300,
-+ },
-+ {
-+ 0x00800000,
-+ 0x0D7CF8FF,
-+ 0x1E70F5FE,
-+ 0x335FF5FB,
-+ 0xF7404000,
-+ 0xF55F33FE,
-+ 0xF5701EFF,
-+ 0xF87C0D00,
-+ },
-+ };
-+
-+ /* Coefficients for horizontal and vertical down-sampling */
-+ static const u32 coef_hvdown[2][8] = {
-+ {
-+ 0x24382400,
-+ 0x28391F04,
-+ 0x2D381B08,
-+ 0x3237170C,
-+ 0x123737F7,
-+ 0x173732F9,
-+ 0x1B382DFB,
-+ 0x1F3928FE,
-+ },
-+ {
-+ 0x24382400,
-+ 0x28371F04,
-+ 0x2C361B08,
-+ 0x3035160C,
-+ 0x113433F7,
-+ 0x163530F9,
-+ 0x1B362CFB,
-+ 0x1F3728FE,
-+ },
-+ };
-+
-+ /* Coefficients for vertical up-sampling */
-+ static const u32 coef_vup[8] = {
-+ 0x00000000,
-+ 0x0000FF00,
-+ 0x0000FEFF,
-+ 0x0000FBFE,
-+ 0x000000F7,
-+ 0x0000FEFB,
-+ 0x0000FFFE,
-+ 0x000000FF,
-+ };
-+
-+
-+ /* Coefficients for vertical down-sampling */
-+ static const u32 coef_vdown[8] = {
-+ 0x00000000,
-+ 0x000004FE,
-+ 0x000008FB,
-+ 0x00000CF9,
-+ 0x0000F711,
-+ 0x0000F90C,
-+ 0x0000FB08,
-+ 0x0000FE04,
-+ };
-+
-+ const u32 *h_coef;
-+ const u32 *hv_coef;
-+ const u32 *hv_coef_mod;
-+ const u32 *v_coef;
-+ int i;
-+
-+ if (hscaleup)
-+ h_coef = coef_hup;
-+ else
-+ h_coef = coef_hdown;
-+
-+ if (vscaleup) {
-+ hv_coef = coef_hvup[five_taps];
-+ v_coef = coef_vup;
-+
-+ if (hscaleup)
-+ hv_coef_mod = NULL;
-+ else
-+ hv_coef_mod = coef_hvdown[five_taps];
-+ } else {
-+ hv_coef = coef_hvdown[five_taps];
-+ v_coef = coef_vdown;
-+
-+ if (hscaleup)
-+ hv_coef_mod = coef_hvup[five_taps];
-+ else
-+ hv_coef_mod = NULL;
-+ }
-+
-+ for (i = 0; i < 8; i++) {
-+ u32 h, hv;
-+
-+ h = h_coef[i];
-+
-+ hv = hv_coef[i];
-+
-+ if (hv_coef_mod) {
-+ hv &= 0xffffff00;
-+ hv |= (hv_coef_mod[i] & 0xff);
-+ }
-+
-+ _dispc_write_firh_reg(plane, i, h);
-+ _dispc_write_firhv_reg(plane, i, hv);
-+ }
-+
-+ if (!five_taps)
-+ return;
-+
-+ for (i = 0; i < 8; i++) {
-+ u32 v;
-+ v = v_coef[i];
-+ _dispc_write_firv_reg(plane, i, v);
-+ }
-+}
-+
-+static void _dispc_setup_color_conv_coef(void)
-+{
-+ const struct color_conv_coef {
-+ int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
-+ int full_range;
-+ } ctbl_bt601_5 = {
-+ 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
-+ };
-+
-+ const struct color_conv_coef *ct;
-+
-+#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
-+
-+ ct = &ctbl_bt601_5;
-+
-+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
-+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy, ct->rcb));
-+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
-+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
-+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0, ct->bcb));
-+
-+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
-+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy, ct->rcb));
-+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
-+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
-+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0, ct->bcb));
-+
-+#undef CVAL
-+
-+ REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
-+ REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
-+}
-+
-+
-+static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
-+{
-+ const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
-+ DISPC_VID_BA0(0),
-+ DISPC_VID_BA0(1) };
-+
-+ dispc_write_reg(ba0_reg[plane], paddr);
-+}
-+
-+static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
-+{
-+ const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
-+ DISPC_VID_BA1(0),
-+ DISPC_VID_BA1(1) };
-+
-+ dispc_write_reg(ba1_reg[plane], paddr);
-+}
-+
-+static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
-+{
-+ const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
-+ DISPC_VID_POSITION(0),
-+ DISPC_VID_POSITION(1) };
-+
-+ u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
-+ dispc_write_reg(pos_reg[plane], val);
-+}
-+
-+static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
-+{
-+ const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
-+ DISPC_VID_PICTURE_SIZE(0),
-+ DISPC_VID_PICTURE_SIZE(1) };
-+ u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
-+ dispc_write_reg(siz_reg[plane], val);
-+}
-+
-+static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
-+{
-+ u32 val;
-+ const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
-+ DISPC_VID_SIZE(1) };
-+
-+ BUG_ON(plane == OMAP_DSS_GFX);
-+
-+ val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
-+ dispc_write_reg(vsi_reg[plane-1], val);
-+}
-+
-+static void _dispc_set_pix_inc(enum omap_plane plane, u16 inc)
-+{
-+ const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
-+ DISPC_VID_PIXEL_INC(0),
-+ DISPC_VID_PIXEL_INC(1) };
-+
-+ dispc_write_reg(ri_reg[plane], inc);
-+}
-+
-+static void _dispc_set_row_inc(enum omap_plane plane, u16 inc)
-+{
-+ const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
-+ DISPC_VID_ROW_INC(0),
-+ DISPC_VID_ROW_INC(1) };
-+
-+ dispc_write_reg(ri_reg[plane], inc);
-+}
-+
-+static void _dispc_set_color_mode(enum omap_plane plane,
-+ enum omap_color_mode color_mode)
-+{
-+ u32 m = 0;
-+
-+ switch (color_mode) {
-+ case OMAP_DSS_COLOR_CLUT1:
-+ m = 0x0; break;
-+ case OMAP_DSS_COLOR_CLUT2:
-+ m = 0x1; break;
-+ case OMAP_DSS_COLOR_CLUT4:
-+ m = 0x2; break;
-+ case OMAP_DSS_COLOR_CLUT8:
-+ m = 0x3; break;
-+ case OMAP_DSS_COLOR_RGB12U:
-+ m = 0x4; break;
-+ case OMAP_DSS_COLOR_ARGB16:
-+ m = 0x5; break;
-+ case OMAP_DSS_COLOR_RGB16:
-+ m = 0x6; break;
-+ case OMAP_DSS_COLOR_RGB24U:
-+ m = 0x8; break;
-+ case OMAP_DSS_COLOR_RGB24P:
-+ m = 0x9; break;
-+ case OMAP_DSS_COLOR_YUV2:
-+ m = 0xa; break;
-+ case OMAP_DSS_COLOR_UYVY:
-+ m = 0xb; break;
-+ case OMAP_DSS_COLOR_ARGB32:
-+ m = 0xc; break;
-+ case OMAP_DSS_COLOR_RGBA32:
-+ m = 0xd; break;
-+ case OMAP_DSS_COLOR_RGBX32:
-+ m = 0xe; break;
-+ default:
-+ BUG(); break;
-+ }
-+
-+ REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
-+}
-+
-+static void _dispc_set_channel_out(enum omap_plane plane,
-+ enum omap_channel channel)
-+{
-+ int shift;
-+ u32 val;
-+
-+ switch (plane) {
-+ case OMAP_DSS_GFX:
-+ shift = 8;
-+ break;
-+ case OMAP_DSS_VIDEO1:
-+ case OMAP_DSS_VIDEO2:
-+ shift = 16;
-+ break;
-+ default:
-+ BUG();
-+ return;
-+ }
-+
-+ val = dispc_read_reg(dispc_reg_att[plane]);
-+ val = FLD_MOD(val, channel, shift, shift);
-+ dispc_write_reg(dispc_reg_att[plane], val);
-+}
-+
-+void dispc_set_burst_size(enum omap_plane plane,
-+ enum omap_burst_size burst_size)
-+{
-+ int shift;
-+ u32 val;
-+
-+ enable_clocks(1);
-+
-+ switch (plane) {
-+ case OMAP_DSS_GFX:
-+ shift = 6;
-+ break;
-+ case OMAP_DSS_VIDEO1:
-+ case OMAP_DSS_VIDEO2:
-+ shift = 14;
-+ break;
-+ default:
-+ BUG();
-+ return;
-+ }
-+
-+ val = dispc_read_reg(dispc_reg_att[plane]);
-+ val = FLD_MOD(val, burst_size, shift+1, shift);
-+ dispc_write_reg(dispc_reg_att[plane], val);
-+
-+ enable_clocks(0);
-+}
-+
-+static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
-+{
-+ u32 val;
-+
-+ BUG_ON(plane == OMAP_DSS_GFX);
-+
-+ val = dispc_read_reg(dispc_reg_att[plane]);
-+ val = FLD_MOD(val, enable, 9, 9);
-+ dispc_write_reg(dispc_reg_att[plane], val);
-+}
-+
-+void dispc_set_lcd_size(u16 width, u16 height)
-+{
-+ u32 val;
-+ BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
-+ val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
-+ enable_clocks(1);
-+ dispc_write_reg(DISPC_SIZE_LCD, val);
-+ enable_clocks(0);
-+}
-+
-+void dispc_set_digit_size(u16 width, u16 height)
-+{
-+ u32 val;
-+ BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
-+ val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
-+ enable_clocks(1);
-+ dispc_write_reg(DISPC_SIZE_DIG, val);
-+ enable_clocks(0);
-+}
-+
-+u32 dispc_get_plane_fifo_size(enum omap_plane plane)
-+{
-+ const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
-+ DISPC_VID_FIFO_SIZE_STATUS(0),
-+ DISPC_VID_FIFO_SIZE_STATUS(1) };
-+ u32 size;
-+
-+ enable_clocks(1);
-+
-+ if (cpu_is_omap24xx())
-+ size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
-+ else if (cpu_is_omap34xx())
-+ size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
-+ else
-+ BUG();
-+
-+ if (cpu_is_omap34xx()) {
-+ /* FIFOMERGE */
-+ if (REG_GET(DISPC_CONFIG, 14, 14))
-+ size *= 3;
-+ }
-+
-+ enable_clocks(0);
-+
-+ return size;
-+}
-+
-+void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
-+{
-+ const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
-+ DISPC_VID_FIFO_THRESHOLD(0),
-+ DISPC_VID_FIFO_THRESHOLD(1) };
-+ u32 size;
-+
-+ enable_clocks(1);
-+
-+ size = dispc_get_plane_fifo_size(plane);
-+
-+ BUG_ON(low > size || high > size);
-+
-+ DSSDBG("fifo(%d) size %d, low/high old %u/%u, new %u/%u\n",
-+ plane, size,
-+ REG_GET(ftrs_reg[plane], 11, 0),
-+ REG_GET(ftrs_reg[plane], 27, 16),
-+ low, high);
-+
-+ if (cpu_is_omap24xx())
-+ dispc_write_reg(ftrs_reg[plane],
-+ FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
-+ else
-+ dispc_write_reg(ftrs_reg[plane],
-+ FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
-+
-+ enable_clocks(0);
-+}
-+
-+void dispc_enable_fifomerge(bool enable)
-+{
-+ enable_clocks(1);
-+
-+ DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
-+ REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
-+
-+ enable_clocks(0);
-+}
-+
-+static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
-+{
-+ u32 val;
-+ const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
-+ DISPC_VID_FIR(1) };
-+
-+ BUG_ON(plane == OMAP_DSS_GFX);
-+
-+ val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
-+ dispc_write_reg(fir_reg[plane-1], val);
-+}
-+
-+static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
-+{
-+ u32 val;
-+ const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
-+ DISPC_VID_ACCU0(1) };
-+
-+ BUG_ON(plane == OMAP_DSS_GFX);
-+
-+ val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
-+ dispc_write_reg(ac0_reg[plane-1], val);
-+}
-+
-+static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
-+{
-+ u32 val;
-+ const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
-+ DISPC_VID_ACCU1(1) };
-+
-+ BUG_ON(plane == OMAP_DSS_GFX);
-+
-+ val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
-+ dispc_write_reg(ac1_reg[plane-1], val);
-+}
-+
-+
-+static void _dispc_set_scaling(enum omap_plane plane,
-+ u16 orig_width, u16 orig_height,
-+ u16 out_width, u16 out_height,
-+ bool ilace)
-+{
-+ int fir_hinc;
-+ int fir_vinc;
-+ int hscaleup, vscaleup, five_taps;
-+ int fieldmode = 0;
-+ int accu0 = 0;
-+ int accu1 = 0;
-+ u32 l;
-+
-+ BUG_ON(plane == OMAP_DSS_GFX);
-+
-+ hscaleup = orig_width <= out_width;
-+ vscaleup = orig_height <= out_height;
-+ five_taps = orig_height > out_height * 2;
-+
-+ _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
-+
-+ if (!orig_width || orig_width == out_width)
-+ fir_hinc = 0;
-+ else
-+ fir_hinc = 1024 * orig_width / out_width;
-+
-+ if (!orig_height || orig_height == out_height)
-+ fir_vinc = 0;
-+ else
-+ fir_vinc = 1024 * orig_height / out_height;
-+
-+ _dispc_set_fir(plane, fir_hinc, fir_vinc);
-+
-+ l = dispc_read_reg(dispc_reg_att[plane]);
-+ l &= ~((0x0f << 5) | (0x3 << 21));
-+
-+ l |= fir_hinc ? (1 << 5) : 0;
-+ l |= fir_vinc ? (1 << 6) : 0;
-+
-+ l |= hscaleup ? 0 : (1 << 7);
-+ l |= vscaleup ? 0 : (1 << 8);
-+
-+ l |= five_taps ? (1 << 21) : 0;
-+ l |= five_taps ? (1 << 22) : 0;
-+
-+ dispc_write_reg(dispc_reg_att[plane], l);
-+
-+ if (ilace) {
-+ if (fieldmode) {
-+ accu0 = fir_vinc / 2;
-+ accu1 = 0;
-+ } else {
-+ accu0 = 0;
-+ accu1 = fir_vinc / 2;
-+ if (accu1 >= 1024/2) {
-+ accu0 = 1024/2;
-+ accu1 -= accu0;
-+ }
-+ }
-+ }
-+
-+ _dispc_set_vid_accu0(plane, 0, accu0);
-+ _dispc_set_vid_accu1(plane, 0, accu1);
-+}
-+
-+static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
-+ bool mirroring, enum omap_color_mode color_mode)
-+{
-+ if (color_mode == OMAP_DSS_COLOR_YUV2 ||
-+ color_mode == OMAP_DSS_COLOR_UYVY) {
-+ int vidrot = 0;
-+
-+ if (mirroring) {
-+ switch (rotation) {
-+ case 0: vidrot = 2; break;
-+ case 1: vidrot = 3; break;
-+ case 2: vidrot = 0; break;
-+ case 3: vidrot = 1; break;
-+ }
-+ } else {
-+ switch (rotation) {
-+ case 0: vidrot = 0; break;
-+ case 1: vidrot = 1; break;
-+ case 2: vidrot = 2; break;
-+ case 3: vidrot = 1; break;
-+ }
-+ }
-+
-+ REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
-+
-+ if (rotation == 1 || rotation == 3)
-+ REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
-+ else
-+ REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
-+ } else {
-+ REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
-+ REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
-+ }
-+}
-+
-+static int pixinc(int pixels, u8 ps)
-+{
-+ if (pixels == 1)
-+ return 1;
-+ else if (pixels > 1)
-+ return 1 + (pixels - 1) * ps;
-+ else if (pixels < 0)
-+ return 1 - (-pixels + 1) * ps;
-+ else
-+ BUG();
-+}
-+
-+static void calc_rotation_offset(u8 rotation, bool mirror,
-+ u16 screen_width,
-+ u16 width, u16 height,
-+ enum omap_color_mode color_mode, bool fieldmode,
-+ unsigned *offset0, unsigned *offset1,
-+ u16 *row_inc, u16 *pix_inc)
-+{
-+ u8 ps;
-+ u16 fbw, fbh;
-+
-+ switch (color_mode) {
-+ case OMAP_DSS_COLOR_RGB16:
-+ case OMAP_DSS_COLOR_ARGB16:
-+ ps = 2;
-+ break;
-+
-+ case OMAP_DSS_COLOR_RGB24P:
-+ ps = 3;
-+ break;
-+
-+ case OMAP_DSS_COLOR_RGB24U:
-+ case OMAP_DSS_COLOR_ARGB32:
-+ case OMAP_DSS_COLOR_RGBA32:
-+ case OMAP_DSS_COLOR_RGBX32:
-+ ps = 4;
-+ break;
-+
-+ case OMAP_DSS_COLOR_YUV2:
-+ case OMAP_DSS_COLOR_UYVY:
-+ ps = 2;
-+ break;
-+ default:
-+ BUG();
-+ return;
-+ }
-+
-+ DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
-+ width, height);
-+
-+ /* width & height are overlay sizes, convert to fb sizes */
-+
-+ if (rotation == 0 || rotation == 2) {
-+ fbw = width;
-+ fbh = height;
-+ } else {
-+ fbw = height;
-+ fbh = width;
-+ }
-+
-+ switch (rotation + mirror * 4) {
-+ case 0:
-+ *offset0 = 0;
-+ if (fieldmode)
-+ *offset1 = screen_width * ps;
-+ else
-+ *offset1 = 0;
-+ *row_inc = pixinc(1 + (screen_width - fbw) +
-+ (fieldmode ? screen_width : 0),
-+ ps);
-+ *pix_inc = pixinc(1, ps);
-+ break;
-+ case 1:
-+ *offset0 = screen_width * (fbh - 1) * ps;
-+ if (fieldmode)
-+ *offset1 = *offset0 + ps;
-+ else
-+ *offset1 = *offset0;
-+ *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
-+ (fieldmode ? 1 : 0), ps);
-+ *pix_inc = pixinc(-screen_width, ps);
-+ break;
-+ case 2:
-+ *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
-+ if (fieldmode)
-+ *offset1 = *offset0 - screen_width * ps;
-+ else
-+ *offset1 = *offset0;
-+ *row_inc = pixinc(-1 -
-+ (screen_width - fbw) -
-+ (fieldmode ? screen_width : 0),
-+ ps);
-+ *pix_inc = pixinc(-1, ps);
-+ break;
-+ case 3:
-+ *offset0 = (fbw - 1) * ps;
-+ if (fieldmode)
-+ *offset1 = *offset0 - ps;
-+ else
-+ *offset1 = *offset0;
-+ *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
-+ (fieldmode ? 1 : 0), ps);
-+ *pix_inc = pixinc(screen_width, ps);
-+ break;
-+
-+ /* mirroring */
-+ case 0 + 4:
-+ *offset0 = (fbw - 1) * ps;
-+ if (fieldmode)
-+ *offset1 = *offset0 + screen_width * ps;
-+ else
-+ *offset1 = *offset0;
-+ *row_inc = pixinc(screen_width * 2 - 1 +
-+ (fieldmode ? screen_width : 0),
-+ ps);
-+ *pix_inc = pixinc(-1, ps);
-+ break;
-+
-+ case 1 + 4:
-+ *offset0 = 0;
-+ if (fieldmode)
-+ *offset1 = *offset0 + screen_width * ps;
-+ else
-+ *offset1 = *offset0;
-+ *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
-+ (fieldmode ? 1 : 0),
-+ ps);
-+ *pix_inc = pixinc(screen_width, ps);
-+ break;
-+
-+ case 2 + 4:
-+ *offset0 = screen_width * (fbh - 1) * ps;
-+ if (fieldmode)
-+ *offset1 = *offset0 + screen_width * ps;
-+ else
-+ *offset1 = *offset0;
-+ *row_inc = pixinc(1 - screen_width * 2 -
-+ (fieldmode ? screen_width : 0),
-+ ps);
-+ *pix_inc = pixinc(1, ps);
-+ break;
-+
-+ case 3 + 4:
-+ *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
-+ if (fieldmode)
-+ *offset1 = *offset0 + screen_width * ps;
-+ else
-+ *offset1 = *offset0;
-+ *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
-+ (fieldmode ? 1 : 0),
-+ ps);
-+ *pix_inc = pixinc(-screen_width, ps);
-+ break;
-+
-+ default:
-+ BUG();
-+ }
-+}
-+
-+static int _dispc_setup_plane(enum omap_plane plane,
-+ enum omap_channel channel_out,
-+ u32 paddr, u16 screen_width,
-+ u16 pos_x, u16 pos_y,
-+ u16 width, u16 height,
-+ u16 out_width, u16 out_height,
-+ enum omap_color_mode color_mode,
-+ bool ilace,
-+ u8 rotation, int mirror)
-+{
-+ const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
-+ bool five_taps = height > out_height * 2;
-+ bool fieldmode = 0;
-+ int cconv = 0;
-+ unsigned offset0, offset1;
-+ u16 row_inc;
-+ u16 pix_inc;
-+
-+ if (plane == OMAP_DSS_GFX) {
-+ if (width != out_width || height != out_height)
-+ return -EINVAL;
-+
-+ switch (color_mode) {
-+ case OMAP_DSS_COLOR_ARGB16:
-+ case OMAP_DSS_COLOR_RGB16:
-+ case OMAP_DSS_COLOR_RGB24P:
-+ case OMAP_DSS_COLOR_RGB24U:
-+ case OMAP_DSS_COLOR_ARGB32:
-+ case OMAP_DSS_COLOR_RGBA32:
-+ case OMAP_DSS_COLOR_RGBX32:
-+ break;
-+
-+ default:
-+ return -EINVAL;
-+ }
-+ } else {
-+ /* video plane */
-+ if (width > (2048 >> five_taps))
-+ return -EINVAL;
-+
-+ if (out_width < width / maxdownscale ||
-+ out_width > width * 8)
-+ return -EINVAL;
-+
-+ if (out_height < height / maxdownscale ||
-+ out_height > height * 8)
-+ return -EINVAL;
-+
-+ switch (color_mode) {
-+ case OMAP_DSS_COLOR_RGB16:
-+ case OMAP_DSS_COLOR_RGB24P:
-+ case OMAP_DSS_COLOR_RGB24U:
-+ case OMAP_DSS_COLOR_RGBX32:
-+ break;
-+
-+ case OMAP_DSS_COLOR_ARGB16:
-+ case OMAP_DSS_COLOR_ARGB32:
-+ case OMAP_DSS_COLOR_RGBA32:
-+ if (plane == OMAP_DSS_VIDEO1)
-+ return -EINVAL;
-+ break;
-+
-+ case OMAP_DSS_COLOR_YUV2:
-+ case OMAP_DSS_COLOR_UYVY:
-+ cconv = 1;
-+ break;
-+
-+ default:
-+ return -EINVAL;
-+ }
-+ }
-+
-+ if (ilace && height >= out_height)
-+ fieldmode = 1;
-+
-+ calc_rotation_offset(rotation, mirror,
-+ screen_width, width, height, color_mode,
-+ fieldmode,
-+ &offset0, &offset1, &row_inc, &pix_inc);
-+
-+ DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
-+ offset0, offset1, row_inc, pix_inc);
-+
-+ if (ilace) {
-+ if (fieldmode)
-+ height /= 2;
-+ pos_y /= 2;
-+ out_height /= 2;
-+
-+ DSSDBG("adjusting for ilace: height %d, pos_y %d, "
-+ "out_height %d\n",
-+ height, pos_y, out_height);
-+ }
-+
-+ _dispc_set_channel_out(plane, channel_out);
-+ _dispc_set_color_mode(plane, color_mode);
-+
-+ _dispc_set_plane_ba0(plane, paddr + offset0);
-+ _dispc_set_plane_ba1(plane, paddr + offset1);
-+
-+ _dispc_set_row_inc(plane, row_inc);
-+ _dispc_set_pix_inc(plane, pix_inc);
-+
-+ DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
-+ out_width, out_height);
-+
-+ _dispc_set_plane_pos(plane, pos_x, pos_y);
-+
-+ _dispc_set_pic_size(plane, width, height);
-+
-+ if (plane != OMAP_DSS_GFX) {
-+ _dispc_set_scaling(plane, width, height,
-+ out_width, out_height,
-+ ilace);
-+ _dispc_set_vid_size(plane, out_width, out_height);
-+ _dispc_set_vid_color_conv(plane, cconv);
-+ }
-+
-+ _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
-+
-+ return 0;
-+}
-+
-+static void _dispc_enable_plane(enum omap_plane plane, bool enable)
-+{
-+ REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
-+}
-+
-+static void dispc_disable_isr(void *data, u32 mask)
-+{
-+ struct completion *compl = data;
-+ complete(compl);
-+}
-+
-+static void _enable_lcd_out(bool enable)
-+{
-+ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
-+}
-+
-+void dispc_enable_lcd_out(bool enable)
-+{
-+ struct completion frame_done_completion;
-+ bool is_on;
-+ int r;
-+
-+ enable_clocks(1);
-+
-+ /* When we disable LCD output, we need to wait until frame is done.
-+ * Otherwise the DSS is still working, and turning off the clocks
-+ * prevents DSS from going to OFF mode */
-+ is_on = REG_GET(DISPC_CONTROL, 0, 0);
-+
-+ if (!enable && is_on) {
-+ init_completion(&frame_done_completion);
-+
-+ r = omap_dispc_register_isr(dispc_disable_isr,
-+ &frame_done_completion,
-+ DISPC_IRQ_FRAMEDONE);
-+
-+ if (r)
-+ DSSERR("failed to register FRAMEDONE isr\n");
-+ }
-+
-+ _enable_lcd_out(enable);
-+
-+ if (!enable && is_on) {
-+ if (!wait_for_completion_timeout(&frame_done_completion,
-+ msecs_to_jiffies(100)))
-+ DSSERR("timeout waiting for FRAME DONE\n");
-+
-+ r = omap_dispc_unregister_isr(dispc_disable_isr,
-+ &frame_done_completion,
-+ DISPC_IRQ_FRAMEDONE);
-+
-+ if (r)
-+ DSSERR("failed to unregister FRAMEDONE isr\n");
-+ }
-+
-+ enable_clocks(0);
-+}
-+
-+static void _enable_digit_out(bool enable)
-+{
-+ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
-+}
-+
-+void dispc_enable_digit_out(bool enable)
-+{
-+ struct completion frame_done_completion;
-+ int r;
-+
-+ enable_clocks(1);
-+
-+ if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
-+ enable_clocks(0);
-+ return;
-+ }
-+
-+ if (enable) {
-+ /* When we enable digit output, we'll get an extra digit
-+ * sync lost interrupt, that we need to ignore */
-+ dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
-+ omap_dispc_set_irqs();
-+ }
-+
-+ /* When we disable digit output, we need to wait until fields are done.
-+ * Otherwise the DSS is still working, and turning off the clocks
-+ * prevents DSS from going to OFF mode. And when enabling, we need to
-+ * wait for the extra sync losts */
-+ init_completion(&frame_done_completion);
-+
-+ r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
-+ DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
-+ if (r)
-+ DSSERR("failed to register EVSYNC isr\n");
-+
-+ _enable_digit_out(enable);
-+
-+ /* XXX I understand from TRM that we should only wait for the
-+ * current field to complete. But it seems we have to wait
-+ * for both fields */
-+ if (!wait_for_completion_timeout(&frame_done_completion,
-+ msecs_to_jiffies(100)))
-+ DSSERR("timeout waiting for EVSYNC\n");
-+
-+ if (!wait_for_completion_timeout(&frame_done_completion,
-+ msecs_to_jiffies(100)))
-+ DSSERR("timeout waiting for EVSYNC\n");
-+
-+ r = omap_dispc_unregister_isr(dispc_disable_isr,
-+ &frame_done_completion,
-+ DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
-+ if (r)
-+ DSSERR("failed to unregister EVSYNC isr\n");
-+
-+ if (enable) {
-+ dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
-+ dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
-+ omap_dispc_set_irqs();
-+ }
-+
-+ enable_clocks(0);
-+}
-+
-+void dispc_lcd_enable_signal_polarity(bool act_high)
-+{
-+ enable_clocks(1);
-+ REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
-+ enable_clocks(0);
-+}
-+
-+void dispc_lcd_enable_signal(bool enable)
-+{
-+ enable_clocks(1);
-+ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
-+ enable_clocks(0);
-+}
-+
-+void dispc_pck_free_enable(bool enable)
-+{
-+ enable_clocks(1);
-+ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
-+ enable_clocks(0);
-+}
-+
-+void dispc_enable_fifohandcheck(bool enable)
-+{
-+ enable_clocks(1);
-+ REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
-+ enable_clocks(0);
-+}
-+
-+
-+void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
-+{
-+ int mode;
-+
-+ switch (type) {
-+ case OMAP_DSS_LCD_DISPLAY_STN:
-+ mode = 0;
-+ break;
-+
-+ case OMAP_DSS_LCD_DISPLAY_TFT:
-+ mode = 1;
-+ break;
-+
-+ default:
-+ BUG();
-+ return;
-+ }
-+
-+ enable_clocks(1);
-+ REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
-+ enable_clocks(0);
-+}
-+
-+void dispc_set_loadmode(enum omap_dss_load_mode mode)
-+{
-+ enable_clocks(1);
-+ REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
-+ enable_clocks(0);
-+}
-+
-+
-+void dispc_set_default_color(enum omap_channel channel, u32 color)
-+{
-+ const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
-+ DISPC_DEFAULT_COLOR1 };
-+
-+ enable_clocks(1);
-+ dispc_write_reg(def_reg[channel], color);
-+ enable_clocks(0);
-+}
-+
-+u32 dispc_get_default_color(enum omap_channel channel)
-+{
-+ const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
-+ DISPC_DEFAULT_COLOR1 };
-+ u32 l;
-+
-+ BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
-+ channel != OMAP_DSS_CHANNEL_LCD);
-+
-+ enable_clocks(1);
-+ l = dispc_read_reg(def_reg[channel]);
-+ enable_clocks(0);
-+
-+ return l;
-+}
-+
-+void dispc_set_trans_key(enum omap_channel ch,
-+ enum omap_dss_color_key_type type,
-+ u32 trans_key)
-+{
-+ const struct dispc_reg tr_reg[] = {
-+ DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
-+
-+ enable_clocks(1);
-+ if (ch == OMAP_DSS_CHANNEL_LCD)
-+ REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
-+ else /* OMAP_DSS_CHANNEL_DIGIT */
-+ REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
-+
-+ dispc_write_reg(tr_reg[ch], trans_key);
-+ enable_clocks(0);
-+}
-+
-+void dispc_get_trans_key(enum omap_channel ch,
-+ enum omap_dss_color_key_type *type,
-+ u32 *trans_key)
-+{
-+ const struct dispc_reg tr_reg[] = {
-+ DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
-+
-+ enable_clocks(1);
-+ if (type) {
-+ if (ch == OMAP_DSS_CHANNEL_LCD)
-+ *type = REG_GET(DISPC_CONFIG, 11, 11) >> 11;
-+ else if (ch == OMAP_DSS_CHANNEL_DIGIT)
-+ *type = REG_GET(DISPC_CONFIG, 13, 13) >> 13;
-+ else
-+ BUG();
-+ }
-+
-+ if (trans_key)
-+ *trans_key = dispc_read_reg(tr_reg[ch]);
-+ enable_clocks(0);
-+}
-+
-+void dispc_enable_trans_key(enum omap_channel ch, bool enable)
-+{
-+ enable_clocks(1);
-+ if (ch == OMAP_DSS_CHANNEL_LCD)
-+ REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
-+ else /* OMAP_DSS_CHANNEL_DIGIT */
-+ REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
-+ enable_clocks(0);
-+}
-+
-+bool dispc_trans_key_enabled(enum omap_channel ch)
-+{
-+ bool enabled;
-+
-+ enable_clocks(1);
-+ if (ch == OMAP_DSS_CHANNEL_LCD)
-+ enabled = REG_GET(DISPC_CONFIG, 10, 10);
-+ else if (ch == OMAP_DSS_CHANNEL_DIGIT)
-+ enabled = REG_GET(DISPC_CONFIG, 12, 12);
-+ else BUG();
-+ enable_clocks(0);
-+
-+ return enabled;
-+}
-+
-+
-+void dispc_set_tft_data_lines(u8 data_lines)
-+{
-+ int code;
-+
-+ switch (data_lines) {
-+ case 12:
-+ code = 0;
-+ break;
-+ case 16:
-+ code = 1;
-+ break;
-+ case 18:
-+ code = 2;
-+ break;
-+ case 24:
-+ code = 3;
-+ break;
-+ default:
-+ BUG();
-+ return;
-+ }
-+
-+ enable_clocks(1);
-+ REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
-+ enable_clocks(0);
-+}
-+
-+void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
-+{
-+ u32 l;
-+ int stallmode;
-+ int gpout0 = 1;
-+ int gpout1;
-+
-+ switch (mode) {
-+ case OMAP_DSS_PARALLELMODE_BYPASS:
-+ stallmode = 0;
-+ gpout1 = 1;
-+ break;
-+
-+ case OMAP_DSS_PARALLELMODE_RFBI:
-+ stallmode = 1;
-+ gpout1 = 0;
-+ break;
-+
-+ case OMAP_DSS_PARALLELMODE_DSI:
-+ stallmode = 1;
-+ gpout1 = 1;
-+ break;
-+
-+ default:
-+ BUG();
-+ return;
-+ }
-+
-+ enable_clocks(1);
-+
-+ l = dispc_read_reg(DISPC_CONTROL);
-+
-+ l = FLD_MOD(l, stallmode, 11, 11);
-+ l = FLD_MOD(l, gpout0, 15, 15);
-+ l = FLD_MOD(l, gpout1, 16, 16);
-+
-+ dispc_write_reg(DISPC_CONTROL, l);
-+
-+ enable_clocks(0);
-+}
-+
-+static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
-+ int vsw, int vfp, int vbp)
-+{
-+ u32 timing_h, timing_v;
-+
-+ if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
-+ BUG_ON(hsw < 1 || hsw > 64);
-+ BUG_ON(hfp < 1 || hfp > 256);
-+ BUG_ON(hbp < 1 || hbp > 256);
-+
-+ BUG_ON(vsw < 1 || vsw > 64);
-+ BUG_ON(vfp < 0 || vfp > 255);
-+ BUG_ON(vbp < 0 || vbp > 255);
-+
-+ timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
-+ FLD_VAL(hbp-1, 27, 20);
-+
-+ timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
-+ FLD_VAL(vbp, 27, 20);
-+ } else {
-+ BUG_ON(hsw < 1 || hsw > 256);
-+ BUG_ON(hfp < 1 || hfp > 4096);
-+ BUG_ON(hbp < 1 || hbp > 4096);
-+
-+ BUG_ON(vsw < 1 || vsw > 256);
-+ BUG_ON(vfp < 0 || vfp > 4095);
-+ BUG_ON(vbp < 0 || vbp > 4095);
-+
-+ timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
-+ FLD_VAL(hbp-1, 31, 20);
-+
-+ timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
-+ FLD_VAL(vbp, 31, 20);
-+ }
-+
-+ enable_clocks(1);
-+ dispc_write_reg(DISPC_TIMING_H, timing_h);
-+ dispc_write_reg(DISPC_TIMING_V, timing_v);
-+ enable_clocks(0);
-+}
-+
-+/* change name to mode? */
-+void dispc_set_lcd_timings(struct omap_video_timings *timings)
-+{
-+ unsigned xtot, ytot;
-+ unsigned long ht, vt;
-+
-+ _dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
-+ timings->vsw, timings->vfp, timings->vbp);
-+
-+ dispc_set_lcd_size(timings->x_res, timings->y_res);
-+
-+ xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
-+ ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
-+
-+ ht = (timings->pixel_clock * 1000) / xtot;
-+ vt = (timings->pixel_clock * 1000) / xtot / ytot;
-+
-+ DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
-+ DSSDBG("pck %u\n", timings->pixel_clock);
-+ DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
-+ timings->hsw, timings->hfp, timings->hbp,
-+ timings->vsw, timings->vfp, timings->vbp);
-+
-+ DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
-+}
-+
-+void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
-+{
-+ BUG_ON(lck_div < 1);
-+ BUG_ON(pck_div < 2);
-+
-+ enable_clocks(1);
-+ dispc_write_reg(DISPC_DIVISOR,
-+ FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
-+ enable_clocks(0);
-+}
-+
-+static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
-+{
-+ u32 l;
-+ l = dispc_read_reg(DISPC_DIVISOR);
-+ *lck_div = FLD_GET(l, 23, 16);
-+ *pck_div = FLD_GET(l, 7, 0);
-+}
-+
-+unsigned long dispc_fclk_rate(void)
-+{
-+ unsigned long r = 0;
-+
-+ if (dss_get_dispc_clk_source() == 0)
-+ r = dss_clk_get_rate(DSS_CLK_FCK1);
-+ else
-+#ifdef CONFIG_OMAP2_DSS_DSI
-+ r = dsi_get_dsi1_pll_rate();
-+#else
-+ BUG();
-+#endif
-+ return r;
-+}
-+
-+unsigned long dispc_pclk_rate(void)
-+{
-+ int lcd, pcd;
-+ unsigned long r;
-+ u32 l;
-+
-+ l = dispc_read_reg(DISPC_DIVISOR);
-+
-+ lcd = FLD_GET(l, 23, 16);
-+ pcd = FLD_GET(l, 7, 0);
-+
-+ r = dispc_fclk_rate();
-+
-+ return r / lcd / pcd;
-+}
-+
-+void dispc_dump_clocks(struct seq_file *s)
-+{
-+ int lcd, pcd;
-+
-+ enable_clocks(1);
-+
-+ dispc_get_lcd_divisor(&lcd, &pcd);
-+
-+ seq_printf(s, "- dispc -\n");
-+
-+ seq_printf(s, "dispc fclk source = %s\n",
-+ dss_get_dispc_clk_source() == 0 ?
-+ "dss1_alwon_fclk" : "dsi1_pll_fclk");
-+
-+ seq_printf(s, "pixel clk = %lu / %d / %d = %lu\n",
-+ dispc_fclk_rate(),
-+ lcd, pcd,
-+ dispc_pclk_rate());
-+
-+ enable_clocks(0);
-+}
-+
-+void dispc_dump_regs(struct seq_file *s)
-+{
-+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
-+
-+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+
-+ DUMPREG(DISPC_REVISION);
-+ DUMPREG(DISPC_SYSCONFIG);
-+ DUMPREG(DISPC_SYSSTATUS);
-+ DUMPREG(DISPC_IRQSTATUS);
-+ DUMPREG(DISPC_IRQENABLE);
-+ DUMPREG(DISPC_CONTROL);
-+ DUMPREG(DISPC_CONFIG);
-+ DUMPREG(DISPC_CAPABLE);
-+ DUMPREG(DISPC_DEFAULT_COLOR0);
-+ DUMPREG(DISPC_DEFAULT_COLOR1);
-+ DUMPREG(DISPC_TRANS_COLOR0);
-+ DUMPREG(DISPC_TRANS_COLOR1);
-+ DUMPREG(DISPC_LINE_STATUS);
-+ DUMPREG(DISPC_LINE_NUMBER);
-+ DUMPREG(DISPC_TIMING_H);
-+ DUMPREG(DISPC_TIMING_V);
-+ DUMPREG(DISPC_POL_FREQ);
-+ DUMPREG(DISPC_DIVISOR);
-+ DUMPREG(DISPC_GLOBAL_ALPHA);
-+ DUMPREG(DISPC_SIZE_DIG);
-+ DUMPREG(DISPC_SIZE_LCD);
-+
-+ DUMPREG(DISPC_GFX_BA0);
-+ DUMPREG(DISPC_GFX_BA1);
-+ DUMPREG(DISPC_GFX_POSITION);
-+ DUMPREG(DISPC_GFX_SIZE);
-+ DUMPREG(DISPC_GFX_ATTRIBUTES);
-+ DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
-+ DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
-+ DUMPREG(DISPC_GFX_ROW_INC);
-+ DUMPREG(DISPC_GFX_PIXEL_INC);
-+ DUMPREG(DISPC_GFX_WINDOW_SKIP);
-+ DUMPREG(DISPC_GFX_TABLE_BA);
-+
-+ DUMPREG(DISPC_DATA_CYCLE1);
-+ DUMPREG(DISPC_DATA_CYCLE2);
-+ DUMPREG(DISPC_DATA_CYCLE3);
-+
-+ DUMPREG(DISPC_CPR_COEF_R);
-+ DUMPREG(DISPC_CPR_COEF_G);
-+ DUMPREG(DISPC_CPR_COEF_B);
-+
-+ DUMPREG(DISPC_GFX_PRELOAD);
-+
-+ DUMPREG(DISPC_VID_BA0(0));
-+ DUMPREG(DISPC_VID_BA1(0));
-+ DUMPREG(DISPC_VID_POSITION(0));
-+ DUMPREG(DISPC_VID_SIZE(0));
-+ DUMPREG(DISPC_VID_ATTRIBUTES(0));
-+ DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
-+ DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
-+ DUMPREG(DISPC_VID_ROW_INC(0));
-+ DUMPREG(DISPC_VID_PIXEL_INC(0));
-+ DUMPREG(DISPC_VID_FIR(0));
-+ DUMPREG(DISPC_VID_PICTURE_SIZE(0));
-+ DUMPREG(DISPC_VID_ACCU0(0));
-+ DUMPREG(DISPC_VID_ACCU1(0));
-+
-+ DUMPREG(DISPC_VID_BA0(1));
-+ DUMPREG(DISPC_VID_BA1(1));
-+ DUMPREG(DISPC_VID_POSITION(1));
-+ DUMPREG(DISPC_VID_SIZE(1));
-+ DUMPREG(DISPC_VID_ATTRIBUTES(1));
-+ DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
-+ DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
-+ DUMPREG(DISPC_VID_ROW_INC(1));
-+ DUMPREG(DISPC_VID_PIXEL_INC(1));
-+ DUMPREG(DISPC_VID_FIR(1));
-+ DUMPREG(DISPC_VID_PICTURE_SIZE(1));
-+ DUMPREG(DISPC_VID_ACCU0(1));
-+ DUMPREG(DISPC_VID_ACCU1(1));
-+
-+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
-+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
-+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
-+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
-+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
-+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
-+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
-+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
-+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
-+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
-+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
-+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
-+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
-+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
-+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
-+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
-+ DUMPREG(DISPC_VID_CONV_COEF(0, 0));
-+ DUMPREG(DISPC_VID_CONV_COEF(0, 1));
-+ DUMPREG(DISPC_VID_CONV_COEF(0, 2));
-+ DUMPREG(DISPC_VID_CONV_COEF(0, 3));
-+ DUMPREG(DISPC_VID_CONV_COEF(0, 4));
-+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
-+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
-+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
-+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
-+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
-+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
-+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
-+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
-+
-+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
-+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
-+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
-+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
-+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
-+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
-+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
-+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
-+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
-+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
-+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
-+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
-+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
-+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
-+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
-+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
-+ DUMPREG(DISPC_VID_CONV_COEF(1, 0));
-+ DUMPREG(DISPC_VID_CONV_COEF(1, 1));
-+ DUMPREG(DISPC_VID_CONV_COEF(1, 2));
-+ DUMPREG(DISPC_VID_CONV_COEF(1, 3));
-+ DUMPREG(DISPC_VID_CONV_COEF(1, 4));
-+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
-+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
-+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
-+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
-+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
-+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
-+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
-+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
-+
-+ DUMPREG(DISPC_VID_PRELOAD(0));
-+ DUMPREG(DISPC_VID_PRELOAD(1));
-+
-+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+#undef DUMPREG
-+}
-+
-+static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
-+ bool ihs, bool ivs, u8 acbi, u8 acb)
-+{
-+ u32 l = 0;
-+
-+ DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
-+ onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
-+
-+ l |= FLD_VAL(onoff, 17, 17);
-+ l |= FLD_VAL(rf, 16, 16);
-+ l |= FLD_VAL(ieo, 15, 15);
-+ l |= FLD_VAL(ipc, 14, 14);
-+ l |= FLD_VAL(ihs, 13, 13);
-+ l |= FLD_VAL(ivs, 12, 12);
-+ l |= FLD_VAL(acbi, 11, 8);
-+ l |= FLD_VAL(acb, 7, 0);
-+
-+ enable_clocks(1);
-+ dispc_write_reg(DISPC_POL_FREQ, l);
-+ enable_clocks(0);
-+}
-+
-+void dispc_set_pol_freq(struct omap_panel *panel)
-+{
-+ _dispc_set_pol_freq((panel->config & OMAP_DSS_LCD_ONOFF) != 0,
-+ (panel->config & OMAP_DSS_LCD_RF) != 0,
-+ (panel->config & OMAP_DSS_LCD_IEO) != 0,
-+ (panel->config & OMAP_DSS_LCD_IPC) != 0,
-+ (panel->config & OMAP_DSS_LCD_IHS) != 0,
-+ (panel->config & OMAP_DSS_LCD_IVS) != 0,
-+ panel->acbi, panel->acb);
-+}
-+
-+void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
-+ u16 *lck_div, u16 *pck_div)
-+{
-+ u16 pcd_min = is_tft ? 2 : 3;
-+ unsigned long best_pck;
-+ u16 best_ld, cur_ld;
-+ u16 best_pd, cur_pd;
-+
-+ best_pck = 0;
-+ best_ld = 0;
-+ best_pd = 0;
-+
-+ for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
-+ unsigned long lck = fck / cur_ld;
-+
-+ for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
-+ unsigned long pck = lck / cur_pd;
-+ long old_delta = abs(best_pck - req_pck);
-+ long new_delta = abs(pck - req_pck);
-+
-+ if (best_pck == 0 || new_delta < old_delta) {
-+ best_pck = pck;
-+ best_ld = cur_ld;
-+ best_pd = cur_pd;
-+
-+ if (pck == req_pck)
-+ goto found;
-+ }
-+
-+ if (pck < req_pck)
-+ break;
-+ }
-+
-+ if (lck / pcd_min < req_pck)
-+ break;
-+ }
-+
-+found:
-+ *lck_div = best_ld;
-+ *pck_div = best_pd;
-+}
-+
-+int dispc_calc_clock_div(bool is_tft, unsigned long req_pck,
-+ struct dispc_clock_info *cinfo)
-+{
-+ unsigned long prate;
-+ struct dispc_clock_info cur, best;
-+ int match = 0;
-+ int min_fck_per_pck;
-+ unsigned long fck_rate = dss_clk_get_rate(DSS_CLK_FCK1);
-+
-+ if (cpu_is_omap34xx())
-+ prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
-+ else
-+ prate = 0;
-+
-+ if (req_pck == dispc.cache_req_pck &&
-+ ((cpu_is_omap34xx() && prate == dispc.cache_prate) ||
-+ dispc.cache_cinfo.fck == fck_rate)) {
-+ DSSDBG("dispc clock info found from cache.\n");
-+ *cinfo = dispc.cache_cinfo;
-+ return 0;
-+ }
-+
-+ min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
-+
-+ if (min_fck_per_pck &&
-+ req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
-+ DSSERR("Requested pixel clock not possible with the current "
-+ "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
-+ "the constraint off.\n");
-+ min_fck_per_pck = 0;
-+ }
-+
-+retry:
-+ memset(&cur, 0, sizeof(cur));
-+ memset(&best, 0, sizeof(best));
-+
-+ if (cpu_is_omap24xx()) {
-+ /* XXX can we change the clock on omap2? */
-+ cur.fck = dss_clk_get_rate(DSS_CLK_FCK1);
-+ cur.fck_div = 1;
-+
-+ match = 1;
-+
-+ find_lck_pck_divs(is_tft, req_pck, cur.fck,
-+ &cur.lck_div, &cur.pck_div);
-+
-+ cur.lck = cur.fck / cur.lck_div;
-+ cur.pck = cur.lck / cur.pck_div;
-+
-+ best = cur;
-+
-+ goto found;
-+ } else if (cpu_is_omap34xx()) {
-+ for (cur.fck_div = 16; cur.fck_div > 0; --cur.fck_div) {
-+ cur.fck = prate / cur.fck_div * 2;
-+
-+ if (cur.fck > DISPC_MAX_FCK)
-+ continue;
-+
-+ if (min_fck_per_pck &&
-+ cur.fck < req_pck * min_fck_per_pck)
-+ continue;
-+
-+ match = 1;
-+
-+ find_lck_pck_divs(is_tft, req_pck, cur.fck,
-+ &cur.lck_div, &cur.pck_div);
-+
-+ cur.lck = cur.fck / cur.lck_div;
-+ cur.pck = cur.lck / cur.pck_div;
-+
-+ if (abs(cur.pck - req_pck) < abs(best.pck - req_pck)) {
-+ best = cur;
-+
-+ if (cur.pck == req_pck)
-+ goto found;
-+ }
-+ }
-+ } else {
-+ BUG();
-+ }
-+
-+found:
-+ if (!match) {
-+ if (min_fck_per_pck) {
-+ DSSERR("Could not find suitable clock settings.\n"
-+ "Turning FCK/PCK constraint off and"
-+ "trying again.\n");
-+ min_fck_per_pck = 0;
-+ goto retry;
-+ }
-+
-+ DSSERR("Could not find suitable clock settings.\n");
-+
-+ return -EINVAL;
-+ }
-+
-+ if (cinfo)
-+ *cinfo = best;
-+
-+ dispc.cache_req_pck = req_pck;
-+ dispc.cache_prate = prate;
-+ dispc.cache_cinfo = best;
-+
-+ return 0;
-+}
-+
-+int dispc_set_clock_div(struct dispc_clock_info *cinfo)
-+{
-+ unsigned long prate;
-+ int r;
-+
-+ if (cpu_is_omap34xx()) {
-+ prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
-+ DSSDBG("dpll4_m4 = %ld\n", prate);
-+ }
-+
-+ DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
-+ DSSDBG("lck = %ld (%d)\n", cinfo->lck, cinfo->lck_div);
-+ DSSDBG("pck = %ld (%d)\n", cinfo->pck, cinfo->pck_div);
-+
-+ if (cpu_is_omap34xx()) {
-+ r = clk_set_rate(dispc.dpll4_m4_ck, prate / cinfo->fck_div);
-+ if (r)
-+ return r;
-+ }
-+
-+ dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
-+
-+ return 0;
-+}
-+
-+int dispc_get_clock_div(struct dispc_clock_info *cinfo)
-+{
-+ cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1);
-+
-+ if (cpu_is_omap34xx()) {
-+ unsigned long prate;
-+ prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
-+ cinfo->fck_div = prate / (cinfo->fck / 2);
-+ } else {
-+ cinfo->fck_div = 0;
-+ }
-+
-+ cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
-+ cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
-+
-+ cinfo->lck = cinfo->fck / cinfo->lck_div;
-+ cinfo->pck = cinfo->lck / cinfo->pck_div;
-+
-+ return 0;
-+}
-+
-+static void omap_dispc_set_irqs(void)
-+{
-+ unsigned long flags;
-+ u32 mask = dispc.irq_error_mask;
-+ int i;
-+ struct omap_dispc_isr_data *isr_data;
-+
-+ spin_lock_irqsave(&dispc.irq_lock, flags);
-+
-+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
-+ isr_data = &dispc.registered_isr[i];
-+
-+ if (isr_data->isr == NULL)
-+ continue;
-+
-+ mask |= isr_data->mask;
-+ }
-+
-+ enable_clocks(1);
-+ dispc_write_reg(DISPC_IRQENABLE, mask);
-+ enable_clocks(0);
-+
-+ spin_unlock_irqrestore(&dispc.irq_lock, flags);
-+}
-+
-+int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
-+{
-+ int i;
-+ int ret;
-+ unsigned long flags;
-+ struct omap_dispc_isr_data *isr_data;
-+
-+ if (isr == NULL)
-+ return -EINVAL;
-+
-+ spin_lock_irqsave(&dispc.irq_lock, flags);
-+
-+ /* check for duplicate entry */
-+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
-+ isr_data = &dispc.registered_isr[i];
-+ if (isr_data->isr == isr && isr_data->arg == arg &&
-+ isr_data->mask == mask) {
-+ ret = -EINVAL;
-+ goto err;
-+ }
-+ }
-+
-+ isr_data = NULL;
-+ ret = -EBUSY;
-+
-+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
-+ isr_data = &dispc.registered_isr[i];
-+
-+ if (isr_data->isr != NULL)
-+ continue;
-+
-+ isr_data->isr = isr;
-+ isr_data->arg = arg;
-+ isr_data->mask = mask;
-+ ret = 0;
-+
-+ break;
-+ }
-+err:
-+ spin_unlock_irqrestore(&dispc.irq_lock, flags);
-+
-+ if (ret == 0)
-+ omap_dispc_set_irqs();
-+
-+ return ret;
-+}
-+EXPORT_SYMBOL(omap_dispc_register_isr);
-+
-+int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
-+{
-+ int i;
-+ unsigned long flags;
-+ int ret = -EINVAL;
-+ struct omap_dispc_isr_data *isr_data;
-+
-+ spin_lock_irqsave(&dispc.irq_lock, flags);
-+
-+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
-+ isr_data = &dispc.registered_isr[i];
-+ if (isr_data->isr != isr || isr_data->arg != arg ||
-+ isr_data->mask != mask)
-+ continue;
-+
-+ /* found the correct isr */
-+
-+ isr_data->isr = NULL;
-+ isr_data->arg = NULL;
-+ isr_data->mask = 0;
-+
-+ ret = 0;
-+ break;
-+ }
-+
-+ spin_unlock_irqrestore(&dispc.irq_lock, flags);
-+
-+ if (ret == 0)
-+ omap_dispc_set_irqs();
-+
-+ return ret;
-+}
-+EXPORT_SYMBOL(omap_dispc_unregister_isr);
-+
-+#ifdef DEBUG
-+static void print_irq_status(u32 status)
-+{
-+ if ((status & dispc.irq_error_mask) == 0)
-+ return;
-+
-+ printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
-+
-+#define PIS(x) \
-+ if (status & DISPC_IRQ_##x) \
-+ printk(#x " ");
-+ PIS(GFX_FIFO_UNDERFLOW);
-+ PIS(OCP_ERR);
-+ PIS(VID1_FIFO_UNDERFLOW);
-+ PIS(VID2_FIFO_UNDERFLOW);
-+ PIS(SYNC_LOST);
-+ PIS(SYNC_LOST_DIGIT);
-+#undef PIS
-+
-+ printk("\n");
-+}
-+#endif
-+
-+/* Called from dss.c. Note that we don't touch clocks here,
-+ * but we presume they are on because we got an IRQ. However,
-+ * an irq handler may turn the clocks off, so we may not have
-+ * clock later in the function. */
-+void dispc_irq_handler(void)
-+{
-+ int i;
-+ u32 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
-+ u32 handledirqs = 0;
-+ u32 unhandled_errors;
-+ struct omap_dispc_isr_data *isr_data;
-+
-+#ifdef DEBUG
-+ if (dss_debug)
-+ print_irq_status(irqstatus);
-+#endif
-+ /* Ack the interrupt. Do it here before clocks are possibly turned
-+ * off */
-+ dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
-+
-+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
-+ isr_data = &dispc.registered_isr[i];
-+
-+ if (!isr_data->isr)
-+ continue;
-+
-+ if (isr_data->mask & irqstatus) {
-+ isr_data->isr(isr_data->arg, irqstatus);
-+ handledirqs |= isr_data->mask;
-+ }
-+ }
-+
-+ unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
-+
-+ if (unhandled_errors) {
-+ spin_lock(&dispc.error_lock);
-+ dispc.error_irqs |= unhandled_errors;
-+ spin_unlock(&dispc.error_lock);
-+
-+ dispc.irq_error_mask &= ~unhandled_errors;
-+ omap_dispc_set_irqs();
-+
-+ schedule_work(&dispc.error_work);
-+ }
-+}
-+
-+static void dispc_error_worker(struct work_struct *work)
-+{
-+ int i;
-+ u32 errors;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&dispc.error_lock, flags);
-+ errors = dispc.error_irqs;
-+ dispc.error_irqs = 0;
-+ spin_unlock_irqrestore(&dispc.error_lock, flags);
-+
-+ if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
-+ DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
-+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
-+ struct omap_overlay *ovl;
-+ ovl = omap_dss_get_overlay(i);
-+
-+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
-+ continue;
-+
-+ if (ovl->id == 0) {
-+ dispc_enable_plane(ovl->id, 0);
-+ dispc_go(ovl->manager->id);
-+ mdelay(50);
-+ break;
-+ }
-+ }
-+ }
-+
-+ if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
-+ DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
-+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
-+ struct omap_overlay *ovl;
-+ ovl = omap_dss_get_overlay(i);
-+
-+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
-+ continue;
-+
-+ if (ovl->id == 1) {
-+ dispc_enable_plane(ovl->id, 0);
-+ dispc_go(ovl->manager->id);
-+ mdelay(50);
-+ break;
-+ }
-+ }
-+ }
-+
-+ if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
-+ DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
-+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
-+ struct omap_overlay *ovl;
-+ ovl = omap_dss_get_overlay(i);
-+
-+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
-+ continue;
-+
-+ if (ovl->id == 2) {
-+ dispc_enable_plane(ovl->id, 0);
-+ dispc_go(ovl->manager->id);
-+ mdelay(50);
-+ break;
-+ }
-+ }
-+ }
-+
-+ if (errors & DISPC_IRQ_SYNC_LOST) {
-+ DSSERR("SYNC_LOST, disabling LCD\n");
-+ for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
-+ struct omap_overlay_manager *mgr;
-+ mgr = omap_dss_get_overlay_manager(i);
-+
-+ if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
-+ mgr->display->disable(mgr->display);
-+ break;
-+ }
-+ }
-+ }
-+
-+ if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
-+ DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
-+ for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
-+ struct omap_overlay_manager *mgr;
-+ mgr = omap_dss_get_overlay_manager(i);
-+
-+ if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
-+ mgr->display->disable(mgr->display);
-+ break;
-+ }
-+ }
-+ }
-+
-+ if (errors & DISPC_IRQ_OCP_ERR) {
-+ DSSERR("OCP_ERR\n");
-+ for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
-+ struct omap_overlay_manager *mgr;
-+ mgr = omap_dss_get_overlay_manager(i);
-+
-+ if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
-+ mgr->display->disable(mgr->display);
-+ }
-+ }
-+
-+ dispc.irq_error_mask |= errors;
-+ omap_dispc_set_irqs();
-+}
-+
-+int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
-+{
-+ void dispc_irq_wait_handler(void *data, u32 mask)
-+ {
-+ complete((struct completion *)data);
-+ }
-+
-+ int r;
-+ DECLARE_COMPLETION_ONSTACK(completion);
-+
-+ r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
-+ irqmask);
-+
-+ if (r)
-+ return r;
-+
-+ timeout = wait_for_completion_timeout(&completion, timeout);
-+
-+ omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
-+
-+ if (timeout == 0)
-+ return -ETIMEDOUT;
-+
-+ if (timeout == -ERESTARTSYS)
-+ return -ERESTARTSYS;
-+
-+ return 0;
-+}
-+
-+int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
-+ unsigned long timeout)
-+{
-+ void dispc_irq_wait_handler(void *data, u32 mask)
-+ {
-+ complete((struct completion *)data);
-+ }
-+
-+ int r;
-+ DECLARE_COMPLETION_ONSTACK(completion);
-+
-+ r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
-+ irqmask);
-+
-+ if (r)
-+ return r;
-+
-+ timeout = wait_for_completion_interruptible_timeout(&completion,
-+ timeout);
-+
-+ omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
-+
-+ if (timeout == 0)
-+ return -ETIMEDOUT;
-+
-+ if (timeout == -ERESTARTSYS)
-+ return -ERESTARTSYS;
-+
-+ return 0;
-+}
-+
-+#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
-+void dispc_fake_vsync_irq(void)
-+{
-+ u32 irqstatus = DISPC_IRQ_VSYNC;
-+ int i;
-+
-+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
-+ struct omap_dispc_isr_data *isr_data;
-+ isr_data = &dispc.registered_isr[i];
-+
-+ if (!isr_data->isr)
-+ continue;
-+
-+ if (isr_data->mask & irqstatus)
-+ isr_data->isr(isr_data->arg, irqstatus);
-+ }
-+}
-+#endif
-+
-+static void _omap_dispc_initialize_irq(void)
-+{
-+ memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
-+
-+ dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
-+
-+ /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
-+ * so clear it */
-+ dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
-+
-+ omap_dispc_set_irqs();
-+}
-+
-+static void _omap_dispc_initial_config(void)
-+{
-+ u32 l;
-+
-+ l = dispc_read_reg(DISPC_SYSCONFIG);
-+ l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */
-+ l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */
-+ l = FLD_MOD(l, 1, 2, 2); /* ENWAKEUP */
-+ l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */
-+ dispc_write_reg(DISPC_SYSCONFIG, l);
-+
-+ /* FUNCGATED */
-+ REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
-+
-+ /* L3 firewall setting: enable access to OCM RAM */
-+ if (cpu_is_omap24xx())
-+ __raw_writel(0x402000b0, IO_ADDRESS(0x680050a0));
-+
-+ _dispc_setup_color_conv_coef();
-+
-+ dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
-+}
-+
-+int dispc_init(void)
-+{
-+ u32 rev;
-+
-+ spin_lock_init(&dispc.irq_lock);
-+ spin_lock_init(&dispc.error_lock);
-+
-+ INIT_WORK(&dispc.error_work, dispc_error_worker);
-+
-+ dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
-+ if (!dispc.base) {
-+ DSSERR("can't ioremap DISPC\n");
-+ return -ENOMEM;
-+ }
-+
-+ if (cpu_is_omap34xx()) {
-+ dispc.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
-+ if (IS_ERR(dispc.dpll4_m4_ck)) {
-+ DSSERR("Failed to get dpll4_m4_ck\n");
-+ return -ENODEV;
-+ }
-+ }
-+
-+ enable_clocks(1);
-+
-+ _omap_dispc_initial_config();
-+
-+ _omap_dispc_initialize_irq();
-+
-+ dispc_save_context();
-+
-+ rev = dispc_read_reg(DISPC_REVISION);
-+ printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
-+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
-+
-+ enable_clocks(0);
-+
-+ return 0;
-+}
-+
-+void dispc_exit(void)
-+{
-+ if (cpu_is_omap34xx())
-+ clk_put(dispc.dpll4_m4_ck);
-+ iounmap(dispc.base);
-+}
-+
-+int dispc_enable_plane(enum omap_plane plane, bool enable)
-+{
-+ DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
-+
-+ enable_clocks(1);
-+ _dispc_enable_plane(plane, enable);
-+ enable_clocks(0);
-+
-+ return 0;
-+}
-+
-+int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
-+ u32 paddr, u16 screen_width,
-+ u16 pos_x, u16 pos_y,
-+ u16 width, u16 height,
-+ u16 out_width, u16 out_height,
-+ enum omap_color_mode color_mode,
-+ bool ilace,
-+ u8 rotation, bool mirror)
-+{
-+ int r = 0;
-+
-+ DSSDBG("dispc_setup_plane %d, ch %d, pa %x, sw %d, %d,%d, %dx%d -> "
-+ "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
-+ plane, channel_out, paddr, screen_width, pos_x, pos_y,
-+ width, height,
-+ out_width, out_height,
-+ ilace, color_mode,
-+ rotation, mirror);
-+
-+ enable_clocks(1);
-+
-+ r = _dispc_setup_plane(plane, channel_out,
-+ paddr, screen_width,
-+ pos_x, pos_y,
-+ width, height,
-+ out_width, out_height,
-+ color_mode, ilace,
-+ rotation, mirror);
-+
-+ enable_clocks(0);
-+
-+ return r;
-+}
-+
-+static int dispc_is_intersecting(int x1, int y1, int w1, int h1,
-+ int x2, int y2, int w2, int h2)
-+{
-+ if (x1 >= (x2+w2))
-+ return 0;
-+
-+ if ((x1+w1) <= x2)
-+ return 0;
-+
-+ if (y1 >= (y2+h2))
-+ return 0;
-+
-+ if ((y1+h1) <= y2)
-+ return 0;
-+
-+ return 1;
-+}
-+
-+static int dispc_is_overlay_scaled(struct omap_overlay_info *pi)
-+{
-+ if (pi->width != pi->out_width)
-+ return 1;
-+
-+ if (pi->height != pi->out_height)
-+ return 1;
-+
-+ return 0;
-+}
-+
-+/* returns the area that needs updating */
-+void dispc_setup_partial_planes(struct omap_display *display,
-+ u16 *xi, u16 *yi, u16 *wi, u16 *hi)
-+{
-+ struct omap_overlay_manager *mgr;
-+ int i;
-+
-+ int x, y, w, h;
-+
-+ x = *xi;
-+ y = *yi;
-+ w = *wi;
-+ h = *hi;
-+
-+ DSSDBG("dispc_setup_partial_planes %d,%d %dx%d\n",
-+ *xi, *yi, *wi, *hi);
-+
-+
-+ mgr = display->manager;
-+
-+ if (!mgr) {
-+ DSSDBG("no manager\n");
-+ return;
-+ }
-+
-+ for (i = 0; i < mgr->num_overlays; i++) {
-+ struct omap_overlay *ovl;
-+ struct omap_overlay_info *pi;
-+ ovl = mgr->overlays[i];
-+
-+ if (ovl->manager != mgr)
-+ continue;
-+
-+ if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
-+ continue;
-+
-+ pi = &ovl->info;
-+
-+ if (!pi->enabled)
-+ continue;
-+ /*
-+ * If the plane is intersecting and scaled, we
-+ * enlarge the update region to accomodate the
-+ * whole area
-+ */
-+
-+ if (dispc_is_intersecting(x, y, w, h,
-+ pi->pos_x, pi->pos_y,
-+ pi->out_width, pi->out_height)) {
-+ if (dispc_is_overlay_scaled(pi)) {
-+
-+ int x1, y1, x2, y2;
-+
-+ if (x > pi->pos_x)
-+ x1 = pi->pos_x;
-+ else
-+ x1 = x;
-+
-+ if (y > pi->pos_y)
-+ y1 = pi->pos_y;
-+ else
-+ y1 = y;
-+
-+ if ((x + w) < (pi->pos_x + pi->out_width))
-+ x2 = pi->pos_x + pi->out_width;
-+ else
-+ x2 = x + w;
-+
-+ if ((y + h) < (pi->pos_y + pi->out_height))
-+ y2 = pi->pos_y + pi->out_height;
-+ else
-+ y2 = y + h;
-+
-+ x = x1;
-+ y = y1;
-+ w = x2 - x1;
-+ h = y2 - y1;
-+
-+ DSSDBG("Update area after enlarge due to "
-+ "scaling %d, %d %dx%d\n",
-+ x, y, w, h);
-+ }
-+ }
-+ }
-+
-+ for (i = 0; i < mgr->num_overlays; i++) {
-+ struct omap_overlay *ovl = mgr->overlays[i];
-+ struct omap_overlay_info *pi = &ovl->info;
-+
-+ int px = pi->pos_x;
-+ int py = pi->pos_y;
-+ int pw = pi->width;
-+ int ph = pi->height;
-+ int pow = pi->out_width;
-+ int poh = pi->out_height;
-+ u32 pa = pi->paddr;
-+ int psw = pi->screen_width;
-+ int bpp;
-+
-+ if (ovl->manager != mgr)
-+ continue;
-+
-+ /*
-+ * If plane is not enabled or the update region
-+ * does not intersect with the plane in question,
-+ * we really disable the plane from hardware
-+ */
-+
-+ if (!pi->enabled ||
-+ !dispc_is_intersecting(x, y, w, h,
-+ px, py, pow, poh)) {
-+ dispc_enable_plane(ovl->id, 0);
-+ continue;
-+ }
-+
-+ switch (pi->color_mode) {
-+ case OMAP_DSS_COLOR_RGB16:
-+ case OMAP_DSS_COLOR_ARGB16:
-+ case OMAP_DSS_COLOR_YUV2:
-+ case OMAP_DSS_COLOR_UYVY:
-+ bpp = 16;
-+ break;
-+
-+ case OMAP_DSS_COLOR_RGB24P:
-+ bpp = 24;
-+ break;
-+
-+ case OMAP_DSS_COLOR_RGB24U:
-+ case OMAP_DSS_COLOR_ARGB32:
-+ case OMAP_DSS_COLOR_RGBA32:
-+ case OMAP_DSS_COLOR_RGBX32:
-+ bpp = 32;
-+ break;
-+
-+ default:
-+ BUG();
-+ return;
-+ }
-+
-+ if (x > pi->pos_x) {
-+ px = 0;
-+ pw -= (x - pi->pos_x);
-+ pa += (x - pi->pos_x) * bpp / 8;
-+ } else {
-+ px = pi->pos_x - x;
-+ }
-+
-+ if (y > pi->pos_y) {
-+ py = 0;
-+ ph -= (y - pi->pos_y);
-+ pa += (y - pi->pos_y) * psw * bpp / 8;
-+ } else {
-+ py = pi->pos_y - y;
-+ }
-+
-+ if (w < (px+pw))
-+ pw -= (px+pw) - (w);
-+
-+ if (h < (py+ph))
-+ ph -= (py+ph) - (h);
-+
-+ /* Can't scale the GFX plane */
-+ if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0 ||
-+ dispc_is_overlay_scaled(pi) == 0) {
-+ pow = pw;
-+ poh = ph;
-+ }
-+
-+ DSSDBG("calc plane %d, %x, sw %d, %d,%d, %dx%d -> %dx%d\n",
-+ ovl->id, pa, psw, px, py, pw, ph, pow, poh);
-+
-+ dispc_setup_plane(ovl->id, mgr->id,
-+ pa, psw,
-+ px, py,
-+ pw, ph,
-+ pow, poh,
-+ pi->color_mode, 0,
-+ pi->rotation, // XXX rotation probably wrong
-+ pi->mirror);
-+
-+ dispc_enable_plane(ovl->id, 1);
-+ }
-+
-+ *xi = x;
-+ *yi = y;
-+ *wi = w;
-+ *hi = h;
-+
-+}
-+
-diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c
-new file mode 100644
-index 0000000..9aaf392
---- /dev/null
-+++ b/drivers/video/omap2/dss/display.c
-@@ -0,0 +1,693 @@
-+/*
-+ * linux/drivers/video/omap2/dss/display.c
-+ *
-+ * Copyright (C) 2009 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * Some code and ideas taken from drivers/video/omap/ driver
-+ * by Imre Deak.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#define DSS_SUBSYS_NAME "DISPLAY"
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/jiffies.h>
-+#include <linux/list.h>
-+#include <linux/platform_device.h>
-+
-+#include <mach/display.h>
-+#include "dss.h"
-+
-+static int num_displays;
-+static LIST_HEAD(display_list);
-+
-+static ssize_t display_name_show(struct omap_display *display, char *buf)
-+{
-+ return snprintf(buf, PAGE_SIZE, "%s\n", display->name);
-+}
-+
-+static ssize_t display_enabled_show(struct omap_display *display, char *buf)
-+{
-+ bool enabled = display->state != OMAP_DSS_DISPLAY_DISABLED;
-+
-+ return snprintf(buf, PAGE_SIZE, "%d\n", enabled);
-+}
-+
-+static ssize_t display_enabled_store(struct omap_display *display,
-+ const char *buf, size_t size)
-+{
-+ bool enabled, r;
-+
-+ enabled = simple_strtoul(buf, NULL, 10);
-+
-+ if (enabled != (display->state != OMAP_DSS_DISPLAY_DISABLED)) {
-+ if (enabled) {
-+ r = display->enable(display);
-+ if (r)
-+ return r;
-+ } else {
-+ display->disable(display);
-+ }
-+ }
-+
-+ return size;
-+}
-+
-+static ssize_t display_upd_mode_show(struct omap_display *display, char *buf)
-+{
-+ enum omap_dss_update_mode mode = OMAP_DSS_UPDATE_AUTO;
-+ if (display->get_update_mode)
-+ mode = display->get_update_mode(display);
-+ return snprintf(buf, PAGE_SIZE, "%d\n", mode);
-+}
-+
-+static ssize_t display_upd_mode_store(struct omap_display *display,
-+ const char *buf, size_t size)
-+{
-+ int val, r;
-+ enum omap_dss_update_mode mode;
-+
-+ val = simple_strtoul(buf, NULL, 10);
-+
-+ switch (val) {
-+ case OMAP_DSS_UPDATE_DISABLED:
-+ case OMAP_DSS_UPDATE_AUTO:
-+ case OMAP_DSS_UPDATE_MANUAL:
-+ mode = (enum omap_dss_update_mode)val;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ if ((r = display->set_update_mode(display, mode)))
-+ return r;
-+
-+ return size;
-+}
-+
-+static ssize_t display_tear_show(struct omap_display *display, char *buf)
-+{
-+ return snprintf(buf, PAGE_SIZE, "%d\n",
-+ display->get_te ? display->get_te(display) : 0);
-+}
-+
-+static ssize_t display_tear_store(struct omap_display *display,
-+ const char *buf, size_t size)
-+{
-+ unsigned long te;
-+ int r;
-+
-+ if (!display->enable_te || !display->get_te)
-+ return -ENOENT;
-+
-+ te = simple_strtoul(buf, NULL, 0);
-+
-+ if ((r = display->enable_te(display, te)))
-+ return r;
-+
-+ return size;
-+}
-+
-+static ssize_t display_timings_show(struct omap_display *display, char *buf)
-+{
-+ struct omap_video_timings t;
-+
-+ if (!display->get_timings)
-+ return -ENOENT;
-+
-+ display->get_timings(display, &t);
-+
-+ return snprintf(buf, PAGE_SIZE, "%u,%u/%u/%u/%u,%u/%u/%u/%u\n",
-+ t.pixel_clock,
-+ t.x_res, t.hfp, t.hbp, t.hsw,
-+ t.y_res, t.vfp, t.vbp, t.vsw);
-+}
-+
-+static ssize_t display_timings_store(struct omap_display *display,
-+ const char *buf, size_t size)
-+{
-+ struct omap_video_timings t;
-+ int r, found;
-+
-+ if (!display->set_timings || !display->check_timings)
-+ return -ENOENT;
-+
-+ found = 0;
-+#ifdef CONFIG_OMAP2_DSS_VENC
-+ if (strncmp("pal", buf, 3) == 0) {
-+ t = omap_dss_pal_timings;
-+ found = 1;
-+ } else if (strncmp("ntsc", buf, 4) == 0) {
-+ t = omap_dss_ntsc_timings;
-+ found = 1;
-+ }
-+#endif
-+ if (!found && sscanf(buf, "%u,%hu/%hu/%hu/%hu,%hu/%hu/%hu/%hu",
-+ &t.pixel_clock,
-+ &t.x_res, &t.hfp, &t.hbp, &t.hsw,
-+ &t.y_res, &t.vfp, &t.vbp, &t.vsw) != 9)
-+ return -EINVAL;
-+
-+ if ((r = display->check_timings(display, &t)))
-+ return r;
-+
-+ display->set_timings(display, &t);
-+
-+ return size;
-+}
-+
-+static ssize_t display_rotate_show(struct omap_display *display, char *buf)
-+{
-+ int rotate;
-+ if (!display->get_rotate)
-+ return -ENOENT;
-+ rotate = display->get_rotate(display);
-+ return snprintf(buf, PAGE_SIZE, "%u\n", rotate);
-+}
-+
-+static ssize_t display_rotate_store(struct omap_display *display,
-+ const char *buf, size_t size)
-+{
-+ unsigned long rot;
-+ int r;
-+
-+ if (!display->set_rotate || !display->get_rotate)
-+ return -ENOENT;
-+
-+ rot = simple_strtoul(buf, NULL, 0);
-+
-+ if ((r = display->set_rotate(display, rot)))
-+ return r;
-+
-+ return size;
-+}
-+
-+static ssize_t display_mirror_show(struct omap_display *display, char *buf)
-+{
-+ int mirror;
-+ if (!display->get_mirror)
-+ return -ENOENT;
-+ mirror = display->get_mirror(display);
-+ return snprintf(buf, PAGE_SIZE, "%u\n", mirror);
-+}
-+
-+static ssize_t display_mirror_store(struct omap_display *display,
-+ const char *buf, size_t size)
-+{
-+ unsigned long mirror;
-+ int r;
-+
-+ if (!display->set_mirror || !display->get_mirror)
-+ return -ENOENT;
-+
-+ mirror = simple_strtoul(buf, NULL, 0);
-+
-+ if ((r = display->set_mirror(display, mirror)))
-+ return r;
-+
-+ return size;
-+}
-+
-+static ssize_t display_panel_name_show(struct omap_display *display, char *buf)
-+{
-+ return snprintf(buf, PAGE_SIZE, "%s\n",
-+ display->panel ? display->panel->name : "");
-+}
-+
-+static ssize_t display_ctrl_name_show(struct omap_display *display, char *buf)
-+{
-+ return snprintf(buf, PAGE_SIZE, "%s\n",
-+ display->ctrl ? display->ctrl->name : "");
-+}
-+
-+struct display_attribute {
-+ struct attribute attr;
-+ ssize_t (*show)(struct omap_display *, char *);
-+ ssize_t (*store)(struct omap_display *, const char *, size_t);
-+};
-+
-+#define DISPLAY_ATTR(_name, _mode, _show, _store) \
-+ struct display_attribute display_attr_##_name = \
-+ __ATTR(_name, _mode, _show, _store)
-+
-+static DISPLAY_ATTR(name, S_IRUGO, display_name_show, NULL);
-+static DISPLAY_ATTR(enabled, S_IRUGO|S_IWUSR,
-+ display_enabled_show, display_enabled_store);
-+static DISPLAY_ATTR(update_mode, S_IRUGO|S_IWUSR,
-+ display_upd_mode_show, display_upd_mode_store);
-+static DISPLAY_ATTR(tear_elim, S_IRUGO|S_IWUSR,
-+ display_tear_show, display_tear_store);
-+static DISPLAY_ATTR(timings, S_IRUGO|S_IWUSR,
-+ display_timings_show, display_timings_store);
-+static DISPLAY_ATTR(rotate, S_IRUGO|S_IWUSR,
-+ display_rotate_show, display_rotate_store);
-+static DISPLAY_ATTR(mirror, S_IRUGO|S_IWUSR,
-+ display_mirror_show, display_mirror_store);
-+static DISPLAY_ATTR(panel_name, S_IRUGO, display_panel_name_show, NULL);
-+static DISPLAY_ATTR(ctrl_name, S_IRUGO, display_ctrl_name_show, NULL);
-+
-+static struct attribute *display_sysfs_attrs[] = {
-+ &display_attr_name.attr,
-+ &display_attr_enabled.attr,
-+ &display_attr_update_mode.attr,
-+ &display_attr_tear_elim.attr,
-+ &display_attr_timings.attr,
-+ &display_attr_rotate.attr,
-+ &display_attr_mirror.attr,
-+ &display_attr_panel_name.attr,
-+ &display_attr_ctrl_name.attr,
-+ NULL
-+};
-+
-+static ssize_t display_attr_show(struct kobject *kobj, struct attribute *attr, char *buf)
-+{
-+ struct omap_display *display;
-+ struct display_attribute *display_attr;
-+
-+ display = container_of(kobj, struct omap_display, kobj);
-+ display_attr = container_of(attr, struct display_attribute, attr);
-+
-+ if (!display_attr->show)
-+ return -ENOENT;
-+
-+ return display_attr->show(display, buf);
-+}
-+
-+static ssize_t display_attr_store(struct kobject *kobj, struct attribute *attr,
-+ const char *buf, size_t size)
-+{
-+ struct omap_display *display;
-+ struct display_attribute *display_attr;
-+
-+ display = container_of(kobj, struct omap_display, kobj);
-+ display_attr = container_of(attr, struct display_attribute, attr);
-+
-+ if (!display_attr->store)
-+ return -ENOENT;
-+
-+ return display_attr->store(display, buf, size);
-+}
-+
-+static struct sysfs_ops display_sysfs_ops = {
-+ .show = display_attr_show,
-+ .store = display_attr_store,
-+};
-+
-+static struct kobj_type display_ktype = {
-+ .sysfs_ops = &display_sysfs_ops,
-+ .default_attrs = display_sysfs_attrs,
-+};
-+
-+static void default_get_resolution(struct omap_display *display,
-+ u16 *xres, u16 *yres)
-+{
-+ *xres = display->panel->timings.x_res;
-+ *yres = display->panel->timings.y_res;
-+}
-+
-+static void default_configure_overlay(struct omap_overlay *ovl)
-+{
-+ unsigned low, high, size;
-+ enum omap_burst_size burst;
-+ enum omap_plane plane = ovl->id;
-+
-+ burst = OMAP_DSS_BURST_16x32;
-+ size = 16 * 32 / 8;
-+
-+ dispc_set_burst_size(plane, burst);
-+
-+ high = dispc_get_plane_fifo_size(plane) - 1;
-+ low = dispc_get_plane_fifo_size(plane) - size;
-+
-+ dispc_setup_plane_fifo(plane, low, high);
-+}
-+
-+static int default_wait_vsync(struct omap_display *display)
-+{
-+ unsigned long timeout = msecs_to_jiffies(500);
-+ u32 irq;
-+
-+ if (display->type == OMAP_DISPLAY_TYPE_VENC)
-+ irq = DISPC_IRQ_EVSYNC_ODD;
-+ else
-+ irq = DISPC_IRQ_VSYNC;
-+
-+ return omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
-+}
-+
-+static int default_get_recommended_bpp(struct omap_display *display)
-+{
-+ if (display->panel->recommended_bpp)
-+ return display->panel->recommended_bpp;
-+
-+ switch (display->type) {
-+ case OMAP_DISPLAY_TYPE_DPI:
-+ if (display->hw_config.u.dpi.data_lines == 24)
-+ return 24;
-+ else
-+ return 16;
-+
-+ case OMAP_DISPLAY_TYPE_DBI:
-+ case OMAP_DISPLAY_TYPE_DSI:
-+ if (display->ctrl->pixel_size == 24)
-+ return 24;
-+ else
-+ return 16;
-+ case OMAP_DISPLAY_TYPE_VENC:
-+ case OMAP_DISPLAY_TYPE_SDI:
-+ return 24;
-+ return 24;
-+ default:
-+ BUG();
-+ }
-+}
-+
-+void dss_init_displays(struct platform_device *pdev)
-+{
-+ struct omap_dss_board_info *pdata = pdev->dev.platform_data;
-+ int i, r;
-+
-+ INIT_LIST_HEAD(&display_list);
-+
-+ num_displays = 0;
-+
-+ for (i = 0; i < pdata->num_displays; ++i) {
-+ struct omap_display *display;
-+
-+ switch (pdata->displays[i]->type) {
-+ case OMAP_DISPLAY_TYPE_DPI:
-+#ifdef CONFIG_OMAP2_DSS_RFBI
-+ case OMAP_DISPLAY_TYPE_DBI:
-+#endif
-+#ifdef CONFIG_OMAP2_DSS_SDI
-+ case OMAP_DISPLAY_TYPE_SDI:
-+#endif
-+#ifdef CONFIG_OMAP2_DSS_DSI
-+ case OMAP_DISPLAY_TYPE_DSI:
-+#endif
-+#ifdef CONFIG_OMAP2_DSS_VENC
-+ case OMAP_DISPLAY_TYPE_VENC:
-+#endif
-+ break;
-+ default:
-+ DSSERR("Support for display '%s' not compiled in.\n",
-+ pdata->displays[i]->name);
-+ continue;
-+ }
-+
-+ display = kzalloc(sizeof(*display), GFP_KERNEL);
-+
-+ /*atomic_set(&display->ref_count, 0);*/
-+ display->ref_count = 0;
-+
-+ display->hw_config = *pdata->displays[i];
-+ display->type = pdata->displays[i]->type;
-+ display->name = pdata->displays[i]->name;
-+
-+ display->get_resolution = default_get_resolution;
-+ display->get_recommended_bpp = default_get_recommended_bpp;
-+ display->configure_overlay = default_configure_overlay;
-+ display->wait_vsync = default_wait_vsync;
-+
-+ switch (display->type) {
-+ case OMAP_DISPLAY_TYPE_DPI:
-+ dpi_init_display(display);
-+ break;
-+#ifdef CONFIG_OMAP2_DSS_RFBI
-+ case OMAP_DISPLAY_TYPE_DBI:
-+ rfbi_init_display(display);
-+ break;
-+#endif
-+#ifdef CONFIG_OMAP2_DSS_VENC
-+ case OMAP_DISPLAY_TYPE_VENC:
-+ venc_init_display(display);
-+ break;
-+#endif
-+#ifdef CONFIG_OMAP2_DSS_SDI
-+ case OMAP_DISPLAY_TYPE_SDI:
-+ sdi_init_display(display);
-+ break;
-+#endif
-+#ifdef CONFIG_OMAP2_DSS_DSI
-+ case OMAP_DISPLAY_TYPE_DSI:
-+ dsi_init_display(display);
-+ break;
-+#endif
-+ default:
-+ BUG();
-+ }
-+
-+ r = kobject_init_and_add(&display->kobj, &display_ktype,
-+ &pdev->dev.kobj, "display%d", num_displays);
-+
-+ if (r) {
-+ DSSERR("failed to create sysfs file\n");
-+ continue;
-+ }
-+
-+ num_displays++;
-+
-+ list_add_tail(&display->list, &display_list);
-+ }
-+}
-+
-+void dss_uninit_displays(struct platform_device *pdev)
-+{
-+ struct omap_display *display;
-+
-+ while (!list_empty(&display_list)) {
-+ display = list_first_entry(&display_list,
-+ struct omap_display, list);
-+ list_del(&display->list);
-+ kobject_del(&display->kobj);
-+ kobject_put(&display->kobj);
-+ kfree(display);
-+ }
-+
-+ num_displays = 0;
-+}
-+
-+int dss_suspend_all_displays(void)
-+{
-+ int r;
-+ struct omap_display *display;
-+
-+ list_for_each_entry(display, &display_list, list) {
-+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE) {
-+ display->activate_after_resume = 0;
-+ continue;
-+ }
-+
-+ if (!display->suspend) {
-+ DSSERR("display '%s' doesn't implement suspend\n",
-+ display->name);
-+ r = -ENOSYS;
-+ goto err;
-+ }
-+
-+ r = display->suspend(display);
-+
-+ if (r)
-+ goto err;
-+
-+ display->activate_after_resume = 1;
-+ }
-+
-+ return 0;
-+err:
-+ /* resume all displays that were suspended */
-+ dss_resume_all_displays();
-+ return r;
-+}
-+
-+int dss_resume_all_displays(void)
-+{
-+ int r;
-+ struct omap_display *display;
-+
-+ list_for_each_entry(display, &display_list, list) {
-+ if (display->activate_after_resume && display->resume) {
-+ r = display->resume(display);
-+ if (r)
-+ return r;
-+ }
-+
-+ display->activate_after_resume = 0;
-+ }
-+
-+ return 0;
-+}
-+
-+int omap_dss_get_num_displays(void)
-+{
-+ return num_displays;
-+}
-+EXPORT_SYMBOL(omap_dss_get_num_displays);
-+
-+struct omap_display *dss_get_display(int no)
-+{
-+ int i = 0;
-+ struct omap_display *display;
-+
-+ list_for_each_entry(display, &display_list, list) {
-+ if (i++ == no)
-+ return display;
-+ }
-+
-+ return NULL;
-+}
-+
-+struct omap_display *omap_dss_get_display(int no)
-+{
-+ struct omap_display *display;
-+
-+ display = dss_get_display(no);
-+
-+ if (!display)
-+ return NULL;
-+
-+ switch (display->type) {
-+ case OMAP_DISPLAY_TYPE_VENC:
-+ break;
-+
-+ case OMAP_DISPLAY_TYPE_DPI:
-+ case OMAP_DISPLAY_TYPE_SDI:
-+ if (display->panel == NULL)
-+ return NULL;
-+ break;
-+
-+ case OMAP_DISPLAY_TYPE_DBI:
-+ case OMAP_DISPLAY_TYPE_DSI:
-+ if (display->panel == NULL || display->ctrl == NULL)
-+ return NULL;
-+ break;
-+
-+ default:
-+ return NULL;
-+ }
-+
-+ if (display->ctrl) {
-+ if (!try_module_get(display->ctrl->owner))
-+ goto err0;
-+
-+ if (display->ctrl->init)
-+ if (display->ctrl->init(display) != 0)
-+ goto err1;
-+ }
-+
-+ if (display->panel) {
-+ if (!try_module_get(display->panel->owner))
-+ goto err2;
-+
-+ if (display->panel->init)
-+ if (display->panel->init(display) != 0)
-+ goto err3;
-+ }
-+
-+ display->ref_count++;
-+ /*
-+ if (atomic_cmpxchg(&display->ref_count, 0, 1) != 0)
-+ return 0;
-+*/
-+
-+ return display;
-+err3:
-+ if (display->panel)
-+ module_put(display->panel->owner);
-+err2:
-+ if (display->ctrl && display->ctrl->cleanup)
-+ display->ctrl->cleanup(display);
-+err1:
-+ if (display->ctrl)
-+ module_put(display->ctrl->owner);
-+err0:
-+ return NULL;
-+}
-+EXPORT_SYMBOL(omap_dss_get_display);
-+
-+void omap_dss_put_display(struct omap_display *display)
-+{
-+ if (--display->ref_count > 0)
-+ return;
-+/*
-+ if (atomic_cmpxchg(&display->ref_count, 1, 0) != 1)
-+ return;
-+*/
-+ if (display->ctrl) {
-+ if (display->ctrl->cleanup)
-+ display->ctrl->cleanup(display);
-+ module_put(display->ctrl->owner);
-+ }
-+
-+ if (display->panel) {
-+ if (display->panel->cleanup)
-+ display->panel->cleanup(display);
-+ module_put(display->panel->owner);
-+ }
-+}
-+EXPORT_SYMBOL(omap_dss_put_display);
-+
-+void omap_dss_register_ctrl(struct omap_ctrl *ctrl)
-+{
-+ struct omap_display *display;
-+
-+ list_for_each_entry(display, &display_list, list) {
-+ if (display->hw_config.ctrl_name &&
-+ strcmp(display->hw_config.ctrl_name, ctrl->name) == 0) {
-+ display->ctrl = ctrl;
-+ DSSDBG("ctrl '%s' registered\n", ctrl->name);
-+ }
-+ }
-+}
-+EXPORT_SYMBOL(omap_dss_register_ctrl);
-+
-+void omap_dss_register_panel(struct omap_panel *panel)
-+{
-+ struct omap_display *display;
-+
-+ list_for_each_entry(display, &display_list, list) {
-+ if (display->hw_config.panel_name &&
-+ strcmp(display->hw_config.panel_name, panel->name) == 0) {
-+ display->panel = panel;
-+ DSSDBG("panel '%s' registered\n", panel->name);
-+ }
-+ }
-+}
-+EXPORT_SYMBOL(omap_dss_register_panel);
-+
-+void omap_dss_unregister_ctrl(struct omap_ctrl *ctrl)
-+{
-+ struct omap_display *display;
-+
-+ list_for_each_entry(display, &display_list, list) {
-+ if (display->hw_config.ctrl_name &&
-+ strcmp(display->hw_config.ctrl_name, ctrl->name) == 0)
-+ display->ctrl = NULL;
-+ }
-+}
-+EXPORT_SYMBOL(omap_dss_unregister_ctrl);
-+
-+void omap_dss_unregister_panel(struct omap_panel *panel)
-+{
-+ struct omap_display *display;
-+
-+ list_for_each_entry(display, &display_list, list) {
-+ if (display->hw_config.panel_name &&
-+ strcmp(display->hw_config.panel_name, panel->name) == 0)
-+ display->panel = NULL;
-+ }
-+}
-+EXPORT_SYMBOL(omap_dss_unregister_panel);
-diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c
-new file mode 100644
-index 0000000..71fffca
---- /dev/null
-+++ b/drivers/video/omap2/dss/dpi.c
-@@ -0,0 +1,393 @@
-+/*
-+ * linux/drivers/video/omap2/dss/dpi.c
-+ *
-+ * Copyright (C) 2009 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * Some code and ideas taken from drivers/video/omap/ driver
-+ * by Imre Deak.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/errno.h>
-+
-+#include <mach/board.h>
-+#include <mach/display.h>
-+#include <mach/cpu.h>
-+
-+#include "dss.h"
-+
-+static struct {
-+ int update_enabled;
-+} dpi;
-+
-+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
-+static int dpi_set_dsi_clk(bool is_tft, unsigned long pck_req,
-+ unsigned long *fck, int *lck_div, int *pck_div)
-+{
-+ struct dsi_clock_info cinfo;
-+ int r;
-+
-+ r = dsi_pll_calc_pck(is_tft, pck_req, &cinfo);
-+ if (r)
-+ return r;
-+
-+ r = dsi_pll_program(&cinfo);
-+ if (r)
-+ return r;
-+
-+ dss_select_clk_source(0, 1);
-+
-+ dispc_set_lcd_divisor(cinfo.lck_div, cinfo.pck_div);
-+
-+ *fck = cinfo.dsi1_pll_fclk;
-+ *lck_div = cinfo.lck_div;
-+ *pck_div = cinfo.pck_div;
-+
-+ return 0;
-+}
-+#else
-+static int dpi_set_dispc_clk(bool is_tft, unsigned long pck_req,
-+ unsigned long *fck, int *lck_div, int *pck_div)
-+{
-+ struct dispc_clock_info cinfo;
-+ int r;
-+
-+ r = dispc_calc_clock_div(is_tft, pck_req, &cinfo);
-+ if (r)
-+ return r;
-+
-+ r = dispc_set_clock_div(&cinfo);
-+ if (r)
-+ return r;
-+
-+ *fck = cinfo.fck;
-+ *lck_div = cinfo.lck_div;
-+ *pck_div = cinfo.pck_div;
-+
-+ return 0;
-+}
-+#endif
-+
-+static int dpi_set_mode(struct omap_display *display)
-+{
-+ struct omap_panel *panel = display->panel;
-+ int lck_div, pck_div;
-+ unsigned long fck;
-+ unsigned long pck;
-+ bool is_tft;
-+ int r = 0;
-+
-+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+
-+ dispc_set_pol_freq(panel);
-+
-+ is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0;
-+
-+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
-+ r = dpi_set_dsi_clk(is_tft, panel->timings.pixel_clock * 1000,
-+ &fck, &lck_div, &pck_div);
-+#else
-+ r = dpi_set_dispc_clk(is_tft, panel->timings.pixel_clock * 1000,
-+ &fck, &lck_div, &pck_div);
-+#endif
-+ if (r)
-+ goto err0;
-+
-+ pck = fck / lck_div / pck_div / 1000;
-+
-+ if (pck != panel->timings.pixel_clock) {
-+ DSSWARN("Could not find exact pixel clock. "
-+ "Requested %d kHz, got %lu kHz\n",
-+ panel->timings.pixel_clock, pck);
-+
-+ panel->timings.pixel_clock = pck;
-+ }
-+
-+ dispc_set_lcd_timings(&panel->timings);
-+
-+err0:
-+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+ return r;
-+}
-+
-+static int dpi_basic_init(struct omap_display *display)
-+{
-+ bool is_tft;
-+
-+ is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0;
-+
-+ dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS);
-+ dispc_set_lcd_display_type(is_tft ? OMAP_DSS_LCD_DISPLAY_TFT :
-+ OMAP_DSS_LCD_DISPLAY_STN);
-+ dispc_set_tft_data_lines(display->hw_config.u.dpi.data_lines);
-+
-+ return 0;
-+}
-+
-+static int dpi_display_enable(struct omap_display *display)
-+{
-+ struct omap_panel *panel = display->panel;
-+ int r;
-+
-+ if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
-+ DSSERR("display already enabled\n");
-+ return -EINVAL;
-+ }
-+
-+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+
-+ r = dpi_basic_init(display);
-+ if (r)
-+ goto err0;
-+
-+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
-+ dss_clk_enable(DSS_CLK_FCK2);
-+ r = dsi_pll_init(0, 1);
-+ if (r)
-+ goto err1;
-+#endif
-+ r = dpi_set_mode(display);
-+ if (r)
-+ goto err2;
-+
-+ mdelay(2);
-+
-+ dispc_enable_lcd_out(1);
-+
-+ r = panel->enable(display);
-+ if (r)
-+ goto err3;
-+
-+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
-+
-+ return 0;
-+
-+err3:
-+ dispc_enable_lcd_out(0);
-+err2:
-+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
-+ dsi_pll_uninit();
-+err1:
-+ dss_clk_disable(DSS_CLK_FCK2);
-+#endif
-+err0:
-+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+ return r;
-+}
-+
-+static int dpi_display_resume(struct omap_display *display);
-+
-+static void dpi_display_disable(struct omap_display *display)
-+{
-+ if (display->state == OMAP_DSS_DISPLAY_DISABLED)
-+ return;
-+
-+ if (display->state == OMAP_DSS_DISPLAY_SUSPENDED)
-+ dpi_display_resume(display);
-+
-+ display->panel->disable(display);
-+
-+ dispc_enable_lcd_out(0);
-+
-+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
-+ dss_select_clk_source(0, 0);
-+ dsi_pll_uninit();
-+ dss_clk_disable(DSS_CLK_FCK2);
-+#endif
-+
-+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+
-+ display->state = OMAP_DSS_DISPLAY_DISABLED;
-+}
-+
-+static int dpi_display_suspend(struct omap_display *display)
-+{
-+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
-+ return -EINVAL;
-+
-+ DSSDBG("dpi_display_suspend\n");
-+
-+ if (display->panel->suspend)
-+ display->panel->suspend(display);
-+
-+ dispc_enable_lcd_out(0);
-+
-+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+
-+ display->state = OMAP_DSS_DISPLAY_SUSPENDED;
-+
-+ return 0;
-+}
-+
-+static int dpi_display_resume(struct omap_display *display)
-+{
-+ if (display->state != OMAP_DSS_DISPLAY_SUSPENDED)
-+ return -EINVAL;
-+
-+ DSSDBG("dpi_display_resume\n");
-+
-+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+
-+ dispc_enable_lcd_out(1);
-+
-+ if (display->panel->resume)
-+ display->panel->resume(display);
-+
-+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
-+
-+ return 0;
-+}
-+
-+static void dpi_set_timings(struct omap_display *display,
-+ struct omap_video_timings *timings)
-+{
-+ DSSDBG("dpi_set_timings\n");
-+ display->panel->timings = *timings;
-+ if (display->state == OMAP_DSS_DISPLAY_ACTIVE) {
-+ dpi_set_mode(display);
-+ dispc_go(OMAP_DSS_CHANNEL_LCD);
-+ }
-+}
-+
-+static int dpi_check_timings(struct omap_display *display,
-+ struct omap_video_timings *timings)
-+{
-+ bool is_tft;
-+ int r;
-+ int lck_div, pck_div;
-+ unsigned long fck;
-+ unsigned long pck;
-+
-+ if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
-+ if (timings->hsw < 1 || timings->hsw > 64 ||
-+ timings->hfp < 1 || timings->hfp > 256 ||
-+ timings->hbp < 1 || timings->hbp > 256) {
-+ return -EINVAL;
-+ }
-+
-+ if (timings->vsw < 1 || timings->vsw > 64 ||
-+ timings->vfp > 255 || timings->vbp > 255) {
-+ return -EINVAL;
-+ }
-+ } else {
-+ if (timings->hsw < 1 || timings->hsw > 256 ||
-+ timings->hfp < 1 || timings->hfp > 4096 ||
-+ timings->hbp < 1 || timings->hbp > 4096) {
-+ return -EINVAL;
-+ }
-+
-+ if (timings->vsw < 1 || timings->vsw > 64 ||
-+ timings->vfp > 4095 || timings->vbp > 4095) {
-+ return -EINVAL;
-+ }
-+ }
-+
-+ if (timings->pixel_clock == 0)
-+ return -EINVAL;
-+
-+ is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0;
-+
-+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
-+ {
-+ struct dsi_clock_info cinfo;
-+ r = dsi_pll_calc_pck(is_tft, timings->pixel_clock * 1000,
-+ &cinfo);
-+
-+ if (r)
-+ return r;
-+
-+ fck = cinfo.dsi1_pll_fclk;
-+ lck_div = cinfo.lck_div;
-+ pck_div = cinfo.pck_div;
-+ }
-+#else
-+ {
-+ struct dispc_clock_info cinfo;
-+ r = dispc_calc_clock_div(is_tft, timings->pixel_clock * 1000,
-+ &cinfo);
-+
-+ if (r)
-+ return r;
-+
-+ fck = cinfo.fck;
-+ lck_div = cinfo.lck_div;
-+ pck_div = cinfo.pck_div;
-+ }
-+#endif
-+
-+ pck = fck / lck_div / pck_div / 1000;
-+
-+ timings->pixel_clock = pck;
-+
-+ return 0;
-+}
-+
-+static void dpi_get_timings(struct omap_display *display,
-+ struct omap_video_timings *timings)
-+{
-+ *timings = display->panel->timings;
-+}
-+
-+static int dpi_display_set_update_mode(struct omap_display *display,
-+ enum omap_dss_update_mode mode)
-+{
-+ if (mode == OMAP_DSS_UPDATE_MANUAL)
-+ return -EINVAL;
-+
-+ if (mode == OMAP_DSS_UPDATE_DISABLED) {
-+ dispc_enable_lcd_out(0);
-+ dpi.update_enabled = 0;
-+ } else {
-+ dispc_enable_lcd_out(1);
-+ dpi.update_enabled = 1;
-+ }
-+
-+ return 0;
-+}
-+
-+static enum omap_dss_update_mode dpi_display_get_update_mode(
-+ struct omap_display *display)
-+{
-+ return dpi.update_enabled ? OMAP_DSS_UPDATE_AUTO :
-+ OMAP_DSS_UPDATE_DISABLED;
-+}
-+
-+void dpi_init_display(struct omap_display *display)
-+{
-+ DSSDBG("DPI init_display\n");
-+
-+ display->enable = dpi_display_enable;
-+ display->disable = dpi_display_disable;
-+ display->suspend = dpi_display_suspend;
-+ display->resume = dpi_display_resume;
-+ display->set_timings = dpi_set_timings;
-+ display->check_timings = dpi_check_timings;
-+ display->get_timings = dpi_get_timings;
-+ display->set_update_mode = dpi_display_set_update_mode;
-+ display->get_update_mode = dpi_display_get_update_mode;
-+}
-+
-+int dpi_init(void)
-+{
-+ return 0;
-+}
-+
-+void dpi_exit(void)
-+{
-+}
-+
-diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
-new file mode 100644
-index 0000000..4442931
---- /dev/null
-+++ b/drivers/video/omap2/dss/dsi.c
-@@ -0,0 +1,3752 @@
-+/*
-+ * linux/drivers/video/omap2/dss/dsi.c
-+ *
-+ * Copyright (C) 2009 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#define DSS_SUBSYS_NAME "DSI"
-+
-+#include <linux/kernel.h>
-+#include <linux/io.h>
-+#include <linux/clk.h>
-+#include <linux/device.h>
-+#include <linux/err.h>
-+#include <linux/interrupt.h>
-+#include <linux/delay.h>
-+#include <linux/workqueue.h>
-+#include <linux/mutex.h>
-+#include <linux/seq_file.h>
-+#include <linux/kfifo.h>
-+
-+#include <mach/board.h>
-+#include <mach/display.h>
-+#include <mach/clock.h>
-+
-+#include "dss.h"
-+
-+/*#define VERBOSE_IRQ*/
-+
-+#define DSI_BASE 0x4804FC00
-+
-+struct dsi_reg { u16 idx; };
-+
-+#define DSI_REG(idx) ((const struct dsi_reg) { idx })
-+
-+#define DSI_SZ_REGS SZ_1K
-+/* DSI Protocol Engine */
-+
-+#define DSI_REVISION DSI_REG(0x0000)
-+#define DSI_SYSCONFIG DSI_REG(0x0010)
-+#define DSI_SYSSTATUS DSI_REG(0x0014)
-+#define DSI_IRQSTATUS DSI_REG(0x0018)
-+#define DSI_IRQENABLE DSI_REG(0x001C)
-+#define DSI_CTRL DSI_REG(0x0040)
-+#define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
-+#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
-+#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
-+#define DSI_CLK_CTRL DSI_REG(0x0054)
-+#define DSI_TIMING1 DSI_REG(0x0058)
-+#define DSI_TIMING2 DSI_REG(0x005C)
-+#define DSI_VM_TIMING1 DSI_REG(0x0060)
-+#define DSI_VM_TIMING2 DSI_REG(0x0064)
-+#define DSI_VM_TIMING3 DSI_REG(0x0068)
-+#define DSI_CLK_TIMING DSI_REG(0x006C)
-+#define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
-+#define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
-+#define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
-+#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
-+#define DSI_VM_TIMING4 DSI_REG(0x0080)
-+#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
-+#define DSI_VM_TIMING5 DSI_REG(0x0088)
-+#define DSI_VM_TIMING6 DSI_REG(0x008C)
-+#define DSI_VM_TIMING7 DSI_REG(0x0090)
-+#define DSI_STOPCLK_TIMING DSI_REG(0x0094)
-+#define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
-+#define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
-+#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
-+#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
-+#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
-+#define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
-+#define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
-+
-+/* DSIPHY_SCP */
-+
-+#define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
-+#define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
-+#define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
-+#define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
-+
-+/* DSI_PLL_CTRL_SCP */
-+
-+#define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
-+#define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
-+#define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
-+#define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
-+#define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
-+
-+#define REG_GET(idx, start, end) \
-+ FLD_GET(dsi_read_reg(idx), start, end)
-+
-+#define REG_FLD_MOD(idx, val, start, end) \
-+ dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
-+
-+/* Global interrupts */
-+#define DSI_IRQ_VC0 (1 << 0)
-+#define DSI_IRQ_VC1 (1 << 1)
-+#define DSI_IRQ_VC2 (1 << 2)
-+#define DSI_IRQ_VC3 (1 << 3)
-+#define DSI_IRQ_WAKEUP (1 << 4)
-+#define DSI_IRQ_RESYNC (1 << 5)
-+#define DSI_IRQ_PLL_LOCK (1 << 7)
-+#define DSI_IRQ_PLL_UNLOCK (1 << 8)
-+#define DSI_IRQ_PLL_RECALL (1 << 9)
-+#define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
-+#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
-+#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
-+#define DSI_IRQ_TE_TRIGGER (1 << 16)
-+#define DSI_IRQ_ACK_TRIGGER (1 << 17)
-+#define DSI_IRQ_SYNC_LOST (1 << 18)
-+#define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
-+#define DSI_IRQ_TA_TIMEOUT (1 << 20)
-+#define DSI_IRQ_ERROR_MASK \
-+ (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
-+ DSI_IRQ_TA_TIMEOUT)
-+#define DSI_IRQ_CHANNEL_MASK 0xf
-+
-+/* Virtual channel interrupts */
-+#define DSI_VC_IRQ_CS (1 << 0)
-+#define DSI_VC_IRQ_ECC_CORR (1 << 1)
-+#define DSI_VC_IRQ_PACKET_SENT (1 << 2)
-+#define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
-+#define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
-+#define DSI_VC_IRQ_BTA (1 << 5)
-+#define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
-+#define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
-+#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
-+#define DSI_VC_IRQ_ERROR_MASK \
-+ (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
-+ DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
-+ DSI_VC_IRQ_FIFO_TX_UDF)
-+
-+/* ComplexIO interrupts */
-+#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
-+#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
-+#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
-+#define DSI_CIO_IRQ_ERRESC1 (1 << 5)
-+#define DSI_CIO_IRQ_ERRESC2 (1 << 6)
-+#define DSI_CIO_IRQ_ERRESC3 (1 << 7)
-+#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
-+#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
-+#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
-+#define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
-+#define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
-+#define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
-+#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
-+#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
-+#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
-+#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
-+#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
-+#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
-+#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
-+#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
-+
-+#define DSI_DT_DCS_SHORT_WRITE_0 0x05
-+#define DSI_DT_DCS_SHORT_WRITE_1 0x15
-+#define DSI_DT_DCS_READ 0x06
-+#define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
-+#define DSI_DT_NULL_PACKET 0x09
-+#define DSI_DT_DCS_LONG_WRITE 0x39
-+
-+#define DSI_DT_RX_ACK_WITH_ERR 0x02
-+#define DSI_DT_RX_DCS_LONG_READ 0x1c
-+#define DSI_DT_RX_SHORT_READ_1 0x21
-+#define DSI_DT_RX_SHORT_READ_2 0x22
-+
-+#define FINT_MAX 2100000
-+#define FINT_MIN 750000
-+#define REGN_MAX (1 << 7)
-+#define REGM_MAX ((1 << 11) - 1)
-+#define REGM3_MAX (1 << 4)
-+#define REGM4_MAX (1 << 4)
-+
-+enum fifo_size {
-+ DSI_FIFO_SIZE_0 = 0,
-+ DSI_FIFO_SIZE_32 = 1,
-+ DSI_FIFO_SIZE_64 = 2,
-+ DSI_FIFO_SIZE_96 = 3,
-+ DSI_FIFO_SIZE_128 = 4,
-+};
-+
-+#define DSI_CMD_FIFO_LEN 16
-+
-+struct dsi_cmd_update {
-+ int bytespp;
-+ u16 x;
-+ u16 y;
-+ u16 w;
-+ u16 h;
-+};
-+
-+struct dsi_cmd_mem_read {
-+ void *buf;
-+ size_t size;
-+ u16 x;
-+ u16 y;
-+ u16 w;
-+ u16 h;
-+ size_t *ret_size;
-+ struct completion *completion;
-+};
-+
-+struct dsi_cmd_test {
-+ int test_num;
-+ int *result;
-+ struct completion *completion;
-+};
-+
-+enum dsi_cmd {
-+ DSI_CMD_UPDATE,
-+ DSI_CMD_AUTOUPDATE,
-+ DSI_CMD_SYNC,
-+ DSI_CMD_MEM_READ,
-+ DSI_CMD_TEST,
-+ DSI_CMD_SET_TE,
-+ DSI_CMD_SET_UPDATE_MODE,
-+ DSI_CMD_SET_ROTATE,
-+ DSI_CMD_SET_MIRROR,
-+};
-+
-+struct dsi_cmd_item {
-+ struct omap_display *display;
-+
-+ enum dsi_cmd cmd;
-+
-+ union {
-+ struct dsi_cmd_update r;
-+ struct completion *sync;
-+ struct dsi_cmd_mem_read mem_read;
-+ struct dsi_cmd_test test;
-+ int te;
-+ enum omap_dss_update_mode update_mode;
-+ int rotate;
-+ int mirror;
-+ } u;
-+};
-+
-+static struct
-+{
-+ void __iomem *base;
-+
-+ unsigned long dsi1_pll_fclk; /* Hz */
-+ unsigned long dsi2_pll_fclk; /* Hz */
-+ unsigned long dsiphy; /* Hz */
-+ unsigned long ddr_clk; /* Hz */
-+
-+ struct {
-+ struct omap_display *display;
-+ enum fifo_size fifo_size;
-+ int dest_per; /* destination peripheral 0-3 */
-+ } vc[4];
-+
-+ struct mutex lock;
-+
-+ unsigned pll_locked;
-+
-+ struct completion bta_completion;
-+
-+ struct work_struct framedone_work;
-+ struct work_struct process_work;
-+ struct workqueue_struct *workqueue;
-+
-+ enum omap_dss_update_mode user_update_mode;
-+ enum omap_dss_update_mode target_update_mode;
-+ enum omap_dss_update_mode update_mode;
-+ int use_te;
-+ int framedone_scheduled; /* helps to catch strange framedone bugs */
-+
-+ unsigned long cache_req_pck;
-+ unsigned long cache_clk_freq;
-+ struct dsi_clock_info cache_cinfo;
-+
-+ struct kfifo *cmd_fifo;
-+ spinlock_t cmd_lock;
-+ struct completion cmd_done;
-+ atomic_t cmd_fifo_full;
-+ atomic_t cmd_pending;
-+
-+ bool autoupdate_setup;
-+
-+#ifdef DEBUG
-+ ktime_t perf_setup_time;
-+ ktime_t perf_start_time;
-+ int perf_measure_frames;
-+
-+ struct {
-+ int x, y, w, h;
-+ int bytespp;
-+ } update_region;
-+
-+#endif
-+ int debug_process;
-+ int debug_read;
-+ int debug_write;
-+} dsi;
-+
-+#ifdef DEBUG
-+static unsigned int dsi_perf;
-+module_param_named(dsi_perf, dsi_perf, bool, 0644);
-+#endif
-+
-+static void dsi_process_cmd_fifo(struct work_struct *work);
-+static void dsi_push_update(struct omap_display *display,
-+ int x, int y, int w, int h);
-+static void dsi_push_autoupdate(struct omap_display *display);
-+
-+static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
-+{
-+ __raw_writel(val, dsi.base + idx.idx);
-+}
-+
-+static inline u32 dsi_read_reg(const struct dsi_reg idx)
-+{
-+ return __raw_readl(dsi.base + idx.idx);
-+}
-+
-+
-+void dsi_save_context(void)
-+{
-+}
-+
-+void dsi_restore_context(void)
-+{
-+}
-+
-+static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
-+ int value)
-+{
-+ int t = 100000;
-+
-+ while (REG_GET(idx, bitnum, bitnum) != value) {
-+ if (--t == 0)
-+ return !value;
-+ }
-+
-+ return value;
-+}
-+
-+#ifdef DEBUG
-+static void perf_mark_setup(void)
-+{
-+ dsi.perf_setup_time = ktime_get();
-+}
-+
-+static void perf_mark_start(void)
-+{
-+ dsi.perf_start_time = ktime_get();
-+}
-+
-+static void perf_show(const char *name)
-+{
-+ ktime_t t, setup_time, trans_time;
-+ u32 total_bytes;
-+ u32 setup_us, trans_us, total_us;
-+ const int numframes = 100;
-+ static u32 s_trans_us, s_min_us = 0xffffffff, s_max_us;
-+
-+ if (!dsi_perf)
-+ return;
-+
-+ if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED)
-+ return;
-+
-+ t = ktime_get();
-+
-+ setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
-+ setup_us = (u32)ktime_to_us(setup_time);
-+ if (setup_us == 0)
-+ setup_us = 1;
-+
-+ trans_time = ktime_sub(t, dsi.perf_start_time);
-+ trans_us = (u32)ktime_to_us(trans_time);
-+ if (trans_us == 0)
-+ trans_us = 1;
-+
-+ total_us = setup_us + trans_us;
-+
-+ total_bytes = dsi.update_region.w *
-+ dsi.update_region.h *
-+ dsi.update_region.bytespp;
-+
-+ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) {
-+ dsi.perf_measure_frames++;
-+
-+ if (trans_us < s_min_us)
-+ s_min_us = trans_us;
-+
-+ if (trans_us > s_max_us)
-+ s_max_us = trans_us;
-+
-+ s_trans_us += trans_us;
-+
-+ if (dsi.perf_measure_frames < numframes)
-+ return;
-+
-+ DSSINFO("%s update: %d frames in %u us "
-+ "(min/max/avg %u/%u/%u), %u fps\n",
-+ name, numframes,
-+ s_trans_us,
-+ s_min_us,
-+ s_max_us,
-+ s_trans_us / numframes,
-+ 1000*1000 / (s_trans_us / numframes));
-+
-+ dsi.perf_measure_frames = 0;
-+ s_trans_us = 0;
-+ s_min_us = 0xffffffff;
-+ s_max_us = 0;
-+ } else {
-+ DSSINFO("%s update %u us + %u us = %u us (%uHz), %u bytes, "
-+ "%u kbytes/sec\n",
-+ name,
-+ setup_us,
-+ trans_us,
-+ total_us,
-+ 1000*1000 / total_us,
-+ total_bytes,
-+ total_bytes * 1000 / total_us);
-+ }
-+}
-+#else
-+#define perf_mark_setup()
-+#define perf_mark_start()
-+#define perf_show(x)
-+#endif
-+
-+static void print_irq_status(u32 status)
-+{
-+#ifndef VERBOSE_IRQ
-+ if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
-+ return;
-+#endif
-+ printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
-+
-+#define PIS(x) \
-+ if (status & DSI_IRQ_##x) \
-+ printk(#x " ");
-+#ifdef VERBOSE_IRQ
-+ PIS(VC0);
-+ PIS(VC1);
-+ PIS(VC2);
-+ PIS(VC3);
-+#endif
-+ PIS(WAKEUP);
-+ PIS(RESYNC);
-+ PIS(PLL_LOCK);
-+ PIS(PLL_UNLOCK);
-+ PIS(PLL_RECALL);
-+ PIS(COMPLEXIO_ERR);
-+ PIS(HS_TX_TIMEOUT);
-+ PIS(LP_RX_TIMEOUT);
-+ PIS(TE_TRIGGER);
-+ PIS(ACK_TRIGGER);
-+ PIS(SYNC_LOST);
-+ PIS(LDO_POWER_GOOD);
-+ PIS(TA_TIMEOUT);
-+#undef PIS
-+
-+ printk("\n");
-+}
-+
-+static void print_irq_status_vc(int channel, u32 status)
-+{
-+#ifndef VERBOSE_IRQ
-+ if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
-+ return;
-+#endif
-+ printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
-+
-+#define PIS(x) \
-+ if (status & DSI_VC_IRQ_##x) \
-+ printk(#x " ");
-+ PIS(CS);
-+ PIS(ECC_CORR);
-+#ifdef VERBOSE_IRQ
-+ PIS(PACKET_SENT);
-+#endif
-+ PIS(FIFO_TX_OVF);
-+ PIS(FIFO_RX_OVF);
-+ PIS(BTA);
-+ PIS(ECC_NO_CORR);
-+ PIS(FIFO_TX_UDF);
-+ PIS(PP_BUSY_CHANGE);
-+#undef PIS
-+ printk("\n");
-+}
-+
-+static void print_irq_status_cio(u32 status)
-+{
-+ printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
-+
-+#define PIS(x) \
-+ if (status & DSI_CIO_IRQ_##x) \
-+ printk(#x " ");
-+ PIS(ERRSYNCESC1);
-+ PIS(ERRSYNCESC2);
-+ PIS(ERRSYNCESC3);
-+ PIS(ERRESC1);
-+ PIS(ERRESC2);
-+ PIS(ERRESC3);
-+ PIS(ERRCONTROL1);
-+ PIS(ERRCONTROL2);
-+ PIS(ERRCONTROL3);
-+ PIS(STATEULPS1);
-+ PIS(STATEULPS2);
-+ PIS(STATEULPS3);
-+ PIS(ERRCONTENTIONLP0_1);
-+ PIS(ERRCONTENTIONLP1_1);
-+ PIS(ERRCONTENTIONLP0_2);
-+ PIS(ERRCONTENTIONLP1_2);
-+ PIS(ERRCONTENTIONLP0_3);
-+ PIS(ERRCONTENTIONLP1_3);
-+ PIS(ULPSACTIVENOT_ALL0);
-+ PIS(ULPSACTIVENOT_ALL1);
-+#undef PIS
-+
-+ printk("\n");
-+}
-+
-+static int debug_irq;
-+
-+/* called from dss */
-+void dsi_irq_handler(void)
-+{
-+ u32 irqstatus, vcstatus, ciostatus;
-+ int i;
-+
-+ irqstatus = dsi_read_reg(DSI_IRQSTATUS);
-+
-+ if (irqstatus & DSI_IRQ_ERROR_MASK) {
-+ DSSERR("DSI error, irqstatus %x\n", irqstatus);
-+ print_irq_status(irqstatus);
-+ } else if (debug_irq) {
-+ print_irq_status(irqstatus);
-+ }
-+
-+ for (i = 0; i < 4; ++i) {
-+ if ((irqstatus & (1<<i)) == 0)
-+ continue;
-+
-+ vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
-+
-+ if (vcstatus & DSI_VC_IRQ_BTA)
-+ complete(&dsi.bta_completion);
-+
-+ if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
-+ DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
-+ i, vcstatus);
-+ print_irq_status_vc(i, vcstatus);
-+ } else if (debug_irq) {
-+ print_irq_status_vc(i, vcstatus);
-+ }
-+
-+ dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
-+ }
-+
-+ if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
-+ ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
-+
-+ dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
-+
-+ DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
-+ print_irq_status_cio(ciostatus);
-+ }
-+
-+ dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
-+}
-+
-+
-+static void _dsi_initialize_irq(void)
-+{
-+ u32 l;
-+ int i;
-+
-+ /* disable all interrupts */
-+ dsi_write_reg(DSI_IRQENABLE, 0);
-+ for (i = 0; i < 4; ++i)
-+ dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
-+ dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
-+
-+ /* clear interrupt status */
-+ l = dsi_read_reg(DSI_IRQSTATUS);
-+ dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
-+
-+ for (i = 0; i < 4; ++i) {
-+ l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
-+ dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
-+ }
-+
-+ l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
-+ dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
-+
-+ /* enable error irqs */
-+ l = DSI_IRQ_ERROR_MASK;
-+ dsi_write_reg(DSI_IRQENABLE, l);
-+
-+ l = DSI_VC_IRQ_ERROR_MASK;
-+ for (i = 0; i < 4; ++i)
-+ dsi_write_reg(DSI_VC_IRQENABLE(i), l);
-+
-+ /* XXX zonda responds incorrectly, causing control error:
-+ Exit from LP-ESC mode to LP11 uses wrong transition states on the
-+ data lines LP0 and LN0. */
-+ dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE,
-+ -1 & (~DSI_CIO_IRQ_ERRCONTROL2));
-+}
-+
-+static void dsi_vc_enable_bta_irq(int channel)
-+{
-+ u32 l;
-+
-+ l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
-+ l |= DSI_VC_IRQ_BTA;
-+ dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
-+}
-+
-+static void dsi_vc_disable_bta_irq(int channel)
-+{
-+ u32 l;
-+
-+ l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
-+ l &= ~DSI_VC_IRQ_BTA;
-+ dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
-+}
-+
-+/* DSI func clock. this could also be DSI2_PLL_FCLK */
-+static inline void enable_clocks(bool enable)
-+{
-+ if (enable)
-+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+ else
-+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+}
-+
-+/* source clock for DSI PLL. this could also be PCLKFREE */
-+static inline void dsi_enable_pll_clock(bool enable)
-+{
-+ if (enable)
-+ dss_clk_enable(DSS_CLK_FCK2);
-+ else
-+ dss_clk_disable(DSS_CLK_FCK2);
-+
-+ if (enable && dsi.pll_locked) {
-+ if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
-+ DSSERR("cannot lock PLL when enabling clocks\n");
-+ }
-+}
-+
-+#ifdef DEBUG
-+static void _dsi_print_reset_status(void)
-+{
-+ u32 l;
-+
-+ if (!dss_debug)
-+ return;
-+
-+ /* A dummy read using the SCP interface to any DSIPHY register is
-+ * required after DSIPHY reset to complete the reset of the DSI complex
-+ * I/O. */
-+ l = dsi_read_reg(DSI_DSIPHY_CFG5);
-+
-+ printk(KERN_DEBUG "DSI resets: ");
-+
-+ l = dsi_read_reg(DSI_PLL_STATUS);
-+ printk("PLL (%d) ", FLD_GET(l, 0, 0));
-+
-+ l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
-+ printk("CIO (%d) ", FLD_GET(l, 29, 29));
-+
-+ l = dsi_read_reg(DSI_DSIPHY_CFG5);
-+ printk("PHY (%x, %d, %d, %d)\n",
-+ FLD_GET(l, 28, 26),
-+ FLD_GET(l, 29, 29),
-+ FLD_GET(l, 30, 30),
-+ FLD_GET(l, 31, 31));
-+}
-+#else
-+#define _dsi_print_reset_status()
-+#endif
-+
-+static inline int dsi_if_enable(bool enable)
-+{
-+ DSSDBG("dsi_if_enable(%d)\n", enable);
-+
-+ enable = enable ? 1 : 0;
-+ REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
-+
-+ if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
-+ DSSERR("Failed to set dsi_if_enable to %d\n", enable);
-+ return -EIO;
-+ }
-+
-+ return 0;
-+}
-+
-+static unsigned long dsi_fclk_rate(void)
-+{
-+ unsigned long r;
-+
-+ if (dss_get_dsi_clk_source() == 0) {
-+ /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
-+ r = dss_clk_get_rate(DSS_CLK_FCK1);
-+ } else {
-+ /* DSI FCLK source is DSI2_PLL_FCLK */
-+ r = dsi.dsi2_pll_fclk;
-+ }
-+
-+ return r;
-+}
-+
-+static int dsi_set_lp_clk_divisor(void)
-+{
-+ int n;
-+ unsigned long dsi_fclk;
-+ unsigned long mhz;
-+
-+ /* LP_CLK_DIVISOR, DSI fclk/n, should be 20MHz - 32kHz */
-+
-+ dsi_fclk = dsi_fclk_rate();
-+
-+ for (n = 1; n < (1 << 13) - 1; ++n) {
-+ mhz = dsi_fclk / n;
-+ if (mhz <= 20*1000*1000)
-+ break;
-+ }
-+
-+ if (n == (1 << 13) - 1) {
-+ DSSERR("Failed to find LP_CLK_DIVISOR\n");
-+ return -EINVAL;
-+ }
-+
-+ DSSDBG("LP_CLK_DIV %d, LP_CLK %ld\n", n, mhz);
-+
-+ REG_FLD_MOD(DSI_CLK_CTRL, n, 12, 0); /* LP_CLK_DIVISOR */
-+ if (dsi_fclk > 30*1000*1000)
-+ REG_FLD_MOD(DSI_CLK_CTRL, 1, 21, 21); /* LP_RX_SYNCHRO_ENABLE */
-+
-+ return 0;
-+}
-+
-+
-+enum dsi_pll_power_state {
-+ DSI_PLL_POWER_OFF = 0x0,
-+ DSI_PLL_POWER_ON_HSCLK = 0x1,
-+ DSI_PLL_POWER_ON_ALL = 0x2,
-+ DSI_PLL_POWER_ON_DIV = 0x3,
-+};
-+
-+static int dsi_pll_power(enum dsi_pll_power_state state)
-+{
-+ int t = 0;
-+
-+ REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
-+
-+ /* PLL_PWR_STATUS */
-+ while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
-+ udelay(1);
-+ if (t++ > 1000) {
-+ DSSERR("Failed to set DSI PLL power mode to %d\n",
-+ state);
-+ return -ENODEV;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+int dsi_pll_calc_pck(bool is_tft, unsigned long req_pck,
-+ struct dsi_clock_info *cinfo)
-+{
-+ struct dsi_clock_info cur, best;
-+ int min_fck_per_pck;
-+ int match = 0;
-+
-+ if (req_pck == dsi.cache_req_pck &&
-+ dsi.cache_cinfo.clkin == dss_clk_get_rate(DSS_CLK_FCK2)) {
-+ DSSDBG("DSI clock info found from cache\n");
-+ *cinfo = dsi.cache_cinfo;
-+ return 0;
-+ }
-+
-+ min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
-+
-+ if (min_fck_per_pck &&
-+ req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
-+ DSSERR("Requested pixel clock not possible with the current "
-+ "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
-+ "the constraint off.\n");
-+ min_fck_per_pck = 0;
-+ }
-+
-+ DSSDBG("dsi_pll_calc\n");
-+
-+retry:
-+ memset(&best, 0, sizeof(best));
-+
-+ memset(&cur, 0, sizeof(cur));
-+ cur.clkin = dss_clk_get_rate(DSS_CLK_FCK2);
-+ cur.use_dss2_fck = 1;
-+ cur.highfreq = 0;
-+
-+ /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
-+ /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
-+ /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
-+ for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
-+ if (cur.highfreq == 0)
-+ cur.fint = cur.clkin / cur.regn;
-+ else
-+ cur.fint = cur.clkin / (2 * cur.regn);
-+
-+ if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
-+ continue;
-+
-+ /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
-+ for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
-+ unsigned long a, b;
-+
-+ a = 2 * cur.regm * (cur.clkin/1000);
-+ b = cur.regn * (cur.highfreq + 1);
-+ cur.dsiphy = a / b * 1000;
-+
-+ if (cur.dsiphy > 1800 * 1000 * 1000)
-+ break;
-+
-+ /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
-+ for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
-+ ++cur.regm3) {
-+ cur.dsi1_pll_fclk = cur.dsiphy / cur.regm3;
-+
-+ /* this will narrow down the search a bit,
-+ * but still give pixclocks below what was
-+ * requested */
-+ if (cur.dsi1_pll_fclk < req_pck)
-+ break;
-+
-+ if (cur.dsi1_pll_fclk > DISPC_MAX_FCK)
-+ continue;
-+
-+ if (min_fck_per_pck &&
-+ cur.dsi1_pll_fclk <
-+ req_pck * min_fck_per_pck)
-+ continue;
-+
-+ match = 1;
-+
-+ find_lck_pck_divs(is_tft, req_pck,
-+ cur.dsi1_pll_fclk,
-+ &cur.lck_div,
-+ &cur.pck_div);
-+
-+ cur.lck = cur.dsi1_pll_fclk / cur.lck_div;
-+ cur.pck = cur.lck / cur.pck_div;
-+
-+ if (abs(cur.pck - req_pck) <
-+ abs(best.pck - req_pck)) {
-+ best = cur;
-+
-+ if (cur.pck == req_pck)
-+ goto found;
-+ }
-+ }
-+ }
-+ }
-+found:
-+ if (!match) {
-+ if (min_fck_per_pck) {
-+ DSSERR("Could not find suitable clock settings.\n"
-+ "Turning FCK/PCK constraint off and"
-+ "trying again.\n");
-+ min_fck_per_pck = 0;
-+ goto retry;
-+ }
-+
-+ DSSERR("Could not find suitable clock settings.\n");
-+
-+ return -EINVAL;
-+ }
-+
-+ /* DSI2_PLL_FCLK (regm4) is not used. Set it to something sane. */
-+ best.regm4 = best.dsiphy / 48000000;
-+ if (best.regm4 > REGM4_MAX)
-+ best.regm4 = REGM4_MAX;
-+ else if (best.regm4 == 0)
-+ best.regm4 = 1;
-+ best.dsi2_pll_fclk = best.dsiphy / best.regm4;
-+
-+ if (cinfo)
-+ *cinfo = best;
-+
-+ dsi.cache_req_pck = req_pck;
-+ dsi.cache_clk_freq = 0;
-+ dsi.cache_cinfo = best;
-+
-+ return 0;
-+}
-+
-+static int dsi_pll_calc_ddrfreq(unsigned long clk_freq,
-+ struct dsi_clock_info *cinfo)
-+{
-+ struct dsi_clock_info cur, best;
-+ const bool use_dss2_fck = 1;
-+ unsigned long datafreq;
-+
-+ DSSDBG("dsi_pll_calc_ddrfreq\n");
-+
-+ if (clk_freq == dsi.cache_clk_freq &&
-+ dsi.cache_cinfo.clkin == dss_clk_get_rate(DSS_CLK_FCK2)) {
-+ DSSDBG("DSI clock info found from cache\n");
-+ *cinfo = dsi.cache_cinfo;
-+ return 0;
-+ }
-+
-+ datafreq = clk_freq * 4;
-+
-+ memset(&best, 0, sizeof(best));
-+
-+ memset(&cur, 0, sizeof(cur));
-+ cur.use_dss2_fck = use_dss2_fck;
-+ if (use_dss2_fck) {
-+ cur.clkin = dss_clk_get_rate(DSS_CLK_FCK2);
-+ cur.highfreq = 0;
-+ } else {
-+ cur.clkin = dispc_pclk_rate();
-+ if (cur.clkin < 32000000)
-+ cur.highfreq = 0;
-+ else
-+ cur.highfreq = 1;
-+ }
-+
-+ /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
-+ /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
-+ /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
-+ for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
-+ if (cur.highfreq == 0)
-+ cur.fint = cur.clkin / cur.regn;
-+ else
-+ cur.fint = cur.clkin / (2 * cur.regn);
-+
-+ if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
-+ continue;
-+
-+ /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
-+ for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
-+ unsigned long a, b;
-+
-+ a = 2 * cur.regm * (cur.clkin/1000);
-+ b = cur.regn * (cur.highfreq + 1);
-+ cur.dsiphy = a / b * 1000;
-+
-+ if (cur.dsiphy > 1800 * 1000 * 1000)
-+ break;
-+
-+ if (abs(cur.dsiphy - datafreq) <
-+ abs(best.dsiphy - datafreq)) {
-+ best = cur;
-+ /* DSSDBG("best %ld\n", best.dsiphy); */
-+ }
-+
-+ if (cur.dsiphy == datafreq)
-+ goto found;
-+ }
-+ }
-+found:
-+ /* DSI1_PLL_FCLK (regm3) is not used. Set it to something sane. */
-+ best.regm3 = best.dsiphy / 48000000;
-+ if (best.regm3 > REGM3_MAX)
-+ best.regm3 = REGM3_MAX;
-+ else if (best.regm3 == 0)
-+ best.regm3 = 1;
-+ best.dsi1_pll_fclk = best.dsiphy / best.regm3;
-+
-+ /* DSI2_PLL_FCLK (regm4) is not used. Set it to something sane. */
-+ best.regm4 = best.dsiphy / 48000000;
-+ if (best.regm4 > REGM4_MAX)
-+ best.regm4 = REGM4_MAX;
-+ else if (best.regm4 == 0)
-+ best.regm4 = 1;
-+ best.dsi2_pll_fclk = best.dsiphy / best.regm4;
-+
-+ if (cinfo)
-+ *cinfo = best;
-+
-+ dsi.cache_clk_freq = clk_freq;
-+ dsi.cache_req_pck = 0;
-+ dsi.cache_cinfo = best;
-+
-+ return 0;
-+}
-+
-+int dsi_pll_program(struct dsi_clock_info *cinfo)
-+{
-+ int r = 0;
-+ u32 l;
-+
-+ DSSDBG("dsi_pll_program\n");
-+
-+ dsi.dsiphy = cinfo->dsiphy;
-+ dsi.ddr_clk = dsi.dsiphy / 4;
-+ dsi.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
-+ dsi.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
-+
-+ DSSDBG("DSI Fint %ld\n", cinfo->fint);
-+
-+ DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
-+ cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
-+ cinfo->clkin,
-+ cinfo->highfreq);
-+
-+ /* DSIPHY == CLKIN4DDR */
-+ DSSDBG("DSIPHY = 2 * %d / %d * %lu / %d = %lu\n",
-+ cinfo->regm,
-+ cinfo->regn,
-+ cinfo->clkin,
-+ cinfo->highfreq + 1,
-+ cinfo->dsiphy);
-+
-+ DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
-+ dsi.dsiphy / 1000 / 1000 / 2);
-+
-+ DSSDBG("Clock lane freq %ld Hz\n", dsi.ddr_clk);
-+
-+ DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
-+ cinfo->regm3, cinfo->dsi1_pll_fclk);
-+ DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
-+ cinfo->regm4, cinfo->dsi2_pll_fclk);
-+
-+ REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
-+
-+ l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
-+ l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
-+ l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */
-+ l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */
-+ l = FLD_MOD(l, cinfo->regm3 - 1, 22, 19); /* DSI_CLOCK_DIV */
-+ l = FLD_MOD(l, cinfo->regm4 - 1, 26, 23); /* DSIPROTO_CLOCK_DIV */
-+ dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
-+
-+ l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
-+ l = FLD_MOD(l, 7, 4, 1); /* DSI_PLL_FREQSEL */
-+ /* DSI_PLL_CLKSEL */
-+ l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1, 11, 11);
-+ l = FLD_MOD(l, cinfo->highfreq, 12, 12); /* DSI_PLL_HIGHFREQ */
-+ l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
-+ l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
-+ l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
-+ dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
-+
-+ REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
-+
-+ if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
-+ DSSERR("dsi pll go bit not going down.\n");
-+ r = -EIO;
-+ goto err;
-+ }
-+
-+ if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
-+ DSSERR("cannot lock PLL\n");
-+ r = -EIO;
-+ goto err;
-+ }
-+
-+ dsi.pll_locked = 1;
-+
-+ l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
-+ l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
-+ l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
-+ l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
-+ l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
-+ l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
-+ l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
-+ l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
-+ l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
-+ l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
-+ l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
-+ l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
-+ l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
-+ l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
-+ l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
-+ dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
-+
-+ DSSDBG("PLL config done\n");
-+err:
-+ return r;
-+}
-+
-+int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
-+{
-+ int r = 0;
-+ enum dsi_pll_power_state pwstate;
-+ struct dispc_clock_info cinfo;
-+
-+ DSSDBG("PLL init\n");
-+
-+ enable_clocks(1);
-+ dsi_enable_pll_clock(1);
-+
-+ /* configure dispc fck and pixel clock to something sane */
-+ r = dispc_calc_clock_div(1, 48 * 1000 * 1000, &cinfo);
-+ if (r)
-+ goto err0;
-+
-+ r = dispc_set_clock_div(&cinfo);
-+ if (r) {
-+ DSSERR("Failed to set basic clocks\n");
-+ goto err0;
-+ }
-+
-+ r = dss_dsi_power_up();
-+ if (r)
-+ goto err0;
-+
-+ /* PLL does not come out of reset without this... */
-+ dispc_pck_free_enable(1);
-+
-+ if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
-+ DSSERR("PLL not coming out of reset.\n");
-+ r = -ENODEV;
-+ goto err1;
-+ }
-+
-+ /* ... but if left on, we get problems when planes do not
-+ * fill the whole display. No idea about this XXX */
-+ dispc_pck_free_enable(0);
-+
-+ if (enable_hsclk && enable_hsdiv)
-+ pwstate = DSI_PLL_POWER_ON_ALL;
-+ else if (enable_hsclk)
-+ pwstate = DSI_PLL_POWER_ON_HSCLK;
-+ else if (enable_hsdiv)
-+ pwstate = DSI_PLL_POWER_ON_DIV;
-+ else
-+ pwstate = DSI_PLL_POWER_OFF;
-+
-+ r = dsi_pll_power(pwstate);
-+
-+ if (r)
-+ goto err1;
-+
-+ DSSDBG("PLL init done\n");
-+
-+ return 0;
-+err1:
-+ dss_dsi_power_down();
-+err0:
-+ enable_clocks(0);
-+ dsi_enable_pll_clock(0);
-+ return r;
-+}
-+
-+void dsi_pll_uninit(void)
-+{
-+ enable_clocks(0);
-+ dsi_enable_pll_clock(0);
-+
-+ dsi.pll_locked = 0;
-+ dsi_pll_power(DSI_PLL_POWER_OFF);
-+ dss_dsi_power_down();
-+ DSSDBG("PLL uninit done\n");
-+}
-+
-+unsigned long dsi_get_dsi1_pll_rate(void)
-+{
-+ return dsi.dsi1_pll_fclk;
-+}
-+
-+unsigned long dsi_get_dsi2_pll_rate(void)
-+{
-+ return dsi.dsi2_pll_fclk;
-+}
-+
-+void dsi_dump_clocks(struct seq_file *s)
-+{
-+ int clksel;
-+
-+ enable_clocks(1);
-+
-+ clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
-+
-+ seq_printf(s, "- dsi -\n");
-+
-+ seq_printf(s, "dsi fclk source = %s\n",
-+ dss_get_dsi_clk_source() == 0 ?
-+ "dss1_alwon_fclk" : "dsi2_pll_fclk");
-+
-+ seq_printf(s, "dsi pll source = %s\n",
-+ clksel == 0 ?
-+ "dss2_alwon_fclk" : "pclkfree");
-+
-+ seq_printf(s, "DSIPHY\t\t%lu\nDDR_CLK\t\t%lu\n",
-+ dsi.dsiphy, dsi.ddr_clk);
-+
-+ seq_printf(s, "dsi1_pll_fck\t%lu (%s)\n"
-+ "dsi2_pll_fck\t%lu (%s)\n",
-+ dsi.dsi1_pll_fclk,
-+ dss_get_dispc_clk_source() == 0 ? "off" : "on",
-+ dsi.dsi2_pll_fclk,
-+ dss_get_dsi_clk_source() == 0 ? "off" : "on");
-+
-+ enable_clocks(0);
-+}
-+
-+void dsi_dump_regs(struct seq_file *s)
-+{
-+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
-+
-+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+
-+ DUMPREG(DSI_REVISION);
-+ DUMPREG(DSI_SYSCONFIG);
-+ DUMPREG(DSI_SYSSTATUS);
-+ DUMPREG(DSI_IRQSTATUS);
-+ DUMPREG(DSI_IRQENABLE);
-+ DUMPREG(DSI_CTRL);
-+ DUMPREG(DSI_COMPLEXIO_CFG1);
-+ DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
-+ DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
-+ DUMPREG(DSI_CLK_CTRL);
-+ DUMPREG(DSI_TIMING1);
-+ DUMPREG(DSI_TIMING2);
-+ DUMPREG(DSI_VM_TIMING1);
-+ DUMPREG(DSI_VM_TIMING2);
-+ DUMPREG(DSI_VM_TIMING3);
-+ DUMPREG(DSI_CLK_TIMING);
-+ DUMPREG(DSI_TX_FIFO_VC_SIZE);
-+ DUMPREG(DSI_RX_FIFO_VC_SIZE);
-+ DUMPREG(DSI_COMPLEXIO_CFG2);
-+ DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
-+ DUMPREG(DSI_VM_TIMING4);
-+ DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
-+ DUMPREG(DSI_VM_TIMING5);
-+ DUMPREG(DSI_VM_TIMING6);
-+ DUMPREG(DSI_VM_TIMING7);
-+ DUMPREG(DSI_STOPCLK_TIMING);
-+
-+ DUMPREG(DSI_VC_CTRL(0));
-+ DUMPREG(DSI_VC_TE(0));
-+ DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
-+ DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
-+ DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
-+ DUMPREG(DSI_VC_IRQSTATUS(0));
-+ DUMPREG(DSI_VC_IRQENABLE(0));
-+
-+ DUMPREG(DSI_VC_CTRL(1));
-+ DUMPREG(DSI_VC_TE(1));
-+ DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
-+ DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
-+ DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
-+ DUMPREG(DSI_VC_IRQSTATUS(1));
-+ DUMPREG(DSI_VC_IRQENABLE(1));
-+
-+ DUMPREG(DSI_VC_CTRL(2));
-+ DUMPREG(DSI_VC_TE(2));
-+ DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
-+ DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
-+ DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
-+ DUMPREG(DSI_VC_IRQSTATUS(2));
-+ DUMPREG(DSI_VC_IRQENABLE(2));
-+
-+ DUMPREG(DSI_VC_CTRL(3));
-+ DUMPREG(DSI_VC_TE(3));
-+ DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
-+ DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
-+ DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
-+ DUMPREG(DSI_VC_IRQSTATUS(3));
-+ DUMPREG(DSI_VC_IRQENABLE(3));
-+
-+ DUMPREG(DSI_DSIPHY_CFG0);
-+ DUMPREG(DSI_DSIPHY_CFG1);
-+ DUMPREG(DSI_DSIPHY_CFG2);
-+ DUMPREG(DSI_DSIPHY_CFG5);
-+
-+ DUMPREG(DSI_PLL_CONTROL);
-+ DUMPREG(DSI_PLL_STATUS);
-+ DUMPREG(DSI_PLL_GO);
-+ DUMPREG(DSI_PLL_CONFIGURATION1);
-+ DUMPREG(DSI_PLL_CONFIGURATION2);
-+
-+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+#undef DUMPREG
-+}
-+
-+enum dsi_complexio_power_state {
-+ DSI_COMPLEXIO_POWER_OFF = 0x0,
-+ DSI_COMPLEXIO_POWER_ON = 0x1,
-+ DSI_COMPLEXIO_POWER_ULPS = 0x2,
-+};
-+
-+static int dsi_complexio_power(enum dsi_complexio_power_state state)
-+{
-+ int t = 0;
-+
-+ /* PWR_CMD */
-+ REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
-+
-+ /* PWR_STATUS */
-+ while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
-+ udelay(1);
-+ if (t++ > 1000) {
-+ DSSERR("failed to set complexio power state to "
-+ "%d\n", state);
-+ return -ENODEV;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static void dsi_complexio_config(struct omap_display *display)
-+{
-+ u32 r;
-+
-+ int clk_lane = display->hw_config.u.dsi.clk_lane;
-+ int data1_lane = display->hw_config.u.dsi.data1_lane;
-+ int data2_lane = display->hw_config.u.dsi.data2_lane;
-+ int clk_pol = display->hw_config.u.dsi.clk_pol;
-+ int data1_pol = display->hw_config.u.dsi.data1_pol;
-+ int data2_pol = display->hw_config.u.dsi.data2_pol;
-+
-+ r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
-+ r = FLD_MOD(r, clk_lane, 2, 0);
-+ r = FLD_MOD(r, clk_pol, 3, 3);
-+ r = FLD_MOD(r, data1_lane, 6, 4);
-+ r = FLD_MOD(r, data1_pol, 7, 7);
-+ r = FLD_MOD(r, data2_lane, 10, 8);
-+ r = FLD_MOD(r, data2_pol, 11, 11);
-+ dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
-+
-+ /* The configuration of the DSI complex I/O (number of data lanes,
-+ position, differential order) should not be changed while
-+ DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
-+ the hardware to take into account a new configuration of the complex
-+ I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
-+ follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
-+ then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
-+ DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
-+ DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
-+ DSI complex I/O configuration is unknown. */
-+
-+ /*
-+ REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
-+ REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
-+ REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
-+ REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
-+ */
-+}
-+
-+static inline unsigned ns2ddr(unsigned ns)
-+{
-+ /* convert time in ns to ddr ticks, rounding up */
-+ return (ns * (dsi.ddr_clk/1000/1000) + 999) / 1000;
-+}
-+
-+static inline unsigned ddr2ns(unsigned ddr)
-+{
-+ return ddr * 1000 * 1000 / (dsi.ddr_clk / 1000);
-+}
-+
-+static void dsi_complexio_timings(void)
-+{
-+ u32 r;
-+ u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
-+ u32 tlpx_half, tclk_trail, tclk_zero;
-+ u32 tclk_prepare;
-+
-+ /* calculate timings */
-+
-+ /* 1 * DDR_CLK = 2 * UI */
-+
-+ /* min 40ns + 4*UI max 85ns + 6*UI */
-+ ths_prepare = ns2ddr(59) + 2;
-+
-+ /* min 145ns + 10*UI */
-+ ths_prepare_ths_zero = ns2ddr(145) + 5;
-+
-+ /* min max(8*UI, 60ns+4*UI) */
-+ ths_trail = max((unsigned)4, ns2ddr(60) + 2);
-+
-+ /* min 100ns */
-+ ths_exit = ns2ddr(100);
-+
-+ /* tlpx min 50n */
-+ tlpx_half = ns2ddr(25);
-+
-+ /* min 60ns */
-+ tclk_trail = ns2ddr(60);
-+
-+ /* min 38ns, max 95ns */
-+ tclk_prepare = ns2ddr(38);
-+
-+ /* min tclk-prepare + tclk-zero = 300ns */
-+ tclk_zero = ns2ddr(300 - 38);
-+
-+ DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
-+ ths_prepare, ddr2ns(ths_prepare),
-+ ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
-+ DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
-+ ths_trail, ddr2ns(ths_trail),
-+ ths_exit, ddr2ns(ths_exit));
-+
-+ DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
-+ "tclk_zero %u (%uns)\n",
-+ tlpx_half, ddr2ns(tlpx_half),
-+ tclk_trail, ddr2ns(tclk_trail),
-+ tclk_zero, ddr2ns(tclk_zero));
-+ DSSDBG("tclk_prepare %u (%uns)\n",
-+ tclk_prepare, ddr2ns(tclk_prepare));
-+
-+ /* program timings */
-+
-+ r = dsi_read_reg(DSI_DSIPHY_CFG0);
-+ r = FLD_MOD(r, ths_prepare, 31, 24);
-+ r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
-+ r = FLD_MOD(r, ths_trail, 15, 8);
-+ r = FLD_MOD(r, ths_exit, 7, 0);
-+ dsi_write_reg(DSI_DSIPHY_CFG0, r);
-+
-+ r = dsi_read_reg(DSI_DSIPHY_CFG1);
-+ r = FLD_MOD(r, tlpx_half, 22, 16);
-+ r = FLD_MOD(r, tclk_trail, 15, 8);
-+ r = FLD_MOD(r, tclk_zero, 7, 0);
-+ dsi_write_reg(DSI_DSIPHY_CFG1, r);
-+
-+ r = dsi_read_reg(DSI_DSIPHY_CFG2);
-+ r = FLD_MOD(r, tclk_prepare, 7, 0);
-+ dsi_write_reg(DSI_DSIPHY_CFG2, r);
-+}
-+
-+
-+static int dsi_complexio_init(struct omap_display *display)
-+{
-+ int r = 0;
-+
-+ DSSDBG("dsi_complexio_init\n");
-+
-+ /* CIO_CLK_ICG, enable L3 clk to CIO */
-+ REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
-+
-+ /* A dummy read using the SCP interface to any DSIPHY register is
-+ * required after DSIPHY reset to complete the reset of the DSI complex
-+ * I/O. */
-+ dsi_read_reg(DSI_DSIPHY_CFG5);
-+
-+ if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
-+ DSSERR("ComplexIO PHY not coming out of reset.\n");
-+ r = -ENODEV;
-+ goto err;
-+ }
-+
-+ dsi_complexio_config(display);
-+
-+ r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
-+
-+ if (r)
-+ goto err;
-+
-+ if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
-+ DSSERR("ComplexIO not coming out of reset.\n");
-+ r = -ENODEV;
-+ goto err;
-+ }
-+
-+ if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
-+ DSSERR("ComplexIO LDO power down.\n");
-+ r = -ENODEV;
-+ goto err;
-+ }
-+
-+ dsi_complexio_timings();
-+
-+ /*
-+ The configuration of the DSI complex I/O (number of data lanes,
-+ position, differential order) should not be changed while
-+ DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
-+ hardware to recognize a new configuration of the complex I/O (done
-+ in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
-+ this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
-+ reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
-+ LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
-+ bit to 1. If the sequence is not followed, the DSi complex I/O
-+ configuration is undetermined.
-+ */
-+ dsi_if_enable(1);
-+ dsi_if_enable(0);
-+ REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
-+ dsi_if_enable(1);
-+ dsi_if_enable(0);
-+
-+ DSSDBG("CIO init done\n");
-+err:
-+ return r;
-+}
-+
-+static void dsi_complexio_uninit(void)
-+{
-+ dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
-+}
-+
-+static int _dsi_wait_reset(void)
-+{
-+ int i = 0;
-+
-+ while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
-+ if (i++ > 5) {
-+ DSSERR("soft reset failed\n");
-+ return -ENODEV;
-+ }
-+ udelay(1);
-+ }
-+
-+ return 0;
-+}
-+
-+static int _dsi_reset(void)
-+{
-+ /* Soft reset */
-+ REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
-+ return _dsi_wait_reset();
-+}
-+
-+
-+static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
-+ enum fifo_size size3, enum fifo_size size4)
-+{
-+ u32 r = 0;
-+ int add = 0;
-+ int i;
-+
-+ dsi.vc[0].fifo_size = size1;
-+ dsi.vc[1].fifo_size = size2;
-+ dsi.vc[2].fifo_size = size3;
-+ dsi.vc[3].fifo_size = size4;
-+
-+ for (i = 0; i < 4; i++) {
-+ u8 v;
-+ int size = dsi.vc[i].fifo_size;
-+
-+ if (add + size > 4) {
-+ DSSERR("Illegal FIFO configuration\n");
-+ BUG();
-+ }
-+
-+ v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
-+ r |= v << (8 * i);
-+ /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
-+ add += size;
-+ }
-+
-+ dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
-+}
-+
-+static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
-+ enum fifo_size size3, enum fifo_size size4)
-+{
-+ u32 r = 0;
-+ int add = 0;
-+ int i;
-+
-+ dsi.vc[0].fifo_size = size1;
-+ dsi.vc[1].fifo_size = size2;
-+ dsi.vc[2].fifo_size = size3;
-+ dsi.vc[3].fifo_size = size4;
-+
-+ for (i = 0; i < 4; i++) {
-+ u8 v;
-+ int size = dsi.vc[i].fifo_size;
-+
-+ if (add + size > 4) {
-+ DSSERR("Illegal FIFO configuration\n");
-+ BUG();
-+ }
-+
-+ v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
-+ r |= v << (8 * i);
-+ /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
-+ add += size;
-+ }
-+
-+ dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
-+}
-+
-+static int dsi_force_tx_stop_mode_io(void)
-+{
-+ u32 r;
-+
-+ r = dsi_read_reg(DSI_TIMING1);
-+ r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
-+ dsi_write_reg(DSI_TIMING1, r);
-+
-+ if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
-+ DSSERR("TX_STOP bit not going down\n");
-+ return -EIO;
-+ }
-+
-+ return 0;
-+}
-+
-+static void dsi_vc_print_status(int channel)
-+{
-+ u32 r;
-+
-+ r = dsi_read_reg(DSI_VC_CTRL(channel));
-+ DSSDBG("vc %d: TX_FIFO_NOT_EMPTY %d, BTA_EN %d, VC_BUSY %d, "
-+ "TX_FIFO_FULL %d, RX_FIFO_NOT_EMPTY %d, ",
-+ channel,
-+ FLD_GET(r, 5, 5),
-+ FLD_GET(r, 6, 6),
-+ FLD_GET(r, 15, 15),
-+ FLD_GET(r, 16, 16),
-+ FLD_GET(r, 20, 20));
-+
-+ r = dsi_read_reg(DSI_TX_FIFO_VC_EMPTINESS);
-+ DSSDBG("EMPTINESS %d\n", (r >> (8 * channel)) & 0xff);
-+}
-+
-+static void dsi_vc_config(int channel)
-+{
-+ u32 r;
-+
-+ DSSDBG("dsi_vc_config %d\n", channel);
-+
-+ r = dsi_read_reg(DSI_VC_CTRL(channel));
-+
-+ r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
-+ r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
-+ r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
-+ r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
-+ r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
-+ r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
-+ r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
-+
-+ r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
-+ r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
-+
-+ dsi_write_reg(DSI_VC_CTRL(channel), r);
-+}
-+
-+static void dsi_vc_config_vp(int channel)
-+{
-+ u32 r;
-+
-+ DSSDBG("dsi_vc_config_vp\n");
-+
-+ r = dsi_read_reg(DSI_VC_CTRL(channel));
-+
-+ r = FLD_MOD(r, 1, 1, 1); /* SOURCE, 1 = video port */
-+ r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
-+ r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
-+ r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
-+ r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
-+ r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
-+ r = FLD_MOD(r, 1, 9, 9); /* MODE_SPEED, high speed on/off */
-+
-+ r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
-+ r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
-+
-+ dsi_write_reg(DSI_VC_CTRL(channel), r);
-+}
-+
-+
-+static int dsi_vc_enable(int channel, bool enable)
-+{
-+ DSSDBG("dsi_vc_enable channel %d, enable %d\n", channel, enable);
-+
-+ enable = enable ? 1 : 0;
-+
-+ REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
-+
-+ if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
-+ DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
-+ return -EIO;
-+ }
-+
-+ return 0;
-+}
-+
-+static void dsi_vc_enable_hs(int channel, bool enable)
-+{
-+ DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
-+
-+ dsi_vc_enable(channel, 0);
-+ dsi_if_enable(0);
-+
-+ REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
-+
-+ dsi_vc_enable(channel, 1);
-+ dsi_if_enable(1);
-+
-+ dsi_force_tx_stop_mode_io();
-+}
-+
-+static void dsi_vc_flush_long_data(int channel)
-+{
-+ while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
-+ u32 val;
-+ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
-+ DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
-+ (val >> 0) & 0xff,
-+ (val >> 8) & 0xff,
-+ (val >> 16) & 0xff,
-+ (val >> 24) & 0xff);
-+ }
-+}
-+
-+static void dsi_show_rx_ack_with_err(u16 err)
-+{
-+ DSSERR("\tACK with ERROR (%#x):\n", err);
-+ if (err & (1 << 0))
-+ DSSERR("\t\tSoT Error\n");
-+ if (err & (1 << 1))
-+ DSSERR("\t\tSoT Sync Error\n");
-+ if (err & (1 << 2))
-+ DSSERR("\t\tEoT Sync Error\n");
-+ if (err & (1 << 3))
-+ DSSERR("\t\tEscape Mode Entry Command Error\n");
-+ if (err & (1 << 4))
-+ DSSERR("\t\tLP Transmit Sync Error\n");
-+ if (err & (1 << 5))
-+ DSSERR("\t\tHS Receive Timeout Error\n");
-+ if (err & (1 << 6))
-+ DSSERR("\t\tFalse Control Error\n");
-+ if (err & (1 << 7))
-+ DSSERR("\t\t(reserved7)\n");
-+ if (err & (1 << 8))
-+ DSSERR("\t\tECC Error, single-bit (corrected)\n");
-+ if (err & (1 << 9))
-+ DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
-+ if (err & (1 << 10))
-+ DSSERR("\t\tChecksum Error\n");
-+ if (err & (1 << 11))
-+ DSSERR("\t\tData type not recognized\n");
-+ if (err & (1 << 12))
-+ DSSERR("\t\tInvalid VC ID\n");
-+ if (err & (1 << 13))
-+ DSSERR("\t\tInvalid Transmission Length\n");
-+ if (err & (1 << 14))
-+ DSSERR("\t\t(reserved14)\n");
-+ if (err & (1 << 15))
-+ DSSERR("\t\tDSI Protocol Violation\n");
-+}
-+
-+static u16 dsi_vc_flush_receive_data(int channel)
-+{
-+ /* RX_FIFO_NOT_EMPTY */
-+ while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
-+ u32 val;
-+ u8 dt;
-+ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
-+ DSSDBG("\trawval %#08x\n", val);
-+ dt = FLD_GET(val, 5, 0);
-+ if (dt == DSI_DT_RX_ACK_WITH_ERR) {
-+ u16 err = FLD_GET(val, 23, 8);
-+ dsi_show_rx_ack_with_err(err);
-+ } else if (dt == DSI_DT_RX_SHORT_READ_1) {
-+ DSSDBG("\tDCS short response, 1 byte: %#x\n",
-+ FLD_GET(val, 23, 8));
-+ } else if (dt == DSI_DT_RX_SHORT_READ_2) {
-+ DSSDBG("\tDCS short response, 2 byte: %#x\n",
-+ FLD_GET(val, 23, 8));
-+ } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
-+ DSSDBG("\tDCS long response, len %d\n",
-+ FLD_GET(val, 23, 8));
-+ dsi_vc_flush_long_data(channel);
-+ } else {
-+ DSSERR("\tunknown datatype 0x%02x\n", dt);
-+ }
-+ }
-+ return 0;
-+}
-+
-+static int dsi_vc_send_bta(int channel)
-+{
-+ unsigned long tmo;
-+
-+ /*DSSDBG("dsi_vc_send_bta_sync %d\n", channel); */
-+
-+ if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
-+ DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
-+ dsi_vc_flush_receive_data(channel);
-+ }
-+
-+ REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
-+
-+ tmo = jiffies + msecs_to_jiffies(10);
-+ while (REG_GET(DSI_VC_CTRL(channel), 6, 6) == 1) {
-+ if (time_after(jiffies, tmo)) {
-+ DSSERR("Failed to send BTA\n");
-+ return -EIO;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int dsi_vc_send_bta_sync(int channel)
-+{
-+ int r = 0;
-+
-+ init_completion(&dsi.bta_completion);
-+
-+ dsi_vc_enable_bta_irq(channel);
-+
-+ r = dsi_vc_send_bta(channel);
-+ if (r)
-+ goto err;
-+
-+ if (wait_for_completion_timeout(&dsi.bta_completion,
-+ msecs_to_jiffies(500)) == 0) {
-+ DSSERR("Failed to receive BTA\n");
-+ r = -EIO;
-+ goto err;
-+ }
-+err:
-+ dsi_vc_disable_bta_irq(channel);
-+
-+ return r;
-+}
-+
-+static inline void dsi_vc_write_long_header(int channel, u8 data_type,
-+ u16 len, u8 ecc)
-+{
-+ u32 val;
-+ u8 data_id;
-+
-+ /*data_id = data_type | channel << 6; */
-+ data_id = data_type | dsi.vc[channel].dest_per << 6;
-+
-+ val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
-+ FLD_VAL(ecc, 31, 24);
-+
-+ dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
-+}
-+
-+static inline void dsi_vc_write_long_payload(int channel,
-+ u8 b1, u8 b2, u8 b3, u8 b4)
-+{
-+ u32 val;
-+
-+ val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
-+
-+/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
-+ b1, b2, b3, b4, val); */
-+
-+ dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
-+}
-+
-+static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
-+ u8 ecc)
-+{
-+ /*u32 val; */
-+ int i;
-+ u8 *p;
-+ int r = 0;
-+ u8 b1, b2, b3, b4;
-+
-+ if (dsi.debug_write)
-+ DSSDBG("dsi_vc_send_long, %d bytes\n", len);
-+
-+ /* len + header */
-+ if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
-+ DSSERR("unable to send long packet: packet too long.\n");
-+ return -EINVAL;
-+ }
-+
-+ dsi_vc_write_long_header(channel, data_type, len, ecc);
-+
-+ /*dsi_vc_print_status(0); */
-+
-+ p = data;
-+ for (i = 0; i < len >> 2; i++) {
-+ if (dsi.debug_write)
-+ DSSDBG("\tsending full packet %d\n", i);
-+ /*dsi_vc_print_status(0); */
-+
-+ b1 = *p++;
-+ b2 = *p++;
-+ b3 = *p++;
-+ b4 = *p++;
-+
-+ dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
-+ }
-+
-+ i = len % 4;
-+ if (i) {
-+ b1 = 0; b2 = 0; b3 = 0;
-+
-+ if (dsi.debug_write)
-+ DSSDBG("\tsending remainder bytes %d\n", i);
-+
-+ switch (i) {
-+ case 3:
-+ b1 = *p++;
-+ b2 = *p++;
-+ b3 = *p++;
-+ break;
-+ case 2:
-+ b1 = *p++;
-+ b2 = *p++;
-+ break;
-+ case 1:
-+ b1 = *p++;
-+ break;
-+ }
-+
-+ dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
-+ }
-+
-+ return r;
-+}
-+
-+static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
-+{
-+ u32 r;
-+ u8 data_id;
-+
-+ if (dsi.debug_write)
-+ DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
-+ channel,
-+ data_type, data & 0xff, (data >> 8) & 0xff);
-+
-+ if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
-+ DSSERR("ERROR FIFO FULL, aborting transfer\n");
-+ return -EINVAL;
-+ }
-+
-+ data_id = data_type | channel << 6;
-+
-+ r = (data_id << 0) | (data << 8) | (ecc << 24);
-+
-+ dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
-+
-+ return 0;
-+}
-+
-+int dsi_vc_send_null(int channel)
-+{
-+ u8 nullpkg[] = {0, 0, 0, 0};
-+ return dsi_vc_send_long(0, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
-+}
-+EXPORT_SYMBOL(dsi_vc_send_null);
-+
-+int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
-+{
-+ int r;
-+
-+ BUG_ON(len == 0);
-+
-+ if (len == 1) {
-+ r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
-+ data[0], 0);
-+ } else if (len == 2) {
-+ r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
-+ data[0] | (data[1] << 8), 0);
-+ } else {
-+ /* 0x39 = DCS Long Write */
-+ r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
-+ data, len, 0);
-+ }
-+
-+ return r;
-+}
-+EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
-+
-+int dsi_vc_dcs_write(int channel, u8 *data, int len)
-+{
-+ int r;
-+
-+ r = dsi_vc_dcs_write_nosync(channel, data, len);
-+ if (r)
-+ return r;
-+
-+ /* Some devices need time to process the msg in low power mode.
-+ This also makes the write synchronous, and checks that
-+ the peripheral is still alive */
-+ r = dsi_vc_send_bta_sync(channel);
-+
-+ return r;
-+}
-+EXPORT_SYMBOL(dsi_vc_dcs_write);
-+
-+int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
-+{
-+ u32 val;
-+ u8 dt;
-+ int r;
-+
-+ if (dsi.debug_read)
-+ DSSDBG("dsi_vc_dcs_read\n");
-+
-+ r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
-+ if (r)
-+ return r;
-+
-+ r = dsi_vc_send_bta_sync(channel);
-+ if (r)
-+ return r;
-+
-+ if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) { /* RX_FIFO_NOT_EMPTY */
-+ DSSERR("RX fifo empty when trying to read.\n");
-+ return -EIO;
-+ }
-+
-+ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
-+ if (dsi.debug_read)
-+ DSSDBG("\theader: %08x\n", val);
-+ dt = FLD_GET(val, 5, 0);
-+ if (dt == DSI_DT_RX_ACK_WITH_ERR) {
-+ u16 err = FLD_GET(val, 23, 8);
-+ dsi_show_rx_ack_with_err(err);
-+ return -1;
-+
-+ } else if (dt == DSI_DT_RX_SHORT_READ_1) {
-+ u8 data = FLD_GET(val, 15, 8);
-+ if (dsi.debug_read)
-+ DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
-+
-+ if (buflen < 1)
-+ return -1;
-+
-+ buf[0] = data;
-+
-+ return 1;
-+ } else if (dt == DSI_DT_RX_SHORT_READ_2) {
-+ u16 data = FLD_GET(val, 23, 8);
-+ if (dsi.debug_read)
-+ DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
-+
-+ if (buflen < 2)
-+ return -1;
-+
-+ buf[0] = data & 0xff;
-+ buf[1] = (data >> 8) & 0xff;
-+
-+ return 2;
-+ } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
-+ int w;
-+ int len = FLD_GET(val, 23, 8);
-+ if (dsi.debug_read)
-+ DSSDBG("\tDCS long response, len %d\n", len);
-+
-+ if (len > buflen)
-+ return -1;
-+
-+ /* two byte checksum ends the packet, not included in len */
-+ for (w = 0; w < len + 2;) {
-+ int b;
-+ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
-+ if (dsi.debug_read)
-+ DSSDBG("\t\t%02x %02x %02x %02x\n",
-+ (val >> 0) & 0xff,
-+ (val >> 8) & 0xff,
-+ (val >> 16) & 0xff,
-+ (val >> 24) & 0xff);
-+
-+ for (b = 0; b < 4; ++b) {
-+ if (w < len)
-+ buf[w] = (val >> (b * 8)) & 0xff;
-+ /* we discard the 2 byte checksum */
-+ ++w;
-+ }
-+ }
-+
-+ return len;
-+
-+ } else {
-+ DSSERR("\tunknown datatype 0x%02x\n", dt);
-+ return -1;
-+ }
-+}
-+EXPORT_SYMBOL(dsi_vc_dcs_read);
-+
-+
-+int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
-+{
-+ return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
-+ len, 0);
-+}
-+EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
-+
-+
-+static int dsi_set_lp_rx_timeout(int ns, int x4, int x16)
-+{
-+ u32 r;
-+ unsigned long fck;
-+ int ticks;
-+
-+ /* ticks in DSI_FCK */
-+
-+ fck = dsi_fclk_rate();
-+ ticks = (fck / 1000 / 1000) * ns / 1000;
-+
-+ if (ticks > 0x1fff) {
-+ DSSERR("LP_TX_TO too high\n");
-+ return -EINVAL;
-+ }
-+
-+ r = dsi_read_reg(DSI_TIMING2);
-+ r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
-+ r = FLD_MOD(r, x16, 14, 14); /* LP_RX_TO_X16 */
-+ r = FLD_MOD(r, x4, 13, 13); /* LP_RX_TO_X4 */
-+ r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
-+ dsi_write_reg(DSI_TIMING2, r);
-+
-+ DSSDBG("LP_RX_TO %ld ns (%#x ticks)\n",
-+ (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
-+ (fck / 1000 / 1000),
-+ ticks);
-+
-+ return 0;
-+}
-+
-+static int dsi_set_ta_timeout(int ns, int x8, int x16)
-+{
-+ u32 r;
-+ unsigned long fck;
-+ int ticks;
-+
-+ /* ticks in DSI_FCK */
-+
-+ fck = dsi_fclk_rate();
-+ ticks = (fck / 1000 / 1000) * ns / 1000;
-+
-+ if (ticks > 0x1fff) {
-+ DSSERR("TA_TO too high\n");
-+ return -EINVAL;
-+ }
-+
-+ r = dsi_read_reg(DSI_TIMING1);
-+ r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
-+ r = FLD_MOD(r, x16, 30, 30); /* TA_TO_X16 */
-+ r = FLD_MOD(r, x8, 29, 29); /* TA_TO_X8 */
-+ r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
-+ dsi_write_reg(DSI_TIMING1, r);
-+
-+ DSSDBG("TA_TO %ld ns (%#x ticks)\n",
-+ (ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1) * 1000) /
-+ (fck / 1000 / 1000),
-+ ticks);
-+
-+ return 0;
-+}
-+
-+static int dsi_set_stop_state_counter(int ns, int x4, int x16)
-+{
-+ u32 r;
-+ unsigned long fck;
-+ int ticks;
-+
-+ /* ticks in DSI_FCK */
-+
-+ fck = dsi_fclk_rate();
-+ ticks = (fck / 1000 / 1000) * ns / 1000;
-+
-+ if (ticks > 0x1fff) {
-+ DSSERR("STOP_STATE_COUNTER_IO too high\n");
-+ return -EINVAL;
-+ }
-+
-+ r = dsi_read_reg(DSI_TIMING1);
-+ r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
-+ r = FLD_MOD(r, x16, 14, 14); /* STOP_STATE_X16_IO */
-+ r = FLD_MOD(r, x4, 13, 13); /* STOP_STATE_X4_IO */
-+ r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
-+ dsi_write_reg(DSI_TIMING1, r);
-+
-+ DSSDBG("STOP_STATE_COUNTER %ld ns (%#x ticks)\n",
-+ (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
-+ (fck / 1000 / 1000),
-+ ticks);
-+
-+ return 0;
-+}
-+
-+static int dsi_set_hs_tx_timeout(int ns, int x4, int x16)
-+{
-+ u32 r;
-+ unsigned long fck;
-+ int ticks;
-+
-+ /* ticks in TxByteClkHS */
-+
-+ fck = dsi.ddr_clk / 4;
-+ ticks = (fck / 1000 / 1000) * ns / 1000;
-+
-+ if (ticks > 0x1fff) {
-+ DSSERR("HS_TX_TO too high\n");
-+ return -EINVAL;
-+ }
-+
-+ r = dsi_read_reg(DSI_TIMING2);
-+ r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
-+ r = FLD_MOD(r, x16, 30, 30); /* HS_TX_TO_X16 */
-+ r = FLD_MOD(r, x4, 29, 29); /* HS_TX_TO_X8 (4 really) */
-+ r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
-+ dsi_write_reg(DSI_TIMING2, r);
-+
-+ DSSDBG("HS_TX_TO %ld ns (%#x ticks)\n",
-+ (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
-+ (fck / 1000 / 1000),
-+ ticks);
-+
-+ return 0;
-+}
-+static int dsi_proto_config(struct omap_display *display)
-+{
-+ u32 r;
-+ int buswidth = 0;
-+
-+ dsi_config_tx_fifo(DSI_FIFO_SIZE_128,
-+ DSI_FIFO_SIZE_0,
-+ DSI_FIFO_SIZE_0,
-+ DSI_FIFO_SIZE_0);
-+
-+ dsi_config_rx_fifo(DSI_FIFO_SIZE_128,
-+ DSI_FIFO_SIZE_0,
-+ DSI_FIFO_SIZE_0,
-+ DSI_FIFO_SIZE_0);
-+
-+ /* XXX what values for the timeouts? */
-+ dsi_set_stop_state_counter(1000, 0, 0);
-+
-+ dsi_set_ta_timeout(50000, 1, 1);
-+
-+ /* 3000ns * 16 */
-+ dsi_set_lp_rx_timeout(3000, 0, 1);
-+
-+ /* 10000ns * 4 */
-+ dsi_set_hs_tx_timeout(10000, 1, 0);
-+
-+ switch (display->ctrl->pixel_size) {
-+ case 16:
-+ buswidth = 0;
-+ break;
-+ case 18:
-+ buswidth = 1;
-+ break;
-+ case 24:
-+ buswidth = 2;
-+ break;
-+ default:
-+ BUG();
-+ }
-+
-+ r = dsi_read_reg(DSI_CTRL);
-+ r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
-+ r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
-+ r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
-+ /* XXX what should the ratio be */
-+ r = FLD_MOD(r, 0, 4, 4); /* VP_CLK_RATIO, VP_PCLK = VP_CLK/2 */
-+ r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
-+ r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
-+ r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
-+ r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
-+ r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
-+ r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
-+ r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
-+
-+ dsi_write_reg(DSI_CTRL, r);
-+
-+ /* we configure vc0 for L4 communication, and
-+ * vc1 for dispc */
-+ dsi_vc_config(0);
-+ dsi_vc_config_vp(1);
-+
-+ /* set all vc targets to peripheral 0 */
-+ dsi.vc[0].dest_per = 0;
-+ dsi.vc[1].dest_per = 0;
-+ dsi.vc[2].dest_per = 0;
-+ dsi.vc[3].dest_per = 0;
-+
-+ return 0;
-+}
-+
-+static void dsi_proto_timings(void)
-+{
-+ int tlpx_half, tclk_zero, tclk_prepare, tclk_trail;
-+ int tclk_pre, tclk_post;
-+ int ddr_clk_pre, ddr_clk_post;
-+ u32 r;
-+
-+ r = dsi_read_reg(DSI_DSIPHY_CFG1);
-+ tlpx_half = FLD_GET(r, 22, 16);
-+ tclk_trail = FLD_GET(r, 15, 8);
-+ tclk_zero = FLD_GET(r, 7, 0);
-+
-+ r = dsi_read_reg(DSI_DSIPHY_CFG2);
-+ tclk_prepare = FLD_GET(r, 7, 0);
-+
-+ /* min 8*UI */
-+ tclk_pre = 20;
-+ /* min 60ns + 52*UI */
-+ tclk_post = ns2ddr(60) + 26;
-+
-+ ddr_clk_pre = (tclk_pre + tlpx_half*2 + tclk_zero + tclk_prepare) / 4;
-+ ddr_clk_post = (tclk_post + tclk_trail) / 4;
-+
-+ r = dsi_read_reg(DSI_CLK_TIMING);
-+ r = FLD_MOD(r, ddr_clk_pre, 15, 8);
-+ r = FLD_MOD(r, ddr_clk_post, 7, 0);
-+ dsi_write_reg(DSI_CLK_TIMING, r);
-+
-+ DSSDBG("ddr_clk_pre %d, ddr_clk_post %d\n",
-+ ddr_clk_pre,
-+ ddr_clk_post);
-+}
-+
-+
-+#define DSI_DECL_VARS \
-+ int __dsi_cb = 0; u32 __dsi_cv = 0;
-+
-+#define DSI_FLUSH(ch) \
-+ if (__dsi_cb > 0) { \
-+ /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
-+ dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
-+ __dsi_cb = __dsi_cv = 0; \
-+ }
-+
-+#define DSI_PUSH(ch, data) \
-+ do { \
-+ __dsi_cv |= (data) << (__dsi_cb * 8); \
-+ /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
-+ if (++__dsi_cb > 3) \
-+ DSI_FLUSH(ch); \
-+ } while (0)
-+
-+static int dsi_update_screen_l4(struct omap_display *display,
-+ int x, int y, int w, int h)
-+{
-+ /* Note: supports only 24bit colors in 32bit container */
-+ int first = 1;
-+ int fifo_stalls = 0;
-+ int max_dsi_packet_size;
-+ int max_data_per_packet;
-+ int max_pixels_per_packet;
-+ int pixels_left;
-+ int bytespp = 3;
-+ int scr_width;
-+ u32 __iomem *data;
-+ int start_offset;
-+ int horiz_inc;
-+ int current_x;
-+ struct omap_overlay *ovl;
-+
-+ debug_irq = 0;
-+
-+ DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
-+ x, y, w, h);
-+
-+ ovl = display->manager->overlays[0];
-+
-+ if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
-+ return -EINVAL;
-+
-+ if (display->ctrl->pixel_size != 24)
-+ return -EINVAL;
-+
-+ scr_width = ovl->info.screen_width;
-+ data = ovl->info.vaddr;
-+
-+ start_offset = scr_width * y + x;
-+ horiz_inc = scr_width - w;
-+ current_x = x;
-+
-+ /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
-+ * in fifo */
-+
-+ /* When using CPU, max long packet size is TX buffer size */
-+ max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
-+
-+ /* we seem to get better perf if we divide the tx fifo to half,
-+ and while the other half is being sent, we fill the other half
-+ max_dsi_packet_size /= 2; */
-+
-+ max_data_per_packet = max_dsi_packet_size - 4 - 1;
-+
-+ max_pixels_per_packet = max_data_per_packet / bytespp;
-+
-+ DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
-+
-+ display->ctrl->setup_update(display, x, y, w, h);
-+
-+ pixels_left = w * h;
-+
-+ DSSDBG("total pixels %d\n", pixels_left);
-+
-+ data += start_offset;
-+
-+#ifdef DEBUG
-+ dsi.update_region.x = x;
-+ dsi.update_region.y = y;
-+ dsi.update_region.w = w;
-+ dsi.update_region.h = h;
-+ dsi.update_region.bytespp = bytespp;
-+#endif
-+
-+ perf_mark_start();
-+
-+ while (pixels_left > 0) {
-+ /* 0x2c = write_memory_start */
-+ /* 0x3c = write_memory_continue */
-+ u8 dcs_cmd = first ? 0x2c : 0x3c;
-+ int pixels;
-+ DSI_DECL_VARS;
-+ first = 0;
-+
-+#if 1
-+ /* using fifo not empty */
-+ /* TX_FIFO_NOT_EMPTY */
-+ while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
-+ udelay(1);
-+ fifo_stalls++;
-+ if (fifo_stalls > 0xfffff) {
-+ DSSERR("fifo stalls overflow, pixels left %d\n",
-+ pixels_left);
-+ dsi_if_enable(0);
-+ return -EIO;
-+ }
-+ }
-+#elif 1
-+ /* using fifo emptiness */
-+ while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
-+ max_dsi_packet_size) {
-+ fifo_stalls++;
-+ if (fifo_stalls > 0xfffff) {
-+ DSSERR("fifo stalls overflow, pixels left %d\n",
-+ pixels_left);
-+ dsi_if_enable(0);
-+ return -EIO;
-+ }
-+ }
-+#else
-+ while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
-+ fifo_stalls++;
-+ if (fifo_stalls > 0xfffff) {
-+ DSSERR("fifo stalls overflow, pixels left %d\n",
-+ pixels_left);
-+ dsi_if_enable(0);
-+ return -EIO;
-+ }
-+ }
-+#endif
-+ pixels = min(max_pixels_per_packet, pixels_left);
-+
-+ pixels_left -= pixels;
-+
-+ dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
-+ 1 + pixels * bytespp, 0);
-+
-+ DSI_PUSH(0, dcs_cmd);
-+
-+ while (pixels-- > 0) {
-+ u32 pix = __raw_readl(data++);
-+
-+ DSI_PUSH(0, (pix >> 16) & 0xff);
-+ DSI_PUSH(0, (pix >> 8) & 0xff);
-+ DSI_PUSH(0, (pix >> 0) & 0xff);
-+
-+ current_x++;
-+ if (current_x == x+w) {
-+ current_x = x;
-+ data += horiz_inc;
-+ }
-+ }
-+
-+ DSI_FLUSH(0);
-+ }
-+
-+ perf_show("L4");
-+
-+ return 0;
-+}
-+
-+#if 0
-+static void dsi_clear_screen_l4(struct omap_display *display,
-+ int x, int y, int w, int h)
-+{
-+ int first = 1;
-+ int fifo_stalls = 0;
-+ int max_dsi_packet_size;
-+ int max_data_per_packet;
-+ int max_pixels_per_packet;
-+ int pixels_left;
-+ int bytespp = 3;
-+ int pixnum;
-+
-+ debug_irq = 0;
-+
-+ DSSDBG("dsi_clear_screen_l4 (%d,%d %dx%d)\n",
-+ x, y, w, h);
-+
-+ if (display->ctrl->bpp != 24)
-+ return -EINVAL;
-+
-+ /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp)
-+ * bytes in fifo */
-+
-+ /* When using CPU, max long packet size is TX buffer size */
-+ max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
-+
-+ max_data_per_packet = max_dsi_packet_size - 4 - 1;
-+
-+ max_pixels_per_packet = max_data_per_packet / bytespp;
-+
-+ enable_clocks(1);
-+
-+ display->ctrl->setup_update(display, x, y, w, h);
-+
-+ pixels_left = w * h;
-+
-+ dsi.update_region.x = x;
-+ dsi.update_region.y = y;
-+ dsi.update_region.w = w;
-+ dsi.update_region.h = h;
-+ dsi.update_region.bytespp = bytespp;
-+
-+ start_measuring();
-+
-+ pixnum = 0;
-+
-+ while (pixels_left > 0) {
-+ /* 0x2c = write_memory_start */
-+ /* 0x3c = write_memory_continue */
-+ u8 dcs_cmd = first ? 0x2c : 0x3c;
-+ int pixels;
-+ DSI_DECL_VARS;
-+ first = 0;
-+
-+ /* TX_FIFO_NOT_EMPTY */
-+ while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
-+ fifo_stalls++;
-+ if (fifo_stalls > 0xfffff) {
-+ DSSERR("fifo stalls overflow\n");
-+ dsi_if_enable(0);
-+ enable_clocks(0);
-+ return;
-+ }
-+ }
-+
-+ pixels = min(max_pixels_per_packet, pixels_left);
-+
-+ pixels_left -= pixels;
-+
-+ dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
-+ 1 + pixels * bytespp, 0);
-+
-+ DSI_PUSH(0, dcs_cmd);
-+
-+ while (pixels-- > 0) {
-+ u32 pix;
-+
-+ pix = 0x000000;
-+
-+ DSI_PUSH(0, (pix >> 16) & 0xff);
-+ DSI_PUSH(0, (pix >> 8) & 0xff);
-+ DSI_PUSH(0, (pix >> 0) & 0xff);
-+ }
-+
-+ DSI_FLUSH(0);
-+ }
-+
-+ enable_clocks(0);
-+
-+ end_measuring("L4 CLEAR");
-+}
-+#endif
-+
-+static void dsi_setup_update_dispc(struct omap_display *display,
-+ u16 x, u16 y, u16 w, u16 h)
-+{
-+ DSSDBG("dsi_setup_update_dispc(%d,%d %dx%d)\n",
-+ x, y, w, h);
-+
-+#ifdef DEBUG
-+ dsi.update_region.x = x;
-+ dsi.update_region.y = y;
-+ dsi.update_region.w = w;
-+ dsi.update_region.h = h;
-+ dsi.update_region.bytespp = 3; // XXX
-+#endif
-+
-+ dispc_setup_partial_planes(display, &x, &y, &w, &h);
-+
-+ dispc_set_lcd_size(w, h);
-+}
-+
-+static void dsi_setup_autoupdate_dispc(struct omap_display *display)
-+{
-+ u16 w, h;
-+
-+ display->get_resolution(display, &w, &h);
-+
-+#ifdef DEBUG
-+ dsi.update_region.x = 0;
-+ dsi.update_region.y = 0;
-+ dsi.update_region.w = w;
-+ dsi.update_region.h = h;
-+ dsi.update_region.bytespp = 3; // XXX
-+#endif
-+
-+ /* the overlay settings may not have been applied, if we were in manual
-+ * mode earlier, so do it here */
-+ display->manager->apply(display->manager);
-+
-+ dispc_set_lcd_size(w, h);
-+
-+ dsi.autoupdate_setup = 0;
-+}
-+
-+static void dsi_update_screen_dispc(struct omap_display *display,
-+ u16 x, u16 y, u16 w, u16 h)
-+{
-+ int bytespp = 3;
-+ int total_len;
-+ int line_packet_len;
-+ u32 l;
-+
-+ if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
-+ DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
-+ x, y, w, h);
-+
-+ /* TODO: one packet could be longer, I think? Max is the line buffer */
-+ line_packet_len = w * bytespp + 1; /* 1 byte for DCS cmd */
-+ total_len = line_packet_len * h;
-+
-+ display->ctrl->setup_update(display, x, y, w, h);
-+
-+ if (0)
-+ dsi_vc_print_status(1);
-+
-+ perf_mark_start();
-+
-+ l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
-+ dsi_write_reg(DSI_VC_TE(1), l);
-+
-+ dsi_vc_write_long_header(1, DSI_DT_DCS_LONG_WRITE, line_packet_len, 0);
-+
-+ if (dsi.use_te)
-+ l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
-+ else
-+ l = FLD_MOD(l, 1, 31, 31); /* TE_START */
-+ dsi_write_reg(DSI_VC_TE(1), l);
-+
-+ dispc_enable_lcd_out(1);
-+
-+ if (dsi.use_te)
-+ dsi_vc_send_bta(1);
-+}
-+
-+static void framedone_callback(void *data, u32 mask)
-+{
-+ if (dsi.framedone_scheduled) {
-+ DSSERR("Framedone already scheduled. Bogus FRAMEDONE IRQ?\n");
-+ return;
-+ }
-+
-+ dsi.framedone_scheduled = 1;
-+
-+ /* We get FRAMEDONE when DISPC has finished sending pixels and turns
-+ * itself off. However, DSI still has the pixels in its buffers, and
-+ * is sending the data. Thus we have to wait until we can do a new
-+ * transfer or turn the clocks off. We do that in a separate work
-+ * func. */
-+ queue_work(dsi.workqueue, &dsi.framedone_work);
-+}
-+
-+static void framedone_worker(struct work_struct *work)
-+{
-+ u32 l;
-+ unsigned long tmo;
-+ int i = 0;
-+
-+ l = REG_GET(DSI_VC_TE(1), 23, 0); /* TE_SIZE */
-+
-+ /* There shouldn't be much stuff in DSI buffers, if any, so we'll
-+ * just busyloop */
-+ if (l > 0) {
-+ tmo = jiffies + msecs_to_jiffies(50);
-+ while (REG_GET(DSI_VC_TE(1), 23, 0) > 0) { /* TE_SIZE */
-+ i++;
-+ if (time_after(jiffies, tmo)) {
-+ DSSERR("timeout waiting TE_SIZE to zero\n");
-+ break;
-+ }
-+ cpu_relax();
-+ }
-+ }
-+
-+ if (REG_GET(DSI_VC_TE(1), 30, 30))
-+ DSSERR("TE_EN not zero\n");
-+
-+ if (REG_GET(DSI_VC_TE(1), 31, 31))
-+ DSSERR("TE_START not zero\n");
-+
-+ perf_show("DISPC");
-+
-+ if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
-+ DSSDBG("FRAMEDONE\n");
-+
-+#if 0
-+ if (l)
-+ DSSWARN("FRAMEDONE irq too early, %d bytes, %d loops\n", l, i);
-+#else
-+ if (l > 1024*3)
-+ DSSWARN("FRAMEDONE irq too early, %d bytes, %d loops\n", l, i);
-+#endif
-+
-+#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
-+ dispc_fake_vsync_irq();
-+#endif
-+ dsi.framedone_scheduled = 0;
-+
-+ /* XXX check that fifo is not full. otherwise we would sleep and never
-+ * get to process_cmd_fifo below */
-+ /* We check for target_update_mode, not update_mode. No reason to push
-+ * new updates if we're turning auto update off */
-+ if (dsi.target_update_mode == OMAP_DSS_UPDATE_AUTO)
-+ dsi_push_autoupdate(dsi.vc[1].display);
-+
-+ atomic_set(&dsi.cmd_pending, 0);
-+ dsi_process_cmd_fifo(NULL);
-+}
-+
-+static void dsi_start_auto_update(struct omap_display *display)
-+{
-+ DSSDBG("starting auto update\n");
-+
-+ dsi.autoupdate_setup = 1;
-+
-+ dsi_push_autoupdate(display);
-+}
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+/* FIFO functions */
-+
-+static void dsi_signal_fifo_waiters(void)
-+{
-+ if (atomic_read(&dsi.cmd_fifo_full) > 0) {
-+ DSSDBG("SIGNALING: Fifo not full for waiter!\n");
-+ complete(&dsi.cmd_done);
-+ atomic_dec(&dsi.cmd_fifo_full);
-+ }
-+}
-+
-+/* returns 1 for async op, and 0 for sync op */
-+static int dsi_do_update(struct omap_display *display,
-+ struct dsi_cmd_update *upd)
-+{
-+ int r;
-+ u16 x = upd->x, y = upd->y, w = upd->w, h = upd->h;
-+ u16 dw, dh;
-+
-+ if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED)
-+ return 0;
-+
-+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
-+ return 0;
-+
-+ display->get_resolution(display, &dw, &dh);
-+ if (x > dw || y > dh)
-+ return 0;
-+
-+ if (x + w > dw)
-+ w = dw - x;
-+
-+ if (y + h > dh)
-+ h = dh - y;
-+
-+ DSSDBGF("%d,%d %dx%d", x, y, w, h);
-+
-+ perf_mark_setup();
-+
-+ if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
-+ dsi_setup_update_dispc(display, x, y, w, h);
-+ dsi_update_screen_dispc(display, x, y, w, h);
-+ return 1;
-+ } else {
-+ r = dsi_update_screen_l4(display, x, y, w, h);
-+ if (r)
-+ DSSERR("L4 update failed\n");
-+ return 0;
-+ }
-+}
-+
-+/* returns 1 for async op, and 0 for sync op */
-+static int dsi_do_autoupdate(struct omap_display *display)
-+{
-+ int r;
-+ u16 w, h;
-+
-+ if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED)
-+ return 0;
-+
-+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
-+ return 0;
-+
-+ display->get_resolution(display, &w, &h);
-+
-+ perf_mark_setup();
-+
-+ if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
-+ if (dsi.autoupdate_setup)
-+ dsi_setup_autoupdate_dispc(display);
-+ dsi_update_screen_dispc(display, 0, 0, w, h);
-+ return 1;
-+ } else {
-+ r = dsi_update_screen_l4(display, 0, 0, w, h);
-+ if (r)
-+ DSSERR("L4 update failed\n");
-+ return 0;
-+ }
-+}
-+
-+static void dsi_do_cmd_mem_read(struct omap_display *display,
-+ struct dsi_cmd_mem_read *mem_read)
-+{
-+ int r;
-+ r = display->ctrl->memory_read(display,
-+ mem_read->buf,
-+ mem_read->size,
-+ mem_read->x,
-+ mem_read->y,
-+ mem_read->w,
-+ mem_read->h);
-+
-+ *mem_read->ret_size = (size_t)r;
-+ complete(mem_read->completion);
-+}
-+
-+static void dsi_do_cmd_test(struct omap_display *display,
-+ struct dsi_cmd_test *test)
-+{
-+ int r = 0;
-+
-+ DSSDBGF("");
-+
-+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
-+ return;
-+
-+ /* run test first in low speed mode */
-+ dsi_vc_enable_hs(0, 0);
-+
-+ if (display->ctrl->run_test) {
-+ r = display->ctrl->run_test(display, test->test_num);
-+ if (r)
-+ goto end;
-+ }
-+
-+ if (display->panel->run_test) {
-+ r = display->panel->run_test(display, test->test_num);
-+ if (r)
-+ goto end;
-+ }
-+
-+ /* then in high speed */
-+ dsi_vc_enable_hs(0, 1);
-+
-+ if (display->ctrl->run_test) {
-+ r = display->ctrl->run_test(display, test->test_num);
-+ if (r)
-+ goto end;
-+ }
-+
-+ if (display->panel->run_test)
-+ r = display->panel->run_test(display, test->test_num);
-+
-+end:
-+ dsi_vc_enable_hs(0, 1);
-+
-+ *test->result = r;
-+ complete(test->completion);
-+
-+ DSSDBG("test end\n");
-+}
-+
-+static void dsi_do_cmd_set_te(struct omap_display *display, bool enable)
-+{
-+ dsi.use_te = enable;
-+
-+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
-+ return;
-+
-+ display->ctrl->enable_te(display, enable);
-+
-+ if (enable) {
-+ /* disable LP_RX_TO, so that we can receive TE.
-+ * Time to wait for TE is longer than the timer allows */
-+ REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
-+ } else {
-+ REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
-+ }
-+}
-+
-+static void dsi_do_cmd_set_update_mode(struct omap_display *display,
-+ enum omap_dss_update_mode mode)
-+{
-+ dsi.update_mode = mode;
-+
-+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
-+ return;
-+
-+ if (mode == OMAP_DSS_UPDATE_AUTO)
-+ dsi_start_auto_update(display);
-+}
-+
-+static void dsi_process_cmd_fifo(struct work_struct *work)
-+{
-+ int len;
-+ struct dsi_cmd_item p;
-+ unsigned long flags;
-+ struct omap_display *display;
-+ int exit = 0;
-+
-+ if (dsi.debug_process)
-+ DSSDBGF("");
-+
-+ if (atomic_cmpxchg(&dsi.cmd_pending, 0, 1) == 1) {
-+ if (dsi.debug_process)
-+ DSSDBG("cmd pending, skip process\n");
-+ return;
-+ }
-+
-+ while (!exit) {
-+ spin_lock_irqsave(dsi.cmd_fifo->lock, flags);
-+
-+ len = __kfifo_get(dsi.cmd_fifo, (unsigned char *)&p,
-+ sizeof(p));
-+ if (len == 0) {
-+ if (dsi.debug_process)
-+ DSSDBG("nothing more in fifo, atomic clear\n");
-+ atomic_set(&dsi.cmd_pending, 0);
-+ spin_unlock_irqrestore(dsi.cmd_fifo->lock, flags);
-+ break;
-+ }
-+
-+ spin_unlock_irqrestore(dsi.cmd_fifo->lock, flags);
-+
-+ BUG_ON(len != sizeof(p));
-+
-+ display = p.display;
-+
-+ if (dsi.debug_process)
-+ DSSDBG("processing cmd %d\n", p.cmd);
-+
-+ switch (p.cmd) {
-+ case DSI_CMD_UPDATE:
-+ if (dsi_do_update(display, &p.u.r)) {
-+ if (dsi.debug_process)
-+ DSSDBG("async update\n");
-+ exit = 1;
-+ } else {
-+ if (dsi.debug_process)
-+ DSSDBG("sync update\n");
-+ }
-+ break;
-+
-+ case DSI_CMD_AUTOUPDATE:
-+ if (dsi_do_autoupdate(display)) {
-+ if (dsi.debug_process)
-+ DSSDBG("async autoupdate\n");
-+ exit = 1;
-+ } else {
-+ if (dsi.debug_process)
-+ DSSDBG("sync autoupdate\n");
-+ }
-+ break;
-+
-+ case DSI_CMD_SYNC:
-+ if (dsi.debug_process)
-+ DSSDBG("Signaling SYNC done!\n");
-+ complete(p.u.sync);
-+ break;
-+
-+ case DSI_CMD_MEM_READ:
-+ dsi_do_cmd_mem_read(display, &p.u.mem_read);
-+ break;
-+
-+ case DSI_CMD_TEST:
-+ dsi_do_cmd_test(display, &p.u.test);
-+ break;
-+
-+ case DSI_CMD_SET_TE:
-+ dsi_do_cmd_set_te(display, p.u.te);
-+ break;
-+
-+ case DSI_CMD_SET_UPDATE_MODE:
-+ dsi_do_cmd_set_update_mode(display, p.u.update_mode);
-+ break;
-+
-+ case DSI_CMD_SET_ROTATE:
-+ display->ctrl->set_rotate(display, p.u.rotate);
-+ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO)
-+ dsi.autoupdate_setup = 1;
-+ break;
-+
-+ case DSI_CMD_SET_MIRROR:
-+ display->ctrl->set_mirror(display, p.u.mirror);
-+ break;
-+
-+ default:
-+ BUG();
-+ }
-+ }
-+
-+ if (dsi.debug_process)
-+ DSSDBG("exit dsi_process_cmd_fifo\n");
-+
-+ dsi_signal_fifo_waiters();
-+}
-+
-+static void dsi_push_cmd(struct dsi_cmd_item *p)
-+{
-+ int ret;
-+
-+ if (dsi.debug_process)
-+ DSSDBGF("");
-+
-+ while (1) {
-+ unsigned long flags;
-+ unsigned avail, used;
-+
-+ spin_lock_irqsave(dsi.cmd_fifo->lock, flags);
-+ used = __kfifo_len(dsi.cmd_fifo) / sizeof(struct dsi_cmd_item);
-+ avail = DSI_CMD_FIFO_LEN - used;
-+
-+ if (dsi.debug_process)
-+ DSSDBG("%u/%u items left in fifo\n", avail, used);
-+
-+ if (avail == 0) {
-+ if (dsi.debug_process)
-+ DSSDBG("cmd fifo full, waiting...\n");
-+ spin_unlock_irqrestore(dsi.cmd_fifo->lock, flags);
-+ atomic_inc(&dsi.cmd_fifo_full);
-+ wait_for_completion(&dsi.cmd_done);
-+ if (dsi.debug_process)
-+ DSSDBG("cmd fifo not full, woke up\n");
-+ continue;
-+ }
-+
-+ ret = __kfifo_put(dsi.cmd_fifo, (unsigned char *)p,
-+ sizeof(*p));
-+
-+ spin_unlock_irqrestore(dsi.cmd_fifo->lock, flags);
-+
-+ BUG_ON(ret != sizeof(*p));
-+
-+ break;
-+ }
-+
-+ queue_work(dsi.workqueue, &dsi.process_work);
-+}
-+
-+static void dsi_push_update(struct omap_display *display,
-+ int x, int y, int w, int h)
-+{
-+ struct dsi_cmd_item p;
-+
-+ p.display = display;
-+ p.cmd = DSI_CMD_UPDATE;
-+
-+ p.u.r.x = x;
-+ p.u.r.y = y;
-+ p.u.r.w = w;
-+ p.u.r.h = h;
-+
-+ DSSDBG("pushing UPDATE %d,%d %dx%d\n", x, y, w, h);
-+
-+ dsi_push_cmd(&p);
-+}
-+
-+static void dsi_push_autoupdate(struct omap_display *display)
-+{
-+ struct dsi_cmd_item p;
-+
-+ p.display = display;
-+ p.cmd = DSI_CMD_AUTOUPDATE;
-+
-+ dsi_push_cmd(&p);
-+}
-+
-+static void dsi_push_sync(struct omap_display *display,
-+ struct completion *sync_comp)
-+{
-+ struct dsi_cmd_item p;
-+
-+ p.display = display;
-+ p.cmd = DSI_CMD_SYNC;
-+ p.u.sync = sync_comp;
-+
-+ DSSDBG("pushing SYNC\n");
-+
-+ dsi_push_cmd(&p);
-+}
-+
-+static void dsi_push_mem_read(struct omap_display *display,
-+ struct dsi_cmd_mem_read *mem_read)
-+{
-+ struct dsi_cmd_item p;
-+
-+ p.display = display;
-+ p.cmd = DSI_CMD_MEM_READ;
-+ p.u.mem_read = *mem_read;
-+
-+ DSSDBG("pushing MEM_READ\n");
-+
-+ dsi_push_cmd(&p);
-+}
-+
-+static void dsi_push_test(struct omap_display *display, int test_num,
-+ int *result, struct completion *completion)
-+{
-+ struct dsi_cmd_item p;
-+
-+ p.display = display;
-+ p.cmd = DSI_CMD_TEST;
-+ p.u.test.test_num = test_num;
-+ p.u.test.result = result;
-+ p.u.test.completion = completion;
-+
-+ DSSDBG("pushing TEST\n");
-+
-+ dsi_push_cmd(&p);
-+}
-+
-+static void dsi_push_set_te(struct omap_display *display, bool enable)
-+{
-+ struct dsi_cmd_item p;
-+
-+ p.display = display;
-+ p.cmd = DSI_CMD_SET_TE;
-+ p.u.te = enable;
-+
-+ DSSDBG("pushing SET_TE\n");
-+
-+ dsi_push_cmd(&p);
-+}
-+
-+static void dsi_push_set_update_mode(struct omap_display *display,
-+ enum omap_dss_update_mode mode)
-+{
-+ struct dsi_cmd_item p;
-+
-+ p.display = display;
-+ p.cmd = DSI_CMD_SET_UPDATE_MODE;
-+ p.u.update_mode = mode;
-+
-+ DSSDBG("pushing SET_UPDATE_MODE\n");
-+
-+ dsi_push_cmd(&p);
-+}
-+
-+static void dsi_push_set_rotate(struct omap_display *display, int rotate)
-+{
-+ struct dsi_cmd_item p;
-+
-+ p.display = display;
-+ p.cmd = DSI_CMD_SET_ROTATE;
-+ p.u.rotate = rotate;
-+
-+ DSSDBG("pushing SET_ROTATE\n");
-+
-+ dsi_push_cmd(&p);
-+}
-+
-+static void dsi_push_set_mirror(struct omap_display *display, int mirror)
-+{
-+ struct dsi_cmd_item p;
-+
-+ p.display = display;
-+ p.cmd = DSI_CMD_SET_MIRROR;
-+ p.u.mirror = mirror;
-+
-+ DSSDBG("pushing SET_MIRROR\n");
-+
-+ dsi_push_cmd(&p);
-+}
-+
-+static int dsi_wait_sync(struct omap_display *display)
-+{
-+ long wait = msecs_to_jiffies(60000);
-+ struct completion compl;
-+
-+ DSSDBGF("");
-+
-+ init_completion(&compl);
-+ dsi_push_sync(display, &compl);
-+
-+ DSSDBG("Waiting for SYNC to happen...\n");
-+ wait = wait_for_completion_timeout(&compl, wait);
-+ DSSDBG("Released from SYNC\n");
-+
-+ if (wait == 0) {
-+ DSSERR("timeout waiting sync\n");
-+ return -ETIME;
-+ }
-+
-+ return 0;
-+}
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+/* Display funcs */
-+
-+static int dsi_display_init_dispc(struct omap_display *display)
-+{
-+ int r;
-+
-+ r = omap_dispc_register_isr(framedone_callback, NULL,
-+ DISPC_IRQ_FRAMEDONE);
-+ if (r) {
-+ DSSERR("can't get FRAMEDONE irq\n");
-+ return r;
-+ }
-+
-+ dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
-+
-+ dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI);
-+ dispc_enable_fifohandcheck(1);
-+
-+ dispc_set_tft_data_lines(display->ctrl->pixel_size);
-+
-+ {
-+ struct omap_video_timings timings = {
-+ .hsw = 1,
-+ .hfp = 1,
-+ .hbp = 1,
-+ .vsw = 1,
-+ .vfp = 0,
-+ .vbp = 0,
-+ };
-+
-+ dispc_set_lcd_timings(&timings);
-+ }
-+
-+ return 0;
-+}
-+
-+static void dsi_display_uninit_dispc(struct omap_display *display)
-+{
-+ omap_dispc_unregister_isr(framedone_callback, NULL,
-+ DISPC_IRQ_FRAMEDONE);
-+}
-+
-+static int dsi_display_init_dsi(struct omap_display *display)
-+{
-+ struct dsi_clock_info cinfo;
-+ int r;
-+
-+ _dsi_print_reset_status();
-+
-+ r = dsi_pll_init(1, 0);
-+ if (r)
-+ goto err0;
-+
-+ r = dsi_pll_calc_ddrfreq(display->hw_config.u.dsi.ddr_clk_hz, &cinfo);
-+ if (r)
-+ goto err1;
-+
-+ r = dsi_pll_program(&cinfo);
-+ if (r)
-+ goto err1;
-+
-+ DSSDBG("PLL OK\n");
-+
-+ r = dsi_complexio_init(display);
-+ if (r)
-+ goto err1;
-+
-+ _dsi_print_reset_status();
-+
-+ dsi_proto_timings();
-+ dsi_set_lp_clk_divisor();
-+
-+ if (1)
-+ _dsi_print_reset_status();
-+
-+ r = dsi_proto_config(display);
-+ if (r)
-+ goto err2;
-+
-+ /* enable interface */
-+ dsi_vc_enable(0, 1);
-+ dsi_vc_enable(1, 1);
-+ dsi_if_enable(1);
-+ dsi_force_tx_stop_mode_io();
-+
-+ if (display->ctrl && display->ctrl->enable) {
-+ r = display->ctrl->enable(display);
-+ if (r)
-+ goto err3;
-+ }
-+
-+ if (display->panel && display->panel->enable) {
-+ r = display->panel->enable(display);
-+ if (r)
-+ goto err4;
-+ }
-+
-+ /* enable high-speed after initial config */
-+ dsi_vc_enable_hs(0, 1);
-+
-+ return 0;
-+err4:
-+ if (display->ctrl && display->ctrl->disable)
-+ display->ctrl->disable(display);
-+err3:
-+ dsi_if_enable(0);
-+err2:
-+ dsi_complexio_uninit();
-+err1:
-+ dsi_pll_uninit();
-+err0:
-+ return r;
-+}
-+
-+static void dsi_display_uninit_dsi(struct omap_display *display)
-+{
-+ if (display->panel && display->panel->disable)
-+ display->panel->disable(display);
-+ if (display->ctrl && display->ctrl->disable)
-+ display->ctrl->disable(display);
-+
-+ dsi_complexio_uninit();
-+ dsi_pll_uninit();
-+}
-+
-+static int dsi_core_init(void)
-+{
-+ /* Autoidle */
-+ REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
-+
-+ /* ENWAKEUP */
-+ REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
-+
-+ /* SIDLEMODE smart-idle */
-+ REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
-+
-+ _dsi_initialize_irq();
-+
-+ return 0;
-+}
-+
-+static int dsi_display_enable(struct omap_display *display)
-+{
-+ int r = 0;
-+
-+ DSSDBG("dsi_display_enable\n");
-+
-+ mutex_lock(&dsi.lock);
-+
-+ if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
-+ DSSERR("display already enabled\n");
-+ r = -EINVAL;
-+ goto err0;
-+ }
-+
-+ enable_clocks(1);
-+ dsi_enable_pll_clock(1);
-+
-+ r = _dsi_reset();
-+ if (r)
-+ return r;
-+
-+ dsi_core_init();
-+
-+ r = dsi_display_init_dispc(display);
-+ if (r)
-+ goto err1;
-+
-+ r = dsi_display_init_dsi(display);
-+ if (r)
-+ goto err2;
-+
-+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
-+
-+ if (dsi.use_te)
-+ dsi_push_set_te(display, 1);
-+
-+ dsi_push_set_update_mode(display, dsi.user_update_mode);
-+ dsi.target_update_mode = dsi.user_update_mode;
-+
-+ mutex_unlock(&dsi.lock);
-+
-+ return dsi_wait_sync(display);
-+
-+err2:
-+ dsi_display_uninit_dispc(display);
-+err1:
-+ enable_clocks(0);
-+ dsi_enable_pll_clock(0);
-+err0:
-+ mutex_unlock(&dsi.lock);
-+ DSSDBG("dsi_display_enable FAILED\n");
-+ return r;
-+}
-+
-+static void dsi_display_disable(struct omap_display *display)
-+{
-+ DSSDBG("dsi_display_disable\n");
-+
-+ mutex_lock(&dsi.lock);
-+
-+ if (display->state == OMAP_DSS_DISPLAY_DISABLED ||
-+ display->state == OMAP_DSS_DISPLAY_SUSPENDED)
-+ goto end;
-+
-+ if (dsi.target_update_mode != OMAP_DSS_UPDATE_DISABLED) {
-+ dsi_push_set_update_mode(display, OMAP_DSS_UPDATE_DISABLED);
-+ dsi.target_update_mode = OMAP_DSS_UPDATE_DISABLED;
-+ }
-+
-+ dsi_wait_sync(display);
-+
-+ display->state = OMAP_DSS_DISPLAY_DISABLED;
-+
-+ dsi_display_uninit_dispc(display);
-+
-+ dsi_display_uninit_dsi(display);
-+
-+ enable_clocks(0);
-+ dsi_enable_pll_clock(0);
-+end:
-+ mutex_unlock(&dsi.lock);
-+}
-+
-+static int dsi_display_suspend(struct omap_display *display)
-+{
-+ DSSDBG("dsi_display_suspend\n");
-+
-+ dsi_display_disable(display);
-+
-+ display->state = OMAP_DSS_DISPLAY_SUSPENDED;
-+
-+ return 0;
-+}
-+
-+static int dsi_display_resume(struct omap_display *display)
-+{
-+ DSSDBG("dsi_display_resume\n");
-+
-+ display->state = OMAP_DSS_DISPLAY_DISABLED;
-+ return dsi_display_enable(display);
-+}
-+
-+static int dsi_display_update(struct omap_display *display,
-+ u16 x, u16 y, u16 w, u16 h)
-+{
-+ DSSDBG("dsi_display_update(%d,%d %dx%d)\n", x, y, w, h);
-+
-+ if (w == 0 || h == 0)
-+ return 0;
-+
-+ mutex_lock(&dsi.lock);
-+
-+ if (dsi.target_update_mode == OMAP_DSS_UPDATE_MANUAL)
-+ dsi_push_update(display, x, y, w, h);
-+ /* XXX else return error? */
-+
-+ mutex_unlock(&dsi.lock);
-+
-+ return 0;
-+}
-+
-+static int dsi_display_sync(struct omap_display *display)
-+{
-+ DSSDBGF("");
-+ return dsi_wait_sync(display);
-+}
-+
-+static int dsi_display_set_update_mode(struct omap_display *display,
-+ enum omap_dss_update_mode mode)
-+{
-+ DSSDBGF("%d", mode);
-+
-+ mutex_lock(&dsi.lock);
-+
-+ if (dsi.target_update_mode != mode) {
-+ dsi_push_set_update_mode(display, mode);
-+
-+ dsi.target_update_mode = mode;
-+ dsi.user_update_mode = mode;
-+ }
-+
-+ mutex_unlock(&dsi.lock);
-+
-+ return dsi_wait_sync(display);
-+}
-+
-+static enum omap_dss_update_mode dsi_display_get_update_mode(
-+ struct omap_display *display)
-+{
-+ return dsi.update_mode;
-+}
-+
-+static int dsi_display_enable_te(struct omap_display *display, bool enable)
-+{
-+ DSSDBGF("%d", enable);
-+
-+ if (!display->ctrl->enable_te)
-+ return -ENOENT;
-+
-+ dsi_push_set_te(display, enable);
-+
-+ return dsi_wait_sync(display);
-+}
-+
-+static int dsi_display_get_te(struct omap_display *display)
-+{
-+ return dsi.use_te;
-+}
-+
-+
-+
-+static int dsi_display_set_rotate(struct omap_display *display, u8 rotate)
-+{
-+ DSSDBGF("%d", rotate);
-+
-+ if (!display->ctrl->set_rotate || !display->ctrl->get_rotate)
-+ return -EINVAL;
-+
-+ dsi_push_set_rotate(display, rotate);
-+
-+ return dsi_wait_sync(display);
-+}
-+
-+static u8 dsi_display_get_rotate(struct omap_display *display)
-+{
-+ if (!display->ctrl->set_rotate || !display->ctrl->get_rotate)
-+ return 0;
-+
-+ return display->ctrl->get_rotate(display);
-+}
-+
-+static int dsi_display_set_mirror(struct omap_display *display, bool mirror)
-+{
-+ DSSDBGF("%d", mirror);
-+
-+ if (!display->ctrl->set_mirror || !display->ctrl->get_mirror)
-+ return -EINVAL;
-+
-+ dsi_push_set_mirror(display, mirror);
-+
-+ return dsi_wait_sync(display);
-+}
-+
-+static bool dsi_display_get_mirror(struct omap_display *display)
-+{
-+ if (!display->ctrl->set_mirror || !display->ctrl->get_mirror)
-+ return 0;
-+
-+ return display->ctrl->get_mirror(display);
-+}
-+
-+static int dsi_display_run_test(struct omap_display *display, int test_num)
-+{
-+ long wait = msecs_to_jiffies(60000);
-+ struct completion compl;
-+ int result;
-+
-+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
-+ return -EIO;
-+
-+ DSSDBGF("%d", test_num);
-+
-+ init_completion(&compl);
-+
-+ dsi_push_test(display, test_num, &result, &compl);
-+
-+ DSSDBG("Waiting for SYNC to happen...\n");
-+ wait = wait_for_completion_timeout(&compl, wait);
-+ DSSDBG("Released from SYNC\n");
-+
-+ if (wait == 0) {
-+ DSSERR("timeout waiting test sync\n");
-+ return -ETIME;
-+ }
-+
-+ return result;
-+}
-+
-+static int dsi_display_memory_read(struct omap_display *display,
-+ void *buf, size_t size,
-+ u16 x, u16 y, u16 w, u16 h)
-+{
-+ long wait = msecs_to_jiffies(60000);
-+ struct completion compl;
-+ struct dsi_cmd_mem_read mem_read;
-+ size_t ret_size;
-+
-+ DSSDBGF("");
-+
-+ if (!display->ctrl->memory_read)
-+ return -EINVAL;
-+
-+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
-+ return -EIO;
-+
-+ init_completion(&compl);
-+
-+ mem_read.x = x;
-+ mem_read.y = y;
-+ mem_read.w = w;
-+ mem_read.h = h;
-+ mem_read.buf = buf;
-+ mem_read.size = size;
-+ mem_read.ret_size = &ret_size;
-+ mem_read.completion = &compl;
-+
-+ dsi_push_mem_read(display, &mem_read);
-+
-+ DSSDBG("Waiting for SYNC to happen...\n");
-+ wait = wait_for_completion_timeout(&compl, wait);
-+ DSSDBG("Released from SYNC\n");
-+
-+ if (wait == 0) {
-+ DSSERR("timeout waiting mem read sync\n");
-+ return -ETIME;
-+ }
-+
-+ return ret_size;
-+}
-+
-+static void dsi_configure_overlay(struct omap_overlay *ovl)
-+{
-+ unsigned low, high, size;
-+ enum omap_burst_size burst;
-+ enum omap_plane plane = ovl->id;
-+
-+ burst = OMAP_DSS_BURST_16x32;
-+ size = 16 * 32 / 8;
-+
-+ dispc_set_burst_size(plane, burst);
-+
-+ high = dispc_get_plane_fifo_size(plane) - size;
-+ low = 0;
-+ dispc_setup_plane_fifo(plane, low, high);
-+}
-+
-+void dsi_init_display(struct omap_display *display)
-+{
-+ DSSDBG("DSI init\n");
-+
-+ display->enable = dsi_display_enable;
-+ display->disable = dsi_display_disable;
-+ display->suspend = dsi_display_suspend;
-+ display->resume = dsi_display_resume;
-+ display->update = dsi_display_update;
-+ display->sync = dsi_display_sync;
-+ display->set_update_mode = dsi_display_set_update_mode;
-+ display->get_update_mode = dsi_display_get_update_mode;
-+ display->enable_te = dsi_display_enable_te;
-+ display->get_te = dsi_display_get_te;
-+
-+ display->get_rotate = dsi_display_get_rotate;
-+ display->set_rotate = dsi_display_set_rotate;
-+
-+ display->get_mirror = dsi_display_get_mirror;
-+ display->set_mirror = dsi_display_set_mirror;
-+
-+ display->run_test = dsi_display_run_test;
-+ display->memory_read = dsi_display_memory_read;
-+
-+ display->configure_overlay = dsi_configure_overlay;
-+
-+ display->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
-+
-+ dsi.vc[0].display = display;
-+ dsi.vc[1].display = display;
-+}
-+
-+int dsi_init(void)
-+{
-+ u32 rev;
-+
-+ spin_lock_init(&dsi.cmd_lock);
-+ dsi.cmd_fifo = kfifo_alloc(
-+ DSI_CMD_FIFO_LEN * sizeof(struct dsi_cmd_item),
-+ GFP_KERNEL,
-+ &dsi.cmd_lock);
-+
-+ init_completion(&dsi.cmd_done);
-+ atomic_set(&dsi.cmd_fifo_full, 0);
-+ atomic_set(&dsi.cmd_pending, 0);
-+
-+ init_completion(&dsi.bta_completion);
-+
-+ dsi.workqueue = create_singlethread_workqueue("dsi");
-+ INIT_WORK(&dsi.framedone_work, framedone_worker);
-+ INIT_WORK(&dsi.process_work, dsi_process_cmd_fifo);
-+
-+ mutex_init(&dsi.lock);
-+
-+ dsi.target_update_mode = OMAP_DSS_UPDATE_DISABLED;
-+ dsi.user_update_mode = OMAP_DSS_UPDATE_DISABLED;
-+
-+ dsi.base = ioremap(DSI_BASE, DSI_SZ_REGS);
-+ if (!dsi.base) {
-+ DSSERR("can't ioremap DSI\n");
-+ return -ENOMEM;
-+ }
-+
-+ enable_clocks(1);
-+
-+ rev = dsi_read_reg(DSI_REVISION);
-+ printk(KERN_INFO "OMAP DSI rev %d.%d\n",
-+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
-+
-+ enable_clocks(0);
-+
-+ return 0;
-+}
-+
-+void dsi_exit(void)
-+{
-+ flush_workqueue(dsi.workqueue);
-+ destroy_workqueue(dsi.workqueue);
-+
-+ iounmap(dsi.base);
-+
-+ kfifo_free(dsi.cmd_fifo);
-+
-+ DSSDBG("omap_dsi_exit\n");
-+}
-+
-diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
-new file mode 100644
-index 0000000..adc1f34
---- /dev/null
-+++ b/drivers/video/omap2/dss/dss.c
-@@ -0,0 +1,345 @@
-+/*
-+ * linux/drivers/video/omap2/dss/dss.c
-+ *
-+ * Copyright (C) 2009 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * Some code and ideas taken from drivers/video/omap/ driver
-+ * by Imre Deak.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#define DSS_SUBSYS_NAME "DSS"
-+
-+#include <linux/kernel.h>
-+#include <linux/io.h>
-+#include <linux/err.h>
-+#include <linux/delay.h>
-+#include <linux/interrupt.h>
-+#include <linux/seq_file.h>
-+
-+#include <mach/display.h>
-+#include "dss.h"
-+
-+#define DSS_BASE 0x48050000
-+
-+#define DSS_SZ_REGS SZ_512
-+
-+struct dss_reg {
-+ u16 idx;
-+};
-+
-+#define DSS_REG(idx) ((const struct dss_reg) { idx })
-+
-+#define DSS_REVISION DSS_REG(0x0000)
-+#define DSS_SYSCONFIG DSS_REG(0x0010)
-+#define DSS_SYSSTATUS DSS_REG(0x0014)
-+#define DSS_IRQSTATUS DSS_REG(0x0018)
-+#define DSS_CONTROL DSS_REG(0x0040)
-+#define DSS_SDI_CONTROL DSS_REG(0x0044)
-+#define DSS_PLL_CONTROL DSS_REG(0x0048)
-+#define DSS_SDI_STATUS DSS_REG(0x005C)
-+
-+#define REG_GET(idx, start, end) \
-+ FLD_GET(dss_read_reg(idx), start, end)
-+
-+#define REG_FLD_MOD(idx, val, start, end) \
-+ dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
-+
-+static struct {
-+ void __iomem *base;
-+
-+ u32 ctx[DSS_SZ_REGS / sizeof(u32)];
-+} dss;
-+
-+static int _omap_dss_wait_reset(void);
-+
-+static inline void dss_write_reg(const struct dss_reg idx, u32 val)
-+{
-+ __raw_writel(val, dss.base + idx.idx);
-+}
-+
-+static inline u32 dss_read_reg(const struct dss_reg idx)
-+{
-+ return __raw_readl(dss.base + idx.idx);
-+}
-+
-+#define SR(reg) \
-+ dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
-+#define RR(reg) \
-+ dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
-+
-+void dss_save_context(void)
-+{
-+ if (cpu_is_omap24xx())
-+ return;
-+
-+ SR(SYSCONFIG);
-+ SR(CONTROL);
-+
-+#ifdef CONFIG_OMAP2_DSS_SDI
-+ SR(SDI_CONTROL);
-+ SR(PLL_CONTROL);
-+#endif
-+}
-+
-+void dss_restore_context(void)
-+{
-+ if (_omap_dss_wait_reset())
-+ DSSERR("DSS not coming out of reset after sleep\n");
-+
-+ RR(SYSCONFIG);
-+ RR(CONTROL);
-+
-+#ifdef CONFIG_OMAP2_DSS_SDI
-+ RR(SDI_CONTROL);
-+ RR(PLL_CONTROL);
-+#endif
-+}
-+
-+#undef SR
-+#undef RR
-+
-+void dss_sdi_init(u8 datapairs)
-+{
-+ u32 l;
-+
-+ BUG_ON(datapairs > 3 || datapairs < 1);
-+
-+ l = dss_read_reg(DSS_SDI_CONTROL);
-+ l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */
-+ l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */
-+ l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */
-+ dss_write_reg(DSS_SDI_CONTROL, l);
-+
-+ l = dss_read_reg(DSS_PLL_CONTROL);
-+ l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */
-+ l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */
-+ l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */
-+ dss_write_reg(DSS_PLL_CONTROL, l);
-+}
-+
-+void dss_sdi_enable(void)
-+{
-+ dispc_pck_free_enable(1);
-+
-+ /* Reset SDI PLL */
-+ REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
-+ udelay(1); /* wait 2x PCLK */
-+
-+ /* Lock SDI PLL */
-+ REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
-+
-+ /* Waiting for PLL lock request to complete */
-+ while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6))
-+ ;
-+
-+ /* Clearing PLL_GO bit */
-+ REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
-+
-+ /* Waiting for PLL to lock */
-+ while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5)))
-+ ;
-+
-+ dispc_lcd_enable_signal(1);
-+
-+ /* Waiting for SDI reset to complete */
-+ while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2)))
-+ ;
-+}
-+
-+void dss_sdi_disable(void)
-+{
-+ dispc_lcd_enable_signal(0);
-+
-+ dispc_pck_free_enable(0);
-+
-+ /* Reset SDI PLL */
-+ REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
-+}
-+
-+void dss_dump_regs(struct seq_file *s)
-+{
-+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
-+
-+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+
-+ DUMPREG(DSS_REVISION);
-+ DUMPREG(DSS_SYSCONFIG);
-+ DUMPREG(DSS_SYSSTATUS);
-+ DUMPREG(DSS_IRQSTATUS);
-+ DUMPREG(DSS_CONTROL);
-+ DUMPREG(DSS_SDI_CONTROL);
-+ DUMPREG(DSS_PLL_CONTROL);
-+ DUMPREG(DSS_SDI_STATUS);
-+
-+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+#undef DUMPREG
-+}
-+
-+void dss_select_clk_source(bool dsi, bool dispc)
-+{
-+ u32 r;
-+ r = dss_read_reg(DSS_CONTROL);
-+ r = FLD_MOD(r, dsi, 1, 1); /* DSI_CLK_SWITCH */
-+ r = FLD_MOD(r, dispc, 0, 0); /* DISPC_CLK_SWITCH */
-+ dss_write_reg(DSS_CONTROL, r);
-+}
-+
-+int dss_get_dsi_clk_source(void)
-+{
-+ return FLD_GET(dss_read_reg(DSS_CONTROL), 1, 1);
-+}
-+
-+int dss_get_dispc_clk_source(void)
-+{
-+ return FLD_GET(dss_read_reg(DSS_CONTROL), 0, 0);
-+}
-+
-+static irqreturn_t dss_irq_handler_omap2(int irq, void *arg)
-+{
-+ dispc_irq_handler();
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static irqreturn_t dss_irq_handler_omap3(int irq, void *arg)
-+{
-+ u32 irqstatus;
-+
-+ irqstatus = dss_read_reg(DSS_IRQSTATUS);
-+
-+ if (irqstatus & (1<<0)) /* DISPC_IRQ */
-+ dispc_irq_handler();
-+#ifdef CONFIG_OMAP2_DSS_DSI
-+ if (irqstatus & (1<<1)) /* DSI_IRQ */
-+ dsi_irq_handler();
-+#endif
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int _omap_dss_wait_reset(void)
-+{
-+ unsigned timeout = 1000;
-+
-+ while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) {
-+ udelay(1);
-+ if (!--timeout) {
-+ DSSERR("soft reset failed\n");
-+ return -ENODEV;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int _omap_dss_reset(void)
-+{
-+ /* Soft reset */
-+ REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1);
-+ return _omap_dss_wait_reset();
-+}
-+
-+void dss_set_venc_output(enum omap_dss_venc_type type)
-+{
-+ int l = 0;
-+
-+ if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
-+ l = 0;
-+ else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
-+ l = 1;
-+ else
-+ BUG();
-+
-+ /* venc out selection. 0 = comp, 1 = svideo */
-+ REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
-+}
-+
-+void dss_set_dac_pwrdn_bgz(bool enable)
-+{
-+ REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
-+}
-+
-+int dss_init(bool skip_init)
-+{
-+ int r;
-+ u32 rev;
-+
-+ dss.base = ioremap(DSS_BASE, DSS_SZ_REGS);
-+ if (!dss.base) {
-+ DSSERR("can't ioremap DSS\n");
-+ r = -ENOMEM;
-+ goto fail0;
-+ }
-+
-+ if (!skip_init) {
-+ /* We need to wait here a bit, otherwise we sometimes start to
-+ * get synclost errors, and after that only power cycle will
-+ * restore DSS functionality. I have no idea why this happens.
-+ * And we have to wait _before_ resetting the DSS, but after
-+ * enabling clocks.
-+ */
-+ msleep(50);
-+
-+ _omap_dss_reset();
-+
-+ }
-+ else
-+ printk("DSS SKIP RESET\n");
-+
-+ /* autoidle */
-+ REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
-+
-+ /* Select DPLL */
-+ REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
-+
-+#ifdef CONFIG_OMAP2_DSS_VENC
-+ REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
-+ REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
-+ REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
-+#endif
-+
-+ r = request_irq(INT_24XX_DSS_IRQ,
-+ cpu_is_omap24xx()
-+ ? dss_irq_handler_omap2
-+ : dss_irq_handler_omap3,
-+ 0, "OMAP DSS", NULL);
-+
-+ if (r < 0) {
-+ DSSERR("omap2 dss: request_irq failed\n");
-+ goto fail1;
-+ }
-+
-+ dss_save_context();
-+
-+ rev = dss_read_reg(DSS_REVISION);
-+ printk(KERN_INFO "OMAP DSS rev %d.%d\n",
-+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
-+
-+ return 0;
-+
-+fail1:
-+ iounmap(dss.base);
-+fail0:
-+ return r;
-+}
-+
-+void dss_exit(void)
-+{
-+ free_irq(INT_24XX_DSS_IRQ, NULL);
-+
-+ iounmap(dss.base);
-+}
-+
-diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
-new file mode 100644
-index 0000000..bac5ece
---- /dev/null
-+++ b/drivers/video/omap2/dss/dss.h
-@@ -0,0 +1,331 @@
-+/*
-+ * linux/drivers/video/omap2/dss/dss.h
-+ *
-+ * Copyright (C) 2009 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * Some code and ideas taken from drivers/video/omap/ driver
-+ * by Imre Deak.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#ifndef __OMAP2_DSS_H
-+#define __OMAP2_DSS_H
-+
-+#ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
-+#define DEBUG
-+#endif
-+
-+#ifdef DEBUG
-+extern unsigned int dss_debug;
-+#ifdef DSS_SUBSYS_NAME
-+#define DSSDBG(format, ...) \
-+ if (dss_debug) \
-+ printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \
-+ ## __VA_ARGS__)
-+#else
-+#define DSSDBG(format, ...) \
-+ if (dss_debug) \
-+ printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__)
-+#endif
-+
-+#ifdef DSS_SUBSYS_NAME
-+#define DSSDBGF(format, ...) \
-+ if (dss_debug) \
-+ printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \
-+ ": %s(" format ")\n", \
-+ __func__, \
-+ ## __VA_ARGS__)
-+#else
-+#define DSSDBGF(format, ...) \
-+ if (dss_debug) \
-+ printk(KERN_DEBUG "omapdss: " \
-+ ": %s(" format ")\n", \
-+ __func__, \
-+ ## __VA_ARGS__)
-+#endif
-+
-+#else /* DEBUG */
-+#define DSSDBG(format, ...)
-+#define DSSDBGF(format, ...)
-+#endif
-+
-+
-+#ifdef DSS_SUBSYS_NAME
-+#define DSSERR(format, ...) \
-+ printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
-+ ## __VA_ARGS__)
-+#else
-+#define DSSERR(format, ...) \
-+ printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
-+#endif
-+
-+#ifdef DSS_SUBSYS_NAME
-+#define DSSINFO(format, ...) \
-+ printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
-+ ## __VA_ARGS__)
-+#else
-+#define DSSINFO(format, ...) \
-+ printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
-+#endif
-+
-+#ifdef DSS_SUBSYS_NAME
-+#define DSSWARN(format, ...) \
-+ printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
-+ ## __VA_ARGS__)
-+#else
-+#define DSSWARN(format, ...) \
-+ printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
-+#endif
-+
-+/* OMAP TRM gives bitfields as start:end, where start is the higher bit
-+ number. For example 7:0 */
-+#define FLD_MASK(start, end) (((1 << (start - end + 1)) - 1) << (end))
-+#define FLD_VAL(val, start, end) (((val) << end) & FLD_MASK(start, end))
-+#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
-+#define FLD_MOD(orig, val, start, end) \
-+ (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
-+
-+#define DISPC_MAX_FCK 173000000
-+
-+enum omap_burst_size {
-+ OMAP_DSS_BURST_4x32 = 0,
-+ OMAP_DSS_BURST_8x32 = 1,
-+ OMAP_DSS_BURST_16x32 = 2,
-+};
-+
-+enum omap_parallel_interface_mode {
-+ OMAP_DSS_PARALLELMODE_BYPASS, /* MIPI DPI */
-+ OMAP_DSS_PARALLELMODE_RFBI, /* MIPI DBI */
-+ OMAP_DSS_PARALLELMODE_DSI,
-+};
-+
-+enum dss_clock {
-+ DSS_CLK_ICK = 1 << 0,
-+ DSS_CLK_FCK1 = 1 << 1,
-+ DSS_CLK_FCK2 = 1 << 2,
-+ DSS_CLK_54M = 1 << 3,
-+ DSS_CLK_96M = 1 << 4,
-+};
-+
-+struct dispc_clock_info {
-+ /* rates that we get with dividers below */
-+ unsigned long fck;
-+ unsigned long lck;
-+ unsigned long pck;
-+
-+ /* dividers */
-+ u16 fck_div;
-+ u16 lck_div;
-+ u16 pck_div;
-+};
-+
-+struct dsi_clock_info {
-+ /* rates that we get with dividers below */
-+ unsigned long fint;
-+ unsigned long dsiphy;
-+ unsigned long clkin;
-+ unsigned long dsi1_pll_fclk;
-+ unsigned long dsi2_pll_fclk;
-+ unsigned long lck;
-+ unsigned long pck;
-+
-+ /* dividers */
-+ u16 regn;
-+ u16 regm;
-+ u16 regm3;
-+ u16 regm4;
-+
-+ u16 lck_div;
-+ u16 pck_div;
-+
-+ u8 highfreq;
-+ bool use_dss2_fck;
-+};
-+
-+struct seq_file;
-+struct platform_device;
-+
-+/* core */
-+void dss_clk_enable(enum dss_clock clks);
-+void dss_clk_disable(enum dss_clock clks);
-+unsigned long dss_clk_get_rate(enum dss_clock clk);
-+int dss_need_ctx_restore(void);
-+void dss_dump_clocks(struct seq_file *s);
-+
-+int dss_dsi_power_up(void);
-+void dss_dsi_power_down(void);
-+
-+/* display */
-+void dss_init_displays(struct platform_device *pdev);
-+void dss_uninit_displays(struct platform_device *pdev);
-+int dss_suspend_all_displays(void);
-+int dss_resume_all_displays(void);
-+struct omap_display *dss_get_display(int no);
-+
-+/* manager */
-+int dss_init_overlay_managers(struct platform_device *pdev);
-+void dss_uninit_overlay_managers(struct platform_device *pdev);
-+
-+/* overlay */
-+void dss_init_overlays(struct platform_device *pdev, const char *def_disp_name);
-+void dss_uninit_overlays(struct platform_device *pdev);
-+int dss_check_overlay(struct omap_overlay *ovl, struct omap_display *display);
-+void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
-+
-+/* DSS */
-+int dss_init(bool skip_init);
-+void dss_exit(void);
-+
-+void dss_save_context(void);
-+void dss_restore_context(void);
-+
-+void dss_dump_regs(struct seq_file *s);
-+
-+void dss_sdi_init(u8 datapairs);
-+void dss_sdi_enable(void);
-+void dss_sdi_disable(void);
-+
-+void dss_select_clk_source(bool dsi, bool dispc);
-+int dss_get_dsi_clk_source(void);
-+int dss_get_dispc_clk_source(void);
-+void dss_set_venc_output(enum omap_dss_venc_type type);
-+void dss_set_dac_pwrdn_bgz(bool enable);
-+
-+/* SDI */
-+int sdi_init(bool skip_init);
-+void sdi_exit(void);
-+void sdi_init_display(struct omap_display *display);
-+
-+/* DSI */
-+int dsi_init(void);
-+void dsi_exit(void);
-+
-+void dsi_dump_clocks(struct seq_file *s);
-+void dsi_dump_regs(struct seq_file *s);
-+
-+void dsi_save_context(void);
-+void dsi_restore_context(void);
-+
-+void dsi_init_display(struct omap_display *display);
-+void dsi_irq_handler(void);
-+unsigned long dsi_get_dsi1_pll_rate(void);
-+unsigned long dsi_get_dsi2_pll_rate(void);
-+int dsi_pll_calc_pck(bool is_tft, unsigned long req_pck,
-+ struct dsi_clock_info *cinfo);
-+int dsi_pll_program(struct dsi_clock_info *cinfo);
-+int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv);
-+void dsi_pll_uninit(void);
-+
-+/* DPI */
-+int dpi_init(void);
-+void dpi_exit(void);
-+void dpi_init_display(struct omap_display *display);
-+
-+/* DISPC */
-+int dispc_init(void);
-+void dispc_exit(void);
-+void dispc_dump_clocks(struct seq_file *s);
-+void dispc_dump_regs(struct seq_file *s);
-+void dispc_irq_handler(void);
-+void dispc_fake_vsync_irq(void);
-+
-+void dispc_save_context(void);
-+void dispc_restore_context(void);
-+
-+void dispc_lcd_enable_signal_polarity(bool act_high);
-+void dispc_lcd_enable_signal(bool enable);
-+void dispc_pck_free_enable(bool enable);
-+void dispc_enable_fifohandcheck(bool enable);
-+
-+void dispc_set_lcd_size(u16 width, u16 height);
-+void dispc_set_digit_size(u16 width, u16 height);
-+u32 dispc_get_plane_fifo_size(enum omap_plane plane);
-+void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high);
-+void dispc_enable_fifomerge(bool enable);
-+void dispc_set_burst_size(enum omap_plane plane,
-+ enum omap_burst_size burst_size);
-+
-+void dispc_set_plane_ba0(enum omap_plane plane, u32 paddr);
-+void dispc_set_plane_ba1(enum omap_plane plane, u32 paddr);
-+void dispc_set_plane_pos(enum omap_plane plane, u16 x, u16 y);
-+void dispc_set_plane_size(enum omap_plane plane, u16 width, u16 height);
-+
-+int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
-+ u32 paddr, u16 screen_width,
-+ u16 pos_x, u16 pos_y,
-+ u16 width, u16 height,
-+ u16 out_width, u16 out_height,
-+ enum omap_color_mode color_mode,
-+ bool ilace,
-+ u8 rotation, bool mirror);
-+
-+void dispc_go(enum omap_channel channel);
-+void dispc_enable_lcd_out(bool enable);
-+void dispc_enable_digit_out(bool enable);
-+int dispc_enable_plane(enum omap_plane plane, bool enable);
-+
-+void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode);
-+void dispc_set_tft_data_lines(u8 data_lines);
-+void dispc_set_lcd_display_type(enum omap_lcd_display_type type);
-+void dispc_set_loadmode(enum omap_dss_load_mode mode);
-+
-+void dispc_set_default_color(enum omap_channel channel, u32 color);
-+u32 dispc_get_default_color(enum omap_channel channel);
-+void dispc_set_trans_key(enum omap_channel ch,
-+ enum omap_dss_color_key_type type,
-+ u32 trans_key);
-+void dispc_get_trans_key(enum omap_channel ch,
-+ enum omap_dss_color_key_type *type,
-+ u32 *trans_key);
-+void dispc_enable_trans_key(enum omap_channel ch, bool enable);
-+bool dispc_trans_key_enabled(enum omap_channel ch);
-+
-+void dispc_set_lcd_timings(struct omap_video_timings *timings);
-+unsigned long dispc_fclk_rate(void);
-+unsigned long dispc_pclk_rate(void);
-+void dispc_set_pol_freq(struct omap_panel *panel);
-+void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
-+ u16 *lck_div, u16 *pck_div);
-+int dispc_calc_clock_div(bool is_tft, unsigned long req_pck,
-+ struct dispc_clock_info *cinfo);
-+int dispc_set_clock_div(struct dispc_clock_info *cinfo);
-+int dispc_get_clock_div(struct dispc_clock_info *cinfo);
-+void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div);
-+
-+void dispc_setup_partial_planes(struct omap_display *display,
-+ u16 *x, u16 *y, u16 *w, u16 *h);
-+void dispc_draw_partial_planes(struct omap_display *display);
-+
-+
-+/* VENC */
-+int venc_init(void);
-+void venc_exit(void);
-+void venc_dump_regs(struct seq_file *s);
-+void venc_init_display(struct omap_display *display);
-+
-+/* RFBI */
-+int rfbi_init(void);
-+void rfbi_exit(void);
-+void rfbi_dump_regs(struct seq_file *s);
-+
-+int rfbi_configure(int rfbi_module, int bpp, int lines);
-+void rfbi_enable_rfbi(bool enable);
-+void rfbi_transfer_area(u16 width, u16 height,
-+ void (callback)(void *data), void *data);
-+void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t);
-+unsigned long rfbi_get_max_tx_rate(void);
-+void rfbi_init_display(struct omap_display *display);
-+
-+#endif
-diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
-new file mode 100644
-index 0000000..b0fee80
---- /dev/null
-+++ b/drivers/video/omap2/dss/manager.c
-@@ -0,0 +1,576 @@
-+/*
-+ * linux/drivers/video/omap2/dss/manager.c
-+ *
-+ * Copyright (C) 2009 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * Some code and ideas taken from drivers/video/omap/ driver
-+ * by Imre Deak.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#define DSS_SUBSYS_NAME "MANAGER"
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <mach/display.h>
-+
-+#include "dss.h"
-+
-+static int num_managers;
-+static struct list_head manager_list;
-+
-+static ssize_t manager_name_show(struct omap_overlay_manager *mgr, char *buf)
-+{
-+ return snprintf(buf, PAGE_SIZE, "%s\n", mgr->name);
-+}
-+
-+static ssize_t manager_display_show(struct omap_overlay_manager *mgr, char *buf)
-+{
-+ return snprintf(buf, PAGE_SIZE, "%s\n",
-+ mgr->display ? mgr->display->name : "<none>");
-+}
-+
-+static ssize_t manager_display_store(struct omap_overlay_manager *mgr, const char *buf, size_t size)
-+{
-+ int r, i;
-+ int len = size;
-+ struct omap_display *display = NULL;
-+
-+ if (buf[size-1] == '\n')
-+ --len;
-+
-+ if (len > 0) {
-+ for (i = 0; i < omap_dss_get_num_displays(); ++i) {
-+ display = dss_get_display(i);
-+
-+ if (strncmp(buf, display->name, len) == 0)
-+ break;
-+
-+ display = NULL;
-+ }
-+ }
-+
-+ if (len > 0 && display == NULL)
-+ return -EINVAL;
-+
-+ if (display)
-+ DSSDBG("display %s found\n", display->name);
-+
-+ if (mgr->display) {
-+ r = mgr->unset_display(mgr);
-+ if (r) {
-+ DSSERR("failed to unset display\n");
-+ return r;
-+ }
-+ }
-+
-+ if (display) {
-+ r = mgr->set_display(mgr, display);
-+ if (r) {
-+ DSSERR("failed to set manager\n");
-+ return r;
-+ }
-+
-+ r = mgr->apply(mgr);
-+ if (r) {
-+ DSSERR("failed to apply dispc config\n");
-+ return r;
-+ }
-+ }
-+
-+ return size;
-+}
-+
-+static ssize_t manager_default_color_show(struct omap_overlay_manager *mgr,
-+ char *buf)
-+{
-+ u32 default_color;
-+
-+ default_color = dispc_get_default_color(mgr->id);
-+ return snprintf(buf, PAGE_SIZE, "%d", default_color);
-+}
-+
-+static ssize_t manager_default_color_store(struct omap_overlay_manager *mgr,
-+ const char *buf, size_t size)
-+{
-+ u32 default_color;
-+
-+ if (sscanf(buf, "%d", &default_color) != 1)
-+ return -EINVAL;
-+ dispc_set_default_color(mgr->id, default_color);
-+
-+ return size;
-+}
-+
-+static const char *color_key_type_str[] = {
-+ "gfx-destination",
-+ "video-source",
-+};
-+
-+static ssize_t manager_color_key_type_show(struct omap_overlay_manager *mgr,
-+ char *buf)
-+{
-+ enum omap_dss_color_key_type key_type;
-+
-+ dispc_get_trans_key(mgr->id, &key_type, NULL);
-+ BUG_ON(key_type >= ARRAY_SIZE(color_key_type_str));
-+
-+ return snprintf(buf, PAGE_SIZE, "%s\n", color_key_type_str[key_type]);
-+}
-+
-+static ssize_t manager_color_key_type_store(struct omap_overlay_manager *mgr,
-+ const char *buf, size_t size)
-+{
-+ enum omap_dss_color_key_type key_type;
-+ u32 key_value;
-+
-+ for (key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
-+ key_type < ARRAY_SIZE(color_key_type_str); key_type++) {
-+ if (sysfs_streq(buf, color_key_type_str[key_type]))
-+ break;
-+ }
-+ if (key_type == ARRAY_SIZE(color_key_type_str))
-+ return -EINVAL;
-+ dispc_get_trans_key(mgr->id, NULL, &key_value);
-+ dispc_set_trans_key(mgr->id, key_type, key_value);
-+
-+ return size;
-+}
-+
-+static ssize_t manager_color_key_value_show(struct omap_overlay_manager *mgr,
-+ char *buf)
-+{
-+ u32 key_value;
-+
-+ dispc_get_trans_key(mgr->id, NULL, &key_value);
-+
-+ return snprintf(buf, PAGE_SIZE, "%d\n", key_value);
-+}
-+
-+static ssize_t manager_color_key_value_store(struct omap_overlay_manager *mgr,
-+ const char *buf, size_t size)
-+{
-+ enum omap_dss_color_key_type key_type;
-+ u32 key_value;
-+
-+ if (sscanf(buf, "%d", &key_value) != 1)
-+ return -EINVAL;
-+ dispc_get_trans_key(mgr->id, &key_type, NULL);
-+ dispc_set_trans_key(mgr->id, key_type, key_value);
-+
-+ return size;
-+}
-+
-+static ssize_t manager_color_key_enabled_show(struct omap_overlay_manager *mgr,
-+ char *buf)
-+{
-+ return snprintf(buf, PAGE_SIZE, "%d\n",
-+ dispc_trans_key_enabled(mgr->id));
-+}
-+
-+static ssize_t manager_color_key_enabled_store(struct omap_overlay_manager *mgr,
-+ const char *buf, size_t size)
-+{
-+ int enable;
-+
-+ if (sscanf(buf, "%d", &enable) != 1)
-+ return -EINVAL;
-+
-+ dispc_enable_trans_key(mgr->id, enable);
-+
-+ return size;
-+}
-+
-+
-+struct manager_attribute {
-+ struct attribute attr;
-+ ssize_t (*show)(struct omap_overlay_manager *, char *);
-+ ssize_t (*store)(struct omap_overlay_manager *, const char *, size_t);
-+};
-+
-+#define MANAGER_ATTR(_name, _mode, _show, _store) \
-+ struct manager_attribute manager_attr_##_name = \
-+ __ATTR(_name, _mode, _show, _store)
-+
-+static MANAGER_ATTR(name, S_IRUGO, manager_name_show, NULL);
-+static MANAGER_ATTR(display, S_IRUGO|S_IWUSR,
-+ manager_display_show, manager_display_store);
-+static MANAGER_ATTR(default_color, S_IRUGO|S_IWUSR,
-+ manager_default_color_show, manager_default_color_store);
-+static MANAGER_ATTR(color_key_type, S_IRUGO|S_IWUSR,
-+ manager_color_key_type_show, manager_color_key_type_store);
-+static MANAGER_ATTR(color_key_value, S_IRUGO|S_IWUSR,
-+ manager_color_key_value_show, manager_color_key_value_store);
-+static MANAGER_ATTR(color_key_enabled, S_IRUGO|S_IWUSR,
-+ manager_color_key_enabled_show, manager_color_key_enabled_store);
-+
-+static struct attribute *manager_sysfs_attrs[] = {
-+ &manager_attr_name.attr,
-+ &manager_attr_display.attr,
-+ &manager_attr_default_color.attr,
-+ &manager_attr_color_key_type.attr,
-+ &manager_attr_color_key_value.attr,
-+ &manager_attr_color_key_enabled.attr,
-+ NULL
-+};
-+
-+static ssize_t manager_attr_show(struct kobject *kobj, struct attribute *attr, char *buf)
-+{
-+ struct omap_overlay_manager *manager;
-+ struct manager_attribute *manager_attr;
-+
-+ manager = container_of(kobj, struct omap_overlay_manager, kobj);
-+ manager_attr = container_of(attr, struct manager_attribute, attr);
-+
-+ if (!manager_attr->show)
-+ return -ENOENT;
-+
-+ return manager_attr->show(manager, buf);
-+}
-+
-+static ssize_t manager_attr_store(struct kobject *kobj, struct attribute *attr,
-+ const char *buf, size_t size)
-+{
-+ struct omap_overlay_manager *manager;
-+ struct manager_attribute *manager_attr;
-+
-+ manager = container_of(kobj, struct omap_overlay_manager, kobj);
-+ manager_attr = container_of(attr, struct manager_attribute, attr);
-+
-+ if (!manager_attr->store)
-+ return -ENOENT;
-+
-+ return manager_attr->store(manager, buf, size);
-+}
-+
-+static struct sysfs_ops manager_sysfs_ops = {
-+ .show = manager_attr_show,
-+ .store = manager_attr_store,
-+};
-+
-+static struct kobj_type manager_ktype = {
-+ .sysfs_ops = &manager_sysfs_ops,
-+ .default_attrs = manager_sysfs_attrs,
-+};
-+
-+static int omap_dss_set_display(struct omap_overlay_manager *mgr,
-+ struct omap_display *display)
-+{
-+ int i;
-+ int r;
-+
-+ if (display->manager) {
-+ DSSERR("display '%s' already has a manager '%s'\n",
-+ display->name, display->manager->name);
-+ return -EINVAL;
-+ }
-+
-+ if ((mgr->supported_displays & display->type) == 0) {
-+ DSSERR("display '%s' does not support manager '%s'\n",
-+ display->name, mgr->name);
-+ return -EINVAL;
-+ }
-+
-+ for (i = 0; i < mgr->num_overlays; i++) {
-+ struct omap_overlay *ovl = mgr->overlays[i];
-+
-+ if (ovl->manager != mgr || !ovl->info.enabled)
-+ continue;
-+
-+ r = dss_check_overlay(ovl, display);
-+ if (r)
-+ return r;
-+ }
-+
-+ display->manager = mgr;
-+ mgr->display = display;
-+
-+ return 0;
-+}
-+
-+static int omap_dss_unset_display(struct omap_overlay_manager *mgr)
-+{
-+ if (!mgr->display) {
-+ DSSERR("failed to unset display, display not set.\n");
-+ return -EINVAL;
-+ }
-+
-+ mgr->display->manager = NULL;
-+ mgr->display = NULL;
-+
-+ return 0;
-+}
-+
-+
-+static int overlay_enabled(struct omap_overlay *ovl)
-+{
-+ return ovl->info.enabled && ovl->manager && ovl->manager->display;
-+}
-+
-+/* We apply settings to both managers here so that we can use optimizations
-+ * like fifomerge. Shadow registers can be changed first and the non-shadowed
-+ * should be changed last, at the same time with GO */
-+static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
-+{
-+ int i;
-+ int ret = 0;
-+ enum omap_dss_update_mode mode;
-+ struct omap_display *display;
-+ struct omap_overlay *ovl;
-+ bool ilace = 0;
-+ int outw, outh;
-+ int r;
-+ int num_planes_enabled = 0;
-+
-+ DSSDBG("omap_dss_mgr_apply(%s)\n", mgr->name);
-+
-+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+
-+ /* Configure normal overlay parameters and disable unused overlays */
-+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
-+ ovl = omap_dss_get_overlay(i);
-+
-+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
-+ continue;
-+
-+ if (!overlay_enabled(ovl)) {
-+ dispc_enable_plane(ovl->id, 0);
-+ continue;
-+ }
-+
-+ display = ovl->manager->display;
-+
-+ if (dss_check_overlay(ovl, display)) {
-+ dispc_enable_plane(ovl->id, 0);
-+ continue;
-+ }
-+
-+ ++num_planes_enabled;
-+
-+ /* On a manual update display, in manual update mode, update()
-+ * handles configuring planes */
-+ mode = OMAP_DSS_UPDATE_AUTO;
-+ if (display->get_update_mode)
-+ mode = display->get_update_mode(mgr->display);
-+
-+ if (display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE &&
-+ mode != OMAP_DSS_UPDATE_AUTO)
-+ continue;
-+
-+ if (display->type == OMAP_DISPLAY_TYPE_VENC)
-+ ilace = 1;
-+
-+ if (ovl->info.out_width == 0)
-+ outw = ovl->info.width;
-+ else
-+ outw = ovl->info.out_width;
-+
-+ if (ovl->info.out_height == 0)
-+ outh = ovl->info.height;
-+ else
-+ outh = ovl->info.out_height;
-+
-+ r = dispc_setup_plane(ovl->id, ovl->manager->id,
-+ ovl->info.paddr,
-+ ovl->info.screen_width,
-+ ovl->info.pos_x,
-+ ovl->info.pos_y,
-+ ovl->info.width,
-+ ovl->info.height,
-+ outw,
-+ outh,
-+ ovl->info.color_mode,
-+ ilace,
-+ ovl->info.rotation,
-+ ovl->info.mirror);
-+
-+ if (r) {
-+ DSSERR("dispc_setup_plane failed for ovl %d\n",
-+ ovl->id);
-+ dispc_enable_plane(ovl->id, 0);
-+ continue;
-+ }
-+
-+ dispc_enable_plane(ovl->id, 1);
-+ }
-+
-+ /* Enable fifo merge if possible */
-+ dispc_enable_fifomerge(num_planes_enabled == 1);
-+
-+ /* Go through overlays again. This time we configure fifos. We have to
-+ * do this after enabling/disabling fifomerge so that we have correct
-+ * knowledge of fifo sizes */
-+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
-+ ovl = omap_dss_get_overlay(i);
-+
-+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
-+ continue;
-+
-+ if (!overlay_enabled(ovl)) {
-+ continue;
-+ }
-+
-+ ovl->manager->display->configure_overlay(ovl);
-+ }
-+
-+ /* Issue GO for managers */
-+ list_for_each_entry(mgr, &manager_list, list) {
-+ if (!(mgr->caps & OMAP_DSS_OVL_MGR_CAP_DISPC))
-+ continue;
-+
-+ display = mgr->display;
-+
-+ if (!display)
-+ continue;
-+
-+ /* We don't need GO with manual update display. LCD iface will
-+ * always be turned off after frame, and new settings will
-+ * be taken in to use at next update */
-+ if (display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE)
-+ continue;
-+
-+ dispc_go(mgr->id);
-+ }
-+
-+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+
-+ return ret;
-+}
-+
-+static void omap_dss_mgr_set_def_color(struct omap_overlay_manager *mgr,
-+ u32 color)
-+{
-+ dispc_set_default_color(mgr->id, color);
-+}
-+
-+static void omap_dss_mgr_set_trans_key(struct omap_overlay_manager *mgr,
-+ enum omap_dss_color_key_type type,
-+ u32 trans_key)
-+{
-+ dispc_set_trans_key(mgr->id, type, trans_key);
-+}
-+
-+static void omap_dss_mgr_enable_trans_key(struct omap_overlay_manager *mgr,
-+ bool enable)
-+{
-+ dispc_enable_trans_key(mgr->id, enable);
-+}
-+
-+static void omap_dss_add_overlay_manager(struct omap_overlay_manager *manager)
-+{
-+ ++num_managers;
-+ list_add_tail(&manager->list, &manager_list);
-+}
-+
-+int dss_init_overlay_managers(struct platform_device *pdev)
-+{
-+ int i, r;
-+
-+ INIT_LIST_HEAD(&manager_list);
-+
-+ num_managers = 0;
-+
-+ for (i = 0; i < 2; ++i) {
-+ struct omap_overlay_manager *mgr;
-+ mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
-+
-+ BUG_ON(mgr == NULL);
-+
-+ switch (i) {
-+ case 0:
-+ mgr->name = "lcd";
-+ mgr->id = OMAP_DSS_CHANNEL_LCD;
-+ mgr->supported_displays =
-+ OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
-+ OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI;
-+ break;
-+ case 1:
-+ mgr->name = "tv";
-+ mgr->id = OMAP_DSS_CHANNEL_DIGIT;
-+ mgr->supported_displays = OMAP_DISPLAY_TYPE_VENC;
-+ break;
-+ }
-+
-+ mgr->set_display = &omap_dss_set_display,
-+ mgr->unset_display = &omap_dss_unset_display,
-+ mgr->apply = &omap_dss_mgr_apply,
-+ mgr->set_default_color = &omap_dss_mgr_set_def_color,
-+ mgr->set_trans_key = &omap_dss_mgr_set_trans_key,
-+ mgr->enable_trans_key = &omap_dss_mgr_enable_trans_key,
-+ mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC,
-+
-+ dss_overlay_setup_dispc_manager(mgr);
-+
-+ omap_dss_add_overlay_manager(mgr);
-+
-+ r = kobject_init_and_add(&mgr->kobj, &manager_ktype,
-+ &pdev->dev.kobj, "manager%d", i);
-+
-+ if (r) {
-+ DSSERR("failed to create sysfs file\n");
-+ continue;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+void dss_uninit_overlay_managers(struct platform_device *pdev)
-+{
-+ struct omap_overlay_manager *mgr;
-+
-+ while (!list_empty(&manager_list)) {
-+ mgr = list_first_entry(&manager_list,
-+ struct omap_overlay_manager, list);
-+ list_del(&mgr->list);
-+ kobject_del(&mgr->kobj);
-+ kobject_put(&mgr->kobj);
-+ kfree(mgr);
-+ }
-+
-+ num_managers = 0;
-+}
-+
-+int omap_dss_get_num_overlay_managers(void)
-+{
-+ return num_managers;
-+}
-+EXPORT_SYMBOL(omap_dss_get_num_overlay_managers);
-+
-+struct omap_overlay_manager *omap_dss_get_overlay_manager(int num)
-+{
-+ int i = 0;
-+ struct omap_overlay_manager *mgr;
-+
-+ list_for_each_entry(mgr, &manager_list, list) {
-+ if (i++ == num)
-+ return mgr;
-+ }
-+
-+ return NULL;
-+}
-+EXPORT_SYMBOL(omap_dss_get_overlay_manager);
-+
-+#ifdef L4_EXAMPLE
-+static int ovl_mgr_apply_l4(struct omap_overlay_manager *mgr)
-+{
-+ DSSDBG("omap_dss_mgr_apply_l4(%s)\n", mgr->name);
-+
-+ return 0;
-+}
-+#endif
-+
-diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c
-new file mode 100644
-index 0000000..968edbe
---- /dev/null
-+++ b/drivers/video/omap2/dss/overlay.c
-@@ -0,0 +1,587 @@
-+/*
-+ * linux/drivers/video/omap2/dss/overlay.c
-+ *
-+ * Copyright (C) 2009 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * Some code and ideas taken from drivers/video/omap/ driver
-+ * by Imre Deak.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#define DSS_SUBSYS_NAME "OVERLAY"
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/err.h>
-+#include <linux/sysfs.h>
-+#include <linux/kobject.h>
-+#include <linux/platform_device.h>
-+
-+#include <mach/display.h>
-+
-+#include "dss.h"
-+
-+static int num_overlays;
-+static struct list_head overlay_list;
-+
-+static ssize_t overlay_name_show(struct omap_overlay *ovl, char *buf)
-+{
-+ return snprintf(buf, PAGE_SIZE, "%s\n", ovl->name);
-+}
-+
-+static ssize_t overlay_manager_show(struct omap_overlay *ovl, char *buf)
-+{
-+ return snprintf(buf, PAGE_SIZE, "%s\n",
-+ ovl->manager ? ovl->manager->name : "<none>");
-+}
-+
-+static ssize_t overlay_manager_store(struct omap_overlay *ovl, const char *buf, size_t size)
-+{
-+ int i, r;
-+ struct omap_overlay_manager *mgr = NULL;
-+ int len = size;
-+
-+ if (buf[size-1] == '\n')
-+ --len;
-+
-+ if (len > 0) {
-+ for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
-+ mgr = omap_dss_get_overlay_manager(i);
-+
-+ if (strncmp(buf, mgr->name, len) == 0)
-+ break;
-+
-+ mgr = NULL;
-+ }
-+ }
-+
-+ if (len > 0 && mgr == NULL)
-+ return -EINVAL;
-+
-+ if (mgr)
-+ DSSDBG("manager %s found\n", mgr->name);
-+
-+ if (mgr != ovl->manager) {
-+ /* detach old manager */
-+ if (ovl->manager) {
-+ r = ovl->unset_manager(ovl);
-+ if (r) {
-+ DSSERR("detach failed\n");
-+ return r;
-+ }
-+ }
-+
-+ if (mgr) {
-+ r = ovl->set_manager(ovl, mgr);
-+ if (r) {
-+ DSSERR("Failed to attach overlay\n");
-+ return r;
-+ }
-+ }
-+ }
-+
-+ if (ovl->manager && (r = ovl->manager->apply(ovl->manager)))
-+ return r;
-+
-+ return size;
-+}
-+
-+static ssize_t overlay_input_size_show(struct omap_overlay *ovl, char *buf)
-+{
-+ return snprintf(buf, PAGE_SIZE, "%d,%d\n",
-+ ovl->info.width, ovl->info.height);
-+}
-+
-+static ssize_t overlay_screen_width_show(struct omap_overlay *ovl, char *buf)
-+{
-+ return snprintf(buf, PAGE_SIZE, "%d\n", ovl->info.screen_width);
-+}
-+
-+static ssize_t overlay_position_show(struct omap_overlay *ovl, char *buf)
-+{
-+ return snprintf(buf, PAGE_SIZE, "%d,%d\n",
-+ ovl->info.pos_x, ovl->info.pos_y);
-+}
-+
-+static ssize_t overlay_position_store(struct omap_overlay *ovl,
-+ const char *buf, size_t size)
-+{
-+ int r;
-+ char *last;
-+ struct omap_overlay_info info;
-+
-+ ovl->get_overlay_info(ovl, &info);
-+
-+ info.pos_x = simple_strtoul(buf, &last, 10);
-+ ++last;
-+ if (last - buf >= size)
-+ return -EINVAL;
-+
-+ info.pos_y = simple_strtoul(last, &last, 10);
-+
-+ if ((r = ovl->set_overlay_info(ovl, &info)))
-+ return r;
-+
-+ if (ovl->manager && (r = ovl->manager->apply(ovl->manager)))
-+ return r;
-+
-+ return size;
-+}
-+
-+static ssize_t overlay_output_size_show(struct omap_overlay *ovl, char *buf)
-+{
-+ return snprintf(buf, PAGE_SIZE, "%d,%d\n",
-+ ovl->info.out_width, ovl->info.out_height);
-+}
-+
-+static ssize_t overlay_output_size_store(struct omap_overlay *ovl,
-+ const char *buf, size_t size)
-+{
-+ int r;
-+ char *last;
-+ struct omap_overlay_info info;
-+
-+ ovl->get_overlay_info(ovl, &info);
-+
-+ info.out_width = simple_strtoul(buf, &last, 10);
-+ ++last;
-+ if (last - buf >= size)
-+ return -EINVAL;
-+
-+ info.out_height = simple_strtoul(last, &last, 10);
-+
-+ if ((r = ovl->set_overlay_info(ovl, &info)))
-+ return r;
-+
-+ if (ovl->manager && (r = ovl->manager->apply(ovl->manager)))
-+ return r;
-+
-+ return size;
-+}
-+
-+static ssize_t overlay_enabled_show(struct omap_overlay *ovl, char *buf)
-+{
-+ return snprintf(buf, PAGE_SIZE, "%d\n", ovl->info.enabled);
-+}
-+
-+static ssize_t overlay_enabled_store(struct omap_overlay *ovl, const char *buf, size_t size)
-+{
-+ int r;
-+ struct omap_overlay_info info;
-+
-+ ovl->get_overlay_info(ovl, &info);
-+
-+ info.enabled = simple_strtoul(buf, NULL, 10);
-+
-+ if ((r = ovl->set_overlay_info(ovl, &info)))
-+ return r;
-+
-+ if (ovl->manager && (r = ovl->manager->apply(ovl->manager)))
-+ return r;
-+
-+ return size;
-+}
-+
-+struct overlay_attribute {
-+ struct attribute attr;
-+ ssize_t (*show)(struct omap_overlay *, char *);
-+ ssize_t (*store)(struct omap_overlay *, const char *, size_t);
-+};
-+
-+#define OVERLAY_ATTR(_name, _mode, _show, _store) \
-+ struct overlay_attribute overlay_attr_##_name = \
-+ __ATTR(_name, _mode, _show, _store)
-+
-+static OVERLAY_ATTR(name, S_IRUGO, overlay_name_show, NULL);
-+static OVERLAY_ATTR(manager, S_IRUGO|S_IWUSR,
-+ overlay_manager_show, overlay_manager_store);
-+static OVERLAY_ATTR(input_size, S_IRUGO, overlay_input_size_show, NULL);
-+static OVERLAY_ATTR(screen_width, S_IRUGO, overlay_screen_width_show, NULL);
-+static OVERLAY_ATTR(position, S_IRUGO|S_IWUSR,
-+ overlay_position_show, overlay_position_store);
-+static OVERLAY_ATTR(output_size, S_IRUGO|S_IWUSR,
-+ overlay_output_size_show, overlay_output_size_store);
-+static OVERLAY_ATTR(enabled, S_IRUGO|S_IWUSR,
-+ overlay_enabled_show, overlay_enabled_store);
-+
-+static struct attribute *overlay_sysfs_attrs[] = {
-+ &overlay_attr_name.attr,
-+ &overlay_attr_manager.attr,
-+ &overlay_attr_input_size.attr,
-+ &overlay_attr_screen_width.attr,
-+ &overlay_attr_position.attr,
-+ &overlay_attr_output_size.attr,
-+ &overlay_attr_enabled.attr,
-+ NULL
-+};
-+
-+static ssize_t overlay_attr_show(struct kobject *kobj, struct attribute *attr, char *buf)
-+{
-+ struct omap_overlay *overlay;
-+ struct overlay_attribute *overlay_attr;
-+
-+ overlay = container_of(kobj, struct omap_overlay, kobj);
-+ overlay_attr = container_of(attr, struct overlay_attribute, attr);
-+
-+ if (!overlay_attr->show)
-+ return -ENOENT;
-+
-+ return overlay_attr->show(overlay, buf);
-+}
-+
-+static ssize_t overlay_attr_store(struct kobject *kobj, struct attribute *attr,
-+ const char *buf, size_t size)
-+{
-+ struct omap_overlay *overlay;
-+ struct overlay_attribute *overlay_attr;
-+
-+ overlay = container_of(kobj, struct omap_overlay, kobj);
-+ overlay_attr = container_of(attr, struct overlay_attribute, attr);
-+
-+ if (!overlay_attr->store)
-+ return -ENOENT;
-+
-+ return overlay_attr->store(overlay, buf, size);
-+}
-+
-+static struct sysfs_ops overlay_sysfs_ops = {
-+ .show = overlay_attr_show,
-+ .store = overlay_attr_store,
-+};
-+
-+static struct kobj_type overlay_ktype = {
-+ .sysfs_ops = &overlay_sysfs_ops,
-+ .default_attrs = overlay_sysfs_attrs,
-+};
-+
-+/* Check if overlay parameters are compatible with display */
-+int dss_check_overlay(struct omap_overlay *ovl, struct omap_display *display)
-+{
-+ struct omap_overlay_info *info;
-+ u16 outw, outh;
-+ u16 dw, dh;
-+
-+ if (!display)
-+ return 0;
-+
-+ if (!ovl->info.enabled)
-+ return 0;
-+
-+ info = &ovl->info;
-+
-+ display->get_resolution(display, &dw, &dh);
-+
-+ DSSDBG("check_overlay %d: (%d,%d %dx%d -> %dx%d) disp (%dx%d)\n",
-+ ovl->id,
-+ info->pos_x, info->pos_y,
-+ info->width, info->height,
-+ info->out_width, info->out_height,
-+ dw, dh);
-+
-+ if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) {
-+ outw = info->width;
-+ outh = info->height;
-+ } else {
-+ if (info->out_width == 0)
-+ outw = info->width;
-+ else
-+ outw = info->out_width;
-+
-+ if (info->out_height == 0)
-+ outh = info->height;
-+ else
-+ outh = info->out_height;
-+ }
-+
-+ if (dw < info->pos_x + outw) {
-+ DSSDBG("check_overlay failed 1: %d < %d + %d\n",
-+ dw, info->pos_x, outw);
-+ return -EINVAL;
-+ }
-+
-+ if (dh < info->pos_y + outh) {
-+ DSSDBG("check_overlay failed 2: %d < %d + %d\n",
-+ dh, info->pos_y, outh);
-+ return -EINVAL;
-+ }
-+
-+ if ((ovl->supported_modes & info->color_mode) == 0) {
-+ DSSERR("overlay doesn't support mode %d\n", info->color_mode);
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+static int dss_ovl_set_overlay_info(struct omap_overlay *ovl,
-+ struct omap_overlay_info *info)
-+{
-+ int r;
-+ struct omap_overlay_info old_info;
-+
-+ old_info = ovl->info;
-+ ovl->info = *info;
-+
-+ if (ovl->manager) {
-+ r = dss_check_overlay(ovl, ovl->manager->display);
-+ if (r) {
-+ ovl->info = old_info;
-+ return r;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static void dss_ovl_get_overlay_info(struct omap_overlay *ovl,
-+ struct omap_overlay_info *info)
-+{
-+ *info = ovl->info;
-+}
-+
-+static int omap_dss_set_manager(struct omap_overlay *ovl,
-+ struct omap_overlay_manager *mgr)
-+{
-+ int r;
-+
-+ if (ovl->manager) {
-+ DSSERR("overlay '%s' already has a manager '%s'\n",
-+ ovl->name, ovl->manager->name);
-+ }
-+
-+ r = dss_check_overlay(ovl, mgr->display);
-+ if (r)
-+ return r;
-+
-+ ovl->manager = mgr;
-+
-+ return 0;
-+}
-+
-+static int omap_dss_unset_manager(struct omap_overlay *ovl)
-+{
-+ if (!ovl->manager) {
-+ DSSERR("failed to detach overlay: manager not set\n");
-+ return -EINVAL;
-+ }
-+
-+ ovl->manager = NULL;
-+
-+ return 0;
-+}
-+
-+int omap_dss_get_num_overlays(void)
-+{
-+ return num_overlays;
-+}
-+EXPORT_SYMBOL(omap_dss_get_num_overlays);
-+
-+struct omap_overlay *omap_dss_get_overlay(int num)
-+{
-+ int i = 0;
-+ struct omap_overlay *ovl;
-+
-+ list_for_each_entry(ovl, &overlay_list, list) {
-+ if (i++ == num)
-+ return ovl;
-+ }
-+
-+ return NULL;
-+}
-+EXPORT_SYMBOL(omap_dss_get_overlay);
-+
-+static void omap_dss_add_overlay(struct omap_overlay *overlay)
-+{
-+ ++num_overlays;
-+ list_add_tail(&overlay->list, &overlay_list);
-+}
-+
-+static struct omap_overlay *dispc_overlays[3];
-+
-+void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr)
-+{
-+ mgr->num_overlays = 3;
-+ mgr->overlays = dispc_overlays;
-+}
-+
-+void dss_init_overlays(struct platform_device *pdev, const char *def_disp_name)
-+{
-+ int i, r;
-+ struct omap_overlay_manager *lcd_mgr;
-+ struct omap_overlay_manager *tv_mgr;
-+ struct omap_overlay_manager *def_mgr = NULL;
-+
-+ INIT_LIST_HEAD(&overlay_list);
-+
-+ num_overlays = 0;
-+
-+ for (i = 0; i < 3; ++i) {
-+ struct omap_overlay *ovl;
-+ ovl = kzalloc(sizeof(*ovl), GFP_KERNEL);
-+
-+ BUG_ON(ovl == NULL);
-+
-+ switch (i) {
-+ case 0:
-+ ovl->name = "gfx";
-+ ovl->id = OMAP_DSS_GFX;
-+ ovl->supported_modes = OMAP_DSS_COLOR_GFX_OMAP3;
-+ ovl->caps = OMAP_DSS_OVL_CAP_DISPC;
-+ break;
-+ case 1:
-+ ovl->name = "vid1";
-+ ovl->id = OMAP_DSS_VIDEO1;
-+ ovl->supported_modes = OMAP_DSS_COLOR_VID_OMAP3;
-+ ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
-+ OMAP_DSS_OVL_CAP_DISPC;
-+ break;
-+ case 2:
-+ ovl->name = "vid2";
-+ ovl->id = OMAP_DSS_VIDEO2;
-+ ovl->supported_modes = OMAP_DSS_COLOR_VID_OMAP3;
-+ ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
-+ OMAP_DSS_OVL_CAP_DISPC;
-+ break;
-+ }
-+
-+ ovl->set_manager = &omap_dss_set_manager;
-+ ovl->unset_manager = &omap_dss_unset_manager;
-+ ovl->set_overlay_info = &dss_ovl_set_overlay_info;
-+ ovl->get_overlay_info = &dss_ovl_get_overlay_info;
-+
-+ omap_dss_add_overlay(ovl);
-+
-+ r = kobject_init_and_add(&ovl->kobj, &overlay_ktype,
-+ &pdev->dev.kobj, "overlay%d", i);
-+
-+ if (r) {
-+ DSSERR("failed to create sysfs file\n");
-+ continue;
-+ }
-+
-+ dispc_overlays[i] = ovl;
-+ }
-+
-+ lcd_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_LCD);
-+ tv_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_TV);
-+
-+ if (def_disp_name) {
-+ for (i = 0; i < omap_dss_get_num_displays() ; i++) {
-+ struct omap_display *display = dss_get_display(i);
-+
-+ if (strcmp(display->name, def_disp_name) == 0) {
-+ if (display->type != OMAP_DISPLAY_TYPE_VENC) {
-+ lcd_mgr->set_display(lcd_mgr, display);
-+ def_mgr = lcd_mgr;
-+ } else {
-+ lcd_mgr->set_display(tv_mgr, display);
-+ def_mgr = tv_mgr;
-+ }
-+
-+ break;
-+ }
-+ }
-+
-+ if (!def_mgr)
-+ DSSWARN("default display %s not found\n",
-+ def_disp_name);
-+ }
-+
-+ if (def_mgr != lcd_mgr) {
-+ /* connect lcd manager to first non-VENC display found */
-+ for (i = 0; i < omap_dss_get_num_displays(); i++) {
-+ struct omap_display *display = dss_get_display(i);
-+ if (display->type != OMAP_DISPLAY_TYPE_VENC) {
-+ lcd_mgr->set_display(lcd_mgr, display);
-+
-+ if (!def_mgr)
-+ def_mgr = lcd_mgr;
-+
-+ break;
-+ }
-+ }
-+ }
-+
-+ if (def_mgr != tv_mgr) {
-+ /* connect tv manager to first VENC display found */
-+ for (i = 0; i < omap_dss_get_num_displays(); i++) {
-+ struct omap_display *display = dss_get_display(i);
-+ if (display->type == OMAP_DISPLAY_TYPE_VENC) {
-+ tv_mgr->set_display(tv_mgr, display);
-+
-+ if (!def_mgr)
-+ def_mgr = tv_mgr;
-+
-+ break;
-+ }
-+ }
-+ }
-+
-+ /* connect all dispc overlays to def_mgr */
-+ if (def_mgr) {
-+ for (i = 0; i < 3; i++) {
-+ struct omap_overlay *ovl;
-+ ovl = omap_dss_get_overlay(i);
-+ omap_dss_set_manager(ovl, def_mgr);
-+ }
-+ }
-+
-+#ifdef L4_EXAMPLE
-+ /* setup L4 overlay as an example */
-+ {
-+ static struct omap_overlay ovl = {
-+ .name = "l4-ovl",
-+ .supported_modes = OMAP_DSS_COLOR_RGB24U,
-+ .set_manager = &omap_dss_set_manager,
-+ .unset_manager = &omap_dss_unset_manager,
-+ .setup_input = &omap_dss_setup_overlay_input,
-+ .setup_output = &omap_dss_setup_overlay_output,
-+ .enable = &omap_dss_enable_overlay,
-+ };
-+
-+ static struct omap_overlay_manager mgr = {
-+ .name = "l4",
-+ .num_overlays = 1,
-+ .overlays = &ovl,
-+ .set_display = &omap_dss_set_display,
-+ .unset_display = &omap_dss_unset_display,
-+ .apply = &ovl_mgr_apply_l4,
-+ .supported_displays =
-+ OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
-+ };
-+
-+ omap_dss_add_overlay(&ovl);
-+ omap_dss_add_overlay_manager(&mgr);
-+ omap_dss_set_manager(&ovl, &mgr);
-+ }
-+#endif
-+}
-+
-+void dss_uninit_overlays(struct platform_device *pdev)
-+{
-+ struct omap_overlay *ovl;
-+
-+ while (!list_empty(&overlay_list)) {
-+ ovl = list_first_entry(&overlay_list,
-+ struct omap_overlay, list);
-+ list_del(&ovl->list);
-+ kobject_del(&ovl->kobj);
-+ kobject_put(&ovl->kobj);
-+ kfree(ovl);
-+ }
-+
-+ num_overlays = 0;
-+}
-+
-diff --git a/drivers/video/omap2/dss/rfbi.c b/drivers/video/omap2/dss/rfbi.c
-new file mode 100644
-index 0000000..3e9ae1e
---- /dev/null
-+++ b/drivers/video/omap2/dss/rfbi.c
-@@ -0,0 +1,1304 @@
-+/*
-+ * linux/drivers/video/omap2/dss/rfbi.c
-+ *
-+ * Copyright (C) 2009 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * Some code and ideas taken from drivers/video/omap/ driver
-+ * by Imre Deak.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#define DSS_SUBSYS_NAME "RFBI"
-+
-+#include <linux/kernel.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/vmalloc.h>
-+#include <linux/clk.h>
-+#include <linux/io.h>
-+#include <linux/delay.h>
-+#include <linux/kfifo.h>
-+#include <linux/ktime.h>
-+#include <linux/hrtimer.h>
-+#include <linux/seq_file.h>
-+
-+#include <mach/board.h>
-+#include <mach/display.h>
-+#include "dss.h"
-+
-+/*#define MEASURE_PERF*/
-+
-+#define RFBI_BASE 0x48050800
-+
-+struct rfbi_reg { u16 idx; };
-+
-+#define RFBI_REG(idx) ((const struct rfbi_reg) { idx })
-+
-+#define RFBI_REVISION RFBI_REG(0x0000)
-+#define RFBI_SYSCONFIG RFBI_REG(0x0010)
-+#define RFBI_SYSSTATUS RFBI_REG(0x0014)
-+#define RFBI_CONTROL RFBI_REG(0x0040)
-+#define RFBI_PIXEL_CNT RFBI_REG(0x0044)
-+#define RFBI_LINE_NUMBER RFBI_REG(0x0048)
-+#define RFBI_CMD RFBI_REG(0x004c)
-+#define RFBI_PARAM RFBI_REG(0x0050)
-+#define RFBI_DATA RFBI_REG(0x0054)
-+#define RFBI_READ RFBI_REG(0x0058)
-+#define RFBI_STATUS RFBI_REG(0x005c)
-+
-+#define RFBI_CONFIG(n) RFBI_REG(0x0060 + (n)*0x18)
-+#define RFBI_ONOFF_TIME(n) RFBI_REG(0x0064 + (n)*0x18)
-+#define RFBI_CYCLE_TIME(n) RFBI_REG(0x0068 + (n)*0x18)
-+#define RFBI_DATA_CYCLE1(n) RFBI_REG(0x006c + (n)*0x18)
-+#define RFBI_DATA_CYCLE2(n) RFBI_REG(0x0070 + (n)*0x18)
-+#define RFBI_DATA_CYCLE3(n) RFBI_REG(0x0074 + (n)*0x18)
-+
-+#define RFBI_VSYNC_WIDTH RFBI_REG(0x0090)
-+#define RFBI_HSYNC_WIDTH RFBI_REG(0x0094)
-+
-+#define RFBI_CMD_FIFO_LEN_BYTES (16 * sizeof(struct update_param))
-+
-+#define REG_FLD_MOD(idx, val, start, end) \
-+ rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end))
-+
-+/* To work around an RFBI transfer rate limitation */
-+#define OMAP_RFBI_RATE_LIMIT 1
-+
-+enum omap_rfbi_cycleformat {
-+ OMAP_DSS_RFBI_CYCLEFORMAT_1_1 = 0,
-+ OMAP_DSS_RFBI_CYCLEFORMAT_2_1 = 1,
-+ OMAP_DSS_RFBI_CYCLEFORMAT_3_1 = 2,
-+ OMAP_DSS_RFBI_CYCLEFORMAT_3_2 = 3,
-+};
-+
-+enum omap_rfbi_datatype {
-+ OMAP_DSS_RFBI_DATATYPE_12 = 0,
-+ OMAP_DSS_RFBI_DATATYPE_16 = 1,
-+ OMAP_DSS_RFBI_DATATYPE_18 = 2,
-+ OMAP_DSS_RFBI_DATATYPE_24 = 3,
-+};
-+
-+enum omap_rfbi_parallelmode {
-+ OMAP_DSS_RFBI_PARALLELMODE_8 = 0,
-+ OMAP_DSS_RFBI_PARALLELMODE_9 = 1,
-+ OMAP_DSS_RFBI_PARALLELMODE_12 = 2,
-+ OMAP_DSS_RFBI_PARALLELMODE_16 = 3,
-+};
-+
-+enum update_cmd {
-+ RFBI_CMD_UPDATE = 0,
-+ RFBI_CMD_SYNC = 1,
-+};
-+
-+static int rfbi_convert_timings(struct rfbi_timings *t);
-+static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div);
-+static void process_cmd_fifo(void);
-+
-+static struct {
-+ void __iomem *base;
-+
-+ unsigned long l4_khz;
-+
-+ enum omap_rfbi_datatype datatype;
-+ enum omap_rfbi_parallelmode parallelmode;
-+
-+ enum omap_rfbi_te_mode te_mode;
-+ int te_enabled;
-+
-+ void (*framedone_callback)(void *data);
-+ void *framedone_callback_data;
-+
-+ struct omap_display *display[2];
-+
-+ struct kfifo *cmd_fifo;
-+ spinlock_t cmd_lock;
-+ struct completion cmd_done;
-+ atomic_t cmd_fifo_full;
-+ atomic_t cmd_pending;
-+#ifdef MEASURE_PERF
-+ unsigned perf_bytes;
-+ ktime_t perf_setup_time;
-+ ktime_t perf_start_time;
-+#endif
-+} rfbi;
-+
-+struct update_region {
-+ u16 x;
-+ u16 y;
-+ u16 w;
-+ u16 h;
-+};
-+
-+struct update_param {
-+ u8 rfbi_module;
-+ u8 cmd;
-+
-+ union {
-+ struct update_region r;
-+ struct completion *sync;
-+ } par;
-+};
-+
-+static inline void rfbi_write_reg(const struct rfbi_reg idx, u32 val)
-+{
-+ __raw_writel(val, rfbi.base + idx.idx);
-+}
-+
-+static inline u32 rfbi_read_reg(const struct rfbi_reg idx)
-+{
-+ return __raw_readl(rfbi.base + idx.idx);
-+}
-+
-+static void rfbi_enable_clocks(bool enable)
-+{
-+ if (enable)
-+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+ else
-+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+}
-+
-+void omap_rfbi_write_command(const void *buf, u32 len)
-+{
-+ rfbi_enable_clocks(1);
-+ switch (rfbi.parallelmode) {
-+ case OMAP_DSS_RFBI_PARALLELMODE_8:
-+ {
-+ const u8 *b = buf;
-+ for (; len; len--)
-+ rfbi_write_reg(RFBI_CMD, *b++);
-+ break;
-+ }
-+
-+ case OMAP_DSS_RFBI_PARALLELMODE_16:
-+ {
-+ const u16 *w = buf;
-+ BUG_ON(len & 1);
-+ for (; len; len -= 2)
-+ rfbi_write_reg(RFBI_CMD, *w++);
-+ break;
-+ }
-+
-+ case OMAP_DSS_RFBI_PARALLELMODE_9:
-+ case OMAP_DSS_RFBI_PARALLELMODE_12:
-+ default:
-+ BUG();
-+ }
-+ rfbi_enable_clocks(0);
-+}
-+EXPORT_SYMBOL(omap_rfbi_write_command);
-+
-+void omap_rfbi_read_data(void *buf, u32 len)
-+{
-+ rfbi_enable_clocks(1);
-+ switch (rfbi.parallelmode) {
-+ case OMAP_DSS_RFBI_PARALLELMODE_8:
-+ {
-+ u8 *b = buf;
-+ for (; len; len--) {
-+ rfbi_write_reg(RFBI_READ, 0);
-+ *b++ = rfbi_read_reg(RFBI_READ);
-+ }
-+ break;
-+ }
-+
-+ case OMAP_DSS_RFBI_PARALLELMODE_16:
-+ {
-+ u16 *w = buf;
-+ BUG_ON(len & ~1);
-+ for (; len; len -= 2) {
-+ rfbi_write_reg(RFBI_READ, 0);
-+ *w++ = rfbi_read_reg(RFBI_READ);
-+ }
-+ break;
-+ }
-+
-+ case OMAP_DSS_RFBI_PARALLELMODE_9:
-+ case OMAP_DSS_RFBI_PARALLELMODE_12:
-+ default:
-+ BUG();
-+ }
-+ rfbi_enable_clocks(0);
-+}
-+EXPORT_SYMBOL(omap_rfbi_read_data);
-+
-+void omap_rfbi_write_data(const void *buf, u32 len)
-+{
-+ rfbi_enable_clocks(1);
-+ switch (rfbi.parallelmode) {
-+ case OMAP_DSS_RFBI_PARALLELMODE_8:
-+ {
-+ const u8 *b = buf;
-+ for (; len; len--)
-+ rfbi_write_reg(RFBI_PARAM, *b++);
-+ break;
-+ }
-+
-+ case OMAP_DSS_RFBI_PARALLELMODE_16:
-+ {
-+ const u16 *w = buf;
-+ BUG_ON(len & 1);
-+ for (; len; len -= 2)
-+ rfbi_write_reg(RFBI_PARAM, *w++);
-+ break;
-+ }
-+
-+ case OMAP_DSS_RFBI_PARALLELMODE_9:
-+ case OMAP_DSS_RFBI_PARALLELMODE_12:
-+ default:
-+ BUG();
-+
-+ }
-+ rfbi_enable_clocks(0);
-+}
-+EXPORT_SYMBOL(omap_rfbi_write_data);
-+
-+void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
-+ u16 x, u16 y,
-+ u16 w, u16 h)
-+{
-+ int start_offset = scr_width * y + x;
-+ int horiz_offset = scr_width - w;
-+ int i;
-+
-+ rfbi_enable_clocks(1);
-+
-+ if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
-+ rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
-+ const u16 __iomem *pd = buf;
-+ pd += start_offset;
-+
-+ for (; h; --h) {
-+ for (i = 0; i < w; ++i) {
-+ const u8 __iomem *b = (const u8 __iomem *)pd;
-+ rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
-+ rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
-+ ++pd;
-+ }
-+ pd += horiz_offset;
-+ }
-+ } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_24 &&
-+ rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
-+ const u32 __iomem *pd = buf;
-+ pd += start_offset;
-+
-+ for (; h; --h) {
-+ for (i = 0; i < w; ++i) {
-+ const u8 __iomem *b = (const u8 __iomem *)pd;
-+ rfbi_write_reg(RFBI_PARAM, __raw_readb(b+2));
-+ rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
-+ rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
-+ ++pd;
-+ }
-+ pd += horiz_offset;
-+ }
-+ } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
-+ rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_16) {
-+ const u16 __iomem *pd = buf;
-+ pd += start_offset;
-+
-+ for (; h; --h) {
-+ for (i = 0; i < w; ++i) {
-+ rfbi_write_reg(RFBI_PARAM, __raw_readw(pd));
-+ ++pd;
-+ }
-+ pd += horiz_offset;
-+ }
-+ } else {
-+ BUG();
-+ }
-+
-+ rfbi_enable_clocks(0);
-+}
-+EXPORT_SYMBOL(omap_rfbi_write_pixels);
-+
-+#ifdef MEASURE_PERF
-+static void perf_mark_setup(void)
-+{
-+ rfbi.perf_setup_time = ktime_get();
-+}
-+
-+static void perf_mark_start(void)
-+{
-+ rfbi.perf_start_time = ktime_get();
-+}
-+
-+static void perf_show(const char *name)
-+{
-+ ktime_t t, setup_time, trans_time;
-+ u32 total_bytes;
-+ u32 setup_us, trans_us, total_us;
-+
-+ t = ktime_get();
-+
-+ setup_time = ktime_sub(rfbi.perf_start_time, rfbi.perf_setup_time);
-+ setup_us = (u32)ktime_to_us(setup_time);
-+ if (setup_us == 0)
-+ setup_us = 1;
-+
-+ trans_time = ktime_sub(t, rfbi.perf_start_time);
-+ trans_us = (u32)ktime_to_us(trans_time);
-+ if (trans_us == 0)
-+ trans_us = 1;
-+
-+ total_us = setup_us + trans_us;
-+
-+ total_bytes = rfbi.perf_bytes;
-+
-+ DSSINFO("%s update %u us + %u us = %u us (%uHz), %u bytes, "
-+ "%u kbytes/sec\n",
-+ name,
-+ setup_us,
-+ trans_us,
-+ total_us,
-+ 1000*1000 / total_us,
-+ total_bytes,
-+ total_bytes * 1000 / total_us);
-+}
-+#else
-+#define perf_mark_setup()
-+#define perf_mark_start()
-+#define perf_show(x)
-+#endif
-+
-+void rfbi_transfer_area(u16 width, u16 height,
-+ void (callback)(void *data), void *data)
-+{
-+ u32 l;
-+
-+ /*BUG_ON(callback == 0);*/
-+ BUG_ON(rfbi.framedone_callback != NULL);
-+
-+ DSSDBG("rfbi_transfer_area %dx%d\n", width, height);
-+
-+ dispc_set_lcd_size(width, height);
-+
-+ dispc_enable_lcd_out(1);
-+
-+ rfbi.framedone_callback = callback;
-+ rfbi.framedone_callback_data = data;
-+
-+ rfbi_enable_clocks(1);
-+
-+ rfbi_write_reg(RFBI_PIXEL_CNT, width * height);
-+
-+ l = rfbi_read_reg(RFBI_CONTROL);
-+ l = FLD_MOD(l, 1, 0, 0); /* enable */
-+ if (!rfbi.te_enabled)
-+ l = FLD_MOD(l, 1, 4, 4); /* ITE */
-+
-+ perf_mark_start();
-+
-+ rfbi_write_reg(RFBI_CONTROL, l);
-+}
-+
-+static void framedone_callback(void *data, u32 mask)
-+{
-+ void (*callback)(void *data);
-+
-+ DSSDBG("FRAMEDONE\n");
-+
-+ perf_show("DISPC");
-+
-+ REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0);
-+
-+ rfbi_enable_clocks(0);
-+
-+ callback = rfbi.framedone_callback;
-+ rfbi.framedone_callback = NULL;
-+
-+ /*callback(rfbi.framedone_callback_data);*/
-+
-+ atomic_set(&rfbi.cmd_pending, 0);
-+
-+ process_cmd_fifo();
-+}
-+
-+#if 1 /* VERBOSE */
-+static void rfbi_print_timings(void)
-+{
-+ u32 l;
-+ u32 time;
-+
-+ l = rfbi_read_reg(RFBI_CONFIG(0));
-+ time = 1000000000 / rfbi.l4_khz;
-+ if (l & (1 << 4))
-+ time *= 2;
-+
-+ DSSDBG("Tick time %u ps\n", time);
-+ l = rfbi_read_reg(RFBI_ONOFF_TIME(0));
-+ DSSDBG("CSONTIME %d, CSOFFTIME %d, WEONTIME %d, WEOFFTIME %d, "
-+ "REONTIME %d, REOFFTIME %d\n",
-+ l & 0x0f, (l >> 4) & 0x3f, (l >> 10) & 0x0f, (l >> 14) & 0x3f,
-+ (l >> 20) & 0x0f, (l >> 24) & 0x3f);
-+
-+ l = rfbi_read_reg(RFBI_CYCLE_TIME(0));
-+ DSSDBG("WECYCLETIME %d, RECYCLETIME %d, CSPULSEWIDTH %d, "
-+ "ACCESSTIME %d\n",
-+ (l & 0x3f), (l >> 6) & 0x3f, (l >> 12) & 0x3f,
-+ (l >> 22) & 0x3f);
-+}
-+#else
-+static void rfbi_print_timings(void) {}
-+#endif
-+
-+
-+
-+
-+static u32 extif_clk_period;
-+
-+static inline unsigned long round_to_extif_ticks(unsigned long ps, int div)
-+{
-+ int bus_tick = extif_clk_period * div;
-+ return (ps + bus_tick - 1) / bus_tick * bus_tick;
-+}
-+
-+static int calc_reg_timing(struct rfbi_timings *t, int div)
-+{
-+ t->clk_div = div;
-+
-+ t->cs_on_time = round_to_extif_ticks(t->cs_on_time, div);
-+
-+ t->we_on_time = round_to_extif_ticks(t->we_on_time, div);
-+ t->we_off_time = round_to_extif_ticks(t->we_off_time, div);
-+ t->we_cycle_time = round_to_extif_ticks(t->we_cycle_time, div);
-+
-+ t->re_on_time = round_to_extif_ticks(t->re_on_time, div);
-+ t->re_off_time = round_to_extif_ticks(t->re_off_time, div);
-+ t->re_cycle_time = round_to_extif_ticks(t->re_cycle_time, div);
-+
-+ t->access_time = round_to_extif_ticks(t->access_time, div);
-+ t->cs_off_time = round_to_extif_ticks(t->cs_off_time, div);
-+ t->cs_pulse_width = round_to_extif_ticks(t->cs_pulse_width, div);
-+
-+ DSSDBG("[reg]cson %d csoff %d reon %d reoff %d\n",
-+ t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
-+ DSSDBG("[reg]weon %d weoff %d recyc %d wecyc %d\n",
-+ t->we_on_time, t->we_off_time, t->re_cycle_time,
-+ t->we_cycle_time);
-+ DSSDBG("[reg]rdaccess %d cspulse %d\n",
-+ t->access_time, t->cs_pulse_width);
-+
-+ return rfbi_convert_timings(t);
-+}
-+
-+static int calc_extif_timings(struct rfbi_timings *t)
-+{
-+ u32 max_clk_div;
-+ int div;
-+
-+ rfbi_get_clk_info(&extif_clk_period, &max_clk_div);
-+ for (div = 1; div <= max_clk_div; div++) {
-+ if (calc_reg_timing(t, div) == 0)
-+ break;
-+ }
-+
-+ if (div <= max_clk_div)
-+ return 0;
-+
-+ DSSERR("can't setup timings\n");
-+ return -1;
-+}
-+
-+
-+void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t)
-+{
-+ int r;
-+
-+ if (!t->converted) {
-+ r = calc_extif_timings(t);
-+ if (r < 0)
-+ DSSERR("Failed to calc timings\n");
-+ }
-+
-+ BUG_ON(!t->converted);
-+
-+ rfbi_enable_clocks(1);
-+ rfbi_write_reg(RFBI_ONOFF_TIME(rfbi_module), t->tim[0]);
-+ rfbi_write_reg(RFBI_CYCLE_TIME(rfbi_module), t->tim[1]);
-+
-+ /* TIMEGRANULARITY */
-+ REG_FLD_MOD(RFBI_CONFIG(rfbi_module),
-+ (t->tim[2] ? 1 : 0), 4, 4);
-+
-+ rfbi_print_timings();
-+ rfbi_enable_clocks(0);
-+}
-+
-+static int ps_to_rfbi_ticks(int time, int div)
-+{
-+ unsigned long tick_ps;
-+ int ret;
-+
-+ /* Calculate in picosecs to yield more exact results */
-+ tick_ps = 1000000000 / (rfbi.l4_khz) * div;
-+
-+ ret = (time + tick_ps - 1) / tick_ps;
-+
-+ return ret;
-+}
-+
-+#ifdef OMAP_RFBI_RATE_LIMIT
-+unsigned long rfbi_get_max_tx_rate(void)
-+{
-+ unsigned long l4_rate, dss1_rate;
-+ int min_l4_ticks = 0;
-+ int i;
-+
-+ /* According to TI this can't be calculated so make the
-+ * adjustments for a couple of known frequencies and warn for
-+ * others.
-+ */
-+ static const struct {
-+ unsigned long l4_clk; /* HZ */
-+ unsigned long dss1_clk; /* HZ */
-+ unsigned long min_l4_ticks;
-+ } ftab[] = {
-+ { 55, 132, 7, }, /* 7.86 MPix/s */
-+ { 110, 110, 12, }, /* 9.16 MPix/s */
-+ { 110, 132, 10, }, /* 11 Mpix/s */
-+ { 120, 120, 10, }, /* 12 Mpix/s */
-+ { 133, 133, 10, }, /* 13.3 Mpix/s */
-+ };
-+
-+ l4_rate = rfbi.l4_khz / 1000;
-+ dss1_rate = dss_clk_get_rate(DSS_CLK_FCK1) / 1000000;
-+
-+ for (i = 0; i < ARRAY_SIZE(ftab); i++) {
-+ /* Use a window instead of an exact match, to account
-+ * for different DPLL multiplier / divider pairs.
-+ */
-+ if (abs(ftab[i].l4_clk - l4_rate) < 3 &&
-+ abs(ftab[i].dss1_clk - dss1_rate) < 3) {
-+ min_l4_ticks = ftab[i].min_l4_ticks;
-+ break;
-+ }
-+ }
-+ if (i == ARRAY_SIZE(ftab)) {
-+ /* Can't be sure, return anyway the maximum not
-+ * rate-limited. This might cause a problem only for the
-+ * tearing synchronisation.
-+ */
-+ DSSERR("can't determine maximum RFBI transfer rate\n");
-+ return rfbi.l4_khz * 1000;
-+ }
-+ return rfbi.l4_khz * 1000 / min_l4_ticks;
-+}
-+#else
-+int rfbi_get_max_tx_rate(void)
-+{
-+ return rfbi.l4_khz * 1000;
-+}
-+#endif
-+
-+static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
-+{
-+ *clk_period = 1000000000 / rfbi.l4_khz;
-+ *max_clk_div = 2;
-+}
-+
-+static int rfbi_convert_timings(struct rfbi_timings *t)
-+{
-+ u32 l;
-+ int reon, reoff, weon, weoff, cson, csoff, cs_pulse;
-+ int actim, recyc, wecyc;
-+ int div = t->clk_div;
-+
-+ if (div <= 0 || div > 2)
-+ return -1;
-+
-+ /* Make sure that after conversion it still holds that:
-+ * weoff > weon, reoff > reon, recyc >= reoff, wecyc >= weoff,
-+ * csoff > cson, csoff >= max(weoff, reoff), actim > reon
-+ */
-+ weon = ps_to_rfbi_ticks(t->we_on_time, div);
-+ weoff = ps_to_rfbi_ticks(t->we_off_time, div);
-+ if (weoff <= weon)
-+ weoff = weon + 1;
-+ if (weon > 0x0f)
-+ return -1;
-+ if (weoff > 0x3f)
-+ return -1;
-+
-+ reon = ps_to_rfbi_ticks(t->re_on_time, div);
-+ reoff = ps_to_rfbi_ticks(t->re_off_time, div);
-+ if (reoff <= reon)
-+ reoff = reon + 1;
-+ if (reon > 0x0f)
-+ return -1;
-+ if (reoff > 0x3f)
-+ return -1;
-+
-+ cson = ps_to_rfbi_ticks(t->cs_on_time, div);
-+ csoff = ps_to_rfbi_ticks(t->cs_off_time, div);
-+ if (csoff <= cson)
-+ csoff = cson + 1;
-+ if (csoff < max(weoff, reoff))
-+ csoff = max(weoff, reoff);
-+ if (cson > 0x0f)
-+ return -1;
-+ if (csoff > 0x3f)
-+ return -1;
-+
-+ l = cson;
-+ l |= csoff << 4;
-+ l |= weon << 10;
-+ l |= weoff << 14;
-+ l |= reon << 20;
-+ l |= reoff << 24;
-+
-+ t->tim[0] = l;
-+
-+ actim = ps_to_rfbi_ticks(t->access_time, div);
-+ if (actim <= reon)
-+ actim = reon + 1;
-+ if (actim > 0x3f)
-+ return -1;
-+
-+ wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div);
-+ if (wecyc < weoff)
-+ wecyc = weoff;
-+ if (wecyc > 0x3f)
-+ return -1;
-+
-+ recyc = ps_to_rfbi_ticks(t->re_cycle_time, div);
-+ if (recyc < reoff)
-+ recyc = reoff;
-+ if (recyc > 0x3f)
-+ return -1;
-+
-+ cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div);
-+ if (cs_pulse > 0x3f)
-+ return -1;
-+
-+ l = wecyc;
-+ l |= recyc << 6;
-+ l |= cs_pulse << 12;
-+ l |= actim << 22;
-+
-+ t->tim[1] = l;
-+
-+ t->tim[2] = div - 1;
-+
-+ t->converted = 1;
-+
-+ return 0;
-+}
-+
-+/* xxx FIX module selection missing */
-+int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
-+ unsigned hs_pulse_time, unsigned vs_pulse_time,
-+ int hs_pol_inv, int vs_pol_inv, int extif_div)
-+{
-+ int hs, vs;
-+ int min;
-+ u32 l;
-+
-+ hs = ps_to_rfbi_ticks(hs_pulse_time, 1);
-+ vs = ps_to_rfbi_ticks(vs_pulse_time, 1);
-+ if (hs < 2)
-+ return -EDOM;
-+ if (mode == OMAP_DSS_RFBI_TE_MODE_2)
-+ min = 2;
-+ else /* OMAP_DSS_RFBI_TE_MODE_1 */
-+ min = 4;
-+ if (vs < min)
-+ return -EDOM;
-+ if (vs == hs)
-+ return -EINVAL;
-+ rfbi.te_mode = mode;
-+ DSSDBG("setup_te: mode %d hs %d vs %d hs_inv %d vs_inv %d\n",
-+ mode, hs, vs, hs_pol_inv, vs_pol_inv);
-+
-+ rfbi_enable_clocks(1);
-+ rfbi_write_reg(RFBI_HSYNC_WIDTH, hs);
-+ rfbi_write_reg(RFBI_VSYNC_WIDTH, vs);
-+
-+ l = rfbi_read_reg(RFBI_CONFIG(0));
-+ if (hs_pol_inv)
-+ l &= ~(1 << 21);
-+ else
-+ l |= 1 << 21;
-+ if (vs_pol_inv)
-+ l &= ~(1 << 20);
-+ else
-+ l |= 1 << 20;
-+ rfbi_enable_clocks(0);
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(omap_rfbi_setup_te);
-+
-+/* xxx FIX module selection missing */
-+int omap_rfbi_enable_te(bool enable, unsigned line)
-+{
-+ u32 l;
-+
-+ DSSDBG("te %d line %d mode %d\n", enable, line, rfbi.te_mode);
-+ if (line > (1 << 11) - 1)
-+ return -EINVAL;
-+
-+ rfbi_enable_clocks(1);
-+ l = rfbi_read_reg(RFBI_CONFIG(0));
-+ l &= ~(0x3 << 2);
-+ if (enable) {
-+ rfbi.te_enabled = 1;
-+ l |= rfbi.te_mode << 2;
-+ } else
-+ rfbi.te_enabled = 0;
-+ rfbi_write_reg(RFBI_CONFIG(0), l);
-+ rfbi_write_reg(RFBI_LINE_NUMBER, line);
-+ rfbi_enable_clocks(0);
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(omap_rfbi_enable_te);
-+
-+#if 0
-+static void rfbi_enable_config(int enable1, int enable2)
-+{
-+ u32 l;
-+ int cs = 0;
-+
-+ if (enable1)
-+ cs |= 1<<0;
-+ if (enable2)
-+ cs |= 1<<1;
-+
-+ rfbi_enable_clocks(1);
-+
-+ l = rfbi_read_reg(RFBI_CONTROL);
-+
-+ l = FLD_MOD(l, cs, 3, 2);
-+ l = FLD_MOD(l, 0, 1, 1);
-+
-+ rfbi_write_reg(RFBI_CONTROL, l);
-+
-+
-+ l = rfbi_read_reg(RFBI_CONFIG(0));
-+ l = FLD_MOD(l, 0, 3, 2); /* TRIGGERMODE: ITE */
-+ /*l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
-+ /*l |= FLD_VAL(0, 8, 7); */ /* L4FORMAT, 1pix/L4 */
-+
-+ l = FLD_MOD(l, 0, 16, 16); /* A0POLARITY */
-+ l = FLD_MOD(l, 1, 20, 20); /* TE_VSYNC_POLARITY */
-+ l = FLD_MOD(l, 1, 21, 21); /* HSYNCPOLARITY */
-+
-+ l = FLD_MOD(l, OMAP_DSS_RFBI_PARALLELMODE_8, 1, 0);
-+ rfbi_write_reg(RFBI_CONFIG(0), l);
-+
-+ rfbi_enable_clocks(0);
-+}
-+#endif
-+
-+int rfbi_configure(int rfbi_module, int bpp, int lines)
-+{
-+ u32 l;
-+ int cycle1 = 0, cycle2 = 0, cycle3 = 0;
-+ enum omap_rfbi_cycleformat cycleformat;
-+ enum omap_rfbi_datatype datatype;
-+ enum omap_rfbi_parallelmode parallelmode;
-+
-+ switch (bpp) {
-+ case 12:
-+ datatype = OMAP_DSS_RFBI_DATATYPE_12;
-+ break;
-+ case 16:
-+ datatype = OMAP_DSS_RFBI_DATATYPE_16;
-+ break;
-+ case 18:
-+ datatype = OMAP_DSS_RFBI_DATATYPE_18;
-+ break;
-+ case 24:
-+ datatype = OMAP_DSS_RFBI_DATATYPE_24;
-+ break;
-+ default:
-+ BUG();
-+ return 1;
-+ }
-+ rfbi.datatype = datatype;
-+
-+ switch (lines) {
-+ case 8:
-+ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_8;
-+ break;
-+ case 9:
-+ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_9;
-+ break;
-+ case 12:
-+ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_12;
-+ break;
-+ case 16:
-+ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_16;
-+ break;
-+ default:
-+ BUG();
-+ return 1;
-+ }
-+ rfbi.parallelmode = parallelmode;
-+
-+ if ((bpp % lines) == 0) {
-+ switch (bpp / lines) {
-+ case 1:
-+ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_1_1;
-+ break;
-+ case 2:
-+ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_2_1;
-+ break;
-+ case 3:
-+ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_1;
-+ break;
-+ default:
-+ BUG();
-+ return 1;
-+ }
-+ } else if ((2 * bpp % lines) == 0) {
-+ if ((2 * bpp / lines) == 3)
-+ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_2;
-+ else {
-+ BUG();
-+ return 1;
-+ }
-+ } else {
-+ BUG();
-+ return 1;
-+ }
-+
-+ switch (cycleformat) {
-+ case OMAP_DSS_RFBI_CYCLEFORMAT_1_1:
-+ cycle1 = lines;
-+ break;
-+
-+ case OMAP_DSS_RFBI_CYCLEFORMAT_2_1:
-+ cycle1 = lines;
-+ cycle2 = lines;
-+ break;
-+
-+ case OMAP_DSS_RFBI_CYCLEFORMAT_3_1:
-+ cycle1 = lines;
-+ cycle2 = lines;
-+ cycle3 = lines;
-+ break;
-+
-+ case OMAP_DSS_RFBI_CYCLEFORMAT_3_2:
-+ cycle1 = lines;
-+ cycle2 = (lines / 2) | ((lines / 2) << 16);
-+ cycle3 = (lines << 16);
-+ break;
-+ }
-+
-+ rfbi_enable_clocks(1);
-+
-+ REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */
-+
-+ l = 0;
-+ l |= FLD_VAL(parallelmode, 1, 0);
-+ l |= FLD_VAL(0, 3, 2); /* TRIGGERMODE: ITE */
-+ l |= FLD_VAL(0, 4, 4); /* TIMEGRANULARITY */
-+ l |= FLD_VAL(datatype, 6, 5);
-+ /* l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
-+ l |= FLD_VAL(0, 8, 7); /* L4FORMAT, 1pix/L4 */
-+ l |= FLD_VAL(cycleformat, 10, 9);
-+ l |= FLD_VAL(0, 12, 11); /* UNUSEDBITS */
-+ l |= FLD_VAL(0, 16, 16); /* A0POLARITY */
-+ l |= FLD_VAL(0, 17, 17); /* REPOLARITY */
-+ l |= FLD_VAL(0, 18, 18); /* WEPOLARITY */
-+ l |= FLD_VAL(0, 19, 19); /* CSPOLARITY */
-+ l |= FLD_VAL(1, 20, 20); /* TE_VSYNC_POLARITY */
-+ l |= FLD_VAL(1, 21, 21); /* HSYNCPOLARITY */
-+ rfbi_write_reg(RFBI_CONFIG(rfbi_module), l);
-+
-+ rfbi_write_reg(RFBI_DATA_CYCLE1(rfbi_module), cycle1);
-+ rfbi_write_reg(RFBI_DATA_CYCLE2(rfbi_module), cycle2);
-+ rfbi_write_reg(RFBI_DATA_CYCLE3(rfbi_module), cycle3);
-+
-+
-+ l = rfbi_read_reg(RFBI_CONTROL);
-+ l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */
-+ l = FLD_MOD(l, 0, 1, 1); /* clear bypass */
-+ rfbi_write_reg(RFBI_CONTROL, l);
-+
-+
-+ DSSDBG("RFBI config: bpp %d, lines %d, cycles: 0x%x 0x%x 0x%x\n",
-+ bpp, lines, cycle1, cycle2, cycle3);
-+
-+ rfbi_enable_clocks(0);
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(rfbi_configure);
-+
-+static int rfbi_find_display(struct omap_display *disp)
-+{
-+ if (disp == rfbi.display[0])
-+ return 0;
-+
-+ if (disp == rfbi.display[1])
-+ return 1;
-+
-+ BUG();
-+ return -1;
-+}
-+
-+
-+static void signal_fifo_waiters(void)
-+{
-+ if (atomic_read(&rfbi.cmd_fifo_full) > 0) {
-+ /* DSSDBG("SIGNALING: Fifo not full for waiter!\n"); */
-+ complete(&rfbi.cmd_done);
-+ atomic_dec(&rfbi.cmd_fifo_full);
-+ }
-+}
-+
-+/* returns 1 for async op, and 0 for sync op */
-+static int do_update(struct omap_display *display, struct update_region *upd)
-+{
-+ u16 x = upd->x;
-+ u16 y = upd->y;
-+ u16 w = upd->w;
-+ u16 h = upd->h;
-+
-+ perf_mark_setup();
-+
-+ if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
-+ /*display->ctrl->enable_te(display, 1); */
-+ dispc_setup_partial_planes(display, &x, &y, &w, &h);
-+ }
-+
-+#ifdef MEASURE_PERF
-+ rfbi.perf_bytes = w * h * 2; /* XXX always 16bit */
-+#endif
-+
-+ display->ctrl->setup_update(display, x, y, w, h);
-+
-+ if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
-+ rfbi_transfer_area(w, h, NULL, NULL);
-+ return 1;
-+ } else {
-+ struct omap_overlay *ovl;
-+ void __iomem *addr;
-+ int scr_width;
-+
-+ ovl = display->manager->overlays[0];
-+ scr_width = ovl->info.screen_width;
-+ addr = ovl->info.vaddr;
-+
-+ omap_rfbi_write_pixels(addr, scr_width, x, y, w, h);
-+
-+ perf_show("L4");
-+
-+ return 0;
-+ }
-+}
-+
-+static void process_cmd_fifo(void)
-+{
-+ int len;
-+ struct update_param p;
-+ struct omap_display *display;
-+ unsigned long flags;
-+
-+ if (atomic_inc_return(&rfbi.cmd_pending) != 1)
-+ return;
-+
-+ while (true) {
-+ spin_lock_irqsave(rfbi.cmd_fifo->lock, flags);
-+
-+ len = __kfifo_get(rfbi.cmd_fifo, (unsigned char *)&p,
-+ sizeof(struct update_param));
-+ if (len == 0) {
-+ DSSDBG("nothing more in fifo\n");
-+ atomic_set(&rfbi.cmd_pending, 0);
-+ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
-+ break;
-+ }
-+
-+ /* DSSDBG("fifo full %d\n", rfbi.cmd_fifo_full.counter);*/
-+
-+ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
-+
-+ BUG_ON(len != sizeof(struct update_param));
-+ BUG_ON(p.rfbi_module > 1);
-+
-+ display = rfbi.display[p.rfbi_module];
-+
-+ if (p.cmd == RFBI_CMD_UPDATE) {
-+ if (do_update(display, &p.par.r))
-+ break; /* async op */
-+ } else if (p.cmd == RFBI_CMD_SYNC) {
-+ DSSDBG("Signaling SYNC done!\n");
-+ complete(p.par.sync);
-+ } else
-+ BUG();
-+ }
-+
-+ signal_fifo_waiters();
-+}
-+
-+static void rfbi_push_cmd(struct update_param *p)
-+{
-+ int ret;
-+
-+ while (1) {
-+ unsigned long flags;
-+ int available;
-+
-+ spin_lock_irqsave(rfbi.cmd_fifo->lock, flags);
-+ available = RFBI_CMD_FIFO_LEN_BYTES -
-+ __kfifo_len(rfbi.cmd_fifo);
-+
-+/* DSSDBG("%d bytes left in fifo\n", available); */
-+ if (available < sizeof(struct update_param)) {
-+ DSSDBG("Going to wait because FIFO FULL..\n");
-+ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
-+ atomic_inc(&rfbi.cmd_fifo_full);
-+ wait_for_completion(&rfbi.cmd_done);
-+ /*DSSDBG("Woke up because fifo not full anymore\n");*/
-+ continue;
-+ }
-+
-+ ret = __kfifo_put(rfbi.cmd_fifo, (unsigned char *)p,
-+ sizeof(struct update_param));
-+/* DSSDBG("pushed %d bytes\n", ret);*/
-+
-+ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
-+
-+ BUG_ON(ret != sizeof(struct update_param));
-+
-+ break;
-+ }
-+}
-+
-+static void rfbi_push_update(int rfbi_module, int x, int y, int w, int h)
-+{
-+ struct update_param p;
-+
-+ p.rfbi_module = rfbi_module;
-+ p.cmd = RFBI_CMD_UPDATE;
-+
-+ p.par.r.x = x;
-+ p.par.r.y = y;
-+ p.par.r.w = w;
-+ p.par.r.h = h;
-+
-+ DSSDBG("RFBI pushed %d,%d %dx%d\n", x, y, w, h);
-+
-+ rfbi_push_cmd(&p);
-+
-+ process_cmd_fifo();
-+}
-+
-+static void rfbi_push_sync(int rfbi_module, struct completion *sync_comp)
-+{
-+ struct update_param p;
-+
-+ p.rfbi_module = rfbi_module;
-+ p.cmd = RFBI_CMD_SYNC;
-+ p.par.sync = sync_comp;
-+
-+ rfbi_push_cmd(&p);
-+
-+ DSSDBG("RFBI sync pushed to cmd fifo\n");
-+
-+ process_cmd_fifo();
-+}
-+
-+void rfbi_dump_regs(struct seq_file *s)
-+{
-+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r))
-+
-+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+
-+ DUMPREG(RFBI_REVISION);
-+ DUMPREG(RFBI_SYSCONFIG);
-+ DUMPREG(RFBI_SYSSTATUS);
-+ DUMPREG(RFBI_CONTROL);
-+ DUMPREG(RFBI_PIXEL_CNT);
-+ DUMPREG(RFBI_LINE_NUMBER);
-+ DUMPREG(RFBI_CMD);
-+ DUMPREG(RFBI_PARAM);
-+ DUMPREG(RFBI_DATA);
-+ DUMPREG(RFBI_READ);
-+ DUMPREG(RFBI_STATUS);
-+
-+ DUMPREG(RFBI_CONFIG(0));
-+ DUMPREG(RFBI_ONOFF_TIME(0));
-+ DUMPREG(RFBI_CYCLE_TIME(0));
-+ DUMPREG(RFBI_DATA_CYCLE1(0));
-+ DUMPREG(RFBI_DATA_CYCLE2(0));
-+ DUMPREG(RFBI_DATA_CYCLE3(0));
-+
-+ DUMPREG(RFBI_CONFIG(1));
-+ DUMPREG(RFBI_ONOFF_TIME(1));
-+ DUMPREG(RFBI_CYCLE_TIME(1));
-+ DUMPREG(RFBI_DATA_CYCLE1(1));
-+ DUMPREG(RFBI_DATA_CYCLE2(1));
-+ DUMPREG(RFBI_DATA_CYCLE3(1));
-+
-+ DUMPREG(RFBI_VSYNC_WIDTH);
-+ DUMPREG(RFBI_HSYNC_WIDTH);
-+
-+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+#undef DUMPREG
-+}
-+
-+int rfbi_init(void)
-+{
-+ u32 rev;
-+ u32 l;
-+
-+ spin_lock_init(&rfbi.cmd_lock);
-+ rfbi.cmd_fifo = kfifo_alloc(RFBI_CMD_FIFO_LEN_BYTES, GFP_KERNEL,
-+ &rfbi.cmd_lock);
-+ if (IS_ERR(rfbi.cmd_fifo))
-+ return -ENOMEM;
-+
-+ init_completion(&rfbi.cmd_done);
-+ atomic_set(&rfbi.cmd_fifo_full, 0);
-+ atomic_set(&rfbi.cmd_pending, 0);
-+
-+ rfbi.base = ioremap(RFBI_BASE, SZ_256);
-+ if (!rfbi.base) {
-+ DSSERR("can't ioremap RFBI\n");
-+ return -ENOMEM;
-+ }
-+
-+ rfbi_enable_clocks(1);
-+
-+ msleep(10);
-+
-+ rfbi.l4_khz = dss_clk_get_rate(DSS_CLK_ICK) / 1000;
-+
-+ /* Enable autoidle and smart-idle */
-+ l = rfbi_read_reg(RFBI_SYSCONFIG);
-+ l |= (1 << 0) | (2 << 3);
-+ rfbi_write_reg(RFBI_SYSCONFIG, l);
-+
-+ rev = rfbi_read_reg(RFBI_REVISION);
-+ printk(KERN_INFO "OMAP RFBI rev %d.%d\n",
-+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
-+
-+ rfbi_enable_clocks(0);
-+
-+ return 0;
-+}
-+
-+void rfbi_exit(void)
-+{
-+ DSSDBG("rfbi_exit\n");
-+
-+ kfifo_free(rfbi.cmd_fifo);
-+
-+ iounmap(rfbi.base);
-+}
-+
-+/* struct omap_display support */
-+static int rfbi_display_update(struct omap_display *display,
-+ u16 x, u16 y, u16 w, u16 h)
-+{
-+ int rfbi_module;
-+
-+ if (w == 0 || h == 0)
-+ return 0;
-+
-+ rfbi_module = rfbi_find_display(display);
-+
-+ rfbi_push_update(rfbi_module, x, y, w, h);
-+
-+ return 0;
-+}
-+
-+static int rfbi_display_sync(struct omap_display *display)
-+{
-+ struct completion sync_comp;
-+ int rfbi_module;
-+
-+ rfbi_module = rfbi_find_display(display);
-+
-+ init_completion(&sync_comp);
-+ rfbi_push_sync(rfbi_module, &sync_comp);
-+ DSSDBG("Waiting for SYNC to happen...\n");
-+ wait_for_completion(&sync_comp);
-+ DSSDBG("Released from SYNC\n");
-+ return 0;
-+}
-+
-+static int rfbi_display_enable_te(struct omap_display *display, bool enable)
-+{
-+ display->ctrl->enable_te(display, enable);
-+ return 0;
-+}
-+
-+static int rfbi_display_enable(struct omap_display *display)
-+{
-+ int r;
-+
-+ BUG_ON(display->panel == NULL || display->ctrl == NULL);
-+
-+ r = omap_dispc_register_isr(framedone_callback, NULL,
-+ DISPC_IRQ_FRAMEDONE);
-+ if (r) {
-+ DSSERR("can't get FRAMEDONE irq\n");
-+ return r;
-+ }
-+
-+ dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
-+
-+ dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_RFBI);
-+
-+ dispc_set_tft_data_lines(display->ctrl->pixel_size);
-+
-+ rfbi_configure(display->hw_config.u.rfbi.channel,
-+ display->ctrl->pixel_size,
-+ display->hw_config.u.rfbi.data_lines);
-+
-+ rfbi_set_timings(display->hw_config.u.rfbi.channel,
-+ &display->ctrl->timings);
-+
-+
-+ if (display->ctrl && display->ctrl->enable) {
-+ r = display->ctrl->enable(display);
-+ if (r)
-+ goto err;
-+ }
-+
-+ if (display->panel && display->panel->enable) {
-+ r = display->panel->enable(display);
-+ if (r)
-+ goto err;
-+ }
-+
-+ return 0;
-+err:
-+ return -ENODEV;
-+}
-+
-+static void rfbi_display_disable(struct omap_display *display)
-+{
-+ display->ctrl->disable(display);
-+ omap_dispc_unregister_isr(framedone_callback, NULL,
-+ DISPC_IRQ_FRAMEDONE);
-+}
-+
-+void rfbi_init_display(struct omap_display *display)
-+{
-+ display->enable = rfbi_display_enable;
-+ display->disable = rfbi_display_disable;
-+ display->update = rfbi_display_update;
-+ display->sync = rfbi_display_sync;
-+ display->enable_te = rfbi_display_enable_te;
-+
-+ rfbi.display[display->hw_config.u.rfbi.channel] = display;
-+
-+ display->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
-+}
-diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c
-new file mode 100644
-index 0000000..fbff2b2
---- /dev/null
-+++ b/drivers/video/omap2/dss/sdi.c
-@@ -0,0 +1,245 @@
-+/*
-+ * linux/drivers/video/omap2/dss/sdi.c
-+ *
-+ * Copyright (C) 2009 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#define DSS_SUBSYS_NAME "SDI"
-+
-+#include <linux/kernel.h>
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+
-+#include <mach/board.h>
-+#include <mach/display.h>
-+#include "dss.h"
-+
-+
-+static struct {
-+ bool skip_init;
-+ bool update_enabled;
-+} sdi;
-+
-+static void sdi_basic_init(void)
-+{
-+ dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS);
-+
-+ dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
-+ dispc_set_tft_data_lines(24);
-+ dispc_lcd_enable_signal_polarity(1);
-+}
-+
-+static int sdi_display_enable(struct omap_display *display)
-+{
-+ struct dispc_clock_info cinfo;
-+ u16 lck_div, pck_div;
-+ unsigned long fck;
-+ struct omap_panel *panel = display->panel;
-+ unsigned long pck;
-+ int r;
-+
-+ if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
-+ DSSERR("display already enabled\n");
-+ return -EINVAL;
-+ }
-+
-+ /* In case of skip_init sdi_init has already enabled the clocks */
-+ if (!sdi.skip_init)
-+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+
-+ sdi_basic_init();
-+
-+ /* 15.5.9.1.2 */
-+ panel->config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF;
-+
-+ dispc_set_pol_freq(panel);
-+
-+ if (!sdi.skip_init)
-+ r = dispc_calc_clock_div(1, panel->timings.pixel_clock * 1000,
-+ &cinfo);
-+ else
-+ r = dispc_get_clock_div(&cinfo);
-+
-+ if (r)
-+ goto err0;
-+
-+ fck = cinfo.fck;
-+ lck_div = cinfo.lck_div;
-+ pck_div = cinfo.pck_div;
-+
-+ pck = fck / lck_div / pck_div / 1000;
-+
-+ if (pck != panel->timings.pixel_clock) {
-+ DSSWARN("Could not find exact pixel clock. Requested %d kHz, "
-+ "got %lu kHz\n",
-+ panel->timings.pixel_clock, pck);
-+
-+ panel->timings.pixel_clock = pck;
-+ }
-+
-+
-+ dispc_set_lcd_timings(&panel->timings);
-+
-+ r = dispc_set_clock_div(&cinfo);
-+ if (r)
-+ goto err1;
-+
-+ if (!sdi.skip_init) {
-+ dss_sdi_init(display->hw_config.u.sdi.datapairs);
-+ dss_sdi_enable();
-+ mdelay(2);
-+ }
-+
-+ dispc_enable_lcd_out(1);
-+
-+ r = panel->enable(display);
-+ if (r)
-+ goto err2;
-+
-+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
-+
-+ sdi.skip_init = 0;
-+
-+ return 0;
-+err2:
-+ dispc_enable_lcd_out(0);
-+err1:
-+err0:
-+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+ return r;
-+}
-+
-+static int sdi_display_resume(struct omap_display *display);
-+
-+static void sdi_display_disable(struct omap_display *display)
-+{
-+ if (display->state == OMAP_DSS_DISPLAY_DISABLED)
-+ return;
-+
-+ if (display->state == OMAP_DSS_DISPLAY_SUSPENDED)
-+ sdi_display_resume(display);
-+
-+ display->panel->disable(display);
-+
-+ dispc_enable_lcd_out(0);
-+
-+ dss_sdi_disable();
-+
-+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+
-+ display->state = OMAP_DSS_DISPLAY_DISABLED;
-+}
-+
-+static int sdi_display_suspend(struct omap_display *display)
-+{
-+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
-+ return -EINVAL;
-+
-+ if (display->panel->suspend)
-+ display->panel->suspend(display);
-+
-+ dispc_enable_lcd_out(0);
-+
-+ dss_sdi_disable();
-+
-+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+
-+ display->state = OMAP_DSS_DISPLAY_SUSPENDED;
-+
-+ return 0;
-+}
-+
-+static int sdi_display_resume(struct omap_display *display)
-+{
-+ if (display->state != OMAP_DSS_DISPLAY_SUSPENDED)
-+ return -EINVAL;
-+
-+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+
-+ dss_sdi_enable();
-+ mdelay(2);
-+
-+ dispc_enable_lcd_out(1);
-+
-+ if (display->panel->resume)
-+ display->panel->resume(display);
-+
-+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
-+
-+ return 0;
-+}
-+
-+static int sdi_display_set_update_mode(struct omap_display *display,
-+ enum omap_dss_update_mode mode)
-+{
-+ if (mode == OMAP_DSS_UPDATE_MANUAL)
-+ return -EINVAL;
-+
-+ if (mode == OMAP_DSS_UPDATE_DISABLED) {
-+ dispc_enable_lcd_out(0);
-+ sdi.update_enabled = 0;
-+ } else {
-+ dispc_enable_lcd_out(1);
-+ sdi.update_enabled = 1;
-+ }
-+
-+ return 0;
-+}
-+
-+static enum omap_dss_update_mode sdi_display_get_update_mode(
-+ struct omap_display *display)
-+{
-+ return sdi.update_enabled ? OMAP_DSS_UPDATE_AUTO :
-+ OMAP_DSS_UPDATE_DISABLED;
-+}
-+
-+static void sdi_get_timings(struct omap_display *display,
-+ struct omap_video_timings *timings)
-+{
-+ *timings = display->panel->timings;
-+}
-+
-+void sdi_init_display(struct omap_display *display)
-+{
-+ DSSDBG("SDI init\n");
-+
-+ display->enable = sdi_display_enable;
-+ display->disable = sdi_display_disable;
-+ display->suspend = sdi_display_suspend;
-+ display->resume = sdi_display_resume;
-+ display->set_update_mode = sdi_display_set_update_mode;
-+ display->get_update_mode = sdi_display_get_update_mode;
-+ display->get_timings = sdi_get_timings;
-+}
-+
-+int sdi_init(bool skip_init)
-+{
-+ /* we store this for first display enable, then clear it */
-+ sdi.skip_init = skip_init;
-+
-+ /*
-+ * Enable clocks already here, otherwise there would be a toggle
-+ * of them until sdi_display_enable is called.
-+ */
-+ if (skip_init)
-+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
-+ return 0;
-+}
-+
-+void sdi_exit(void)
-+{
-+}
-diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c
-new file mode 100644
-index 0000000..aceed9f
---- /dev/null
-+++ b/drivers/video/omap2/dss/venc.c
-@@ -0,0 +1,600 @@
-+/*
-+ * linux/drivers/video/omap2/dss/venc.c
-+ *
-+ * Copyright (C) 2009 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * VENC settings from TI's DSS driver
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#define DSS_SUBSYS_NAME "VENC"
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/mutex.h>
-+#include <linux/completion.h>
-+#include <linux/delay.h>
-+#include <linux/string.h>
-+
-+#include <mach/display.h>
-+#include <mach/cpu.h>
-+
-+#include "dss.h"
-+
-+#define VENC_BASE 0x48050C00
-+
-+/* Venc registers */
-+#define VENC_REV_ID 0x00
-+#define VENC_STATUS 0x04
-+#define VENC_F_CONTROL 0x08
-+#define VENC_VIDOUT_CTRL 0x10
-+#define VENC_SYNC_CTRL 0x14
-+#define VENC_LLEN 0x1C
-+#define VENC_FLENS 0x20
-+#define VENC_HFLTR_CTRL 0x24
-+#define VENC_CC_CARR_WSS_CARR 0x28
-+#define VENC_C_PHASE 0x2C
-+#define VENC_GAIN_U 0x30
-+#define VENC_GAIN_V 0x34
-+#define VENC_GAIN_Y 0x38
-+#define VENC_BLACK_LEVEL 0x3C
-+#define VENC_BLANK_LEVEL 0x40
-+#define VENC_X_COLOR 0x44
-+#define VENC_M_CONTROL 0x48
-+#define VENC_BSTAMP_WSS_DATA 0x4C
-+#define VENC_S_CARR 0x50
-+#define VENC_LINE21 0x54
-+#define VENC_LN_SEL 0x58
-+#define VENC_L21__WC_CTL 0x5C
-+#define VENC_HTRIGGER_VTRIGGER 0x60
-+#define VENC_SAVID__EAVID 0x64
-+#define VENC_FLEN__FAL 0x68
-+#define VENC_LAL__PHASE_RESET 0x6C
-+#define VENC_HS_INT_START_STOP_X 0x70
-+#define VENC_HS_EXT_START_STOP_X 0x74
-+#define VENC_VS_INT_START_X 0x78
-+#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
-+#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
-+#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
-+#define VENC_VS_EXT_STOP_Y 0x88
-+#define VENC_AVID_START_STOP_X 0x90
-+#define VENC_AVID_START_STOP_Y 0x94
-+#define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
-+#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
-+#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
-+#define VENC_TVDETGP_INT_START_STOP_X 0xB0
-+#define VENC_TVDETGP_INT_START_STOP_Y 0xB4
-+#define VENC_GEN_CTRL 0xB8
-+#define VENC_OUTPUT_CONTROL 0xC4
-+#define VENC_DAC_B__DAC_C 0xC8
-+
-+struct venc_config {
-+ u32 f_control;
-+ u32 vidout_ctrl;
-+ u32 sync_ctrl;
-+ u32 llen;
-+ u32 flens;
-+ u32 hfltr_ctrl;
-+ u32 cc_carr_wss_carr;
-+ u32 c_phase;
-+ u32 gain_u;
-+ u32 gain_v;
-+ u32 gain_y;
-+ u32 black_level;
-+ u32 blank_level;
-+ u32 x_color;
-+ u32 m_control;
-+ u32 bstamp_wss_data;
-+ u32 s_carr;
-+ u32 line21;
-+ u32 ln_sel;
-+ u32 l21__wc_ctl;
-+ u32 htrigger_vtrigger;
-+ u32 savid__eavid;
-+ u32 flen__fal;
-+ u32 lal__phase_reset;
-+ u32 hs_int_start_stop_x;
-+ u32 hs_ext_start_stop_x;
-+ u32 vs_int_start_x;
-+ u32 vs_int_stop_x__vs_int_start_y;
-+ u32 vs_int_stop_y__vs_ext_start_x;
-+ u32 vs_ext_stop_x__vs_ext_start_y;
-+ u32 vs_ext_stop_y;
-+ u32 avid_start_stop_x;
-+ u32 avid_start_stop_y;
-+ u32 fid_int_start_x__fid_int_start_y;
-+ u32 fid_int_offset_y__fid_ext_start_x;
-+ u32 fid_ext_start_y__fid_ext_offset_y;
-+ u32 tvdetgp_int_start_stop_x;
-+ u32 tvdetgp_int_start_stop_y;
-+ u32 gen_ctrl;
-+};
-+
-+/* from TRM */
-+static const struct venc_config venc_config_pal_trm = {
-+ .f_control = 0,
-+ .vidout_ctrl = 1,
-+ .sync_ctrl = 0x40,
-+ .llen = 0x35F, /* 863 */
-+ .flens = 0x270, /* 624 */
-+ .hfltr_ctrl = 0,
-+ .cc_carr_wss_carr = 0x2F7225ED,
-+ .c_phase = 0,
-+ .gain_u = 0x111,
-+ .gain_v = 0x181,
-+ .gain_y = 0x140,
-+ .black_level = 0x3B,
-+ .blank_level = 0x3B,
-+ .x_color = 0x7,
-+ .m_control = 0x2,
-+ .bstamp_wss_data = 0x3F,
-+ .s_carr = 0x2A098ACB,
-+ .line21 = 0,
-+ .ln_sel = 0x01290015,
-+ .l21__wc_ctl = 0x0000F603,
-+ .htrigger_vtrigger = 0,
-+
-+ .savid__eavid = 0x06A70108,
-+ .flen__fal = 0x00180270,
-+ .lal__phase_reset = 0x00040135,
-+ .hs_int_start_stop_x = 0x00880358,
-+ .hs_ext_start_stop_x = 0x000F035F,
-+ .vs_int_start_x = 0x01A70000,
-+ .vs_int_stop_x__vs_int_start_y = 0x000001A7,
-+ .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
-+ .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
-+ .vs_ext_stop_y = 0x00000025,
-+ .avid_start_stop_x = 0x03530083,
-+ .avid_start_stop_y = 0x026C002E,
-+ .fid_int_start_x__fid_int_start_y = 0x0001008A,
-+ .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
-+ .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
-+
-+ .tvdetgp_int_start_stop_x = 0x00140001,
-+ .tvdetgp_int_start_stop_y = 0x00010001,
-+ .gen_ctrl = 0x00FF0000,
-+};
-+
-+/* from TRM */
-+static const struct venc_config venc_config_ntsc_trm = {
-+ .f_control = 0,
-+ .vidout_ctrl = 1,
-+ .sync_ctrl = 0x8040,
-+ .llen = 0x359,
-+ .flens = 0x20C,
-+ .hfltr_ctrl = 0,
-+ .cc_carr_wss_carr = 0x043F2631,
-+ .c_phase = 0,
-+ .gain_u = 0x102,
-+ .gain_v = 0x16C,
-+ .gain_y = 0x12F,
-+ .black_level = 0x43,
-+ .blank_level = 0x38,
-+ .x_color = 0x7,
-+ .m_control = 0x1,
-+ .bstamp_wss_data = 0x38,
-+ .s_carr = 0x21F07C1F,
-+ .line21 = 0,
-+ .ln_sel = 0x01310011,
-+ .l21__wc_ctl = 0x0000F003,
-+ .htrigger_vtrigger = 0,
-+
-+ .savid__eavid = 0x069300F4,
-+ .flen__fal = 0x0016020C,
-+ .lal__phase_reset = 0x00060107,
-+ .hs_int_start_stop_x = 0x008E0350,
-+ .hs_ext_start_stop_x = 0x000F0359,
-+ .vs_int_start_x = 0x01A00000,
-+ .vs_int_stop_x__vs_int_start_y = 0x020701A0,
-+ .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
-+ .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
-+ .vs_ext_stop_y = 0x00000006,
-+ .avid_start_stop_x = 0x03480078,
-+ .avid_start_stop_y = 0x02060024,
-+ .fid_int_start_x__fid_int_start_y = 0x0001008A,
-+ .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
-+ .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
-+
-+ .tvdetgp_int_start_stop_x = 0x00140001,
-+ .tvdetgp_int_start_stop_y = 0x00010001,
-+ .gen_ctrl = 0x00F90000,
-+};
-+
-+static const struct venc_config venc_config_pal_bdghi = {
-+ .f_control = 0,
-+ .vidout_ctrl = 0,
-+ .sync_ctrl = 0,
-+ .hfltr_ctrl = 0,
-+ .x_color = 0,
-+ .line21 = 0,
-+ .ln_sel = 21,
-+ .htrigger_vtrigger = 0,
-+ .tvdetgp_int_start_stop_x = 0x00140001,
-+ .tvdetgp_int_start_stop_y = 0x00010001,
-+ .gen_ctrl = 0x00FB0000,
-+
-+ .llen = 864-1,
-+ .flens = 625-1,
-+ .cc_carr_wss_carr = 0x2F7625ED,
-+ .c_phase = 0xDF,
-+ .gain_u = 0x111,
-+ .gain_v = 0x181,
-+ .gain_y = 0x140,
-+ .black_level = 0x3e,
-+ .blank_level = 0x3e,
-+ .m_control = 0<<2 | 1<<1,
-+ .bstamp_wss_data = 0x42,
-+ .s_carr = 0x2a098acb,
-+ .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
-+ .savid__eavid = 0x06A70108,
-+ .flen__fal = 23<<16 | 624<<0,
-+ .lal__phase_reset = 2<<17 | 310<<0,
-+ .hs_int_start_stop_x = 0x00920358,
-+ .hs_ext_start_stop_x = 0x000F035F,
-+ .vs_int_start_x = 0x1a7<<16,
-+ .vs_int_stop_x__vs_int_start_y = 0x000601A7,
-+ .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
-+ .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
-+ .vs_ext_stop_y = 0x05,
-+ .avid_start_stop_x = 0x03530082,
-+ .avid_start_stop_y = 0x0270002E,
-+ .fid_int_start_x__fid_int_start_y = 0x0005008A,
-+ .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
-+ .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
-+};
-+
-+const struct omap_video_timings omap_dss_pal_timings = {
-+ .x_res = 720,
-+ .y_res = 574,
-+ .pixel_clock = 26181,
-+ .hsw = 32,
-+ .hfp = 80,
-+ .hbp = 48,
-+ .vsw = 7,
-+ .vfp = 3,
-+ .vbp = 6,
-+};
-+EXPORT_SYMBOL(omap_dss_pal_timings);
-+
-+const struct omap_video_timings omap_dss_ntsc_timings = {
-+ .x_res = 720,
-+ .y_res = 482,
-+ .pixel_clock = 22153,
-+ .hsw = 32,
-+ .hfp = 80,
-+ .hbp = 48,
-+ .vsw = 10,
-+ .vfp = 3,
-+ .vbp = 6,
-+};
-+EXPORT_SYMBOL(omap_dss_ntsc_timings);
-+
-+static struct {
-+ void __iomem *base;
-+ struct mutex venc_lock;
-+} venc;
-+
-+static struct omap_panel venc_panel = {
-+ .name = "tv-out",
-+};
-+
-+static inline void venc_write_reg(int idx, u32 val)
-+{
-+ __raw_writel(val, venc.base + idx);
-+}
-+
-+static inline u32 venc_read_reg(int idx)
-+{
-+ u32 l = __raw_readl(venc.base + idx);
-+ return l;
-+}
-+
-+static void venc_write_config(const struct venc_config *config)
-+{
-+ DSSDBG("write venc conf\n");
-+
-+ venc_write_reg(VENC_LLEN, config->llen);
-+ venc_write_reg(VENC_FLENS, config->flens);
-+ venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
-+ venc_write_reg(VENC_C_PHASE, config->c_phase);
-+ venc_write_reg(VENC_GAIN_U, config->gain_u);
-+ venc_write_reg(VENC_GAIN_V, config->gain_v);
-+ venc_write_reg(VENC_GAIN_Y, config->gain_y);
-+ venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
-+ venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
-+ venc_write_reg(VENC_M_CONTROL, config->m_control);
-+ venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data);
-+ venc_write_reg(VENC_S_CARR, config->s_carr);
-+ venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
-+ venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
-+ venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
-+ venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
-+ venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
-+ venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
-+ venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
-+ venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
-+ config->vs_int_stop_x__vs_int_start_y);
-+ venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
-+ config->vs_int_stop_y__vs_ext_start_x);
-+ venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
-+ config->vs_ext_stop_x__vs_ext_start_y);
-+ venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
-+ venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
-+ venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
-+ venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
-+ config->fid_int_start_x__fid_int_start_y);
-+ venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
-+ config->fid_int_offset_y__fid_ext_start_x);
-+ venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
-+ config->fid_ext_start_y__fid_ext_offset_y);
-+
-+ venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C));
-+ venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
-+ venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
-+ venc_write_reg(VENC_X_COLOR, config->x_color);
-+ venc_write_reg(VENC_LINE21, config->line21);
-+ venc_write_reg(VENC_LN_SEL, config->ln_sel);
-+ venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
-+ venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
-+ config->tvdetgp_int_start_stop_x);
-+ venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
-+ config->tvdetgp_int_start_stop_y);
-+ venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
-+ venc_write_reg(VENC_F_CONTROL, config->f_control);
-+ venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
-+}
-+
-+static void venc_reset(void)
-+{
-+ int t = 1000;
-+
-+ venc_write_reg(VENC_F_CONTROL, 1<<8);
-+ while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
-+ if (--t == 0) {
-+ DSSERR("Failed to reset venc\n");
-+ return;
-+ }
-+ }
-+
-+ /* the magical sleep that makes things work */
-+ msleep(20);
-+}
-+
-+static void venc_enable_clocks(int enable)
-+{
-+ if (enable)
-+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M |
-+ DSS_CLK_96M);
-+ else
-+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M |
-+ DSS_CLK_96M);
-+}
-+
-+static const struct venc_config *venc_timings_to_config(
-+ struct omap_video_timings *timings)
-+{
-+ if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
-+ return &venc_config_pal_trm;
-+
-+ if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
-+ return &venc_config_ntsc_trm;
-+
-+ BUG();
-+}
-+
-+int venc_init(void)
-+{
-+ u8 rev_id;
-+
-+ mutex_init(&venc.venc_lock);
-+
-+ venc_panel.timings = omap_dss_pal_timings;
-+
-+ venc.base = ioremap(VENC_BASE, SZ_1K);
-+ if (!venc.base) {
-+ DSSERR("can't ioremap VENC\n");
-+ return -ENOMEM;
-+ }
-+
-+ venc_enable_clocks(1);
-+
-+ rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
-+ printk(KERN_INFO "OMAP VENC rev %d\n", rev_id);
-+
-+ venc_enable_clocks(0);
-+
-+ return 0;
-+}
-+
-+void venc_exit(void)
-+{
-+ iounmap(venc.base);
-+}
-+
-+static void venc_power_on(struct omap_display *display)
-+{
-+ venc_enable_clocks(1);
-+
-+ venc_reset();
-+ venc_write_config(venc_timings_to_config(&display->panel->timings));
-+
-+ dss_set_venc_output(display->hw_config.u.venc.type);
-+ dss_set_dac_pwrdn_bgz(1);
-+
-+ if (display->hw_config.u.venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE) {
-+ if (cpu_is_omap24xx())
-+ venc_write_reg(VENC_OUTPUT_CONTROL, 0x2);
-+ else
-+ venc_write_reg(VENC_OUTPUT_CONTROL, 0xa);
-+ } else { /* S-Video */
-+ venc_write_reg(VENC_OUTPUT_CONTROL, 0xd);
-+ }
-+
-+ dispc_set_digit_size(display->panel->timings.x_res,
-+ display->panel->timings.y_res/2);
-+
-+ if (display->hw_config.panel_enable)
-+ display->hw_config.panel_enable(display);
-+
-+ dispc_enable_digit_out(1);
-+}
-+
-+static void venc_power_off(struct omap_display *display)
-+{
-+ venc_write_reg(VENC_OUTPUT_CONTROL, 0);
-+ dss_set_dac_pwrdn_bgz(0);
-+
-+ dispc_enable_digit_out(0);
-+
-+ if (display->hw_config.panel_disable)
-+ display->hw_config.panel_disable(display);
-+
-+ venc_enable_clocks(0);
-+}
-+
-+static int venc_enable_display(struct omap_display *display)
-+{
-+ int r = 0;
-+
-+ DSSDBG("venc_enable_display\n");
-+
-+ mutex_lock(&venc.venc_lock);
-+
-+ if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
-+ r = -EINVAL;
-+ goto err;
-+ }
-+
-+ venc_power_on(display);
-+
-+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
-+err:
-+ mutex_unlock(&venc.venc_lock);
-+
-+ return r;
-+}
-+
-+static void venc_disable_display(struct omap_display *display)
-+{
-+ DSSDBG("venc_disable_display\n");
-+
-+ mutex_lock(&venc.venc_lock);
-+
-+ if (display->state == OMAP_DSS_DISPLAY_DISABLED)
-+ goto end;
-+
-+ if (display->state == OMAP_DSS_DISPLAY_SUSPENDED) {
-+ /* suspended is the same as disabled with venc */
-+ display->state = OMAP_DSS_DISPLAY_DISABLED;
-+ goto end;
-+ }
-+
-+ venc_power_off(display);
-+
-+ display->state = OMAP_DSS_DISPLAY_DISABLED;
-+end:
-+ mutex_unlock(&venc.venc_lock);
-+}
-+
-+static int venc_display_suspend(struct omap_display *display)
-+{
-+ int r = 0;
-+
-+ DSSDBG("venc_display_suspend\n");
-+
-+ mutex_lock(&venc.venc_lock);
-+
-+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE) {
-+ r = -EINVAL;
-+ goto err;
-+ }
-+
-+ venc_power_off(display);
-+
-+ display->state = OMAP_DSS_DISPLAY_SUSPENDED;
-+err:
-+ mutex_unlock(&venc.venc_lock);
-+
-+ return r;
-+}
-+
-+static int venc_display_resume(struct omap_display *display)
-+{
-+ int r = 0;
-+
-+ DSSDBG("venc_display_resume\n");
-+
-+ mutex_lock(&venc.venc_lock);
-+
-+ if (display->state != OMAP_DSS_DISPLAY_SUSPENDED) {
-+ r = -EINVAL;
-+ goto err;
-+ }
-+
-+ venc_power_on(display);
-+
-+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
-+err:
-+ mutex_unlock(&venc.venc_lock);
-+
-+ return r;
-+}
-+
-+static void venc_get_timings(struct omap_display *display,
-+ struct omap_video_timings *timings)
-+{
-+ *timings = venc_panel.timings;
-+}
-+
-+static void venc_set_timings(struct omap_display *display,
-+ struct omap_video_timings *timings)
-+{
-+ DSSDBG("venc_set_timings\n");
-+ display->panel->timings = *timings;
-+ if (display->state == OMAP_DSS_DISPLAY_ACTIVE) {
-+ /* turn the venc off and on to get new timings to use */
-+ venc_disable_display(display);
-+ venc_enable_display(display);
-+ }
-+}
-+
-+static int venc_check_timings(struct omap_display *display,
-+ struct omap_video_timings *timings)
-+{
-+ DSSDBG("venc_check_timings\n");
-+
-+ if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
-+ return 0;
-+
-+ if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
-+ return 0;
-+
-+ return -EINVAL;
-+}
-+
-+void venc_init_display(struct omap_display *display)
-+{
-+ display->panel = &venc_panel;
-+ display->enable = venc_enable_display;
-+ display->disable = venc_disable_display;
-+ display->suspend = venc_display_suspend;
-+ display->resume = venc_display_resume;
-+ display->get_timings = venc_get_timings;
-+ display->set_timings = venc_set_timings;
-+ display->check_timings = venc_check_timings;
-+}
---
-1.6.2.4
-
+++ /dev/null
-From db9314f01a207e256d545244d3d00dc4ce535280 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Thu, 2 Apr 2009 10:25:48 +0300
-Subject: [PATCH 04/69] DSS2: OMAP framebuffer driver
-
-Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
----
- arch/arm/plat-omap/fb.c | 28 +
- drivers/video/omap/Kconfig | 5 +-
- drivers/video/omap2/omapfb/Kconfig | 35 +
- drivers/video/omap2/omapfb/Makefile | 2 +
- drivers/video/omap2/omapfb/omapfb-ioctl.c | 656 ++++++++++
- drivers/video/omap2/omapfb/omapfb-main.c | 2010 +++++++++++++++++++++++++++++
- drivers/video/omap2/omapfb/omapfb-sysfs.c | 371 ++++++
- drivers/video/omap2/omapfb/omapfb.h | 153 +++
- include/linux/omapfb.h | 20 +
- 9 files changed, 3278 insertions(+), 2 deletions(-)
- create mode 100644 drivers/video/omap2/omapfb/Kconfig
- create mode 100644 drivers/video/omap2/omapfb/Makefile
- create mode 100644 drivers/video/omap2/omapfb/omapfb-ioctl.c
- create mode 100644 drivers/video/omap2/omapfb/omapfb-main.c
- create mode 100644 drivers/video/omap2/omapfb/omapfb-sysfs.c
- create mode 100644 drivers/video/omap2/omapfb/omapfb.h
-
-diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
-index 40615a6..1dc3415 100644
---- a/arch/arm/plat-omap/fb.c
-+++ b/arch/arm/plat-omap/fb.c
-@@ -327,6 +327,34 @@ static inline int omap_init_fb(void)
-
- arch_initcall(omap_init_fb);
-
-+#elif defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
-+
-+static u64 omap_fb_dma_mask = ~(u32)0;
-+static struct omapfb_platform_data omapfb_config;
-+
-+static struct platform_device omap_fb_device = {
-+ .name = "omapfb",
-+ .id = -1,
-+ .dev = {
-+ .dma_mask = &omap_fb_dma_mask,
-+ .coherent_dma_mask = ~(u32)0,
-+ .platform_data = &omapfb_config,
-+ },
-+ .num_resources = 0,
-+};
-+
-+void omapfb_set_platform_data(struct omapfb_platform_data *data)
-+{
-+ omapfb_config = *data;
-+}
-+
-+static inline int omap_init_fb(void)
-+{
-+ return platform_device_register(&omap_fb_device);
-+}
-+
-+arch_initcall(omap_init_fb);
-+
- #else
-
- void omapfb_reserve_sdram(void) {}
-diff --git a/drivers/video/omap/Kconfig b/drivers/video/omap/Kconfig
-index c355b59..a1c10de 100644
---- a/drivers/video/omap/Kconfig
-+++ b/drivers/video/omap/Kconfig
-@@ -1,6 +1,7 @@
- config FB_OMAP
- tristate "OMAP frame buffer support (EXPERIMENTAL)"
-- depends on FB && ARCH_OMAP
-+ depends on FB && ARCH_OMAP && (OMAP2_DSS = "n")
-+
- select FB_CFB_FILLRECT
- select FB_CFB_COPYAREA
- select FB_CFB_IMAGEBLIT
-@@ -72,7 +73,7 @@ config FB_OMAP_LCD_MIPID
-
- config FB_OMAP_BOOTLOADER_INIT
- bool "Check bootloader initialization"
-- depends on FB_OMAP
-+ depends on FB_OMAP || FB_OMAP2
- help
- Say Y here if you want to enable checking if the bootloader has
- already initialized the display controller. In this case the
-diff --git a/drivers/video/omap2/omapfb/Kconfig b/drivers/video/omap2/omapfb/Kconfig
-new file mode 100644
-index 0000000..4f66033
---- /dev/null
-+++ b/drivers/video/omap2/omapfb/Kconfig
-@@ -0,0 +1,35 @@
-+menuconfig FB_OMAP2
-+ tristate "OMAP2/3 frame buffer support (EXPERIMENTAL)"
-+ depends on FB && OMAP2_DSS
-+
-+ select FB_CFB_FILLRECT
-+ select FB_CFB_COPYAREA
-+ select FB_CFB_IMAGEBLIT
-+ help
-+ Frame buffer driver for OMAP2/3 based boards.
-+
-+config FB_OMAP2_DEBUG_SUPPORT
-+ bool "Debug support for OMAP2/3 FB"
-+ default y
-+ depends on FB_OMAP2
-+ help
-+ Support for debug output. You have to enable the actual printing
-+ with debug module parameter.
-+
-+config FB_OMAP2_FORCE_AUTO_UPDATE
-+ bool "Force main display to automatic update mode"
-+ depends on FB_OMAP2
-+ help
-+ Forces main display to automatic update mode (if possible),
-+ and also enables tearsync (if possible). By default
-+ displays that support manual update are started in manual
-+ update mode.
-+
-+config FB_OMAP2_NUM_FBS
-+ int "Number of framebuffers"
-+ range 1 10
-+ default 3
-+ depends on FB_OMAP2
-+ help
-+ Select the number of framebuffers created. OMAP2/3 has 3 overlays
-+ so normally this would be 3.
-diff --git a/drivers/video/omap2/omapfb/Makefile b/drivers/video/omap2/omapfb/Makefile
-new file mode 100644
-index 0000000..51c2e00
---- /dev/null
-+++ b/drivers/video/omap2/omapfb/Makefile
-@@ -0,0 +1,2 @@
-+obj-$(CONFIG_FB_OMAP2) += omapfb.o
-+omapfb-y := omapfb-main.o omapfb-sysfs.o omapfb-ioctl.o
-diff --git a/drivers/video/omap2/omapfb/omapfb-ioctl.c b/drivers/video/omap2/omapfb/omapfb-ioctl.c
-new file mode 100644
-index 0000000..7f18d2a
---- /dev/null
-+++ b/drivers/video/omap2/omapfb/omapfb-ioctl.c
-@@ -0,0 +1,656 @@
-+/*
-+ * linux/drivers/video/omap2/omapfb-ioctl.c
-+ *
-+ * Copyright (C) 2008 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * Some code and ideas taken from drivers/video/omap/ driver
-+ * by Imre Deak.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#include <linux/fb.h>
-+#include <linux/device.h>
-+#include <linux/uaccess.h>
-+#include <linux/platform_device.h>
-+#include <linux/mm.h>
-+#include <linux/omapfb.h>
-+#include <linux/vmalloc.h>
-+
-+#include <mach/display.h>
-+#include <mach/vrfb.h>
-+
-+#include "omapfb.h"
-+
-+static int omapfb_setup_plane(struct fb_info *fbi, struct omapfb_plane_info *pi)
-+{
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+ struct omap_display *display = fb2display(fbi);
-+ struct omap_overlay *ovl;
-+ struct omap_overlay_info info;
-+ int r = 0;
-+
-+ DBG("omapfb_setup_plane\n");
-+
-+ omapfb_lock(fbdev);
-+
-+ if (ofbi->num_overlays != 1) {
-+ r = -EINVAL;
-+ goto out;
-+ }
-+
-+ /* XXX uses only the first overlay */
-+ ovl = ofbi->overlays[0];
-+
-+ if (pi->enabled && !ofbi->region.size) {
-+ /*
-+ * This plane's memory was freed, can't enable it
-+ * until it's reallocated.
-+ */
-+ r = -EINVAL;
-+ goto out;
-+ }
-+
-+ ovl->get_overlay_info(ovl, &info);
-+
-+ info.pos_x = pi->pos_x;
-+ info.pos_y = pi->pos_y;
-+ info.out_width = pi->out_width;
-+ info.out_height = pi->out_height;
-+ info.enabled = pi->enabled;
-+
-+ r = ovl->set_overlay_info(ovl, &info);
-+ if (r)
-+ goto out;
-+
-+ if (ovl->manager) {
-+ r = ovl->manager->apply(ovl->manager);
-+ if (r)
-+ goto out;
-+ }
-+
-+ if (display) {
-+ u16 w, h;
-+
-+ if (display->sync)
-+ display->sync(display);
-+
-+ display->get_resolution(display, &w, &h);
-+
-+ if (display->update)
-+ display->update(display, 0, 0, w, h);
-+ }
-+
-+out:
-+ omapfb_unlock(fbdev);
-+ if (r)
-+ dev_err(fbdev->dev, "setup_plane failed\n");
-+ return r;
-+}
-+
-+static int omapfb_query_plane(struct fb_info *fbi, struct omapfb_plane_info *pi)
-+{
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+
-+ omapfb_lock(fbdev);
-+
-+ if (ofbi->num_overlays != 1) {
-+ memset(pi, 0, sizeof(*pi));
-+ } else {
-+ struct omap_overlay_info *ovli;
-+ struct omap_overlay *ovl;
-+
-+ ovl = ofbi->overlays[0];
-+ ovli = &ovl->info;
-+
-+ pi->pos_x = ovli->pos_x;
-+ pi->pos_y = ovli->pos_y;
-+ pi->enabled = ovli->enabled;
-+ pi->channel_out = 0; /* xxx */
-+ pi->mirror = 0;
-+ pi->out_width = ovli->out_width;
-+ pi->out_height = ovli->out_height;
-+ }
-+
-+ omapfb_unlock(fbdev);
-+
-+ return 0;
-+}
-+
-+static int omapfb_setup_mem(struct fb_info *fbi, struct omapfb_mem_info *mi)
-+{
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+ struct omapfb2_mem_region *rg;
-+ int r, i;
-+ size_t size;
-+
-+ if (mi->type > OMAPFB_MEMTYPE_MAX)
-+ return -EINVAL;
-+
-+ size = PAGE_ALIGN(mi->size);
-+
-+ rg = &ofbi->region;
-+
-+ omapfb_lock(fbdev);
-+
-+ for (i = 0; i < ofbi->num_overlays; i++) {
-+ if (ofbi->overlays[i]->info.enabled) {
-+ r = -EBUSY;
-+ goto out;
-+ }
-+ }
-+
-+ if (rg->size != size || rg->type != mi->type) {
-+ r = omapfb_realloc_fbmem(fbi, size, mi->type);
-+ if (r) {
-+ dev_err(fbdev->dev, "realloc fbmem failed\n");
-+ goto out;
-+ }
-+ }
-+
-+ r = 0;
-+out:
-+ omapfb_unlock(fbdev);
-+
-+ return r;
-+}
-+
-+static int omapfb_query_mem(struct fb_info *fbi, struct omapfb_mem_info *mi)
-+{
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+ struct omapfb2_mem_region *rg;
-+
-+ rg = &ofbi->region;
-+ memset(mi, 0, sizeof(*mi));
-+
-+ omapfb_lock(fbdev);
-+ mi->size = rg->size;
-+ mi->type = rg->type;
-+ omapfb_unlock(fbdev);
-+
-+ return 0;
-+}
-+
-+static int omapfb_update_window(struct fb_info *fbi,
-+ u32 x, u32 y, u32 w, u32 h)
-+{
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+ struct omap_display *display = fb2display(fbi);
-+ u16 dw, dh;
-+
-+ if (!display)
-+ return 0;
-+
-+ if (w == 0 || h == 0)
-+ return 0;
-+
-+ display->get_resolution(display, &dw, &dh);
-+
-+ if (x + w > dw || y + h > dh)
-+ return -EINVAL;
-+
-+ omapfb_lock(fbdev);
-+ display->update(display, x, y, w, h);
-+ omapfb_unlock(fbdev);
-+
-+ return 0;
-+}
-+
-+static int omapfb_set_update_mode(struct fb_info *fbi,
-+ enum omapfb_update_mode mode)
-+{
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+ struct omap_display *display = fb2display(fbi);
-+ enum omap_dss_update_mode um;
-+ int r;
-+
-+ if (!display || !display->set_update_mode)
-+ return -EINVAL;
-+
-+ switch (mode) {
-+ case OMAPFB_UPDATE_DISABLED:
-+ um = OMAP_DSS_UPDATE_DISABLED;
-+ break;
-+
-+ case OMAPFB_AUTO_UPDATE:
-+ um = OMAP_DSS_UPDATE_AUTO;
-+ break;
-+
-+ case OMAPFB_MANUAL_UPDATE:
-+ um = OMAP_DSS_UPDATE_MANUAL;
-+ break;
-+
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ omapfb_lock(fbdev);
-+ r = display->set_update_mode(display, um);
-+ omapfb_unlock(fbdev);
-+
-+ return r;
-+}
-+
-+static int omapfb_get_update_mode(struct fb_info *fbi,
-+ enum omapfb_update_mode *mode)
-+{
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+ struct omap_display *display = fb2display(fbi);
-+ enum omap_dss_update_mode m;
-+
-+ if (!display || !display->get_update_mode)
-+ return -EINVAL;
-+
-+ omapfb_lock(fbdev);
-+ m = display->get_update_mode(display);
-+ omapfb_unlock(fbdev);
-+
-+ switch (m) {
-+ case OMAP_DSS_UPDATE_DISABLED:
-+ *mode = OMAPFB_UPDATE_DISABLED;
-+ break;
-+ case OMAP_DSS_UPDATE_AUTO:
-+ *mode = OMAPFB_AUTO_UPDATE;
-+ break;
-+ case OMAP_DSS_UPDATE_MANUAL:
-+ *mode = OMAPFB_MANUAL_UPDATE;
-+ break;
-+ default:
-+ BUG();
-+ }
-+
-+ return 0;
-+}
-+
-+/* XXX this color key handling is a hack... */
-+static struct omapfb_color_key omapfb_color_keys[2];
-+
-+static int _omapfb_set_color_key(struct omap_overlay_manager *mgr,
-+ struct omapfb_color_key *ck)
-+{
-+ enum omap_dss_color_key_type kt;
-+
-+ if(!mgr->set_default_color || !mgr->set_trans_key ||
-+ !mgr->enable_trans_key)
-+ return 0;
-+
-+ if (ck->key_type == OMAPFB_COLOR_KEY_DISABLED) {
-+ mgr->enable_trans_key(mgr, 0);
-+ omapfb_color_keys[mgr->id] = *ck;
-+ return 0;
-+ }
-+
-+ switch(ck->key_type) {
-+ case OMAPFB_COLOR_KEY_GFX_DST:
-+ kt = OMAP_DSS_COLOR_KEY_GFX_DST;
-+ break;
-+ case OMAPFB_COLOR_KEY_VID_SRC:
-+ kt = OMAP_DSS_COLOR_KEY_VID_SRC;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ mgr->set_default_color(mgr, ck->background);
-+ mgr->set_trans_key(mgr, kt, ck->trans_key);
-+ mgr->enable_trans_key(mgr, 1);
-+
-+ omapfb_color_keys[mgr->id] = *ck;
-+
-+ return 0;
-+}
-+
-+static int omapfb_set_color_key(struct fb_info *fbi,
-+ struct omapfb_color_key *ck)
-+{
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+ int r;
-+ int i;
-+ struct omap_overlay_manager *mgr = NULL;
-+
-+ omapfb_lock(fbdev);
-+
-+ for (i = 0; i < ofbi->num_overlays; i++) {
-+ if (ofbi->overlays[i]->manager) {
-+ mgr = ofbi->overlays[i]->manager;
-+ break;
-+ }
-+ }
-+
-+ if (!mgr) {
-+ r = -EINVAL;
-+ goto err;
-+ }
-+
-+ if(!mgr->set_default_color || !mgr->set_trans_key ||
-+ !mgr->enable_trans_key) {
-+ r = -ENODEV;
-+ goto err;
-+ }
-+
-+ r = _omapfb_set_color_key(mgr, ck);
-+err:
-+ omapfb_unlock(fbdev);
-+
-+ return r;
-+}
-+
-+static int omapfb_get_color_key(struct fb_info *fbi,
-+ struct omapfb_color_key *ck)
-+{
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+ struct omap_overlay_manager *mgr = NULL;
-+ int r = 0;
-+ int i;
-+
-+ omapfb_lock(fbdev);
-+
-+ for (i = 0; i < ofbi->num_overlays; i++) {
-+ if (ofbi->overlays[i]->manager) {
-+ mgr = ofbi->overlays[i]->manager;
-+ break;
-+ }
-+ }
-+
-+ if (!mgr) {
-+ r = -EINVAL;
-+ goto err;
-+ }
-+
-+ if(!mgr->set_default_color || !mgr->set_trans_key ||
-+ !mgr->enable_trans_key) {
-+ r = -ENODEV;
-+ goto err;
-+ }
-+
-+ *ck = omapfb_color_keys[mgr->id];
-+err:
-+ omapfb_unlock(fbdev);
-+
-+ return r;
-+}
-+
-+static int omapfb_memory_read(struct fb_info *fbi,
-+ struct omapfb_memory_read *mr)
-+{
-+ struct omap_display *display = fb2display(fbi);
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+ void *buf;
-+ int r;
-+
-+ if (!display || !display->memory_read)
-+ return -ENOENT;
-+
-+ if (!access_ok(VERIFY_WRITE, mr->buffer, mr->buffer_size))
-+ return -EFAULT;
-+
-+ if (mr->w * mr->h * 3 > mr->buffer_size)
-+ return -EINVAL;
-+
-+ buf = vmalloc(mr->buffer_size);
-+ if (!buf) {
-+ DBG("vmalloc failed\n");
-+ return -ENOMEM;
-+ }
-+
-+ omapfb_lock(fbdev);
-+
-+ r = display->memory_read(display, buf, mr->buffer_size,
-+ mr->x, mr->y, mr->w, mr->h);
-+
-+ if (r > 0) {
-+ if (copy_to_user(mr->buffer, buf, mr->buffer_size))
-+ r = -EFAULT;
-+ }
-+
-+ vfree(buf);
-+
-+ omapfb_unlock(fbdev);
-+
-+ return r;
-+}
-+
-+int omapfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg)
-+{
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+ struct omap_display *display = fb2display(fbi);
-+
-+ union {
-+ struct omapfb_update_window_old uwnd_o;
-+ struct omapfb_update_window uwnd;
-+ struct omapfb_plane_info plane_info;
-+ struct omapfb_caps caps;
-+ struct omapfb_mem_info mem_info;
-+ struct omapfb_color_key color_key;
-+ enum omapfb_update_mode update_mode;
-+ int test_num;
-+ struct omapfb_memory_read memory_read;
-+ } p;
-+
-+ int r = 0;
-+
-+ switch (cmd) {
-+ case OMAPFB_SYNC_GFX:
-+ DBG("ioctl SYNC_GFX\n");
-+ if (!display || !display->sync) {
-+ /* DSS1 never returns an error here, so we neither */
-+ /*r = -EINVAL;*/
-+ break;
-+ }
-+
-+ omapfb_lock(fbdev);
-+ r = display->sync(display);
-+ omapfb_unlock(fbdev);
-+ break;
-+
-+ case OMAPFB_UPDATE_WINDOW_OLD:
-+ DBG("ioctl UPDATE_WINDOW_OLD\n");
-+ if (!display || !display->update) {
-+ r = -EINVAL;
-+ break;
-+ }
-+
-+ if (copy_from_user(&p.uwnd_o,
-+ (void __user *)arg,
-+ sizeof(p.uwnd_o))) {
-+ r = -EFAULT;
-+ break;
-+ }
-+
-+ r = omapfb_update_window(fbi, p.uwnd_o.x, p.uwnd_o.y,
-+ p.uwnd_o.width, p.uwnd_o.height);
-+ break;
-+
-+ case OMAPFB_UPDATE_WINDOW:
-+ DBG("ioctl UPDATE_WINDOW\n");
-+ if (!display || !display->update) {
-+ r = -EINVAL;
-+ break;
-+ }
-+
-+ if (copy_from_user(&p.uwnd, (void __user *)arg,
-+ sizeof(p.uwnd))) {
-+ r = -EFAULT;
-+ break;
-+ }
-+
-+ r = omapfb_update_window(fbi, p.uwnd.x, p.uwnd.y,
-+ p.uwnd.width, p.uwnd.height);
-+ break;
-+
-+ case OMAPFB_SETUP_PLANE:
-+ DBG("ioctl SETUP_PLANE\n");
-+ if (copy_from_user(&p.plane_info, (void __user *)arg,
-+ sizeof(p.plane_info)))
-+ r = -EFAULT;
-+ else
-+ r = omapfb_setup_plane(fbi, &p.plane_info);
-+ break;
-+
-+ case OMAPFB_QUERY_PLANE:
-+ DBG("ioctl QUERY_PLANE\n");
-+ r = omapfb_query_plane(fbi, &p.plane_info);
-+ if (r < 0)
-+ break;
-+ if (copy_to_user((void __user *)arg, &p.plane_info,
-+ sizeof(p.plane_info)))
-+ r = -EFAULT;
-+ break;
-+
-+ case OMAPFB_SETUP_MEM:
-+ DBG("ioctl SETUP_MEM\n");
-+ if (copy_from_user(&p.mem_info, (void __user *)arg,
-+ sizeof(p.mem_info)))
-+ r = -EFAULT;
-+ else
-+ r = omapfb_setup_mem(fbi, &p.mem_info);
-+ break;
-+
-+ case OMAPFB_QUERY_MEM:
-+ DBG("ioctl QUERY_MEM\n");
-+ r = omapfb_query_mem(fbi, &p.mem_info);
-+ if (r < 0)
-+ break;
-+ if (copy_to_user((void __user *)arg, &p.mem_info,
-+ sizeof(p.mem_info)))
-+ r = -EFAULT;
-+ break;
-+
-+ case OMAPFB_GET_CAPS:
-+ DBG("ioctl GET_CAPS\n");
-+ if (!display) {
-+ r = -EINVAL;
-+ break;
-+ }
-+
-+ p.caps.ctrl = display->caps;
-+
-+ if (copy_to_user((void __user *)arg, &p.caps, sizeof(p.caps)))
-+ r = -EFAULT;
-+ break;
-+
-+ case OMAPFB_SET_UPDATE_MODE:
-+ DBG("ioctl SET_UPDATE_MODE\n");
-+ if (get_user(p.update_mode, (int __user *)arg))
-+ r = -EFAULT;
-+ else
-+ r = omapfb_set_update_mode(fbi, p.update_mode);
-+ break;
-+
-+ case OMAPFB_GET_UPDATE_MODE:
-+ DBG("ioctl GET_UPDATE_MODE\n");
-+ r = omapfb_get_update_mode(fbi, &p.update_mode);
-+ if (r)
-+ break;
-+ if (put_user(p.update_mode,
-+ (enum omapfb_update_mode __user *)arg))
-+ r = -EFAULT;
-+ break;
-+
-+ case OMAPFB_SET_COLOR_KEY:
-+ DBG("ioctl SET_COLOR_KEY\n");
-+ if (copy_from_user(&p.color_key, (void __user *)arg,
-+ sizeof(p.color_key)))
-+ r = -EFAULT;
-+ else
-+ r = omapfb_set_color_key(fbi, &p.color_key);
-+ break;
-+
-+ case OMAPFB_GET_COLOR_KEY:
-+ DBG("ioctl GET_COLOR_KEY\n");
-+ if ((r = omapfb_get_color_key(fbi, &p.color_key)) < 0)
-+ break;
-+ if (copy_to_user((void __user *)arg, &p.color_key,
-+ sizeof(p.color_key)))
-+ r = -EFAULT;
-+ break;
-+
-+ case OMAPFB_WAITFORVSYNC:
-+ DBG("ioctl WAITFORVSYNC\n");
-+ if (!display) {
-+ r = -EINVAL;
-+ break;
-+ }
-+
-+ r = display->wait_vsync(display);
-+ break;
-+
-+ /* LCD and CTRL tests do the same thing for backward
-+ * compatibility */
-+ case OMAPFB_LCD_TEST:
-+ DBG("ioctl LCD_TEST\n");
-+ if (get_user(p.test_num, (int __user *)arg)) {
-+ r = -EFAULT;
-+ break;
-+ }
-+ if (!display || !display->run_test) {
-+ r = -EINVAL;
-+ break;
-+ }
-+
-+ r = display->run_test(display, p.test_num);
-+
-+ break;
-+
-+ case OMAPFB_CTRL_TEST:
-+ DBG("ioctl CTRL_TEST\n");
-+ if (get_user(p.test_num, (int __user *)arg)) {
-+ r = -EFAULT;
-+ break;
-+ }
-+ if (!display || !display->run_test) {
-+ r = -EINVAL;
-+ break;
-+ }
-+
-+ r = display->run_test(display, p.test_num);
-+
-+ break;
-+
-+ case OMAPFB_MEMORY_READ:
-+ DBG("ioctl MEMORY_READ\n");
-+
-+ if (copy_from_user(&p.memory_read, (void __user *)arg,
-+ sizeof(p.memory_read))) {
-+ r = -EFAULT;
-+ break;
-+ }
-+
-+ r = omapfb_memory_read(fbi, &p.memory_read);
-+
-+ break;
-+
-+ default:
-+ dev_err(fbdev->dev, "Unknown ioctl 0x%x\n", cmd);
-+ r = -EINVAL;
-+ }
-+
-+ if (r < 0)
-+ DBG("ioctl failed: %d\n", r);
-+
-+ return r;
-+}
-+
-+
-diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
-new file mode 100644
-index 0000000..852abe5
---- /dev/null
-+++ b/drivers/video/omap2/omapfb/omapfb-main.c
-@@ -0,0 +1,2010 @@
-+/*
-+ * linux/drivers/video/omap2/omapfb-main.c
-+ *
-+ * Copyright (C) 2008 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * Some code and ideas taken from drivers/video/omap/ driver
-+ * by Imre Deak.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/delay.h>
-+#include <linux/fb.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/vmalloc.h>
-+#include <linux/device.h>
-+#include <linux/platform_device.h>
-+#include <linux/omapfb.h>
-+
-+#include <mach/display.h>
-+#include <mach/vram.h>
-+#include <mach/vrfb.h>
-+
-+#include "omapfb.h"
-+
-+#define MODULE_NAME "omapfb"
-+
-+static char *def_mode;
-+static char *def_vram;
-+static int def_vrfb;
-+static int def_rotate;
-+static int def_mirror;
-+
-+#ifdef DEBUG
-+unsigned int omapfb_debug;
-+module_param_named(debug, omapfb_debug, bool, 0644);
-+static unsigned int omapfb_test_pattern;
-+module_param_named(test, omapfb_test_pattern, bool, 0644);
-+#endif
-+
-+#ifdef DEBUG
-+static void draw_pixel(struct fb_info *fbi, int x, int y, unsigned color)
-+{
-+ struct fb_var_screeninfo *var = &fbi->var;
-+ struct fb_fix_screeninfo *fix = &fbi->fix;
-+ void __iomem *addr = fbi->screen_base;
-+ const unsigned bytespp = var->bits_per_pixel >> 3;
-+ const unsigned line_len = fix->line_length / bytespp;
-+
-+ int r = (color >> 16) & 0xff;
-+ int g = (color >> 8) & 0xff;
-+ int b = (color >> 0) & 0xff;
-+
-+ if (var->bits_per_pixel == 16) {
-+ u16 __iomem *p = (u16 __iomem *)addr;
-+ p += y * line_len + x;
-+
-+ r = r * 32 / 256;
-+ g = g * 64 / 256;
-+ b = b * 32 / 256;
-+
-+ __raw_writew((r << 11) | (g << 5) | (b << 0), p);
-+ } else if (var->bits_per_pixel == 24) {
-+ u8 __iomem *p = (u8 __iomem *)addr;
-+ p += (y * line_len + x) * 3;
-+
-+ __raw_writeb(b, p + 0);
-+ __raw_writeb(g, p + 1);
-+ __raw_writeb(r, p + 2);
-+ } else if (var->bits_per_pixel == 32) {
-+ u32 __iomem *p = (u32 __iomem *)addr;
-+ p += y * line_len + x;
-+ __raw_writel(color, p);
-+ }
-+}
-+
-+static void fill_fb(struct fb_info *fbi)
-+{
-+ struct fb_var_screeninfo *var = &fbi->var;
-+ const short w = var->xres_virtual;
-+ const short h = var->yres_virtual;
-+ void __iomem *addr = fbi->screen_base;
-+ int y, x;
-+
-+ if (!addr)
-+ return;
-+
-+ DBG("fill_fb %dx%d, line_len %d bytes\n", w, h, fbi->fix.line_length);
-+
-+ for (y = 0; y < h; y++) {
-+ for (x = 0; x < w; x++) {
-+ if (x < 20 && y < 20)
-+ draw_pixel(fbi, x, y, 0xffffff);
-+ else if (x < 20 && (y > 20 && y < h - 20))
-+ draw_pixel(fbi, x, y, 0xff);
-+ else if (y < 20 && (x > 20 && x < w - 20))
-+ draw_pixel(fbi, x, y, 0xff00);
-+ else if (x > w - 20 && (y > 20 && y < h - 20))
-+ draw_pixel(fbi, x, y, 0xff0000);
-+ else if (y > h - 20 && (x > 20 && x < w - 20))
-+ draw_pixel(fbi, x, y, 0xffff00);
-+ else if (x == 20 || x == w - 20 ||
-+ y == 20 || y == h - 20)
-+ draw_pixel(fbi, x, y, 0xffffff);
-+ else if (x == y || w - x == h - y)
-+ draw_pixel(fbi, x, y, 0xff00ff);
-+ else if (w - x == y || x == h - y)
-+ draw_pixel(fbi, x, y, 0x00ffff);
-+ else if (x > 20 && y > 20 && x < w - 20 && y < h - 20) {
-+ int t = x * 3 / w;
-+ unsigned r = 0, g = 0, b = 0;
-+ unsigned c;
-+ if (var->bits_per_pixel == 16) {
-+ if (t == 0)
-+ b = (y % 32) * 256 / 32;
-+ else if (t == 1)
-+ g = (y % 64) * 256 / 64;
-+ else if (t == 2)
-+ r = (y % 32) * 256 / 32;
-+ } else {
-+ if (t == 0)
-+ b = (y % 256);
-+ else if (t == 1)
-+ g = (y % 256);
-+ else if (t == 2)
-+ r = (y % 256);
-+ }
-+ c = (r << 16) | (g << 8) | (b << 0);
-+ draw_pixel(fbi, x, y, c);
-+ } else {
-+ draw_pixel(fbi, x, y, 0);
-+ }
-+ }
-+ }
-+}
-+#endif
-+
-+static unsigned omapfb_get_vrfb_offset(struct omapfb_info *ofbi, int rot)
-+{
-+ struct vrfb *vrfb = &ofbi->region.vrfb;
-+ unsigned offset;
-+
-+ switch (rot) {
-+ case FB_ROTATE_UR:
-+ offset = 0;
-+ break;
-+ case FB_ROTATE_CW:
-+ offset = vrfb->yoffset;
-+ break;
-+ case FB_ROTATE_UD:
-+ offset = vrfb->yoffset * OMAP_VRFB_LINE_LEN + vrfb->xoffset;
-+ break;
-+ case FB_ROTATE_CCW:
-+ offset = vrfb->xoffset * OMAP_VRFB_LINE_LEN;
-+ break;
-+ default:
-+ BUG();
-+ }
-+
-+ offset *= vrfb->bytespp;
-+
-+ return offset;
-+}
-+
-+static u32 omapfb_get_region_rot_paddr(struct omapfb_info *ofbi)
-+{
-+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
-+ unsigned offset;
-+ int rot;
-+
-+ rot = ofbi->rotation;
-+
-+ offset = omapfb_get_vrfb_offset(ofbi, rot);
-+
-+ return ofbi->region.vrfb.paddr[rot] + offset;
-+ } else {
-+ return ofbi->region.paddr;
-+ }
-+}
-+
-+u32 omapfb_get_region_paddr(struct omapfb_info *ofbi)
-+{
-+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
-+ return ofbi->region.vrfb.paddr[0];
-+ else
-+ return ofbi->region.paddr;
-+}
-+
-+void __iomem *omapfb_get_region_vaddr(struct omapfb_info *ofbi)
-+{
-+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
-+ return ofbi->region.vrfb.vaddr[0];
-+ else
-+ return ofbi->region.vaddr;
-+}
-+
-+static struct omapfb_colormode omapfb_colormodes[] = {
-+ {
-+ .dssmode = OMAP_DSS_COLOR_UYVY,
-+ .bits_per_pixel = 16,
-+ .nonstd = OMAPFB_COLOR_YUV422,
-+ }, {
-+ .dssmode = OMAP_DSS_COLOR_YUV2,
-+ .bits_per_pixel = 16,
-+ .nonstd = OMAPFB_COLOR_YUY422,
-+ }, {
-+ .dssmode = OMAP_DSS_COLOR_ARGB16,
-+ .bits_per_pixel = 16,
-+ .red = { .length = 4, .offset = 8, .msb_right = 0 },
-+ .green = { .length = 4, .offset = 4, .msb_right = 0 },
-+ .blue = { .length = 4, .offset = 0, .msb_right = 0 },
-+ .transp = { .length = 4, .offset = 12, .msb_right = 0 },
-+ }, {
-+ .dssmode = OMAP_DSS_COLOR_RGB16,
-+ .bits_per_pixel = 16,
-+ .red = { .length = 5, .offset = 11, .msb_right = 0 },
-+ .green = { .length = 6, .offset = 5, .msb_right = 0 },
-+ .blue = { .length = 5, .offset = 0, .msb_right = 0 },
-+ .transp = { .length = 0, .offset = 0, .msb_right = 0 },
-+ }, {
-+ .dssmode = OMAP_DSS_COLOR_RGB24P,
-+ .bits_per_pixel = 24,
-+ .red = { .length = 8, .offset = 16, .msb_right = 0 },
-+ .green = { .length = 8, .offset = 8, .msb_right = 0 },
-+ .blue = { .length = 8, .offset = 0, .msb_right = 0 },
-+ .transp = { .length = 0, .offset = 0, .msb_right = 0 },
-+ }, {
-+ .dssmode = OMAP_DSS_COLOR_RGB24U,
-+ .bits_per_pixel = 32,
-+ .red = { .length = 8, .offset = 16, .msb_right = 0 },
-+ .green = { .length = 8, .offset = 8, .msb_right = 0 },
-+ .blue = { .length = 8, .offset = 0, .msb_right = 0 },
-+ .transp = { .length = 0, .offset = 0, .msb_right = 0 },
-+ }, {
-+ .dssmode = OMAP_DSS_COLOR_ARGB32,
-+ .bits_per_pixel = 32,
-+ .red = { .length = 8, .offset = 16, .msb_right = 0 },
-+ .green = { .length = 8, .offset = 8, .msb_right = 0 },
-+ .blue = { .length = 8, .offset = 0, .msb_right = 0 },
-+ .transp = { .length = 8, .offset = 24, .msb_right = 0 },
-+ }, {
-+ .dssmode = OMAP_DSS_COLOR_RGBA32,
-+ .bits_per_pixel = 32,
-+ .red = { .length = 8, .offset = 24, .msb_right = 0 },
-+ .green = { .length = 8, .offset = 16, .msb_right = 0 },
-+ .blue = { .length = 8, .offset = 8, .msb_right = 0 },
-+ .transp = { .length = 8, .offset = 0, .msb_right = 0 },
-+ }, {
-+ .dssmode = OMAP_DSS_COLOR_RGBX32,
-+ .bits_per_pixel = 32,
-+ .red = { .length = 8, .offset = 24, .msb_right = 0 },
-+ .green = { .length = 8, .offset = 16, .msb_right = 0 },
-+ .blue = { .length = 8, .offset = 8, .msb_right = 0 },
-+ .transp = { .length = 0, .offset = 0, .msb_right = 0 },
-+ },
-+};
-+
-+static bool cmp_var_to_colormode(struct fb_var_screeninfo *var,
-+ struct omapfb_colormode *color)
-+{
-+ bool cmp_component(struct fb_bitfield *f1, struct fb_bitfield *f2)
-+ {
-+ return f1->length == f2->length &&
-+ f1->offset == f2->offset &&
-+ f1->msb_right == f2->msb_right;
-+ }
-+
-+ if (var->bits_per_pixel == 0 ||
-+ var->red.length == 0 ||
-+ var->blue.length == 0 ||
-+ var->green.length == 0)
-+ return 0;
-+
-+ return var->bits_per_pixel == color->bits_per_pixel &&
-+ cmp_component(&var->red, &color->red) &&
-+ cmp_component(&var->green, &color->green) &&
-+ cmp_component(&var->blue, &color->blue) &&
-+ cmp_component(&var->transp, &color->transp);
-+}
-+
-+static void assign_colormode_to_var(struct fb_var_screeninfo *var,
-+ struct omapfb_colormode *color)
-+{
-+ var->bits_per_pixel = color->bits_per_pixel;
-+ var->nonstd = color->nonstd;
-+ var->red = color->red;
-+ var->green = color->green;
-+ var->blue = color->blue;
-+ var->transp = color->transp;
-+}
-+
-+static enum omap_color_mode fb_mode_to_dss_mode(struct fb_var_screeninfo *var)
-+{
-+ enum omap_color_mode dssmode;
-+ int i;
-+
-+ /* first match with nonstd field */
-+ if (var->nonstd) {
-+ for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) {
-+ struct omapfb_colormode *mode = &omapfb_colormodes[i];
-+ if (var->nonstd == mode->nonstd) {
-+ assign_colormode_to_var(var, mode);
-+ return mode->dssmode;
-+ }
-+ }
-+
-+ return -EINVAL;
-+ }
-+
-+ /* then try exact match of bpp and colors */
-+ for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) {
-+ struct omapfb_colormode *mode = &omapfb_colormodes[i];
-+ if (cmp_var_to_colormode(var, mode)) {
-+ assign_colormode_to_var(var, mode);
-+ return mode->dssmode;
-+ }
-+ }
-+
-+ /* match with bpp if user has not filled color fields
-+ * properly */
-+ switch (var->bits_per_pixel) {
-+ case 1:
-+ dssmode = OMAP_DSS_COLOR_CLUT1;
-+ break;
-+ case 2:
-+ dssmode = OMAP_DSS_COLOR_CLUT2;
-+ break;
-+ case 4:
-+ dssmode = OMAP_DSS_COLOR_CLUT4;
-+ break;
-+ case 8:
-+ dssmode = OMAP_DSS_COLOR_CLUT8;
-+ break;
-+ case 12:
-+ dssmode = OMAP_DSS_COLOR_RGB12U;
-+ break;
-+ case 16:
-+ dssmode = OMAP_DSS_COLOR_RGB16;
-+ break;
-+ case 24:
-+ dssmode = OMAP_DSS_COLOR_RGB24P;
-+ break;
-+ case 32:
-+ dssmode = OMAP_DSS_COLOR_RGB24U;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) {
-+ struct omapfb_colormode *mode = &omapfb_colormodes[i];
-+ if (dssmode == mode->dssmode) {
-+ assign_colormode_to_var(var, mode);
-+ return mode->dssmode;
-+ }
-+ }
-+
-+ return -EINVAL;
-+}
-+
-+void set_fb_fix(struct fb_info *fbi)
-+{
-+ struct fb_fix_screeninfo *fix = &fbi->fix;
-+ struct fb_var_screeninfo *var = &fbi->var;
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_mem_region *rg = &ofbi->region;
-+
-+ DBG("set_fb_fix\n");
-+
-+ /* used by open/write in fbmem.c */
-+ fbi->screen_base = (char __iomem *)omapfb_get_region_vaddr(ofbi);
-+
-+ /* used by mmap in fbmem.c */
-+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
-+ fix->line_length =
-+ (OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 3;
-+ else
-+ fix->line_length =
-+ (var->xres_virtual * var->bits_per_pixel) >> 3;
-+ fix->smem_start = omapfb_get_region_paddr(ofbi);
-+ fix->smem_len = rg->size;
-+
-+ fix->type = FB_TYPE_PACKED_PIXELS;
-+
-+ if (var->nonstd)
-+ fix->visual = FB_VISUAL_PSEUDOCOLOR;
-+ else {
-+ switch (var->bits_per_pixel) {
-+ case 32:
-+ case 24:
-+ case 16:
-+ case 12:
-+ fix->visual = FB_VISUAL_TRUECOLOR;
-+ /* 12bpp is stored in 16 bits */
-+ break;
-+ case 1:
-+ case 2:
-+ case 4:
-+ case 8:
-+ fix->visual = FB_VISUAL_PSEUDOCOLOR;
-+ break;
-+ }
-+ }
-+
-+ fix->accel = FB_ACCEL_NONE;
-+
-+ fix->xpanstep = 1;
-+ fix->ypanstep = 1;
-+
-+ if (rg->size) {
-+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
-+ omap_vrfb_setup(&rg->vrfb, rg->paddr,
-+ var->xres_virtual, var->yres_virtual,
-+ var->bits_per_pixel >> 3);
-+ }
-+}
-+
-+/* check new var and possibly modify it to be ok */
-+int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var)
-+{
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omap_display *display = fb2display(fbi);
-+ unsigned long max_frame_size;
-+ unsigned long line_size;
-+ int xres_min, yres_min;
-+ int xres_max, yres_max;
-+ enum omap_color_mode mode = 0;
-+ int i;
-+ int bytespp;
-+
-+ DBG("check_fb_var %d\n", ofbi->id);
-+
-+ if (ofbi->region.size == 0)
-+ return 0;
-+
-+ mode = fb_mode_to_dss_mode(var);
-+ if (mode < 0) {
-+ DBG("cannot convert var to omap dss mode\n");
-+ return -EINVAL;
-+ }
-+
-+ for (i = 0; i < ofbi->num_overlays; ++i) {
-+ if ((ofbi->overlays[i]->supported_modes & mode) == 0) {
-+ DBG("invalid mode\n");
-+ return -EINVAL;
-+ }
-+ }
-+
-+ if (var->rotate < 0 || var->rotate > 3)
-+ return -EINVAL;
-+
-+ if (var->rotate != fbi->var.rotate) {
-+ DBG("rotation changing\n");
-+
-+ ofbi->rotation = var->rotate;
-+
-+ if (abs(var->rotate - fbi->var.rotate) != 2) {
-+ int tmp;
-+ DBG("rotate changing 90/270 degrees. "
-+ "swapping x/y res\n");
-+
-+ tmp = var->yres;
-+ var->yres = var->xres;
-+ var->xres = tmp;
-+
-+ tmp = var->yres_virtual;
-+ var->yres_virtual = var->xres_virtual;
-+ var->xres_virtual = tmp;
-+ }
-+ }
-+
-+ xres_min = OMAPFB_PLANE_XRES_MIN;
-+ xres_max = 2048;
-+ yres_min = OMAPFB_PLANE_YRES_MIN;
-+ yres_max = 2048;
-+
-+ bytespp = var->bits_per_pixel >> 3;
-+
-+ /* XXX: some applications seem to set virtual res to 0. */
-+ if (var->xres_virtual == 0)
-+ var->xres_virtual = var->xres;
-+
-+ if (var->yres_virtual == 0)
-+ var->yres_virtual = var->yres;
-+
-+ if (var->xres_virtual < xres_min || var->yres_virtual < yres_min)
-+ return -EINVAL;
-+
-+ if (var->xres < xres_min)
-+ var->xres = xres_min;
-+ if (var->yres < yres_min)
-+ var->yres = yres_min;
-+ if (var->xres > xres_max)
-+ var->xres = xres_max;
-+ if (var->yres > yres_max)
-+ var->yres = yres_max;
-+
-+ if (var->xres > var->xres_virtual)
-+ var->xres = var->xres_virtual;
-+ if (var->yres > var->yres_virtual)
-+ var->yres = var->yres_virtual;
-+
-+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
-+ line_size = OMAP_VRFB_LINE_LEN * bytespp;
-+ else
-+ line_size = var->xres_virtual * bytespp;
-+
-+ max_frame_size = ofbi->region.size;
-+
-+ DBG("max frame size %lu, line size %lu\n", max_frame_size, line_size);
-+
-+ if (line_size * var->yres_virtual > max_frame_size) {
-+ DBG("can't fit FB into memory, reducing y\n");
-+ var->yres_virtual = max_frame_size / line_size;
-+
-+ if (var->yres_virtual < yres_min)
-+ var->yres_virtual = yres_min;
-+
-+ if (var->yres > var->yres_virtual)
-+ var->yres = var->yres_virtual;
-+ }
-+
-+ if (line_size * var->yres_virtual > max_frame_size) {
-+ DBG("can't fit FB into memory, reducing x\n");
-+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
-+ return -EINVAL;
-+
-+ var->xres_virtual = max_frame_size / var->yres_virtual /
-+ bytespp;
-+
-+ if (var->xres_virtual < xres_min)
-+ var->xres_virtual = xres_min;
-+
-+ if (var->xres > var->xres_virtual)
-+ var->xres = var->xres_virtual;
-+
-+ line_size = var->xres_virtual * bytespp;
-+ }
-+
-+ if (line_size * var->yres_virtual > max_frame_size) {
-+ DBG("cannot fit FB to memory\n");
-+ return -EINVAL;
-+ }
-+
-+ if (var->xres + var->xoffset > var->xres_virtual)
-+ var->xoffset = var->xres_virtual - var->xres;
-+ if (var->yres + var->yoffset > var->yres_virtual)
-+ var->yoffset = var->yres_virtual - var->yres;
-+
-+ DBG("xres = %d, yres = %d, vxres = %d, vyres = %d\n",
-+ var->xres, var->yres,
-+ var->xres_virtual, var->yres_virtual);
-+
-+ var->height = -1;
-+ var->width = -1;
-+ var->grayscale = 0;
-+
-+ if (display && display->get_timings) {
-+ struct omap_video_timings timings;
-+ display->get_timings(display, &timings);
-+
-+ /* pixclock in ps, the rest in pixclock */
-+ var->pixclock = timings.pixel_clock != 0 ?
-+ KHZ2PICOS(timings.pixel_clock) :
-+ 0;
-+ var->left_margin = timings.hfp;
-+ var->right_margin = timings.hbp;
-+ var->upper_margin = timings.vfp;
-+ var->lower_margin = timings.vbp;
-+ var->hsync_len = timings.hsw;
-+ var->vsync_len = timings.vsw;
-+ } else {
-+ var->pixclock = 0;
-+ var->left_margin = 0;
-+ var->right_margin = 0;
-+ var->upper_margin = 0;
-+ var->lower_margin = 0;
-+ var->hsync_len = 0;
-+ var->vsync_len = 0;
-+ }
-+
-+ /* TODO: get these from panel->config */
-+ var->vmode = FB_VMODE_NONINTERLACED;
-+ var->sync = 0;
-+
-+ return 0;
-+}
-+
-+/*
-+ * ---------------------------------------------------------------------------
-+ * fbdev framework callbacks
-+ * ---------------------------------------------------------------------------
-+ */
-+static int omapfb_open(struct fb_info *fbi, int user)
-+{
-+ return 0;
-+}
-+
-+static int omapfb_release(struct fb_info *fbi, int user)
-+{
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+ struct omap_display *display = fb2display(fbi);
-+
-+ DBG("Closing fb with plane index %d\n", ofbi->id);
-+
-+ omapfb_lock(fbdev);
-+#if 1
-+ if (display && display->get_update_mode && display->update) {
-+ /* XXX this update should be removed, I think. But it's
-+ * good for debugging */
-+ if (display->get_update_mode(display) ==
-+ OMAP_DSS_UPDATE_MANUAL) {
-+ u16 w, h;
-+
-+ if (display->sync)
-+ display->sync(display);
-+
-+ display->get_resolution(display, &w, &h);
-+ display->update(display, 0, 0, w, h);
-+ }
-+ }
-+#endif
-+
-+ if (display && display->sync)
-+ display->sync(display);
-+
-+ omapfb_unlock(fbdev);
-+
-+ return 0;
-+}
-+
-+/* setup overlay according to the fb */
-+static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
-+ u16 posx, u16 posy, u16 outw, u16 outh)
-+{
-+ int r = 0;
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct fb_var_screeninfo *var = &fbi->var;
-+ struct fb_fix_screeninfo *fix = &fbi->fix;
-+ enum omap_color_mode mode = 0;
-+ int offset;
-+ u32 data_start_p;
-+ void __iomem *data_start_v;
-+ struct omap_overlay_info info;
-+ int xres, yres;
-+ int screen_width;
-+ int rot, mirror;
-+
-+ DBG("setup_overlay %d, posx %d, posy %d, outw %d, outh %d\n", ofbi->id,
-+ posx, posy, outw, outh);
-+
-+ if (ofbi->rotation == FB_ROTATE_CW || ofbi->rotation == FB_ROTATE_CCW) {
-+ xres = var->yres;
-+ yres = var->xres;
-+ } else {
-+ xres = var->xres;
-+ yres = var->yres;
-+ }
-+
-+ offset = ((var->yoffset * var->xres_virtual +
-+ var->xoffset) * var->bits_per_pixel) >> 3;
-+
-+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
-+ data_start_p = omapfb_get_region_rot_paddr(ofbi);
-+ data_start_v = NULL;
-+ } else {
-+ data_start_p = omapfb_get_region_paddr(ofbi);
-+ data_start_v = omapfb_get_region_vaddr(ofbi);
-+ }
-+
-+ data_start_p += offset;
-+ data_start_v += offset;
-+
-+ mode = fb_mode_to_dss_mode(var);
-+
-+ if (mode == -EINVAL) {
-+ DBG("fb_mode_to_dss_mode failed");
-+ r = -EINVAL;
-+ goto err;
-+ }
-+
-+ screen_width = fix->line_length / (var->bits_per_pixel >> 3);
-+
-+ ovl->get_overlay_info(ovl, &info);
-+
-+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
-+ rot = 0;
-+ mirror = 0;
-+ } else {
-+ rot = ofbi->rotation;
-+ mirror = ofbi->mirror;
-+ }
-+
-+ info.paddr = data_start_p;
-+ info.vaddr = data_start_v;
-+ info.screen_width = screen_width;
-+ info.width = xres;
-+ info.height = yres;
-+ info.color_mode = mode;
-+ info.rotation = rot;
-+ info.mirror = mirror;
-+
-+ info.pos_x = posx;
-+ info.pos_y = posy;
-+ info.out_width = outw;
-+ info.out_height = outh;
-+
-+ r = ovl->set_overlay_info(ovl, &info);
-+ if (r) {
-+ DBG("ovl->setup_overlay_info failed\n");
-+ goto err;
-+ }
-+
-+ return 0;
-+
-+err:
-+ DBG("setup_overlay failed\n");
-+ return r;
-+}
-+
-+/* apply var to the overlay */
-+int omapfb_apply_changes(struct fb_info *fbi, int init)
-+{
-+ int r = 0;
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct fb_var_screeninfo *var = &fbi->var;
-+ struct omap_overlay *ovl;
-+ u16 posx, posy;
-+ u16 outw, outh;
-+ int i;
-+
-+#ifdef DEBUG
-+ if (omapfb_test_pattern)
-+ fill_fb(fbi);
-+#endif
-+
-+ for (i = 0; i < ofbi->num_overlays; i++) {
-+ ovl = ofbi->overlays[i];
-+
-+ DBG("apply_changes, fb %d, ovl %d\n", ofbi->id, ovl->id);
-+
-+ if (ofbi->region.size == 0) {
-+ /* the fb is not available. disable the overlay */
-+ omapfb_overlay_enable(ovl, 0);
-+ if (!init && ovl->manager)
-+ ovl->manager->apply(ovl->manager);
-+ continue;
-+ }
-+
-+ if (init || (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) {
-+ if (ofbi->rotation == FB_ROTATE_CW ||
-+ ofbi->rotation == FB_ROTATE_CCW) {
-+ outw = var->yres;
-+ outh = var->xres;
-+ } else {
-+ outw = var->xres;
-+ outh = var->yres;
-+ }
-+ } else {
-+ outw = ovl->info.out_width;
-+ outh = ovl->info.out_height;
-+ }
-+
-+ if (init) {
-+ posx = 0;
-+ posy = 0;
-+ } else {
-+ posx = ovl->info.pos_x;
-+ posy = ovl->info.pos_y;
-+ }
-+
-+ r = omapfb_setup_overlay(fbi, ovl, posx, posy, outw, outh);
-+ if (r)
-+ goto err;
-+
-+ if (!init && ovl->manager)
-+ ovl->manager->apply(ovl->manager);
-+ }
-+ return 0;
-+err:
-+ DBG("apply_changes failed\n");
-+ return r;
-+}
-+
-+/* checks var and eventually tweaks it to something supported,
-+ * DO NOT MODIFY PAR */
-+static int omapfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi)
-+{
-+ int r;
-+
-+ DBG("check_var(%d)\n", FB2OFB(fbi)->id);
-+
-+ r = check_fb_var(fbi, var);
-+
-+ return r;
-+}
-+
-+/* set the video mode according to info->var */
-+static int omapfb_set_par(struct fb_info *fbi)
-+{
-+ int r;
-+
-+ DBG("set_par(%d)\n", FB2OFB(fbi)->id);
-+
-+ set_fb_fix(fbi);
-+ r = omapfb_apply_changes(fbi, 0);
-+
-+ return r;
-+}
-+
-+static int omapfb_pan_display(struct fb_var_screeninfo *var,
-+ struct fb_info *fbi)
-+{
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+ int r = 0;
-+
-+ DBG("pan_display(%d)\n", ofbi->id);
-+
-+ omapfb_lock(fbdev);
-+
-+ if (var->xoffset != fbi->var.xoffset ||
-+ var->yoffset != fbi->var.yoffset) {
-+ struct fb_var_screeninfo new_var;
-+
-+ new_var = fbi->var;
-+ new_var.xoffset = var->xoffset;
-+ new_var.yoffset = var->yoffset;
-+
-+ r = check_fb_var(fbi, &new_var);
-+
-+ if (r == 0) {
-+ fbi->var = new_var;
-+ set_fb_fix(fbi);
-+ r = omapfb_apply_changes(fbi, 0);
-+ }
-+ }
-+
-+ omapfb_unlock(fbdev);
-+
-+ return r;
-+}
-+
-+static void mmap_user_open(struct vm_area_struct *vma)
-+{
-+ struct omapfb_info *ofbi = (struct omapfb_info *)vma->vm_private_data;
-+
-+ atomic_inc(&ofbi->map_count);
-+}
-+
-+static void mmap_user_close(struct vm_area_struct *vma)
-+{
-+ struct omapfb_info *ofbi = (struct omapfb_info *)vma->vm_private_data;
-+
-+ atomic_dec(&ofbi->map_count);
-+}
-+
-+static struct vm_operations_struct mmap_user_ops = {
-+ .open = mmap_user_open,
-+ .close = mmap_user_close,
-+};
-+
-+static int omapfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
-+{
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct fb_fix_screeninfo *fix = &fbi->fix;
-+ unsigned long off;
-+ unsigned long start;
-+ u32 len;
-+
-+ if (vma->vm_end - vma->vm_start == 0)
-+ return 0;
-+ if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
-+ return -EINVAL;
-+ off = vma->vm_pgoff << PAGE_SHIFT;
-+
-+ start = omapfb_get_region_paddr(ofbi);
-+ len = fix->smem_len;
-+ if (off >= len)
-+ return -EINVAL;
-+ if ((vma->vm_end - vma->vm_start + off) > len)
-+ return -EINVAL;
-+
-+ off += start;
-+
-+ DBG("user mmap region start %lx, len %d, off %lx\n", start, len, off);
-+
-+ vma->vm_pgoff = off >> PAGE_SHIFT;
-+ vma->vm_flags |= VM_IO | VM_RESERVED;
-+ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
-+ vma->vm_ops = &mmap_user_ops;
-+ vma->vm_private_data = ofbi;
-+ if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
-+ vma->vm_end - vma->vm_start, vma->vm_page_prot))
-+ return -EAGAIN;
-+ /* vm_ops.open won't be called for mmap itself. */
-+ atomic_inc(&ofbi->map_count);
-+ return 0;
-+}
-+
-+/* Store a single color palette entry into a pseudo palette or the hardware
-+ * palette if one is available. For now we support only 16bpp and thus store
-+ * the entry only to the pseudo palette.
-+ */
-+static int _setcolreg(struct fb_info *fbi, u_int regno, u_int red, u_int green,
-+ u_int blue, u_int transp, int update_hw_pal)
-+{
-+ /*struct omapfb_info *ofbi = FB2OFB(fbi);*/
-+ /*struct omapfb2_device *fbdev = ofbi->fbdev;*/
-+ struct fb_var_screeninfo *var = &fbi->var;
-+ int r = 0;
-+
-+ enum omapfb_color_format mode = OMAPFB_COLOR_RGB24U; /* XXX */
-+
-+ /*switch (plane->color_mode) {*/
-+ switch (mode) {
-+ case OMAPFB_COLOR_YUV422:
-+ case OMAPFB_COLOR_YUV420:
-+ case OMAPFB_COLOR_YUY422:
-+ r = -EINVAL;
-+ break;
-+ case OMAPFB_COLOR_CLUT_8BPP:
-+ case OMAPFB_COLOR_CLUT_4BPP:
-+ case OMAPFB_COLOR_CLUT_2BPP:
-+ case OMAPFB_COLOR_CLUT_1BPP:
-+ /*
-+ if (fbdev->ctrl->setcolreg)
-+ r = fbdev->ctrl->setcolreg(regno, red, green, blue,
-+ transp, update_hw_pal);
-+ */
-+ /* Fallthrough */
-+ r = -EINVAL;
-+ break;
-+ case OMAPFB_COLOR_RGB565:
-+ case OMAPFB_COLOR_RGB444:
-+ case OMAPFB_COLOR_RGB24P:
-+ case OMAPFB_COLOR_RGB24U:
-+ if (r != 0)
-+ break;
-+
-+ if (regno < 0) {
-+ r = -EINVAL;
-+ break;
-+ }
-+
-+ if (regno < 16) {
-+ u16 pal;
-+ pal = ((red >> (16 - var->red.length)) <<
-+ var->red.offset) |
-+ ((green >> (16 - var->green.length)) <<
-+ var->green.offset) |
-+ (blue >> (16 - var->blue.length));
-+ ((u32 *)(fbi->pseudo_palette))[regno] = pal;
-+ }
-+ break;
-+ default:
-+ BUG();
-+ }
-+ return r;
-+}
-+
-+static int omapfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
-+ u_int transp, struct fb_info *info)
-+{
-+ DBG("setcolreg\n");
-+
-+ return _setcolreg(info, regno, red, green, blue, transp, 1);
-+}
-+
-+static int omapfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
-+{
-+ int count, index, r;
-+ u16 *red, *green, *blue, *transp;
-+ u16 trans = 0xffff;
-+
-+ DBG("setcmap\n");
-+
-+ red = cmap->red;
-+ green = cmap->green;
-+ blue = cmap->blue;
-+ transp = cmap->transp;
-+ index = cmap->start;
-+
-+ for (count = 0; count < cmap->len; count++) {
-+ if (transp)
-+ trans = *transp++;
-+ r = _setcolreg(info, index++, *red++, *green++, *blue++, trans,
-+ count == cmap->len - 1);
-+ if (r != 0)
-+ return r;
-+ }
-+
-+ return 0;
-+}
-+
-+static int omapfb_blank(int blank, struct fb_info *fbi)
-+{
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+ struct omap_display *display = fb2display(fbi);
-+ int do_update = 0;
-+ int r = 0;
-+
-+ omapfb_lock(fbdev);
-+
-+ switch (blank) {
-+ case FB_BLANK_UNBLANK:
-+ if (display->state != OMAP_DSS_DISPLAY_SUSPENDED)
-+ goto exit;
-+
-+ if (display->resume)
-+ r = display->resume(display);
-+
-+ if (r == 0 && display->get_update_mode &&
-+ display->get_update_mode(display) ==
-+ OMAP_DSS_UPDATE_MANUAL)
-+ do_update = 1;
-+
-+ break;
-+
-+ case FB_BLANK_NORMAL:
-+ /* FB_BLANK_NORMAL could be implemented.
-+ * Needs DSS additions. */
-+ case FB_BLANK_VSYNC_SUSPEND:
-+ case FB_BLANK_HSYNC_SUSPEND:
-+ case FB_BLANK_POWERDOWN:
-+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
-+ goto exit;
-+
-+ if (display->suspend)
-+ r = display->suspend(display);
-+
-+ break;
-+
-+ default:
-+ r = -EINVAL;
-+ }
-+
-+exit:
-+ omapfb_unlock(fbdev);
-+
-+ if (r == 0 && do_update && display->update) {
-+ u16 w, h;
-+ display->get_resolution(display, &w, &h);
-+
-+ r = display->update(display, 0, 0, w, h);
-+ }
-+
-+ return r;
-+}
-+
-+#if 0
-+/* XXX fb_read and fb_write are needed for VRFB */
-+ssize_t omapfb_write(struct fb_info *info, const char __user *buf,
-+ size_t count, loff_t *ppos)
-+{
-+ DBG("omapfb_write %d, %lu\n", count, (unsigned long)*ppos);
-+ // XXX needed for VRFB
-+ return count;
-+}
-+#endif
-+
-+static struct fb_ops omapfb_ops = {
-+ .owner = THIS_MODULE,
-+ .fb_open = omapfb_open,
-+ .fb_release = omapfb_release,
-+ .fb_fillrect = cfb_fillrect,
-+ .fb_copyarea = cfb_copyarea,
-+ .fb_imageblit = cfb_imageblit,
-+ .fb_blank = omapfb_blank,
-+ .fb_ioctl = omapfb_ioctl,
-+ .fb_check_var = omapfb_check_var,
-+ .fb_set_par = omapfb_set_par,
-+ .fb_pan_display = omapfb_pan_display,
-+ .fb_mmap = omapfb_mmap,
-+ .fb_setcolreg = omapfb_setcolreg,
-+ .fb_setcmap = omapfb_setcmap,
-+ //.fb_write = omapfb_write,
-+};
-+
-+static void omapfb_free_fbmem(struct fb_info *fbi)
-+{
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+ struct omapfb2_mem_region *rg;
-+
-+ rg = &ofbi->region;
-+
-+ if (rg->paddr)
-+ if (omap_vram_free(rg->paddr, rg->size))
-+ dev_err(fbdev->dev, "VRAM FREE failed\n");
-+
-+ if (rg->vaddr)
-+ iounmap(rg->vaddr);
-+
-+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
-+ /* unmap the 0 angle rotation */
-+ if (rg->vrfb.vaddr[0]) {
-+ iounmap(rg->vrfb.vaddr[0]);
-+ omap_vrfb_release_ctx(&rg->vrfb);
-+ }
-+ }
-+
-+ rg->vaddr = NULL;
-+ rg->paddr = 0;
-+ rg->alloc = 0;
-+ rg->size = 0;
-+}
-+
-+static int omapfb_free_all_fbmem(struct omapfb2_device *fbdev)
-+{
-+ int i;
-+
-+ DBG("free all fbmem\n");
-+
-+ for (i = 0; i < fbdev->num_fbs; i++) {
-+ struct fb_info *fbi = fbdev->fbs[i];
-+ omapfb_free_fbmem(fbi);
-+ memset(&fbi->fix, 0, sizeof(fbi->fix));
-+ memset(&fbi->var, 0, sizeof(fbi->var));
-+ }
-+
-+ return 0;
-+}
-+
-+static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
-+ unsigned long paddr)
-+{
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+ struct omapfb2_mem_region *rg;
-+ void __iomem *vaddr;
-+ int r;
-+ int clear = 0;
-+
-+ rg = &ofbi->region;
-+ memset(rg, 0, sizeof(*rg));
-+
-+ size = PAGE_ALIGN(size);
-+
-+ if (!paddr) {
-+ DBG("allocating %lu bytes for fb %d\n", size, ofbi->id);
-+ r = omap_vram_alloc(OMAPFB_MEMTYPE_SDRAM, size, &paddr);
-+ clear = 1;
-+ } else {
-+ DBG("reserving %lu bytes at %lx for fb %d\n", size, paddr,
-+ ofbi->id);
-+ r = omap_vram_reserve(paddr, size);
-+ }
-+
-+ if (r) {
-+ dev_err(fbdev->dev, "failed to allocate framebuffer\n");
-+ return -ENOMEM;
-+ }
-+
-+ if (ofbi->rotation_type != OMAPFB_ROT_VRFB) {
-+ vaddr = ioremap_wc(paddr, size);
-+
-+ if (!vaddr) {
-+ dev_err(fbdev->dev, "failed to ioremap framebuffer\n");
-+ omap_vram_free(paddr, size);
-+ return -ENOMEM;
-+ }
-+
-+ DBG("allocated VRAM paddr %lx, vaddr %p\n", paddr, vaddr);
-+
-+ if (clear)
-+ memset_io(vaddr, 0, size);
-+ } else {
-+ void __iomem *va;
-+
-+ r = omap_vrfb_request_ctx(&rg->vrfb);
-+ if (r) {
-+ dev_err(fbdev->dev, "vrfb create ctx failed\n");
-+ return r;
-+ }
-+
-+ /* only ioremap the 0 angle view */
-+ va = ioremap_wc(rg->vrfb.paddr[0], size);
-+
-+ if(!va) {
-+ printk(KERN_ERR "vrfb: ioremap failed\n");
-+ return -ENOMEM;
-+ }
-+
-+ DBG("ioremapped vrfb area 0 to %p\n", va);
-+
-+ rg->vrfb.vaddr[0] = va;
-+
-+ vaddr = NULL;
-+
-+ if (clear)
-+ memset_io(va, 0, size);
-+ }
-+
-+ rg->paddr = paddr;
-+ rg->vaddr = vaddr;
-+ rg->size = size;
-+ rg->alloc = 1;
-+
-+ return 0;
-+}
-+
-+/* allocate fbmem using display resolution as reference */
-+static int omapfb_alloc_fbmem_display(struct fb_info *fbi, unsigned long size,
-+ unsigned long paddr)
-+{
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omap_display *display;
-+ int bytespp;
-+
-+ display = fb2display(fbi);
-+
-+ if (!display)
-+ return 0;
-+
-+ switch (display->get_recommended_bpp(display)) {
-+ case 16:
-+ bytespp = 2;
-+ break;
-+ case 24:
-+ bytespp = 4;
-+ break;
-+ default:
-+ bytespp = 4;
-+ break;
-+ }
-+
-+ if (!size) {
-+ u16 w, h;
-+
-+ display->get_resolution(display, &w, &h);
-+
-+ if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
-+ int oldw = w, oldh = h;
-+
-+ omap_vrfb_adjust_size(&w, &h, bytespp);
-+
-+ /* Because we change the resolution of the 0 degree view,
-+ * we need to alloc max(w, h) for height */
-+ h = max(w, h);
-+ w = OMAP_VRFB_LINE_LEN;
-+
-+ DBG("adjusting fb mem size for VRFB, %dx%d -> %dx%d\n",
-+ oldw, oldh, w, h);
-+ }
-+
-+ size = w * h * bytespp;
-+ }
-+
-+ return omapfb_alloc_fbmem(fbi, size, paddr);
-+}
-+
-+static int omapfb_parse_vram_param(const char *param, int max_entries,
-+ unsigned long *sizes, unsigned long *paddrs)
-+{
-+ int fbnum;
-+ unsigned long size;
-+ unsigned long paddr = 0;
-+ char *p, *start;
-+
-+ start = (char *)param;
-+
-+ while (1) {
-+ p = start;
-+
-+ fbnum = simple_strtoul(p, &p, 10);
-+
-+ if (p == param)
-+ return -EINVAL;
-+
-+ if (*p != ':')
-+ return -EINVAL;
-+
-+ if (fbnum >= max_entries)
-+ return -EINVAL;
-+
-+ size = memparse(p + 1, &p);
-+
-+ if (!size)
-+ return -EINVAL;
-+
-+ paddr = 0;
-+
-+ if (*p == '@') {
-+ paddr = simple_strtoul(p + 1, &p, 16);
-+
-+ if (!paddr)
-+ return -EINVAL;
-+
-+ }
-+
-+ paddrs[fbnum] = paddr;
-+ sizes[fbnum] = size;
-+
-+ if (*p == 0)
-+ break;
-+
-+ if (*p != ',')
-+ return -EINVAL;
-+
-+ ++p;
-+
-+ start = p;
-+ }
-+
-+ return 0;
-+}
-+
-+static int omapfb_allocate_all_fbs(struct omapfb2_device *fbdev)
-+{
-+ int i, r;
-+ unsigned long vram_sizes[10];
-+ unsigned long vram_paddrs[10];
-+
-+ memset(&vram_sizes, 0, sizeof(vram_sizes));
-+ memset(&vram_paddrs, 0, sizeof(vram_paddrs));
-+
-+ if (def_vram && omapfb_parse_vram_param(def_vram, 10,
-+ vram_sizes, vram_paddrs)) {
-+ dev_err(fbdev->dev, "failed to parse vram parameter\n");
-+
-+ memset(&vram_sizes, 0, sizeof(vram_sizes));
-+ memset(&vram_paddrs, 0, sizeof(vram_paddrs));
-+ }
-+
-+ if (fbdev->dev->platform_data) {
-+ struct omapfb_platform_data *opd;
-+ opd = fbdev->dev->platform_data;
-+ for (i = 0; i < opd->mem_desc.region_cnt; ++i) {
-+ if (!vram_sizes[i]) {
-+ unsigned long size;
-+ unsigned long paddr;
-+
-+ size = opd->mem_desc.region[i].size;
-+ paddr = opd->mem_desc.region[i].paddr;
-+
-+ vram_sizes[i] = size;
-+ vram_paddrs[i] = paddr;
-+ }
-+ }
-+ }
-+
-+ for (i = 0; i < fbdev->num_fbs; i++) {
-+ /* allocate memory automatically only for fb0, or if
-+ * excplicitly defined with vram or plat data option */
-+ if (i == 0 || vram_sizes[i] != 0) {
-+ r = omapfb_alloc_fbmem_display(fbdev->fbs[i],
-+ vram_sizes[i], vram_paddrs[i]);
-+
-+ if (r)
-+ return r;
-+ }
-+ }
-+
-+ for (i = 0; i < fbdev->num_fbs; i++) {
-+ struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
-+ struct omapfb2_mem_region *rg;
-+ rg = &ofbi->region;
-+
-+ DBG("region%d phys %08x virt %p size=%lu\n",
-+ i,
-+ rg->paddr,
-+ rg->vaddr,
-+ rg->size);
-+ }
-+
-+ return 0;
-+}
-+
-+int omapfb_realloc_fbmem(struct fb_info *fbi, unsigned long size, int type)
-+{
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+ struct omap_display *display = fb2display(fbi);
-+ struct omapfb2_mem_region *rg = &ofbi->region;
-+ unsigned long old_size = rg->size;
-+ unsigned long old_paddr = rg->paddr;
-+ int old_type = rg->type;
-+ int r;
-+
-+ if (type > OMAPFB_MEMTYPE_MAX)
-+ return -EINVAL;
-+
-+ size = PAGE_ALIGN(size);
-+
-+ if (old_size == size && old_type == type)
-+ return 0;
-+
-+ if (display && display->sync)
-+ display->sync(display);
-+
-+ omapfb_free_fbmem(fbi);
-+
-+ if (size == 0) {
-+ memset(&fbi->fix, 0, sizeof(fbi->fix));
-+ memset(&fbi->var, 0, sizeof(fbi->var));
-+ return 0;
-+ }
-+
-+ r = omapfb_alloc_fbmem(fbi, size, 0);
-+
-+ if (r) {
-+ if (old_size)
-+ omapfb_alloc_fbmem(fbi, old_size, old_paddr);
-+
-+ if (rg->size == 0) {
-+ memset(&fbi->fix, 0, sizeof(fbi->fix));
-+ memset(&fbi->var, 0, sizeof(fbi->var));
-+ }
-+
-+ return r;
-+ }
-+
-+ if (old_size == size)
-+ return 0;
-+
-+ if (old_size == 0) {
-+ DBG("initializing fb %d\n", ofbi->id);
-+ r = omapfb_fb_init(fbdev, fbi);
-+ if (r) {
-+ DBG("omapfb_fb_init failed\n");
-+ goto err;
-+ }
-+ r = omapfb_apply_changes(fbi, 1);
-+ if (r) {
-+ DBG("omapfb_apply_changes failed\n");
-+ goto err;
-+ }
-+ } else {
-+ struct fb_var_screeninfo new_var;
-+ memcpy(&new_var, &fbi->var, sizeof(new_var));
-+ r = check_fb_var(fbi, &new_var);
-+ if (r)
-+ goto err;
-+ memcpy(&fbi->var, &new_var, sizeof(fbi->var));
-+ set_fb_fix(fbi);
-+ }
-+
-+ return 0;
-+err:
-+ omapfb_free_fbmem(fbi);
-+ memset(&fbi->fix, 0, sizeof(fbi->fix));
-+ memset(&fbi->var, 0, sizeof(fbi->var));
-+ return r;
-+}
-+
-+/* initialize fb_info, var, fix to something sane based on the display */
-+int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi)
-+{
-+ struct fb_var_screeninfo *var = &fbi->var;
-+ struct fb_fix_screeninfo *fix = &fbi->fix;
-+ struct omap_display *display = fb2display(fbi);
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ int r = 0;
-+
-+ fbi->fbops = &omapfb_ops;
-+ fbi->flags = FBINFO_FLAG_DEFAULT;
-+ fbi->pseudo_palette = fbdev->pseudo_palette;
-+
-+ strncpy(fix->id, MODULE_NAME, sizeof(fix->id));
-+
-+ if (ofbi->region.size == 0) {
-+ memset(&fbi->fix, 0, sizeof(fbi->fix));
-+ memset(&fbi->var, 0, sizeof(fbi->var));
-+ return 0;
-+ }
-+
-+ var->nonstd = 0;
-+
-+ var->rotate = ofbi->rotation;
-+
-+ if (display) {
-+ u16 w, h;
-+ display->get_resolution(display, &w, &h);
-+
-+ if (ofbi->rotation == FB_ROTATE_CW ||
-+ ofbi->rotation == FB_ROTATE_CCW) {
-+ var->xres = h;
-+ var->yres = w;
-+ } else {
-+ var->xres = w;
-+ var->yres = h;
-+ }
-+
-+ var->xres_virtual = var->xres;
-+ var->yres_virtual = var->yres;
-+
-+ switch (display->get_recommended_bpp(display)) {
-+ case 16:
-+ var->bits_per_pixel = 16;
-+ break;
-+ case 24:
-+ var->bits_per_pixel = 32;
-+ break;
-+ default:
-+ dev_err(fbdev->dev, "illegal display bpp\n");
-+ return -EINVAL;
-+ }
-+ } else {
-+ /* if there's no display, let's just guess some basic values */
-+ var->xres = 320;
-+ var->yres = 240;
-+ var->xres_virtual = var->xres;
-+ var->yres_virtual = var->yres;
-+ var->bits_per_pixel = 16;
-+ }
-+
-+ r = check_fb_var(fbi, var);
-+ if (r)
-+ goto err;
-+
-+ set_fb_fix(fbi);
-+err:
-+ return r;
-+}
-+
-+static void fbinfo_cleanup(struct omapfb2_device *fbdev, struct fb_info *fbi)
-+{
-+ fb_dealloc_cmap(&fbi->cmap);
-+}
-+
-+
-+static void omapfb_free_resources(struct omapfb2_device *fbdev)
-+{
-+ int i;
-+
-+ DBG("free_resources\n");
-+
-+ if (fbdev == NULL)
-+ return;
-+
-+ for (i = 0; i < fbdev->num_fbs; i++)
-+ unregister_framebuffer(fbdev->fbs[i]);
-+
-+ /* free the reserved fbmem */
-+ omapfb_free_all_fbmem(fbdev);
-+
-+ for (i = 0; i < fbdev->num_fbs; i++) {
-+ fbinfo_cleanup(fbdev, fbdev->fbs[i]);
-+ framebuffer_release(fbdev->fbs[i]);
-+ }
-+
-+ for (i = 0; i < fbdev->num_displays; i++) {
-+ if (fbdev->displays[i]->state != OMAP_DSS_DISPLAY_DISABLED)
-+ fbdev->displays[i]->disable(fbdev->displays[i]);
-+
-+ omap_dss_put_display(fbdev->displays[i]);
-+ }
-+
-+ dev_set_drvdata(fbdev->dev, NULL);
-+ kfree(fbdev);
-+}
-+
-+static int omapfb_create_framebuffers(struct omapfb2_device *fbdev)
-+{
-+ int r, i;
-+
-+ fbdev->num_fbs = 0;
-+
-+ DBG("create %d framebuffers\n", CONFIG_FB_OMAP2_NUM_FBS);
-+
-+ /* allocate fb_infos */
-+ for (i = 0; i < CONFIG_FB_OMAP2_NUM_FBS; i++) {
-+ struct fb_info *fbi;
-+ struct omapfb_info *ofbi;
-+
-+ fbi = framebuffer_alloc(sizeof(struct omapfb_info),
-+ fbdev->dev);
-+
-+ if (fbi == NULL) {
-+ dev_err(fbdev->dev,
-+ "unable to allocate memory for plane info\n");
-+ return -ENOMEM;
-+ }
-+
-+ fbdev->fbs[i] = fbi;
-+
-+ ofbi = FB2OFB(fbi);
-+ ofbi->fbdev = fbdev;
-+ ofbi->id = i;
-+
-+ /* assign these early, so that fb alloc can use them */
-+ ofbi->rotation_type = def_vrfb ? OMAPFB_ROT_VRFB :
-+ OMAPFB_ROT_DMA;
-+ ofbi->rotation = def_rotate;
-+ ofbi->mirror = def_mirror;
-+
-+ fbdev->num_fbs++;
-+ }
-+
-+ DBG("fb_infos allocated\n");
-+
-+ /* assign overlays for the fbs */
-+ for (i = 0; i < min(fbdev->num_fbs, fbdev->num_overlays); i++) {
-+ struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
-+
-+ ofbi->overlays[0] = fbdev->overlays[i];
-+ ofbi->num_overlays = 1;
-+ }
-+
-+ /* allocate fb memories */
-+ r = omapfb_allocate_all_fbs(fbdev);
-+ if (r) {
-+ dev_err(fbdev->dev, "failed to allocate fbmem\n");
-+ return r;
-+ }
-+
-+ DBG("fbmems allocated\n");
-+
-+ /* setup fb_infos */
-+ for (i = 0; i < fbdev->num_fbs; i++) {
-+ r = omapfb_fb_init(fbdev, fbdev->fbs[i]);
-+ if (r) {
-+ dev_err(fbdev->dev, "failed to setup fb_info\n");
-+ return r;
-+ }
-+ }
-+
-+ DBG("fb_infos initialized\n");
-+
-+ for (i = 0; i < fbdev->num_fbs; i++) {
-+ r = register_framebuffer(fbdev->fbs[i]);
-+ if (r != 0) {
-+ dev_err(fbdev->dev,
-+ "registering framebuffer %d failed\n", i);
-+ return r;
-+ }
-+ }
-+
-+ DBG("framebuffers registered\n");
-+
-+ for (i = 0; i < fbdev->num_fbs; i++) {
-+ r = omapfb_apply_changes(fbdev->fbs[i], 1);
-+ if (r) {
-+ dev_err(fbdev->dev, "failed to change mode\n");
-+ return r;
-+ }
-+ }
-+
-+ DBG("create sysfs for fbs\n");
-+ r = omapfb_create_sysfs(fbdev);
-+ if (r) {
-+ dev_err(fbdev->dev, "failed to create sysfs entries\n");
-+ return r;
-+ }
-+
-+ /* Enable fb0 */
-+ if (fbdev->num_fbs > 0) {
-+ struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[0]);
-+
-+ if (ofbi->num_overlays > 0 ) {
-+ struct omap_overlay *ovl = ofbi->overlays[0];
-+
-+ r = omapfb_overlay_enable(ovl, 1);
-+
-+ if (r) {
-+ dev_err(fbdev->dev,
-+ "failed to enable overlay\n");
-+ return r;
-+ }
-+ }
-+ }
-+
-+ DBG("create_framebuffers done\n");
-+
-+ return 0;
-+}
-+
-+int omapfb_mode_to_timings(const char *mode_str,
-+ struct omap_video_timings *timings, u8 *bpp)
-+{
-+ struct fb_info fbi;
-+ struct fb_var_screeninfo var;
-+ struct fb_ops fbops;
-+ int r;
-+
-+#ifdef CONFIG_OMAP2_DSS_VENC
-+ if (strcmp(mode_str, "pal") == 0) {
-+ *timings = omap_dss_pal_timings;
-+ *bpp = 0;
-+ return 0;
-+ } else if (strcmp(mode_str, "ntsc") == 0) {
-+ *timings = omap_dss_ntsc_timings;
-+ *bpp = 0;
-+ return 0;
-+ }
-+#endif
-+
-+ /* this is quite a hack, but I wanted to use the modedb and for
-+ * that we need fb_info and var, so we create dummy ones */
-+
-+ memset(&fbi, 0, sizeof(fbi));
-+ memset(&var, 0, sizeof(var));
-+ memset(&fbops, 0, sizeof(fbops));
-+ fbi.fbops = &fbops;
-+
-+ r = fb_find_mode(&var, &fbi, mode_str, NULL, 0, NULL, 24);
-+
-+ if (r != 0) {
-+ timings->pixel_clock = PICOS2KHZ(var.pixclock);
-+ timings->hfp = var.left_margin;
-+ timings->hbp = var.right_margin;
-+ timings->vfp = var.upper_margin;
-+ timings->vbp = var.lower_margin;
-+ timings->hsw = var.hsync_len;
-+ timings->vsw = var.vsync_len;
-+ timings->x_res = var.xres;
-+ timings->y_res = var.yres;
-+
-+ switch (var.bits_per_pixel) {
-+ case 16:
-+ *bpp = 16;
-+ break;
-+ case 24:
-+ case 32:
-+ default:
-+ *bpp = 24;
-+ break;
-+ }
-+
-+ return 0;
-+ } else {
-+ return -EINVAL;
-+ }
-+}
-+
-+static int omapfb_set_def_mode(struct omap_display *display, char *mode_str)
-+{
-+ int r;
-+ u8 bpp;
-+ struct omap_video_timings timings;
-+
-+ r = omapfb_mode_to_timings(mode_str, &timings, &bpp);
-+ if (r)
-+ return r;
-+
-+ display->panel->recommended_bpp = bpp;
-+
-+ if (!display->check_timings || !display->set_timings)
-+ return -EINVAL;
-+
-+ r = display->check_timings(display, &timings);
-+ if (r)
-+ return r;
-+
-+ display->set_timings(display, &timings);
-+
-+ return 0;
-+}
-+
-+static int omapfb_parse_def_modes(struct omapfb2_device *fbdev)
-+{
-+ char *str, *options, *this_opt;
-+ int r = 0;
-+
-+ str = kmalloc(strlen(def_mode) + 1, GFP_KERNEL);
-+ strcpy(str, def_mode);
-+ options = str;
-+
-+ while (!r && (this_opt = strsep(&options, ",")) != NULL) {
-+ char *p, *display_str, *mode_str;
-+ struct omap_display *display;
-+ int i;
-+
-+ p = strchr(this_opt, ':');
-+ if (!p) {
-+ r = -EINVAL;
-+ break;
-+ }
-+
-+ *p = 0;
-+ display_str = this_opt;
-+ mode_str = p + 1;
-+
-+ display = NULL;
-+ for (i = 0; i < fbdev->num_displays; ++i) {
-+ if (strcmp(fbdev->displays[i]->name,
-+ display_str) == 0) {
-+ display = fbdev->displays[i];
-+ break;
-+ }
-+ }
-+
-+ if (!display) {
-+ r = -EINVAL;
-+ break;
-+ }
-+
-+ r = omapfb_set_def_mode(display, mode_str);
-+ if (r)
-+ break;
-+ }
-+
-+ kfree(str);
-+
-+ return r;
-+}
-+
-+static int omapfb_probe(struct platform_device *pdev)
-+{
-+ struct omapfb2_device *fbdev = NULL;
-+ int r = 0;
-+ int i, t;
-+ struct omap_overlay *ovl;
-+ struct omap_display *def_display;
-+
-+ DBG("omapfb_probe\n");
-+
-+ if (pdev->num_resources != 0) {
-+ dev_err(&pdev->dev, "probed for an unknown device\n");
-+ r = -ENODEV;
-+ goto err0;
-+ }
-+
-+ fbdev = kzalloc(sizeof(struct omapfb2_device), GFP_KERNEL);
-+ if (fbdev == NULL) {
-+ r = -ENOMEM;
-+ goto err0;
-+ }
-+
-+ mutex_init(&fbdev->mtx);
-+
-+ fbdev->dev = &pdev->dev;
-+ platform_set_drvdata(pdev, fbdev);
-+
-+ fbdev->num_displays = 0;
-+ t = omap_dss_get_num_displays();
-+ for (i = 0; i < t; i++) {
-+ struct omap_display *display;
-+ display = omap_dss_get_display(i);
-+ if (!display) {
-+ dev_err(&pdev->dev, "can't get display %d\n", i);
-+ r = -EINVAL;
-+ goto cleanup;
-+ }
-+
-+ fbdev->displays[fbdev->num_displays++] = display;
-+ }
-+
-+ if (fbdev->num_displays == 0) {
-+ dev_err(&pdev->dev, "no displays\n");
-+ r = -EINVAL;
-+ goto cleanup;
-+ }
-+
-+ fbdev->num_overlays = omap_dss_get_num_overlays();
-+ for (i = 0; i < fbdev->num_overlays; i++)
-+ fbdev->overlays[i] = omap_dss_get_overlay(i);
-+
-+ fbdev->num_managers = omap_dss_get_num_overlay_managers();
-+ for (i = 0; i < fbdev->num_managers; i++)
-+ fbdev->managers[i] = omap_dss_get_overlay_manager(i);
-+
-+
-+ /* gfx overlay should be the default one. find a display
-+ * connected to that, and use it as default display */
-+ ovl = omap_dss_get_overlay(0);
-+ if (ovl->manager && ovl->manager->display) {
-+ def_display = ovl->manager->display;
-+ } else {
-+ dev_err(&pdev->dev, "cannot find default display\n");
-+ r = -EINVAL;
-+ goto cleanup;
-+ }
-+
-+ if (def_mode && strlen(def_mode) > 0) {
-+ if (omapfb_parse_def_modes(fbdev))
-+ dev_err(&pdev->dev, "cannot parse default modes\n");
-+ }
-+
-+ r = omapfb_create_framebuffers(fbdev);
-+ if (r)
-+ goto cleanup;
-+
-+ for (i = 0; i < fbdev->num_managers; i++) {
-+ struct omap_overlay_manager *mgr;
-+ mgr = fbdev->managers[i];
-+ r = mgr->apply(mgr);
-+ if (r) {
-+ dev_err(fbdev->dev, "failed to apply dispc config\n");
-+ goto cleanup;
-+ }
-+ }
-+
-+ DBG("mgr->apply'ed\n");
-+
-+ r = def_display->enable(def_display);
-+ if (r) {
-+ dev_err(fbdev->dev, "Failed to enable display '%s'\n",
-+ def_display->name);
-+ goto cleanup;
-+ }
-+
-+ /* set the update mode */
-+ if (def_display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
-+#ifdef CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE
-+ if (def_display->set_update_mode)
-+ def_display->set_update_mode(def_display,
-+ OMAP_DSS_UPDATE_AUTO);
-+ if (def_display->enable_te)
-+ def_display->enable_te(def_display, 1);
-+#else
-+ if (def_display->set_update_mode)
-+ def_display->set_update_mode(def_display,
-+ OMAP_DSS_UPDATE_MANUAL);
-+ if (def_display->enable_te)
-+ def_display->enable_te(def_display, 0);
-+#endif
-+ } else {
-+ if (def_display->set_update_mode)
-+ def_display->set_update_mode(def_display,
-+ OMAP_DSS_UPDATE_AUTO);
-+ }
-+
-+ for (i = 0; i < fbdev->num_displays; i++) {
-+ struct omap_display *display = fbdev->displays[i];
-+ u16 w, h;
-+
-+ if (!display->get_update_mode || !display->update)
-+ continue;
-+
-+ if (display->get_update_mode(display) ==
-+ OMAP_DSS_UPDATE_MANUAL) {
-+
-+ display->get_resolution(display, &w, &h);
-+ display->update(display, 0, 0, w, h);
-+ }
-+ }
-+
-+ DBG("display->updated\n");
-+
-+ return 0;
-+
-+cleanup:
-+ omapfb_free_resources(fbdev);
-+err0:
-+ dev_err(&pdev->dev, "failed to setup omapfb\n");
-+ return r;
-+}
-+
-+static int omapfb_remove(struct platform_device *pdev)
-+{
-+ struct omapfb2_device *fbdev = platform_get_drvdata(pdev);
-+
-+ /* FIXME: wait till completion of pending events */
-+
-+ omapfb_remove_sysfs(fbdev);
-+
-+ omapfb_free_resources(fbdev);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver omapfb_driver = {
-+ .probe = omapfb_probe,
-+ .remove = omapfb_remove,
-+ .driver = {
-+ .name = "omapfb",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int __init omapfb_init(void)
-+{
-+ DBG("omapfb_init\n");
-+
-+ if (platform_driver_register(&omapfb_driver)) {
-+ printk(KERN_ERR "failed to register omapfb driver\n");
-+ return -ENODEV;
-+ }
-+
-+ return 0;
-+}
-+
-+static void __exit omapfb_exit(void)
-+{
-+ DBG("omapfb_exit\n");
-+ platform_driver_unregister(&omapfb_driver);
-+}
-+
-+module_param_named(mode, def_mode, charp, 0);
-+module_param_named(vram, def_vram, charp, 0);
-+module_param_named(rotate, def_rotate, int, 0);
-+module_param_named(vrfb, def_vrfb, bool, 0);
-+module_param_named(mirror, def_mirror, bool, 0);
-+
-+/* late_initcall to let panel/ctrl drivers loaded first.
-+ * I guess better option would be a more dynamic approach,
-+ * so that omapfb reacts to new panels when they are loaded */
-+late_initcall(omapfb_init);
-+/*module_init(omapfb_init);*/
-+module_exit(omapfb_exit);
-+
-+MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
-+MODULE_DESCRIPTION("OMAP2/3 Framebuffer");
-+MODULE_LICENSE("GPL v2");
-diff --git a/drivers/video/omap2/omapfb/omapfb-sysfs.c b/drivers/video/omap2/omapfb/omapfb-sysfs.c
-new file mode 100644
-index 0000000..2c88718
---- /dev/null
-+++ b/drivers/video/omap2/omapfb/omapfb-sysfs.c
-@@ -0,0 +1,371 @@
-+/*
-+ * linux/drivers/video/omap2/omapfb-sysfs.c
-+ *
-+ * Copyright (C) 2008 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * Some code and ideas taken from drivers/video/omap/ driver
-+ * by Imre Deak.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#include <linux/fb.h>
-+#include <linux/sysfs.h>
-+#include <linux/device.h>
-+#include <linux/uaccess.h>
-+#include <linux/platform_device.h>
-+#include <linux/kernel.h>
-+#include <linux/mm.h>
-+#include <linux/omapfb.h>
-+
-+#include <mach/display.h>
-+#include <mach/vrfb.h>
-+
-+#include "omapfb.h"
-+
-+static ssize_t show_rotate_type(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct fb_info *fbi = dev_get_drvdata(dev);
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+
-+ return snprintf(buf, PAGE_SIZE, "%d\n", ofbi->rotation_type);
-+}
-+
-+static ssize_t show_mirror(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct fb_info *fbi = dev_get_drvdata(dev);
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+
-+ return snprintf(buf, PAGE_SIZE, "%d\n", ofbi->mirror);
-+}
-+
-+static ssize_t store_mirror(struct device *dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ struct fb_info *fbi = dev_get_drvdata(dev);
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+ bool mirror;
-+ int r;
-+ struct fb_var_screeninfo new_var;
-+
-+ mirror = simple_strtoul(buf, NULL, 0);
-+
-+ if (mirror != 0 && mirror != 1)
-+ return -EINVAL;
-+
-+ omapfb_lock(fbdev);
-+
-+ ofbi->mirror = mirror;
-+
-+ memcpy(&new_var, &fbi->var, sizeof(new_var));
-+ r = check_fb_var(fbi, &new_var);
-+ if (r)
-+ goto out;
-+ memcpy(&fbi->var, &new_var, sizeof(fbi->var));
-+
-+ set_fb_fix(fbi);
-+
-+ r = omapfb_apply_changes(fbi, 0);
-+ if (r)
-+ goto out;
-+
-+ r = count;
-+out:
-+ omapfb_unlock(fbdev);
-+
-+ return r;
-+}
-+
-+static ssize_t show_overlays(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct fb_info *fbi = dev_get_drvdata(dev);
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+ ssize_t l = 0;
-+ int t;
-+
-+ for (t = 0; t < ofbi->num_overlays; t++) {
-+ struct omap_overlay *ovl = ofbi->overlays[t];
-+ int ovlnum;
-+
-+ for (ovlnum = 0; ovlnum < fbdev->num_overlays; ++ovlnum)
-+ if (ovl == fbdev->overlays[ovlnum])
-+ break;
-+
-+ l += snprintf(buf + l, PAGE_SIZE - l, "%s%d",
-+ t == 0 ? "" : ",", ovlnum);
-+ }
-+
-+ l += snprintf(buf + l, PAGE_SIZE - l, "\n");
-+
-+ return l;
-+}
-+
-+static struct omapfb_info *get_overlay_fb(struct omapfb2_device *fbdev,
-+ struct omap_overlay *ovl)
-+{
-+ int i, t;
-+
-+ for (i = 0; i < fbdev->num_fbs; i++) {
-+ struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
-+
-+ for (t = 0; t < ofbi->num_overlays; t++) {
-+ if (ofbi->overlays[t] == ovl)
-+ return ofbi;
-+ }
-+ }
-+
-+ return NULL;
-+}
-+
-+static ssize_t store_overlays(struct device *dev, struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ struct fb_info *fbi = dev_get_drvdata(dev);
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+ struct omap_overlay *ovls[OMAPFB_MAX_OVL_PER_FB];
-+ struct omap_overlay *ovl;
-+ int num_ovls, r, i;
-+ int len;
-+
-+ num_ovls = 0;
-+
-+ len = strlen(buf);
-+ if (buf[len - 1] == '\n')
-+ len = len - 1;
-+
-+ omapfb_lock(fbdev);
-+
-+ if (len > 0) {
-+ char *p = (char *)buf;
-+ int ovlnum;
-+
-+ while (p < buf + len) {
-+ int found;
-+ if (num_ovls == OMAPFB_MAX_OVL_PER_FB) {
-+ r = -EINVAL;
-+ goto out;
-+ }
-+
-+ ovlnum = simple_strtoul(p, &p, 0);
-+ if (ovlnum > fbdev->num_overlays) {
-+ r = -EINVAL;
-+ goto out;
-+ }
-+
-+ found = 0;
-+ for (i = 0; i < num_ovls; ++i) {
-+ if (ovls[i] == fbdev->overlays[ovlnum]) {
-+ found = 1;
-+ break;
-+ }
-+ }
-+
-+ if (!found)
-+ ovls[num_ovls++] = fbdev->overlays[ovlnum];
-+
-+ p++;
-+ }
-+ }
-+
-+ for (i = 0; i < num_ovls; ++i) {
-+ struct omapfb_info *ofbi2 = get_overlay_fb(fbdev, ovls[i]);
-+ if (ofbi2 && ofbi2 != ofbi) {
-+ dev_err(fbdev->dev, "overlay already in use\n");
-+ r = -EINVAL;
-+ goto out;
-+ }
-+ }
-+
-+ /* detach unused overlays */
-+ for (i = 0; i < ofbi->num_overlays; ++i) {
-+ int t, found;
-+
-+ ovl = ofbi->overlays[i];
-+
-+ found = 0;
-+
-+ for (t = 0; t < num_ovls; ++t) {
-+ if (ovl == ovls[t]) {
-+ found = 1;
-+ break;
-+ }
-+ }
-+
-+ if (found)
-+ continue;
-+
-+ DBG("detaching %d\n", ofbi->overlays[i]->id);
-+
-+ omapfb_overlay_enable(ovl, 0);
-+
-+ if (ovl->manager)
-+ ovl->manager->apply(ovl->manager);
-+
-+ for (t = i + 1; t < ofbi->num_overlays; t++)
-+ ofbi->overlays[t-1] = ofbi->overlays[t];
-+
-+ ofbi->num_overlays--;
-+ i--;
-+ }
-+
-+ for (i = 0; i < num_ovls; ++i) {
-+ int t, found;
-+
-+ ovl = ovls[i];
-+
-+ found = 0;
-+
-+ for (t = 0; t < ofbi->num_overlays; ++t) {
-+ if (ovl == ofbi->overlays[t]) {
-+ found = 1;
-+ break;
-+ }
-+ }
-+
-+ if (found)
-+ continue;
-+
-+ ofbi->overlays[ofbi->num_overlays++] = ovl;
-+
-+ r = omapfb_apply_changes(fbi, 1);
-+ if (r)
-+ goto out;
-+
-+ if (ovl->manager) {
-+ r = ovl->manager->apply(ovl->manager);
-+ if (r)
-+ goto out;
-+ }
-+ }
-+
-+ r = count;
-+out:
-+ omapfb_unlock(fbdev);
-+
-+ return r;
-+}
-+
-+static ssize_t show_size(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct fb_info *fbi = dev_get_drvdata(dev);
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+
-+ return snprintf(buf, PAGE_SIZE, "%lu\n", ofbi->region.size);
-+}
-+
-+static ssize_t store_size(struct device *dev, struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ struct fb_info *fbi = dev_get_drvdata(dev);
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+ unsigned long size;
-+ int r;
-+ int i;
-+
-+ size = PAGE_ALIGN(simple_strtoul(buf, NULL, 0));
-+
-+ omapfb_lock(fbdev);
-+
-+ for (i = 0; i < ofbi->num_overlays; i++) {
-+ if (ofbi->overlays[i]->info.enabled) {
-+ r = -EBUSY;
-+ goto out;
-+ }
-+ }
-+
-+ if (size != ofbi->region.size) {
-+ r = omapfb_realloc_fbmem(fbi, size, ofbi->region.type);
-+ if (r) {
-+ dev_err(dev, "realloc fbmem failed\n");
-+ goto out;
-+ }
-+ }
-+
-+ r = count;
-+out:
-+ omapfb_unlock(fbdev);
-+
-+ return r;
-+}
-+
-+static ssize_t show_phys(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct fb_info *fbi = dev_get_drvdata(dev);
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+
-+ return snprintf(buf, PAGE_SIZE, "%0x\n", ofbi->region.paddr);
-+}
-+
-+static ssize_t show_virt(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct fb_info *fbi = dev_get_drvdata(dev);
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+
-+ return snprintf(buf, PAGE_SIZE, "%p\n", ofbi->region.vaddr);
-+}
-+
-+static struct device_attribute omapfb_attrs[] = {
-+ __ATTR(rotate_type, S_IRUGO, show_rotate_type, NULL),
-+ __ATTR(mirror, S_IRUGO | S_IWUSR, show_mirror, store_mirror),
-+ __ATTR(size, S_IRUGO | S_IWUSR, show_size, store_size),
-+ __ATTR(overlays, S_IRUGO | S_IWUSR, show_overlays, store_overlays),
-+ __ATTR(phys_addr, S_IRUGO, show_phys, NULL),
-+ __ATTR(virt_addr, S_IRUGO, show_virt, NULL),
-+};
-+
-+int omapfb_create_sysfs(struct omapfb2_device *fbdev)
-+{
-+ int i;
-+ int r;
-+
-+ DBG("create sysfs for fbs\n");
-+ for (i = 0; i < fbdev->num_fbs; i++) {
-+ int t;
-+ for (t = 0; t < ARRAY_SIZE(omapfb_attrs); t++) {
-+ r = device_create_file(fbdev->fbs[i]->dev,
-+ &omapfb_attrs[t]);
-+
-+ if (r) {
-+ dev_err(fbdev->dev, "failed to create sysfs file\n");
-+ return r;
-+ }
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+void omapfb_remove_sysfs(struct omapfb2_device *fbdev)
-+{
-+ int i, t;
-+
-+ DBG("remove sysfs for fbs\n");
-+ for (i = 0; i < fbdev->num_fbs; i++) {
-+ for (t = 0; t < ARRAY_SIZE(omapfb_attrs); t++)
-+ device_remove_file(fbdev->fbs[i]->dev,
-+ &omapfb_attrs[t]);
-+ }
-+}
-+
-diff --git a/drivers/video/omap2/omapfb/omapfb.h b/drivers/video/omap2/omapfb/omapfb.h
-new file mode 100644
-index 0000000..65e9e6e
---- /dev/null
-+++ b/drivers/video/omap2/omapfb/omapfb.h
-@@ -0,0 +1,153 @@
-+/*
-+ * linux/drivers/video/omap2/omapfb.h
-+ *
-+ * Copyright (C) 2008 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * Some code and ideas taken from drivers/video/omap/ driver
-+ * by Imre Deak.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#ifndef __DRIVERS_VIDEO_OMAP2_OMAPFB_H__
-+#define __DRIVERS_VIDEO_OMAP2_OMAPFB_H__
-+
-+#ifdef CONFIG_FB_OMAP2_DEBUG_SUPPORT
-+#define DEBUG
-+#endif
-+
-+#ifdef DEBUG
-+extern unsigned int omapfb_debug;
-+#define DBG(format, ...) \
-+ if (omapfb_debug) \
-+ printk(KERN_DEBUG "OMAPFB: " format, ## __VA_ARGS__)
-+#else
-+#define DBG(format, ...)
-+#endif
-+
-+#define FB2OFB(fb_info) ((struct omapfb_info *)(fb_info->par))
-+
-+/* max number of overlays to which a framebuffer data can be direct */
-+#define OMAPFB_MAX_OVL_PER_FB 3
-+
-+struct omapfb2_mem_region {
-+ u32 paddr;
-+ void __iomem *vaddr;
-+ struct vrfb vrfb;
-+ unsigned long size;
-+ u8 type; /* OMAPFB_PLANE_MEM_* */
-+ bool alloc; /* allocated by the driver */
-+ bool map; /* kernel mapped by the driver */
-+};
-+
-+enum omapfb_rotation_type {
-+ OMAPFB_ROT_DMA = 0,
-+ OMAPFB_ROT_VRFB = 1,
-+};
-+
-+/* appended to fb_info */
-+struct omapfb_info {
-+ int id;
-+ struct omapfb2_mem_region region;
-+ atomic_t map_count;
-+ int num_overlays;
-+ struct omap_overlay *overlays[OMAPFB_MAX_OVL_PER_FB];
-+ struct omapfb2_device *fbdev;
-+ enum omapfb_rotation_type rotation_type;
-+ u8 rotation;
-+ bool mirror;
-+};
-+
-+struct omapfb2_device {
-+ struct device *dev;
-+ struct mutex mtx;
-+
-+ u32 pseudo_palette[17];
-+
-+ int state;
-+
-+ unsigned num_fbs;
-+ struct fb_info *fbs[10];
-+
-+ unsigned num_displays;
-+ struct omap_display *displays[10];
-+ unsigned num_overlays;
-+ struct omap_overlay *overlays[10];
-+ unsigned num_managers;
-+ struct omap_overlay_manager *managers[10];
-+};
-+
-+struct omapfb_colormode {
-+ enum omap_color_mode dssmode;
-+ u32 bits_per_pixel;
-+ u32 nonstd;
-+ struct fb_bitfield red;
-+ struct fb_bitfield green;
-+ struct fb_bitfield blue;
-+ struct fb_bitfield transp;
-+};
-+
-+u32 omapfb_get_region_paddr(struct omapfb_info *ofbi);
-+void __iomem *omapfb_get_region_vaddr(struct omapfb_info *ofbi);
-+
-+void set_fb_fix(struct fb_info *fbi);
-+int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var);
-+int omapfb_realloc_fbmem(struct fb_info *fbi, unsigned long size, int type);
-+int omapfb_apply_changes(struct fb_info *fbi, int init);
-+int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi);
-+
-+int omapfb_create_sysfs(struct omapfb2_device *fbdev);
-+void omapfb_remove_sysfs(struct omapfb2_device *fbdev);
-+
-+int omapfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg);
-+
-+int omapfb_mode_to_timings(const char *mode_str,
-+ struct omap_video_timings *timings, u8 *bpp);
-+
-+/* find the display connected to this fb, if any */
-+static inline struct omap_display *fb2display(struct fb_info *fbi)
-+{
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ int i;
-+
-+ /* XXX: returns the display connected to first attached overlay */
-+ for (i = 0; i < ofbi->num_overlays; i++) {
-+ if (ofbi->overlays[i]->manager)
-+ return ofbi->overlays[i]->manager->display;
-+ }
-+
-+ return NULL;
-+}
-+
-+static inline void omapfb_lock(struct omapfb2_device *fbdev)
-+{
-+ mutex_lock(&fbdev->mtx);
-+}
-+
-+static inline void omapfb_unlock(struct omapfb2_device *fbdev)
-+{
-+ mutex_unlock(&fbdev->mtx);
-+}
-+
-+static inline int omapfb_overlay_enable(struct omap_overlay *ovl,
-+ int enable)
-+{
-+ struct omap_overlay_info info;
-+
-+ ovl->get_overlay_info(ovl, &info);
-+ info.enabled = enable;
-+ return ovl->set_overlay_info(ovl, &info);
-+}
-+
-+#endif
-diff --git a/include/linux/omapfb.h b/include/linux/omapfb.h
-index b226bdf..96190b2 100644
---- a/include/linux/omapfb.h
-+++ b/include/linux/omapfb.h
-@@ -50,6 +50,8 @@
- #define OMAPFB_UPDATE_WINDOW OMAP_IOW(54, struct omapfb_update_window)
- #define OMAPFB_SETUP_MEM OMAP_IOW(55, struct omapfb_mem_info)
- #define OMAPFB_QUERY_MEM OMAP_IOW(56, struct omapfb_mem_info)
-+#define OMAPFB_WAITFORVSYNC OMAP_IO(57)
-+#define OMAPFB_MEMORY_READ OMAP_IOR(58, struct omapfb_memory_read)
-
- #define OMAPFB_CAPS_GENERIC_MASK 0x00000fff
- #define OMAPFB_CAPS_LCDC_MASK 0x00fff000
-@@ -90,6 +92,13 @@ enum omapfb_color_format {
- OMAPFB_COLOR_CLUT_1BPP,
- OMAPFB_COLOR_RGB444,
- OMAPFB_COLOR_YUY422,
-+
-+ OMAPFB_COLOR_ARGB16,
-+ OMAPFB_COLOR_RGB24U, /* RGB24, 32-bit container */
-+ OMAPFB_COLOR_RGB24P, /* RGB24, 24-bit container */
-+ OMAPFB_COLOR_ARGB32,
-+ OMAPFB_COLOR_RGBA32,
-+ OMAPFB_COLOR_RGBX32,
- };
-
- struct omapfb_update_window {
-@@ -161,6 +170,15 @@ enum omapfb_update_mode {
- OMAPFB_MANUAL_UPDATE
- };
-
-+struct omapfb_memory_read {
-+ __u16 x;
-+ __u16 y;
-+ __u16 w;
-+ __u16 h;
-+ size_t buffer_size;
-+ void __user *buffer;
-+};
-+
- #ifdef __KERNEL__
-
- #include <linux/completion.h>
-@@ -376,6 +394,8 @@ extern struct lcd_ctrl omap1_lcd_ctrl;
- extern struct lcd_ctrl omap2_disp_ctrl;
- #endif
-
-+extern void omapfb_set_platform_data(struct omapfb_platform_data *data);
-+
- extern void omapfb_reserve_sdram(void);
- extern void omapfb_register_panel(struct lcd_panel *panel);
- extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
---
-1.6.2.4
-
+++ /dev/null
-From 4cc0368574f587f448231ccd121266bed4bf9729 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Thu, 2 Apr 2009 10:29:56 +0300
-Subject: [PATCH 05/69] DSS2: Add panel drivers
-
-- Generic panel
-- Samsung LTE430WQ-F0C LCD Panel
-- Sharp LS037V7DW01 LCD Panel
-
-Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
----
- drivers/video/omap2/displays/Kconfig | 21 ++++
- drivers/video/omap2/displays/Makefile | 3 +
- drivers/video/omap2/displays/panel-generic.c | 96 +++++++++++++++++
- .../omap2/displays/panel-samsung-lte430wq-f0c.c | 108 +++++++++++++++++++
- .../video/omap2/displays/panel-sharp-ls037v7dw01.c | 112 ++++++++++++++++++++
- 5 files changed, 340 insertions(+), 0 deletions(-)
- create mode 100644 drivers/video/omap2/displays/Kconfig
- create mode 100644 drivers/video/omap2/displays/Makefile
- create mode 100644 drivers/video/omap2/displays/panel-generic.c
- create mode 100644 drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c
- create mode 100644 drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
-
-diff --git a/drivers/video/omap2/displays/Kconfig b/drivers/video/omap2/displays/Kconfig
-new file mode 100644
-index 0000000..0419ec8
---- /dev/null
-+++ b/drivers/video/omap2/displays/Kconfig
-@@ -0,0 +1,21 @@
-+menu "OMAP2/3 Display Device Drivers"
-+ depends on OMAP2_DSS
-+
-+config PANEL_GENERIC
-+ tristate "Generic Panel"
-+ help
-+ Generic panel driver.
-+ Used for DVI output for Beagle and OMAP3 SDP.
-+
-+config PANEL_SAMSUNG_LTE430WQ_F0C
-+ tristate "Samsung LTE430WQ-F0C LCD Panel"
-+ depends on OMAP2_DSS
-+ help
-+ LCD Panel used on Overo Palo43
-+
-+config PANEL_SHARP_LS037V7DW01
-+ tristate "Sharp LS037V7DW01 LCD Panel"
-+ depends on OMAP2_DSS
-+ help
-+ LCD Panel used in TI's SDP3430 and EVM boards
-+endmenu
-diff --git a/drivers/video/omap2/displays/Makefile b/drivers/video/omap2/displays/Makefile
-new file mode 100644
-index 0000000..a26bbd2
---- /dev/null
-+++ b/drivers/video/omap2/displays/Makefile
-@@ -0,0 +1,3 @@
-+obj-$(CONFIG_PANEL_GENERIC) += panel-generic.o
-+obj-$(CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C) += panel-samsung-lte430wq-f0c.o
-+obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o
-diff --git a/drivers/video/omap2/displays/panel-generic.c b/drivers/video/omap2/displays/panel-generic.c
-new file mode 100644
-index 0000000..8382acb
---- /dev/null
-+++ b/drivers/video/omap2/displays/panel-generic.c
-@@ -0,0 +1,96 @@
-+/*
-+ * Generic panel support
-+ *
-+ * Copyright (C) 2008 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/delay.h>
-+
-+#include <mach/display.h>
-+
-+static int generic_panel_init(struct omap_display *display)
-+{
-+ return 0;
-+}
-+
-+static int generic_panel_enable(struct omap_display *display)
-+{
-+ int r = 0;
-+
-+ if (display->hw_config.panel_enable)
-+ r = display->hw_config.panel_enable(display);
-+
-+ return r;
-+}
-+
-+static void generic_panel_disable(struct omap_display *display)
-+{
-+ if (display->hw_config.panel_disable)
-+ display->hw_config.panel_disable(display);
-+}
-+
-+static int generic_panel_suspend(struct omap_display *display)
-+{
-+ generic_panel_disable(display);
-+ return 0;
-+}
-+
-+static int generic_panel_resume(struct omap_display *display)
-+{
-+ return generic_panel_enable(display);
-+}
-+
-+static struct omap_panel generic_panel = {
-+ .owner = THIS_MODULE,
-+ .name = "panel-generic",
-+ .init = generic_panel_init,
-+ .enable = generic_panel_enable,
-+ .disable = generic_panel_disable,
-+ .suspend = generic_panel_suspend,
-+ .resume = generic_panel_resume,
-+
-+ .timings = {
-+ /* 640 x 480 @ 60 Hz Reduced blanking VESA CVT 0.31M3-R */
-+ .x_res = 640,
-+ .y_res = 480,
-+ .pixel_clock = 23500,
-+ .hfp = 48,
-+ .hsw = 32,
-+ .hbp = 80,
-+ .vfp = 3,
-+ .vsw = 4,
-+ .vbp = 7,
-+ },
-+
-+ .config = OMAP_DSS_LCD_TFT,
-+};
-+
-+
-+static int __init generic_panel_drv_init(void)
-+{
-+ omap_dss_register_panel(&generic_panel);
-+ return 0;
-+}
-+
-+static void __exit generic_panel_drv_exit(void)
-+{
-+ omap_dss_unregister_panel(&generic_panel);
-+}
-+
-+module_init(generic_panel_drv_init);
-+module_exit(generic_panel_drv_exit);
-+MODULE_LICENSE("GPL");
-diff --git a/drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c b/drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c
-new file mode 100644
-index 0000000..e4bb781
---- /dev/null
-+++ b/drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c
-@@ -0,0 +1,108 @@
-+/*
-+ * LCD panel driver for Samsung LTE430WQ-F0C
-+ *
-+ * Author: Steve Sakoman <steve@sakoman.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/delay.h>
-+
-+#include <mach/display.h>
-+
-+static int samsung_lte_panel_init(struct omap_display *display)
-+{
-+ return 0;
-+}
-+
-+static void samsung_lte_panel_cleanup(struct omap_display *display)
-+{
-+}
-+
-+static int samsung_lte_panel_enable(struct omap_display *display)
-+{
-+ int r = 0;
-+
-+ /* wait couple of vsyncs until enabling the LCD */
-+ msleep(50);
-+
-+ if (display->hw_config.panel_enable)
-+ r = display->hw_config.panel_enable(display);
-+
-+ return r;
-+}
-+
-+static void samsung_lte_panel_disable(struct omap_display *display)
-+{
-+ if (display->hw_config.panel_disable)
-+ display->hw_config.panel_disable(display);
-+
-+ /* wait at least 5 vsyncs after disabling the LCD */
-+ msleep(100);
-+}
-+
-+static int samsung_lte_panel_suspend(struct omap_display *display)
-+{
-+ samsung_lte_panel_disable(display);
-+ return 0;
-+}
-+
-+static int samsung_lte_panel_resume(struct omap_display *display)
-+{
-+ return samsung_lte_panel_enable(display);
-+}
-+
-+static struct omap_panel samsung_lte_panel = {
-+ .owner = THIS_MODULE,
-+ .name = "samsung-lte430wq-f0c",
-+ .init = samsung_lte_panel_init,
-+ .cleanup = samsung_lte_panel_cleanup,
-+ .enable = samsung_lte_panel_enable,
-+ .disable = samsung_lte_panel_disable,
-+ .suspend = samsung_lte_panel_suspend,
-+ .resume = samsung_lte_panel_resume,
-+
-+ .timings = {
-+ .x_res = 480,
-+ .y_res = 272,
-+
-+ .pixel_clock = 9200,
-+
-+ .hsw = 41,
-+ .hfp = 8,
-+ .hbp = 45-41,
-+
-+ .vsw = 10,
-+ .vfp = 4,
-+ .vbp = 12-10,
-+ },
-+
-+ .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IVS,
-+};
-+
-+
-+static int __init samsung_lte_panel_drv_init(void)
-+{
-+ omap_dss_register_panel(&samsung_lte_panel);
-+ return 0;
-+}
-+
-+static void __exit samsung_lte_panel_drv_exit(void)
-+{
-+ omap_dss_unregister_panel(&samsung_lte_panel);
-+}
-+
-+module_init(samsung_lte_panel_drv_init);
-+module_exit(samsung_lte_panel_drv_exit);
-+MODULE_LICENSE("GPL");
-diff --git a/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
-new file mode 100644
-index 0000000..1f99150
---- /dev/null
-+++ b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
-@@ -0,0 +1,112 @@
-+/*
-+ * LCD panel driver for Sharp LS037V7DW01
-+ *
-+ * Copyright (C) 2008 Nokia Corporation
-+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/delay.h>
-+
-+#include <mach/display.h>
-+
-+static int sharp_ls_panel_init(struct omap_display *display)
-+{
-+ return 0;
-+}
-+
-+static void sharp_ls_panel_cleanup(struct omap_display *display)
-+{
-+}
-+
-+static int sharp_ls_panel_enable(struct omap_display *display)
-+{
-+ int r = 0;
-+
-+ /* wait couple of vsyncs until enabling the LCD */
-+ msleep(50);
-+
-+ if (display->hw_config.panel_enable)
-+ r = display->hw_config.panel_enable(display);
-+
-+ return r;
-+}
-+
-+static void sharp_ls_panel_disable(struct omap_display *display)
-+{
-+ if (display->hw_config.panel_disable)
-+ display->hw_config.panel_disable(display);
-+
-+ /* wait at least 5 vsyncs after disabling the LCD */
-+
-+ msleep(100);
-+}
-+
-+static int sharp_ls_panel_suspend(struct omap_display *display)
-+{
-+ sharp_ls_panel_disable(display);
-+ return 0;
-+}
-+
-+static int sharp_ls_panel_resume(struct omap_display *display)
-+{
-+ return sharp_ls_panel_enable(display);
-+}
-+
-+static struct omap_panel sharp_ls_panel = {
-+ .owner = THIS_MODULE,
-+ .name = "sharp-ls037v7dw01",
-+ .init = sharp_ls_panel_init,
-+ .cleanup = sharp_ls_panel_cleanup,
-+ .enable = sharp_ls_panel_enable,
-+ .disable = sharp_ls_panel_disable,
-+ .suspend = sharp_ls_panel_suspend,
-+ .resume = sharp_ls_panel_resume,
-+
-+ .timings = {
-+ .x_res = 480,
-+ .y_res = 640,
-+
-+ .pixel_clock = 19200,
-+
-+ .hsw = 2,
-+ .hfp = 1,
-+ .hbp = 28,
-+
-+ .vsw = 1,
-+ .vfp = 1,
-+ .vbp = 1,
-+ },
-+
-+ .acb = 0x28,
-+
-+ .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | OMAP_DSS_LCD_IHS,
-+};
-+
-+
-+static int __init sharp_ls_panel_drv_init(void)
-+{
-+ omap_dss_register_panel(&sharp_ls_panel);
-+ return 0;
-+}
-+
-+static void __exit sharp_ls_panel_drv_exit(void)
-+{
-+ omap_dss_unregister_panel(&sharp_ls_panel);
-+}
-+
-+module_init(sharp_ls_panel_drv_init);
-+module_exit(sharp_ls_panel_drv_exit);
-+MODULE_LICENSE("GPL");
---
-1.6.2.4
-
+++ /dev/null
-From 18a25382e81c03230e022ca2eb7e0fce24479d6a Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Thu, 2 Apr 2009 10:31:57 +0300
-Subject: [PATCH 06/69] DSS2: HACK: Add DSS2 support for N800
-
-Works, but it an ugly quick hack.
-
-Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
----
- arch/arm/mach-omap2/board-n800.c | 216 +++++++++++---
- drivers/video/omap2/displays/Kconfig | 10 +
- drivers/video/omap2/displays/Makefile | 3 +
- drivers/video/omap2/displays/ctrl-blizzard.c | 279 +++++++++++++++++
- drivers/video/omap2/displays/panel-n800.c | 435 ++++++++++++++++++++++++++
- 5 files changed, 905 insertions(+), 38 deletions(-)
- create mode 100644 drivers/video/omap2/displays/ctrl-blizzard.c
- create mode 100644 drivers/video/omap2/displays/panel-n800.c
-
-diff --git a/arch/arm/mach-omap2/board-n800.c b/arch/arm/mach-omap2/board-n800.c
-index f6f6571..6de60ae 100644
---- a/arch/arm/mach-omap2/board-n800.c
-+++ b/arch/arm/mach-omap2/board-n800.c
-@@ -41,6 +41,8 @@
- #include <mach/clock.h>
- #include <mach/gpio-switch.h>
- #include <mach/blizzard.h>
-+#include <mach/display.h>
-+#include <mach/vram.h>
-
- #include <../drivers/cbus/tahvo.h>
- #include <../drivers/media/video/tcm825x.h>
-@@ -161,23 +163,176 @@ static struct omap_uart_config n800_uart_config __initdata = {
-
- #include "../../../drivers/cbus/retu.h"
-
--static struct omap_fbmem_config n800_fbmem0_config __initdata = {
-- .size = 752 * 1024,
-+static struct omap_tmp105_config n800_tmp105_config __initdata = {
-+ .tmp105_irq_pin = 125,
-+ .set_power = n800_tmp105_set_power,
- };
-
--static struct omap_fbmem_config n800_fbmem1_config __initdata = {
-- .size = 752 * 1024,
--};
-
--static struct omap_fbmem_config n800_fbmem2_config __initdata = {
-- .size = 752 * 1024,
-+
-+
-+/* DISPLAY */
-+static struct {
-+ struct clk *sys_ck;
-+} blizzard;
-+
-+static int blizzard_get_clocks(void)
-+{
-+ blizzard.sys_ck = clk_get(0, "osc_ck");
-+ if (IS_ERR(blizzard.sys_ck)) {
-+ printk(KERN_ERR "can't get Blizzard clock\n");
-+ return PTR_ERR(blizzard.sys_ck);
-+ }
-+ return 0;
-+}
-+
-+static unsigned long blizzard_get_clock_rate(void)
-+{
-+ return clk_get_rate(blizzard.sys_ck);
-+}
-+
-+static int n800_pn800_enable(struct omap_display *display)
-+{
-+ if (display->hw_config.panel_reset_gpio != -1) {
-+ printk("enabling panel gpio\n");
-+ gpio_direction_output(display->hw_config.panel_reset_gpio, 1);
-+ }
-+
-+ return 0;
-+}
-+
-+static void n800_pn800_disable(struct omap_display *display)
-+{
-+ if (display->hw_config.panel_reset_gpio != -1) {
-+ printk("disabling panel gpio\n");
-+ gpio_direction_output(display->hw_config.panel_reset_gpio, 0);
-+ msleep(120);
-+ }
-+}
-+
-+static int n800_blizzard_enable(struct omap_display *display)
-+{
-+ printk("enabling bliz powers\n");
-+
-+ /* Vcore to 1.475V */
-+ tahvo_set_clear_reg_bits(0x07, 0, 0xf);
-+ msleep(10);
-+
-+ clk_enable(blizzard.sys_ck);
-+
-+ if (display->hw_config.ctrl_reset_gpio != -1)
-+ gpio_direction_output(display->hw_config.ctrl_reset_gpio, 1);
-+
-+ printk("osc_ck %lu\n", blizzard_get_clock_rate());
-+
-+ return 0;
-+}
-+
-+static void n800_blizzard_disable(struct omap_display *display)
-+{
-+ printk("disabling bliz powers\n");
-+
-+ if (display->hw_config.ctrl_reset_gpio != -1)
-+ gpio_direction_output(display->hw_config.ctrl_reset_gpio, 0);
-+
-+ clk_disable(blizzard.sys_ck);
-+
-+ /* Vcore to 1.005V */
-+ tahvo_set_clear_reg_bits(0x07, 0xf, 0);
-+}
-+
-+static int n800_set_backlight_level(struct omap_display *display, int level)
-+{
-+ return 0;
-+}
-+
-+static struct omap_dss_display_config n800_dsi_display_data = {
-+ .type = OMAP_DISPLAY_TYPE_DBI,
-+ .name = "lcd",
-+ .ctrl_name = "ctrl-blizzard",
-+ .panel_name = "panel-pn800",
-+ .panel_reset_gpio = -1,
-+ .ctrl_reset_gpio = N800_BLIZZARD_POWERDOWN_GPIO,
-+ .panel_enable = n800_pn800_enable,
-+ .panel_disable = n800_pn800_disable,
-+ .ctrl_enable = n800_blizzard_enable,
-+ .ctrl_disable = n800_blizzard_disable,
-+ .set_backlight = n800_set_backlight_level,
-+ .u.rfbi = {
-+ .channel = 0,
-+ /* 8 for cmd mode, 16 for pixel data. ctrl-blizzard handles switching */
-+ .data_lines = 8,
-+ },
-+ .panel_data = 0, // XXX used for panel datalines
-+};
-+static struct omap_dss_board_info n800_dss_data = {
-+ .num_displays = 1,
-+ .displays = {
-+ &n800_dsi_display_data,
-+ },
- };
-
--static struct omap_tmp105_config n800_tmp105_config __initdata = {
-- .tmp105_irq_pin = 125,
-- .set_power = n800_tmp105_set_power,
-+static struct platform_device n800_dss_device = {
-+ .name = "omapdss",
-+ .id = -1,
-+ .dev = {
-+ .platform_data = &n800_dss_data,
-+ },
- };
-
-+static void __init n800_display_init(void)
-+{
-+ int r;
-+ const struct omap_lcd_config *conf;
-+
-+ conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config);
-+ if (conf != NULL) {
-+ n800_dsi_display_data.panel_reset_gpio = conf->nreset_gpio;
-+ n800_dsi_display_data.panel_data =
-+ (void*)(u32)conf->data_lines; // XXX
-+ //printk("\n\nTULI %d\n\n", conf->data_lines);
-+ } else {
-+ printk("\n\nEI TULLU MIOTÄÄÄ\n\n");
-+ }
-+
-+ blizzard_get_clocks();
-+ clk_enable(blizzard.sys_ck); // XXX always enable
-+
-+ //omapfb_set_ctrl_platform_data(&n800_blizzard_data);
-+ //
-+ if (n800_dsi_display_data.ctrl_reset_gpio != -1) {
-+ r = gpio_request(n800_dsi_display_data.ctrl_reset_gpio,
-+ "Blizzard pd");
-+ if (r < 0) {
-+ n800_dsi_display_data.ctrl_reset_gpio = -1;
-+ printk(KERN_ERR "Unable to get Blizzard GPIO\n");
-+ } else {
-+ gpio_direction_output(n800_dsi_display_data.ctrl_reset_gpio,
-+ 1);
-+ // XXX always enable
-+ }
-+ }
-+
-+ if (n800_dsi_display_data.panel_reset_gpio != -1) {
-+ r = gpio_request(n800_dsi_display_data.panel_reset_gpio,
-+ "panel reset");
-+ if (r < 0) {
-+ n800_dsi_display_data.panel_reset_gpio = -1;
-+ printk(KERN_ERR "Unable to get pn800 GPIO\n");
-+ } else {
-+ gpio_direction_output(n800_dsi_display_data.panel_reset_gpio,
-+ 1);
-+ // XXX always enable
-+ }
-+ }
-+}
-+
-+/* DISPLAY END */
-+
-+
-+
-+
-+
- static void mipid_shutdown(struct mipid_platform_data *pdata)
- {
- if (pdata->nreset_gpio != -1) {
-@@ -191,6 +346,7 @@ static struct mipid_platform_data n800_mipid_platform_data = {
- .shutdown = mipid_shutdown,
- };
-
-+#if 0
- static void __init mipid_dev_init(void)
- {
- const struct omap_lcd_config *conf;
-@@ -201,26 +357,9 @@ static void __init mipid_dev_init(void)
- n800_mipid_platform_data.data_lines = conf->data_lines;
- }
- }
-+#endif
-
--static struct {
-- struct clk *sys_ck;
--} blizzard;
--
--static int blizzard_get_clocks(void)
--{
-- blizzard.sys_ck = clk_get(0, "osc_ck");
-- if (IS_ERR(blizzard.sys_ck)) {
-- printk(KERN_ERR "can't get Blizzard clock\n");
-- return PTR_ERR(blizzard.sys_ck);
-- }
-- return 0;
--}
--
--static unsigned long blizzard_get_clock_rate(struct device *dev)
--{
-- return clk_get_rate(blizzard.sys_ck);
--}
--
-+#if 0
- static void blizzard_enable_clocks(int enable)
- {
- if (enable)
-@@ -265,14 +404,12 @@ static void __init blizzard_dev_init(void)
- gpio_direction_output(N800_BLIZZARD_POWERDOWN_GPIO, 1);
-
- blizzard_get_clocks();
-- omapfb_set_ctrl_platform_data(&n800_blizzard_data);
-+ //omapfb_set_ctrl_platform_data(&n800_blizzard_data);
- }
-+#endif
-
- static struct omap_board_config_kernel n800_config[] __initdata = {
- { OMAP_TAG_UART, &n800_uart_config },
-- { OMAP_TAG_FBMEM, &n800_fbmem0_config },
-- { OMAP_TAG_FBMEM, &n800_fbmem1_config },
-- { OMAP_TAG_FBMEM, &n800_fbmem2_config },
- { OMAP_TAG_TMP105, &n800_tmp105_config },
- };
-
-@@ -379,7 +516,7 @@ static struct omap2_mcspi_device_config tsc2005_mcspi_config = {
-
- static struct spi_board_info n800_spi_board_info[] __initdata = {
- {
-- .modalias = "lcd_mipid",
-+ .modalias = "panel-n800",
- .bus_num = 1,
- .chip_select = 1,
- .max_speed_hz = 4000000,
-@@ -404,7 +541,7 @@ static struct spi_board_info n800_spi_board_info[] __initdata = {
-
- static struct spi_board_info n810_spi_board_info[] __initdata = {
- {
-- .modalias = "lcd_mipid",
-+ .modalias = "panel-n800",
- .bus_num = 1,
- .chip_select = 1,
- .max_speed_hz = 4000000,
-@@ -582,6 +719,7 @@ static struct platform_device *n800_devices[] __initdata = {
- #if defined(CONFIG_CBUS_RETU_HEADSET)
- &retu_headset_device,
- #endif
-+ &n800_dss_device,
- };
-
- #ifdef CONFIG_MENELAUS
-@@ -713,9 +851,10 @@ void __init nokia_n800_common_init(void)
- if (machine_is_nokia_n810())
- i2c_register_board_info(2, n810_i2c_board_info_2,
- ARRAY_SIZE(n810_i2c_board_info_2));
--
-- mipid_dev_init();
-- blizzard_dev_init();
-+
-+ //mipid_dev_init();
-+ //blizzard_dev_init();
-+ n800_display_init();
- }
-
- static void __init nokia_n800_init(void)
-@@ -735,6 +874,7 @@ void __init nokia_n800_map_io(void)
- omap_board_config_size = ARRAY_SIZE(n800_config);
-
- omap2_set_globals_242x();
-+ omap2_set_sdram_vram(800 * 480 * 2 * 3, 0);
- omap2_map_common_io();
- }
-
-diff --git a/drivers/video/omap2/displays/Kconfig b/drivers/video/omap2/displays/Kconfig
-index 0419ec8..356ceb1 100644
---- a/drivers/video/omap2/displays/Kconfig
-+++ b/drivers/video/omap2/displays/Kconfig
-@@ -18,4 +18,14 @@ config PANEL_SHARP_LS037V7DW01
- depends on OMAP2_DSS
- help
- LCD Panel used in TI's SDP3430 and EVM boards
-+
-+config PANEL_N800
-+ tristate "Panel N8x0"
-+ help
-+ N8x0 LCD (hack)
-+
-+config CTRL_BLIZZARD
-+ tristate "Blizzard Controller"
-+ help
-+ Blizzard Controller (hack)
- endmenu
-diff --git a/drivers/video/omap2/displays/Makefile b/drivers/video/omap2/displays/Makefile
-index a26bbd2..1b74b7e 100644
---- a/drivers/video/omap2/displays/Makefile
-+++ b/drivers/video/omap2/displays/Makefile
-@@ -1,3 +1,6 @@
- obj-$(CONFIG_PANEL_GENERIC) += panel-generic.o
- obj-$(CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C) += panel-samsung-lte430wq-f0c.o
- obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o
-+
-+obj-$(CONFIG_CTRL_BLIZZARD) += ctrl-blizzard.o
-+obj-$(CONFIG_PANEL_N800) += panel-n800.o
-diff --git a/drivers/video/omap2/displays/ctrl-blizzard.c b/drivers/video/omap2/displays/ctrl-blizzard.c
-new file mode 100644
-index 0000000..6698e4d
---- /dev/null
-+++ b/drivers/video/omap2/displays/ctrl-blizzard.c
-@@ -0,0 +1,279 @@
-+
-+//#define DEBUG
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+
-+#include <mach/display.h>
-+#include <mach/dma.h>
-+
-+#ifdef DEBUG
-+#define DBG(format, ...) printk(KERN_DEBUG "Blizzard: " format, ## __VA_ARGS__)
-+#else
-+#define DBG(format, ...)
-+#endif
-+
-+#define BLIZZARD_REV_CODE 0x00
-+#define BLIZZARD_CONFIG 0x02
-+#define BLIZZARD_PLL_DIV 0x04
-+#define BLIZZARD_PLL_LOCK_RANGE 0x06
-+#define BLIZZARD_PLL_CLOCK_SYNTH_0 0x08
-+#define BLIZZARD_PLL_CLOCK_SYNTH_1 0x0a
-+#define BLIZZARD_PLL_MODE 0x0c
-+#define BLIZZARD_CLK_SRC 0x0e
-+#define BLIZZARD_MEM_BANK0_ACTIVATE 0x10
-+#define BLIZZARD_MEM_BANK0_STATUS 0x14
-+#define BLIZZARD_PANEL_CONFIGURATION 0x28
-+#define BLIZZARD_HDISP 0x2a
-+#define BLIZZARD_HNDP 0x2c
-+#define BLIZZARD_VDISP0 0x2e
-+#define BLIZZARD_VDISP1 0x30
-+#define BLIZZARD_VNDP 0x32
-+#define BLIZZARD_HSW 0x34
-+#define BLIZZARD_VSW 0x38
-+#define BLIZZARD_DISPLAY_MODE 0x68
-+#define BLIZZARD_INPUT_WIN_X_START_0 0x6c
-+#define BLIZZARD_DATA_SOURCE_SELECT 0x8e
-+#define BLIZZARD_DISP_MEM_DATA_PORT 0x90
-+#define BLIZZARD_DISP_MEM_READ_ADDR0 0x92
-+#define BLIZZARD_POWER_SAVE 0xE6
-+#define BLIZZARD_NDISP_CTRL_STATUS 0xE8
-+
-+/* Data source select */
-+/* For S1D13745 */
-+#define BLIZZARD_SRC_WRITE_LCD_BACKGROUND 0x00
-+#define BLIZZARD_SRC_WRITE_LCD_DESTRUCTIVE 0x01
-+#define BLIZZARD_SRC_WRITE_OVERLAY_ENABLE 0x04
-+#define BLIZZARD_SRC_DISABLE_OVERLAY 0x05
-+/* For S1D13744 */
-+#define BLIZZARD_SRC_WRITE_LCD 0x00
-+#define BLIZZARD_SRC_BLT_LCD 0x06
-+
-+#define BLIZZARD_COLOR_RGB565 0x01
-+#define BLIZZARD_COLOR_YUV420 0x09
-+
-+#define BLIZZARD_VERSION_S1D13745 0x01 /* Hailstorm */
-+#define BLIZZARD_VERSION_S1D13744 0x02 /* Blizzard */
-+
-+#define BLIZZARD_AUTO_UPDATE_TIME (HZ / 20)
-+
-+
-+
-+static struct {
-+ int version;
-+} blizzard;
-+
-+
-+static inline void blizzard_cmd(u8 cmd)
-+{
-+ omap_rfbi_write_command(&cmd, 1);
-+}
-+
-+static inline void blizzard_write(u8 cmd, const u8 *buf, int len)
-+{
-+ omap_rfbi_write_command(&cmd, 1);
-+ omap_rfbi_write_data(buf, len);
-+}
-+
-+static inline void blizzard_read(u8 cmd, u8 *buf, int len)
-+{
-+ omap_rfbi_write_command(&cmd, 1);
-+ omap_rfbi_read_data(buf, len);
-+}
-+
-+static u8 blizzard_read_reg(u8 cmd)
-+{
-+ u8 data;
-+ blizzard_read(cmd, &data, 1);
-+ return data;
-+}
-+
-+static int blizzard_ctrl_init(struct omap_display *display)
-+{
-+ DBG("blizzard_ctrl_init\n");
-+
-+ return 0;
-+}
-+
-+
-+static int blizzard_ctrl_enable(struct omap_display *display)
-+{
-+ int r = 0;
-+ u8 rev, conf;
-+
-+ DBG("blizzard_ctrl_enable\n");
-+
-+ if (display->hw_config.ctrl_enable) {
-+ r = display->hw_config.ctrl_enable(display);
-+ if (r)
-+ return r;
-+ }
-+
-+ msleep(100);
-+
-+ rev = blizzard_read_reg(BLIZZARD_CLK_SRC);
-+ printk("CLK_SRC %x\n", rev);
-+
-+ rev = blizzard_read_reg(BLIZZARD_PLL_DIV);
-+ printk("PLLDIV %x\n", rev);
-+
-+ rev = blizzard_read_reg(BLIZZARD_REV_CODE);
-+ conf = blizzard_read_reg(BLIZZARD_CONFIG);
-+
-+ printk("rev %x, conf %x\n", rev, conf);
-+
-+ switch (rev & 0xfc) {
-+ case 0x9c:
-+ blizzard.version = BLIZZARD_VERSION_S1D13744;
-+ pr_info("omapfb: s1d13744 LCD controller rev %d "
-+ "initialized (CNF pins %x)\n", rev & 0x03, conf & 0x07);
-+ break;
-+ case 0xa4:
-+ blizzard.version = BLIZZARD_VERSION_S1D13745;
-+ pr_info("omapfb: s1d13745 LCD controller rev %d "
-+ "initialized (CNF pins %x)\n", rev & 0x03, conf & 0x07);
-+ break;
-+ default:
-+ printk("invalid s1d1374x revision %02x\n",
-+ rev);
-+ r = -ENODEV;
-+ }
-+
-+ return r;
-+}
-+
-+static void blizzard_ctrl_disable(struct omap_display *display)
-+{
-+ DBG("blizzard_ctrl_disable\n");
-+
-+ if (display->hw_config.ctrl_disable)
-+ display->hw_config.ctrl_disable(display);
-+}
-+
-+int rfbi_configure(int rfbi_module, int bpp, int lines);
-+
-+static void blizzard_ctrl_setup_update(struct omap_display *display,
-+ u16 x, u16 y, u16 w, u16 h)
-+{
-+ u8 tmp[18];
-+ int x_end, y_end;
-+
-+ DBG("blizzard_ctrl_setup_update\n");
-+
-+ x_end = x + w - 1;
-+ y_end = y + h - 1;
-+
-+ tmp[0] = x;
-+ tmp[1] = x >> 8;
-+ tmp[2] = y;
-+ tmp[3] = y >> 8;
-+ tmp[4] = x_end;
-+ tmp[5] = x_end >> 8;
-+ tmp[6] = y_end;
-+ tmp[7] = y_end >> 8;
-+
-+ /* scaling? */
-+ tmp[8] = x;
-+ tmp[9] = x >> 8;
-+ tmp[10] = y;
-+ tmp[11] = y >> 8;
-+ tmp[12] = x_end;
-+ tmp[13] = x_end >> 8;
-+ tmp[14] = y_end;
-+ tmp[15] = y_end >> 8;
-+
-+ tmp[16] = BLIZZARD_COLOR_RGB565; //color_mode;
-+
-+ if (blizzard.version == BLIZZARD_VERSION_S1D13745)
-+ tmp[17] = BLIZZARD_SRC_WRITE_LCD_BACKGROUND;
-+ else
-+ tmp[17] = blizzard.version == BLIZZARD_VERSION_S1D13744 ?
-+ BLIZZARD_SRC_WRITE_LCD :
-+ BLIZZARD_SRC_WRITE_LCD_DESTRUCTIVE;
-+
-+ rfbi_configure(display->hw_config.u.rfbi.channel,
-+ 16,
-+ 8);
-+
-+ blizzard_write(BLIZZARD_INPUT_WIN_X_START_0, tmp, 18);
-+
-+ rfbi_configure(display->hw_config.u.rfbi.channel,
-+ 16,
-+ 16);
-+}
-+
-+static int blizzard_ctrl_enable_te(struct omap_display *display, bool enable)
-+{
-+ return 0;
-+}
-+
-+static int blizzard_ctrl_rotate(struct omap_display *display, u8 rotate)
-+{
-+ return 0;
-+}
-+
-+static int blizzard_ctrl_mirror(struct omap_display *display, bool enable)
-+{
-+ return 0;
-+}
-+
-+static int blizzard_run_test(struct omap_display *display, int test_num)
-+{
-+ return 0;
-+}
-+
-+static struct omap_ctrl blizzard_ctrl = {
-+ .owner = THIS_MODULE,
-+ .name = "ctrl-blizzard",
-+ .init = blizzard_ctrl_init,
-+ .enable = blizzard_ctrl_enable,
-+ .disable = blizzard_ctrl_disable,
-+ .setup_update = blizzard_ctrl_setup_update,
-+ .enable_te = blizzard_ctrl_enable_te,
-+ .set_rotate = blizzard_ctrl_rotate,
-+ .set_mirror = blizzard_ctrl_mirror,
-+ .run_test = blizzard_run_test,
-+ .pixel_size = 16,
-+
-+ .timings = {
-+ .cs_on_time = 0,
-+
-+ .we_on_time = 9000,
-+ .we_off_time = 18000,
-+ .we_cycle_time = 36000,
-+
-+ .re_on_time = 9000,
-+ .re_off_time = 27000,
-+ .re_cycle_time = 36000,
-+
-+ .access_time = 27000,
-+ .cs_off_time = 36000,
-+
-+ .cs_pulse_width = 0,
-+ },
-+};
-+
-+
-+static int __init blizzard_init(void)
-+{
-+ DBG("blizzard_init\n");
-+ omap_dss_register_ctrl(&blizzard_ctrl);
-+ return 0;
-+}
-+
-+static void __exit blizzard_exit(void)
-+{
-+ DBG("blizzard_exit\n");
-+
-+ omap_dss_unregister_ctrl(&blizzard_ctrl);
-+}
-+
-+module_init(blizzard_init);
-+module_exit(blizzard_exit);
-+
-+MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
-+MODULE_DESCRIPTION("Blizzard Driver");
-+MODULE_LICENSE("GPL");
-diff --git a/drivers/video/omap2/displays/panel-n800.c b/drivers/video/omap2/displays/panel-n800.c
-new file mode 100644
-index 0000000..91d3e37
---- /dev/null
-+++ b/drivers/video/omap2/displays/panel-n800.c
-@@ -0,0 +1,435 @@
-+
-+/*#define DEBUG*/
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/clk.h>
-+#include <linux/platform_device.h>
-+#include <linux/delay.h>
-+#include <linux/spi/spi.h>
-+#include <linux/jiffies.h>
-+#include <linux/sched.h>
-+#include <linux/backlight.h>
-+#include <linux/fb.h>
-+
-+#include <mach/display.h>
-+#include <mach/dma.h>
-+
-+#define MIPID_CMD_READ_DISP_ID 0x04
-+#define MIPID_CMD_READ_RED 0x06
-+#define MIPID_CMD_READ_GREEN 0x07
-+#define MIPID_CMD_READ_BLUE 0x08
-+#define MIPID_CMD_READ_DISP_STATUS 0x09
-+#define MIPID_CMD_RDDSDR 0x0F
-+#define MIPID_CMD_SLEEP_IN 0x10
-+#define MIPID_CMD_SLEEP_OUT 0x11
-+#define MIPID_CMD_DISP_OFF 0x28
-+#define MIPID_CMD_DISP_ON 0x29
-+
-+#define MIPID_VER_LPH8923 3
-+#define MIPID_VER_LS041Y3 4
-+
-+#define MIPID_ESD_CHECK_PERIOD msecs_to_jiffies(5000)
-+
-+#ifdef DEBUG
-+#define DBG(format, ...) printk(KERN_DEBUG "PN800: " format, ## __VA_ARGS__)
-+#else
-+#define DBG(format, ...)
-+#endif
-+
-+struct pn800_device {
-+ struct backlight_device *bl_dev;
-+ int enabled;
-+ int model;
-+ int revision;
-+ u8 display_id[3];
-+ unsigned int saved_bklight_level;
-+ unsigned long hw_guard_end; /* next value of jiffies
-+ when we can issue the
-+ next sleep in/out command */
-+ unsigned long hw_guard_wait; /* max guard time in jiffies */
-+
-+ struct spi_device *spi;
-+ struct mutex mutex;
-+ struct omap_panel panel;
-+ struct omap_display *display;
-+};
-+
-+
-+static void pn800_transfer(struct pn800_device *md, int cmd,
-+ const u8 *wbuf, int wlen, u8 *rbuf, int rlen)
-+{
-+ struct spi_message m;
-+ struct spi_transfer *x, xfer[4];
-+ u16 w;
-+ int r;
-+
-+ BUG_ON(md->spi == NULL);
-+
-+ spi_message_init(&m);
-+
-+ memset(xfer, 0, sizeof(xfer));
-+ x = &xfer[0];
-+
-+ cmd &= 0xff;
-+ x->tx_buf = &cmd;
-+ x->bits_per_word = 9;
-+ x->len = 2;
-+ spi_message_add_tail(x, &m);
-+
-+ if (wlen) {
-+ x++;
-+ x->tx_buf = wbuf;
-+ x->len = wlen;
-+ x->bits_per_word = 9;
-+ spi_message_add_tail(x, &m);
-+ }
-+
-+ if (rlen) {
-+ x++;
-+ x->rx_buf = &w;
-+ x->len = 1;
-+ spi_message_add_tail(x, &m);
-+
-+ if (rlen > 1) {
-+ /* Arrange for the extra clock before the first
-+ * data bit.
-+ */
-+ x->bits_per_word = 9;
-+ x->len = 2;
-+
-+ x++;
-+ x->rx_buf = &rbuf[1];
-+ x->len = rlen - 1;
-+ spi_message_add_tail(x, &m);
-+ }
-+ }
-+
-+ r = spi_sync(md->spi, &m);
-+ if (r < 0)
-+ dev_dbg(&md->spi->dev, "spi_sync %d\n", r);
-+
-+ if (rlen)
-+ rbuf[0] = w & 0xff;
-+}
-+
-+static inline void pn800_cmd(struct pn800_device *md, int cmd)
-+{
-+ pn800_transfer(md, cmd, NULL, 0, NULL, 0);
-+}
-+
-+static inline void pn800_write(struct pn800_device *md,
-+ int reg, const u8 *buf, int len)
-+{
-+ pn800_transfer(md, reg, buf, len, NULL, 0);
-+}
-+
-+static inline void pn800_read(struct pn800_device *md,
-+ int reg, u8 *buf, int len)
-+{
-+ pn800_transfer(md, reg, NULL, 0, buf, len);
-+}
-+
-+static void set_data_lines(struct pn800_device *md, int data_lines)
-+{
-+ u16 par;
-+
-+ switch (data_lines) {
-+ case 16:
-+ par = 0x150;
-+ break;
-+ case 18:
-+ par = 0x160;
-+ break;
-+ case 24:
-+ par = 0x170;
-+ break;
-+ }
-+ pn800_write(md, 0x3a, (u8 *)&par, 2);
-+}
-+
-+static void send_init_string(struct pn800_device *md)
-+{
-+ u16 initpar[] = { 0x0102, 0x0100, 0x0100 };
-+ int data_lines;
-+
-+ pn800_write(md, 0xc2, (u8 *)initpar, sizeof(initpar));
-+
-+ data_lines = (int)md->display->hw_config.panel_data; // XXX
-+
-+ set_data_lines(md, data_lines);
-+}
-+
-+static void hw_guard_start(struct pn800_device *md, int guard_msec)
-+{
-+ md->hw_guard_wait = msecs_to_jiffies(guard_msec);
-+ md->hw_guard_end = jiffies + md->hw_guard_wait;
-+}
-+
-+static void hw_guard_wait(struct pn800_device *md)
-+{
-+ unsigned long wait = md->hw_guard_end - jiffies;
-+
-+ if ((long)wait > 0 && wait <= md->hw_guard_wait) {
-+ set_current_state(TASK_UNINTERRUPTIBLE);
-+ schedule_timeout(wait);
-+ }
-+}
-+
-+static void set_sleep_mode(struct pn800_device *md, int on)
-+{
-+ int cmd, sleep_time = 50;
-+
-+ if (on)
-+ cmd = MIPID_CMD_SLEEP_IN;
-+ else
-+ cmd = MIPID_CMD_SLEEP_OUT;
-+ hw_guard_wait(md);
-+ pn800_cmd(md, cmd);
-+ hw_guard_start(md, 120);
-+ /*
-+ * When we enable the panel, it seems we _have_ to sleep
-+ * 120 ms before sending the init string. When disabling the
-+ * panel we'll sleep for the duration of 2 frames, so that the
-+ * controller can still provide the PCLK,HS,VS signals. */
-+ if (!on)
-+ sleep_time = 120;
-+ msleep(sleep_time);
-+}
-+
-+static void set_display_state(struct pn800_device *md, int enabled)
-+{
-+ int cmd = enabled ? MIPID_CMD_DISP_ON : MIPID_CMD_DISP_OFF;
-+
-+ pn800_cmd(md, cmd);
-+}
-+
-+static int panel_enabled(struct pn800_device *md)
-+{
-+ u32 disp_status;
-+ int enabled;
-+
-+ pn800_read(md, MIPID_CMD_READ_DISP_STATUS, (u8 *)&disp_status, 4);
-+ disp_status = __be32_to_cpu(disp_status);
-+ enabled = (disp_status & (1 << 17)) && (disp_status & (1 << 10));
-+ dev_dbg(&md->spi->dev,
-+ "LCD panel %s enabled by bootloader (status 0x%04x)\n",
-+ enabled ? "" : "not ", disp_status);
-+ DBG("status %#08x\n", disp_status);
-+ return enabled;
-+}
-+
-+static int panel_detect(struct pn800_device *md)
-+{
-+ pn800_read(md, MIPID_CMD_READ_DISP_ID, md->display_id, 3);
-+ dev_dbg(&md->spi->dev, "MIPI display ID: %02x%02x%02x\n",
-+ md->display_id[0], md->display_id[1], md->display_id[2]);
-+
-+ switch (md->display_id[0]) {
-+ case 0x45:
-+ md->model = MIPID_VER_LPH8923;
-+ md->panel.name = "lph8923";
-+ break;
-+ case 0x83:
-+ md->model = MIPID_VER_LS041Y3;
-+ md->panel.name = "ls041y3";
-+ //md->esd_check = ls041y3_esd_check;
-+ break;
-+ default:
-+ md->panel.name = "unknown";
-+ dev_err(&md->spi->dev, "invalid display ID\n");
-+ return -ENODEV;
-+ }
-+
-+ md->revision = md->display_id[1];
-+ pr_info("omapfb: %s rev %02x LCD detected\n",
-+ md->panel.name, md->revision);
-+
-+ return 0;
-+}
-+
-+
-+
-+static int pn800_panel_enable(struct omap_display *display)
-+{
-+ int r;
-+ struct pn800_device *md =
-+ (struct pn800_device *)display->panel->priv;
-+
-+ DBG("pn800_panel_enable\n");
-+
-+ mutex_lock(&md->mutex);
-+
-+ if (display->hw_config.panel_enable)
-+ display->hw_config.panel_enable(display);
-+
-+ msleep(50); // wait for power up
-+
-+ r = panel_detect(md);
-+ if (r) {
-+ mutex_unlock(&md->mutex);
-+ return r;
-+ }
-+
-+ md->enabled = panel_enabled(md);
-+
-+ if (md->enabled) {
-+ DBG("panel already enabled\n");
-+ ; /*pn800_esd_start_check(md);*/
-+ } else {
-+ ; /*md->saved_bklight_level = pn800_get_bklight_level(panel);*/
-+ }
-+
-+
-+ if (md->enabled) {
-+ mutex_unlock(&md->mutex);
-+ return 0;
-+ }
-+
-+ set_sleep_mode(md, 0);
-+ md->enabled = 1;
-+ send_init_string(md);
-+ set_display_state(md, 1);
-+ //mipid_set_bklight_level(panel, md->saved_bklight_level);
-+ //mipid_esd_start_check(md);
-+
-+ mutex_unlock(&md->mutex);
-+ return 0;
-+}
-+
-+static void pn800_panel_disable(struct omap_display *display)
-+{
-+ struct pn800_device *md =
-+ (struct pn800_device *)display->panel->priv;
-+
-+ DBG("pn800_panel_disable\n");
-+
-+ mutex_lock(&md->mutex);
-+
-+ if (!md->enabled) {
-+ mutex_unlock(&md->mutex);
-+ return;
-+ }
-+ /*md->saved_bklight_level = pn800_get_bklight_level(panel);*/
-+ /*pn800_set_bklight_level(panel, 0);*/
-+
-+ set_display_state(md, 0);
-+ set_sleep_mode(md, 1);
-+ md->enabled = 0;
-+
-+
-+ if (display->hw_config.panel_disable)
-+ display->hw_config.panel_disable(display);
-+
-+ mutex_unlock(&md->mutex);
-+}
-+
-+static int pn800_panel_init(struct omap_display *display)
-+{
-+ struct pn800_device *md =
-+ (struct pn800_device *)display->panel->priv;
-+
-+ DBG("pn800_panel_init\n");
-+
-+ mutex_init(&md->mutex);
-+ md->display = display;
-+
-+ return 0;
-+}
-+
-+static int pn800_run_test(struct omap_display *display, int test_num)
-+{
-+ return 0;
-+}
-+
-+static struct omap_panel pn800_panel = {
-+ .owner = THIS_MODULE,
-+ .name = "panel-pn800",
-+ .init = pn800_panel_init,
-+ /*.remove = pn800_cleanup,*/
-+ .enable = pn800_panel_enable,
-+ .disable = pn800_panel_disable,
-+ //.set_mode = pn800_set_mode,
-+ .run_test = pn800_run_test,
-+
-+ .timings = {
-+ .x_res = 800,
-+ .y_res = 480,
-+
-+ .pixel_clock = 21940,
-+ .hsw = 50,
-+ .hfp = 20,
-+ .hbp = 15,
-+
-+ .vsw = 2,
-+ .vfp = 1,
-+ .vbp = 3,
-+ },
-+ .config = OMAP_DSS_LCD_TFT,
-+};
-+
-+static int pn800_spi_probe(struct spi_device *spi)
-+{
-+ struct pn800_device *md;
-+
-+ DBG("pn800_spi_probe\n");
-+
-+ md = kzalloc(sizeof(*md), GFP_KERNEL);
-+ if (md == NULL) {
-+ dev_err(&spi->dev, "out of memory\n");
-+ return -ENOMEM;
-+ }
-+
-+ spi->mode = SPI_MODE_0;
-+ md->spi = spi;
-+ dev_set_drvdata(&spi->dev, md);
-+ md->panel = pn800_panel;
-+ pn800_panel.priv = md;
-+
-+ omap_dss_register_panel(&pn800_panel);
-+
-+ return 0;
-+}
-+
-+static int pn800_spi_remove(struct spi_device *spi)
-+{
-+ struct pn800_device *md = dev_get_drvdata(&spi->dev);
-+
-+ DBG("pn800_spi_remove\n");
-+
-+ omap_dss_unregister_panel(&pn800_panel);
-+
-+ /*pn800_disable(&md->panel);*/
-+ kfree(md);
-+
-+ return 0;
-+}
-+
-+static struct spi_driver pn800_spi_driver = {
-+ .driver = {
-+ .name = "panel-n800",
-+ .bus = &spi_bus_type,
-+ .owner = THIS_MODULE,
-+ },
-+ .probe = pn800_spi_probe,
-+ .remove = __devexit_p(pn800_spi_remove),
-+};
-+
-+static int __init pn800_init(void)
-+{
-+ DBG("pn800_init\n");
-+ return spi_register_driver(&pn800_spi_driver);
-+}
-+
-+static void __exit pn800_exit(void)
-+{
-+ DBG("pn800_exit\n");
-+ spi_unregister_driver(&pn800_spi_driver);
-+}
-+
-+module_init(pn800_init);
-+module_exit(pn800_exit);
-+
-+MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
-+MODULE_DESCRIPTION("N800 LCD Driver");
-+MODULE_LICENSE("GPL");
---
-1.6.2.4
-
+++ /dev/null
-From 9292aae93419867b9d0fce5cf3b2697e9250f5b5 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Thu, 2 Apr 2009 10:36:05 +0300
-Subject: [PATCH] DSS2: Add DSS2 support for SDP, Beagle, Overo, EVM
-
-Also custom dss_*_defconfigs as an example.
-
-Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
----
- arch/arm/configs/dss_omap3_beagle_defconfig | 1371 ++++++++++++++++++++
- arch/arm/configs/dss_omap_3430sdp_defconfig | 1634 +++++++++++++++++++++++
- arch/arm/configs/dss_overo_defconfig | 1862 +++++++++++++++++++++++++++
- arch/arm/mach-omap2/board-3430sdp.c | 227 ++++-
- arch/arm/mach-omap2/board-omap3beagle.c | 95 ++-
- arch/arm/mach-omap2/board-omap3evm.c | 217 +++-
- arch/arm/mach-omap2/board-overo.c | 98 ++-
- 7 files changed, 5475 insertions(+), 29 deletions(-)
- create mode 100644 arch/arm/configs/dss_omap3_beagle_defconfig
- create mode 100644 arch/arm/configs/dss_omap_3430sdp_defconfig
- create mode 100644 arch/arm/configs/dss_overo_defconfig
-
-diff --git a/arch/arm/configs/dss_omap3_beagle_defconfig b/arch/arm/configs/dss_omap3_beagle_defconfig
-new file mode 100644
-index 0000000..7143168
---- /dev/null
-+++ b/arch/arm/configs/dss_omap3_beagle_defconfig
-@@ -0,0 +1,1371 @@
-+#
-+# Automatically generated make config: don't edit
-+# Linux kernel version: 2.6.29-omap1
-+# Thu Apr 2 11:24:09 2009
-+#
-+CONFIG_ARM=y
-+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-+CONFIG_GENERIC_GPIO=y
-+CONFIG_GENERIC_TIME=y
-+CONFIG_GENERIC_CLOCKEVENTS=y
-+CONFIG_MMU=y
-+# CONFIG_NO_IOPORT is not set
-+CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_STACKTRACE_SUPPORT=y
-+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-+CONFIG_LOCKDEP_SUPPORT=y
-+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-+CONFIG_HARDIRQS_SW_RESEND=y
-+CONFIG_GENERIC_IRQ_PROBE=y
-+CONFIG_RWSEM_GENERIC_SPINLOCK=y
-+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-+CONFIG_GENERIC_HWEIGHT=y
-+CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-+CONFIG_VECTORS_BASE=0xffff0000
-+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-+
-+#
-+# General setup
-+#
-+CONFIG_EXPERIMENTAL=y
-+CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-+CONFIG_LOCALVERSION=""
-+CONFIG_LOCALVERSION_AUTO=y
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_SYSVIPC_SYSCTL=y
-+# CONFIG_POSIX_MQUEUE is not set
-+CONFIG_BSD_PROCESS_ACCT=y
-+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_AUDIT is not set
-+
-+#
-+# RCU Subsystem
-+#
-+CONFIG_CLASSIC_RCU=y
-+# CONFIG_TREE_RCU is not set
-+# CONFIG_PREEMPT_RCU is not set
-+# CONFIG_TREE_RCU_TRACE is not set
-+# CONFIG_PREEMPT_RCU_TRACE is not set
-+# CONFIG_IKCONFIG is not set
-+CONFIG_LOG_BUF_SHIFT=14
-+CONFIG_GROUP_SCHED=y
-+CONFIG_FAIR_GROUP_SCHED=y
-+# CONFIG_RT_GROUP_SCHED is not set
-+CONFIG_USER_SCHED=y
-+# CONFIG_CGROUP_SCHED is not set
-+# CONFIG_CGROUPS is not set
-+CONFIG_SYSFS_DEPRECATED=y
-+CONFIG_SYSFS_DEPRECATED_V2=y
-+# CONFIG_RELAY is not set
-+# CONFIG_NAMESPACES is not set
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE=""
-+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-+CONFIG_SYSCTL=y
-+CONFIG_ANON_INODES=y
-+CONFIG_EMBEDDED=y
-+CONFIG_UID16=y
-+# CONFIG_SYSCTL_SYSCALL is not set
-+CONFIG_KALLSYMS=y
-+# CONFIG_KALLSYMS_ALL is not set
-+CONFIG_KALLSYMS_EXTRA_PASS=y
-+CONFIG_HOTPLUG=y
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_ELF_CORE=y
-+CONFIG_BASE_FULL=y
-+CONFIG_FUTEX=y
-+CONFIG_EPOLL=y
-+CONFIG_SIGNALFD=y
-+CONFIG_TIMERFD=y
-+CONFIG_EVENTFD=y
-+CONFIG_SHMEM=y
-+CONFIG_AIO=y
-+CONFIG_VM_EVENT_COUNTERS=y
-+CONFIG_COMPAT_BRK=y
-+CONFIG_SLAB=y
-+# CONFIG_SLUB is not set
-+# CONFIG_SLOB is not set
-+# CONFIG_PROFILING is not set
-+CONFIG_HAVE_OPROFILE=y
-+# CONFIG_KPROBES is not set
-+CONFIG_HAVE_KPROBES=y
-+CONFIG_HAVE_KRETPROBES=y
-+CONFIG_HAVE_CLK=y
-+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-+CONFIG_SLABINFO=y
-+CONFIG_RT_MUTEXES=y
-+CONFIG_BASE_SMALL=0
-+CONFIG_MODULES=y
-+# CONFIG_MODULE_FORCE_LOAD is not set
-+CONFIG_MODULE_UNLOAD=y
-+# CONFIG_MODULE_FORCE_UNLOAD is not set
-+CONFIG_MODVERSIONS=y
-+CONFIG_MODULE_SRCVERSION_ALL=y
-+CONFIG_BLOCK=y
-+# CONFIG_LBD is not set
-+# CONFIG_BLK_DEV_IO_TRACE is not set
-+# CONFIG_BLK_DEV_BSG is not set
-+# CONFIG_BLK_DEV_INTEGRITY is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+CONFIG_IOSCHED_AS=y
-+CONFIG_IOSCHED_DEADLINE=y
-+CONFIG_IOSCHED_CFQ=y
-+CONFIG_DEFAULT_AS=y
-+# CONFIG_DEFAULT_DEADLINE is not set
-+# CONFIG_DEFAULT_CFQ is not set
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="anticipatory"
-+# CONFIG_FREEZER is not set
-+
-+#
-+# System Type
-+#
-+# CONFIG_ARCH_AAEC2000 is not set
-+# CONFIG_ARCH_INTEGRATOR is not set
-+# CONFIG_ARCH_REALVIEW is not set
-+# CONFIG_ARCH_VERSATILE is not set
-+# CONFIG_ARCH_AT91 is not set
-+# CONFIG_ARCH_CLPS711X is not set
-+# CONFIG_ARCH_EBSA110 is not set
-+# CONFIG_ARCH_EP93XX is not set
-+# CONFIG_ARCH_FOOTBRIDGE is not set
-+# CONFIG_ARCH_NETX is not set
-+# CONFIG_ARCH_H720X is not set
-+# CONFIG_ARCH_IMX is not set
-+# CONFIG_ARCH_IOP13XX is not set
-+# CONFIG_ARCH_IOP32X is not set
-+# CONFIG_ARCH_IOP33X is not set
-+# CONFIG_ARCH_IXP23XX is not set
-+# CONFIG_ARCH_IXP2000 is not set
-+# CONFIG_ARCH_IXP4XX is not set
-+# CONFIG_ARCH_L7200 is not set
-+# CONFIG_ARCH_KIRKWOOD is not set
-+# CONFIG_ARCH_KS8695 is not set
-+# CONFIG_ARCH_NS9XXX is not set
-+# CONFIG_ARCH_LOKI is not set
-+# CONFIG_ARCH_MV78XX0 is not set
-+# CONFIG_ARCH_MXC is not set
-+# CONFIG_ARCH_ORION5X is not set
-+# CONFIG_ARCH_PNX4008 is not set
-+# CONFIG_ARCH_PXA is not set
-+# CONFIG_ARCH_RPC is not set
-+# CONFIG_ARCH_SA1100 is not set
-+# CONFIG_ARCH_S3C2410 is not set
-+# CONFIG_ARCH_S3C64XX is not set
-+# CONFIG_ARCH_SHARK is not set
-+# CONFIG_ARCH_LH7A40X is not set
-+# CONFIG_ARCH_DAVINCI is not set
-+CONFIG_ARCH_OMAP=y
-+# CONFIG_ARCH_MSM is not set
-+# CONFIG_ARCH_W90X900 is not set
-+
-+#
-+# TI OMAP Implementations
-+#
-+CONFIG_ARCH_OMAP_OTG=y
-+# CONFIG_ARCH_OMAP1 is not set
-+# CONFIG_ARCH_OMAP2 is not set
-+CONFIG_ARCH_OMAP3=y
-+
-+#
-+# OMAP Feature Selections
-+#
-+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
-+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
-+# CONFIG_OMAP_SMARTREFLEX is not set
-+# CONFIG_OMAP_RESET_CLOCKS is not set
-+CONFIG_OMAP_BOOT_TAG=y
-+CONFIG_OMAP_BOOT_REASON=y
-+# CONFIG_OMAP_COMPONENT_VERSION is not set
-+# CONFIG_OMAP_GPIO_SWITCH is not set
-+# CONFIG_OMAP_MUX is not set
-+# CONFIG_OMAP_MCBSP is not set
-+# CONFIG_OMAP_MBOX_FWK is not set
-+# CONFIG_OMAP_MPU_TIMER is not set
-+CONFIG_OMAP_32K_TIMER=y
-+CONFIG_OMAP_32K_TIMER_HZ=128
-+CONFIG_OMAP_TICK_GPTIMER=12
-+CONFIG_OMAP_DM_TIMER=y
-+# CONFIG_OMAP_LL_DEBUG_UART1 is not set
-+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
-+CONFIG_OMAP_LL_DEBUG_UART3=y
-+CONFIG_ARCH_OMAP34XX=y
-+CONFIG_ARCH_OMAP3430=y
-+
-+#
-+# OMAP Board Type
-+#
-+# CONFIG_MACH_NOKIA_RX51 is not set
-+# CONFIG_MACH_OMAP_LDP is not set
-+# CONFIG_MACH_OMAP_3430SDP is not set
-+# CONFIG_MACH_OMAP3EVM is not set
-+CONFIG_MACH_OMAP3_BEAGLE=y
-+# CONFIG_MACH_OVERO is not set
-+# CONFIG_MACH_OMAP3_PANDORA is not set
-+
-+#
-+# Processor Type
-+#
-+CONFIG_CPU_32=y
-+CONFIG_CPU_32v6K=y
-+CONFIG_CPU_V7=y
-+CONFIG_CPU_32v7=y
-+CONFIG_CPU_ABRT_EV7=y
-+CONFIG_CPU_PABRT_IFAR=y
-+CONFIG_CPU_CACHE_V7=y
-+CONFIG_CPU_CACHE_VIPT=y
-+CONFIG_CPU_COPY_V6=y
-+CONFIG_CPU_TLB_V7=y
-+CONFIG_CPU_HAS_ASID=y
-+CONFIG_CPU_CP15=y
-+CONFIG_CPU_CP15_MMU=y
-+
-+#
-+# Processor Features
-+#
-+CONFIG_ARM_THUMB=y
-+# CONFIG_ARM_THUMBEE is not set
-+# CONFIG_CPU_ICACHE_DISABLE is not set
-+# CONFIG_CPU_DCACHE_DISABLE is not set
-+# CONFIG_CPU_BPREDICT_DISABLE is not set
-+CONFIG_HAS_TLS_REG=y
-+# CONFIG_OUTER_CACHE is not set
-+
-+#
-+# Bus support
-+#
-+# CONFIG_PCI_SYSCALL is not set
-+# CONFIG_ARCH_SUPPORTS_MSI is not set
-+# CONFIG_PCCARD is not set
-+
-+#
-+# Kernel Features
-+#
-+CONFIG_TICK_ONESHOT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-+CONFIG_VMSPLIT_3G=y
-+# CONFIG_VMSPLIT_2G is not set
-+# CONFIG_VMSPLIT_1G is not set
-+CONFIG_PAGE_OFFSET=0xC0000000
-+# CONFIG_PREEMPT is not set
-+CONFIG_HZ=128
-+CONFIG_AEABI=y
-+CONFIG_OABI_COMPAT=y
-+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
-+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-+CONFIG_SELECT_MEMORY_MODEL=y
-+CONFIG_FLATMEM_MANUAL=y
-+# CONFIG_DISCONTIGMEM_MANUAL is not set
-+# CONFIG_SPARSEMEM_MANUAL is not set
-+CONFIG_FLATMEM=y
-+CONFIG_FLAT_NODE_MEM_MAP=y
-+CONFIG_PAGEFLAGS_EXTENDED=y
-+CONFIG_SPLIT_PTLOCK_CPUS=4
-+# CONFIG_PHYS_ADDR_T_64BIT is not set
-+CONFIG_ZONE_DMA_FLAG=0
-+CONFIG_VIRT_TO_BUS=y
-+CONFIG_UNEVICTABLE_LRU=y
-+# CONFIG_LEDS is not set
-+CONFIG_ALIGNMENT_TRAP=y
-+
-+#
-+# Boot options
-+#
-+CONFIG_ZBOOT_ROM_TEXT=0x0
-+CONFIG_ZBOOT_ROM_BSS=0x0
-+CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.2.14:/tftpboot/rootfs ip=192.168.2.15 nolock,rsize=1024,wsize=1024 rw"
-+# CONFIG_XIP_KERNEL is not set
-+# CONFIG_KEXEC is not set
-+
-+#
-+# CPU Power Management
-+#
-+# CONFIG_CPU_FREQ is not set
-+# CONFIG_CPU_IDLE is not set
-+
-+#
-+# Floating point emulation
-+#
-+
-+#
-+# At least one emulation must be selected
-+#
-+CONFIG_FPE_NWFPE=y
-+# CONFIG_FPE_NWFPE_XP is not set
-+# CONFIG_FPE_FASTFPE is not set
-+CONFIG_VFP=y
-+CONFIG_VFPv3=y
-+# CONFIG_NEON is not set
-+
-+#
-+# Userspace binary formats
-+#
-+CONFIG_BINFMT_ELF=y
-+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-+CONFIG_HAVE_AOUT=y
-+# CONFIG_BINFMT_AOUT is not set
-+CONFIG_BINFMT_MISC=y
-+
-+#
-+# Power management options
-+#
-+CONFIG_PM=y
-+# CONFIG_PM_DEBUG is not set
-+# CONFIG_SUSPEND is not set
-+# CONFIG_APM_EMULATION is not set
-+CONFIG_ARCH_SUSPEND_POSSIBLE=y
-+CONFIG_NET=y
-+
-+#
-+# Networking options
-+#
-+CONFIG_COMPAT_NET_DEV_OPS=y
-+CONFIG_PACKET=y
-+# CONFIG_PACKET_MMAP is not set
-+CONFIG_UNIX=y
-+CONFIG_XFRM=y
-+# CONFIG_XFRM_USER is not set
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+CONFIG_NET_KEY=y
-+# CONFIG_NET_KEY_MIGRATE is not set
-+CONFIG_INET=y
-+# CONFIG_IP_MULTICAST is not set
-+# CONFIG_IP_ADVANCED_ROUTER is not set
-+CONFIG_IP_FIB_HASH=y
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+CONFIG_IP_PNP_BOOTP=y
-+CONFIG_IP_PNP_RARP=y
-+# CONFIG_NET_IPIP is not set
-+# CONFIG_NET_IPGRE is not set
-+# CONFIG_ARPD is not set
-+# CONFIG_SYN_COOKIES is not set
-+# CONFIG_INET_AH is not set
-+# CONFIG_INET_ESP is not set
-+# CONFIG_INET_IPCOMP is not set
-+# CONFIG_INET_XFRM_TUNNEL is not set
-+# CONFIG_INET_TUNNEL is not set
-+CONFIG_INET_XFRM_MODE_TRANSPORT=y
-+CONFIG_INET_XFRM_MODE_TUNNEL=y
-+CONFIG_INET_XFRM_MODE_BEET=y
-+# CONFIG_INET_LRO is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
-+# CONFIG_TCP_CONG_ADVANCED is not set
-+CONFIG_TCP_CONG_CUBIC=y
-+CONFIG_DEFAULT_TCP_CONG="cubic"
-+# CONFIG_TCP_MD5SIG is not set
-+# CONFIG_IPV6 is not set
-+# CONFIG_NETWORK_SECMARK is not set
-+# CONFIG_NETFILTER is not set
-+# CONFIG_IP_DCCP is not set
-+# CONFIG_IP_SCTP is not set
-+# CONFIG_TIPC is not set
-+# CONFIG_ATM is not set
-+# CONFIG_BRIDGE is not set
-+# CONFIG_NET_DSA is not set
-+# CONFIG_VLAN_8021Q is not set
-+# CONFIG_DECNET is not set
-+# CONFIG_LLC2 is not set
-+# CONFIG_IPX is not set
-+# CONFIG_ATALK is not set
-+# CONFIG_X25 is not set
-+# CONFIG_LAPB is not set
-+# CONFIG_ECONET is not set
-+# CONFIG_WAN_ROUTER is not set
-+# CONFIG_NET_SCHED is not set
-+# CONFIG_DCB is not set
-+
-+#
-+# Network testing
-+#
-+# CONFIG_NET_PKTGEN is not set
-+# CONFIG_HAMRADIO is not set
-+# CONFIG_CAN is not set
-+# CONFIG_IRDA is not set
-+# CONFIG_BT is not set
-+# CONFIG_AF_RXRPC is not set
-+# CONFIG_PHONET is not set
-+CONFIG_WIRELESS=y
-+# CONFIG_CFG80211 is not set
-+CONFIG_WIRELESS_OLD_REGULATORY=y
-+# CONFIG_WIRELESS_EXT is not set
-+# CONFIG_LIB80211 is not set
-+# CONFIG_MAC80211 is not set
-+# CONFIG_WIMAX is not set
-+# CONFIG_RFKILL is not set
-+# CONFIG_NET_9P is not set
-+
-+#
-+# Device Drivers
-+#
-+
-+#
-+# Generic Driver Options
-+#
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-+CONFIG_STANDALONE=y
-+CONFIG_PREVENT_FIRMWARE_BUILD=y
-+# CONFIG_FW_LOADER is not set
-+# CONFIG_DEBUG_DRIVER is not set
-+# CONFIG_DEBUG_DEVRES is not set
-+# CONFIG_SYS_HYPERVISOR is not set
-+# CONFIG_CONNECTOR is not set
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+# CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
-+# CONFIG_MTD_TESTS is not set
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+# CONFIG_MTD_CMDLINE_PARTS is not set
-+# CONFIG_MTD_AFS_PARTS is not set
-+# CONFIG_MTD_AR7_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLKDEVS=y
-+CONFIG_MTD_BLOCK=y
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+# CONFIG_SSFDC is not set
-+# CONFIG_MTD_OOPS is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+# CONFIG_MTD_CFI is not set
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+# CONFIG_MTD_PLATRAM is not set
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+CONFIG_MTD_NAND=y
-+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
-+# CONFIG_MTD_NAND_ECC_SMC is not set
-+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-+# CONFIG_MTD_NAND_GPIO is not set
-+CONFIG_MTD_NAND_OMAP2=y
-+CONFIG_MTD_NAND_IDS=y
-+# CONFIG_MTD_NAND_DISKONCHIP is not set
-+# CONFIG_MTD_NAND_NANDSIM is not set
-+# CONFIG_MTD_NAND_PLATFORM is not set
-+# CONFIG_MTD_ONENAND is not set
-+
-+#
-+# LPDDR flash memory drivers
-+#
-+# CONFIG_MTD_LPDDR is not set
-+
-+#
-+# UBI - Unsorted block images
-+#
-+# CONFIG_MTD_UBI is not set
-+# CONFIG_PARPORT is not set
-+CONFIG_BLK_DEV=y
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+CONFIG_BLK_DEV_LOOP=y
-+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-+# CONFIG_BLK_DEV_NBD is not set
-+CONFIG_BLK_DEV_RAM=y
-+CONFIG_BLK_DEV_RAM_COUNT=16
-+CONFIG_BLK_DEV_RAM_SIZE=16384
-+# CONFIG_BLK_DEV_XIP is not set
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+# CONFIG_MISC_DEVICES is not set
-+CONFIG_HAVE_IDE=y
-+# CONFIG_IDE is not set
-+
-+#
-+# SCSI device support
-+#
-+# CONFIG_RAID_ATTRS is not set
-+CONFIG_SCSI=y
-+CONFIG_SCSI_DMA=y
-+# CONFIG_SCSI_TGT is not set
-+# CONFIG_SCSI_NETLINK is not set
-+CONFIG_SCSI_PROC_FS=y
-+
-+#
-+# SCSI support type (disk, tape, CD-ROM)
-+#
-+CONFIG_BLK_DEV_SD=y
-+# CONFIG_CHR_DEV_ST is not set
-+# CONFIG_CHR_DEV_OSST is not set
-+# CONFIG_BLK_DEV_SR is not set
-+# CONFIG_CHR_DEV_SG is not set
-+# CONFIG_CHR_DEV_SCH is not set
-+
-+#
-+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-+#
-+# CONFIG_SCSI_MULTI_LUN is not set
-+# CONFIG_SCSI_CONSTANTS is not set
-+# CONFIG_SCSI_LOGGING is not set
-+# CONFIG_SCSI_SCAN_ASYNC is not set
-+CONFIG_SCSI_WAIT_SCAN=m
-+
-+#
-+# SCSI Transports
-+#
-+# CONFIG_SCSI_SPI_ATTRS is not set
-+# CONFIG_SCSI_FC_ATTRS is not set
-+# CONFIG_SCSI_ISCSI_ATTRS is not set
-+# CONFIG_SCSI_SAS_LIBSAS is not set
-+# CONFIG_SCSI_SRP_ATTRS is not set
-+CONFIG_SCSI_LOWLEVEL=y
-+# CONFIG_ISCSI_TCP is not set
-+# CONFIG_LIBFC is not set
-+# CONFIG_SCSI_DEBUG is not set
-+# CONFIG_SCSI_DH is not set
-+# CONFIG_ATA is not set
-+# CONFIG_MD is not set
-+CONFIG_NETDEVICES=y
-+# CONFIG_DUMMY is not set
-+# CONFIG_BONDING is not set
-+# CONFIG_MACVLAN is not set
-+# CONFIG_EQUALIZER is not set
-+# CONFIG_TUN is not set
-+# CONFIG_VETH is not set
-+# CONFIG_NET_ETHERNET is not set
-+# CONFIG_NETDEV_1000 is not set
-+# CONFIG_NETDEV_10000 is not set
-+
-+#
-+# Wireless LAN
-+#
-+# CONFIG_WLAN_PRE80211 is not set
-+# CONFIG_WLAN_80211 is not set
-+# CONFIG_IWLWIFI_LEDS is not set
-+
-+#
-+# Enable WiMAX (Networking options) to see the WiMAX drivers
-+#
-+# CONFIG_WAN is not set
-+# CONFIG_PPP is not set
-+# CONFIG_SLIP is not set
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
-+# CONFIG_ISDN is not set
-+
-+#
-+# Input device support
-+#
-+CONFIG_INPUT=y
-+# CONFIG_INPUT_FF_MEMLESS is not set
-+# CONFIG_INPUT_POLLDEV is not set
-+
-+#
-+# Userland interfaces
-+#
-+# CONFIG_INPUT_MOUSEDEV is not set
-+# CONFIG_INPUT_JOYDEV is not set
-+# CONFIG_INPUT_EVDEV is not set
-+# CONFIG_INPUT_EVBUG is not set
-+
-+#
-+# Input Device Drivers
-+#
-+# CONFIG_INPUT_KEYBOARD is not set
-+# CONFIG_INPUT_MOUSE is not set
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TABLET is not set
-+# CONFIG_INPUT_TOUCHSCREEN is not set
-+# CONFIG_INPUT_MISC is not set
-+
-+#
-+# Hardware I/O ports
-+#
-+# CONFIG_SERIO is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
-+# Character devices
-+#
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+CONFIG_DEVKMEM=y
-+# CONFIG_SERIAL_NONSTANDARD is not set
-+
-+#
-+# Serial drivers
-+#
-+CONFIG_SERIAL_8250=y
-+CONFIG_SERIAL_8250_CONSOLE=y
-+CONFIG_SERIAL_8250_NR_UARTS=32
-+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-+CONFIG_SERIAL_8250_EXTENDED=y
-+CONFIG_SERIAL_8250_MANY_PORTS=y
-+CONFIG_SERIAL_8250_SHARE_IRQ=y
-+CONFIG_SERIAL_8250_DETECT_IRQ=y
-+CONFIG_SERIAL_8250_RSA=y
-+
-+#
-+# Non-8250 serial port support
-+#
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+CONFIG_UNIX98_PTYS=y
-+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_IPMI_HANDLER is not set
-+CONFIG_HW_RANDOM=y
-+# CONFIG_R3964 is not set
-+# CONFIG_RAW_DRIVER is not set
-+# CONFIG_TCG_TPM is not set
-+CONFIG_I2C=y
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_CHARDEV=y
-+CONFIG_I2C_HELPER_AUTO=y
-+
-+#
-+# I2C Hardware Bus support
-+#
-+
-+#
-+# I2C system bus drivers (mostly embedded / system-on-chip)
-+#
-+# CONFIG_I2C_GPIO is not set
-+# CONFIG_I2C_OCORES is not set
-+CONFIG_I2C_OMAP=y
-+# CONFIG_I2C_SIMTEC is not set
-+
-+#
-+# External I2C/SMBus adapter drivers
-+#
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+
-+#
-+# Other I2C/SMBus bus drivers
-+#
-+# CONFIG_I2C_PCA_PLATFORM is not set
-+# CONFIG_I2C_STUB is not set
-+
-+#
-+# Miscellaneous I2C Chip support
-+#
-+# CONFIG_DS1682 is not set
-+# CONFIG_SENSORS_PCF8574 is not set
-+# CONFIG_PCF8575 is not set
-+# CONFIG_SENSORS_PCA9539 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+# CONFIG_TWL4030_MADC is not set
-+# CONFIG_TWL4030_POWEROFF is not set
-+# CONFIG_SENSORS_MAX6875 is not set
-+# CONFIG_SENSORS_TSL2550 is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+# CONFIG_I2C_DEBUG_CHIP is not set
-+# CONFIG_SPI is not set
-+CONFIG_ARCH_REQUIRE_GPIOLIB=y
-+CONFIG_GPIOLIB=y
-+# CONFIG_DEBUG_GPIO is not set
-+# CONFIG_GPIO_SYSFS is not set
-+
-+#
-+# Memory mapped GPIO expanders:
-+#
-+
-+#
-+# I2C GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX732X is not set
-+# CONFIG_GPIO_PCA953X is not set
-+# CONFIG_GPIO_PCF857X is not set
-+CONFIG_GPIO_TWL4030=y
-+
-+#
-+# PCI GPIO expanders:
-+#
-+
-+#
-+# SPI GPIO expanders:
-+#
-+# CONFIG_W1 is not set
-+# CONFIG_POWER_SUPPLY is not set
-+# CONFIG_HWMON is not set
-+# CONFIG_THERMAL is not set
-+# CONFIG_THERMAL_HWMON is not set
-+# CONFIG_WATCHDOG is not set
-+CONFIG_SSB_POSSIBLE=y
-+
-+#
-+# Sonics Silicon Backplane
-+#
-+# CONFIG_SSB is not set
-+
-+#
-+# Multifunction device drivers
-+#
-+# CONFIG_MFD_CORE is not set
-+# CONFIG_MFD_SM501 is not set
-+# CONFIG_MFD_ASIC3 is not set
-+# CONFIG_HTC_EGPIO is not set
-+# CONFIG_HTC_PASIC3 is not set
-+# CONFIG_TPS65010 is not set
-+CONFIG_TWL4030_CORE=y
-+# CONFIG_TWL4030_POWER is not set
-+# CONFIG_MFD_TMIO is not set
-+# CONFIG_MFD_T7L66XB is not set
-+# CONFIG_MFD_TC6387XB is not set
-+# CONFIG_MFD_TC6393XB is not set
-+# CONFIG_PMIC_DA903X is not set
-+# CONFIG_MFD_WM8400 is not set
-+# CONFIG_MFD_WM8350_I2C is not set
-+# CONFIG_MFD_PCF50633 is not set
-+
-+#
-+# Multimedia devices
-+#
-+
-+#
-+# Multimedia core support
-+#
-+# CONFIG_VIDEO_DEV is not set
-+# CONFIG_DVB_CORE is not set
-+# CONFIG_VIDEO_MEDIA is not set
-+
-+#
-+# Multimedia drivers
-+#
-+CONFIG_DAB=y
-+
-+#
-+# Graphics support
-+#
-+# CONFIG_VGASTATE is not set
-+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-+CONFIG_FB=y
-+# CONFIG_FIRMWARE_EDID is not set
-+# CONFIG_FB_DDC is not set
-+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-+CONFIG_FB_CFB_FILLRECT=m
-+CONFIG_FB_CFB_COPYAREA=m
-+CONFIG_FB_CFB_IMAGEBLIT=m
-+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-+# CONFIG_FB_SYS_FILLRECT is not set
-+# CONFIG_FB_SYS_COPYAREA is not set
-+# CONFIG_FB_SYS_IMAGEBLIT is not set
-+# CONFIG_FB_FOREIGN_ENDIAN is not set
-+# CONFIG_FB_SYS_FOPS is not set
-+# CONFIG_FB_SVGALIB is not set
-+# CONFIG_FB_MACMODES is not set
-+# CONFIG_FB_BACKLIGHT is not set
-+# CONFIG_FB_MODE_HELPERS is not set
-+# CONFIG_FB_TILEBLITTING is not set
-+
-+#
-+# Frame buffer hardware drivers
-+#
-+# CONFIG_FB_S1D13XXX is not set
-+# CONFIG_FB_VIRTUAL is not set
-+# CONFIG_FB_METRONOME is not set
-+# CONFIG_FB_MB862XX is not set
-+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
-+CONFIG_OMAP2_DSS=m
-+CONFIG_OMAP2_DSS_VRAM_SIZE=12
-+CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
-+# CONFIG_OMAP2_DSS_RFBI is not set
-+CONFIG_OMAP2_DSS_VENC=y
-+# CONFIG_OMAP2_DSS_SDI is not set
-+# CONFIG_OMAP2_DSS_DSI is not set
-+# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
-+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
-+
-+#
-+# OMAP2/3 Display Device Drivers
-+#
-+CONFIG_PANEL_GENERIC=m
-+# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set
-+# CONFIG_PANEL_SHARP_LS037V7DW01 is not set
-+# CONFIG_PANEL_N800 is not set
-+# CONFIG_CTRL_BLIZZARD is not set
-+CONFIG_FB_OMAP2=m
-+CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
-+# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
-+CONFIG_FB_OMAP2_NUM_FBS=3
-+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-+
-+#
-+# Display device support
-+#
-+# CONFIG_DISPLAY_SUPPORT is not set
-+
-+#
-+# Console display driver support
-+#
-+# CONFIG_VGA_CONSOLE is not set
-+CONFIG_DUMMY_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE is not set
-+# CONFIG_LOGO is not set
-+# CONFIG_SOUND is not set
-+# CONFIG_HID_SUPPORT is not set
-+CONFIG_USB_SUPPORT=y
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB is not set
-+# CONFIG_USB_OTG_WHITELIST is not set
-+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+CONFIG_USB_MUSB_HDRC=y
-+CONFIG_USB_MUSB_SOC=y
-+
-+#
-+# OMAP 343x high speed USB support
-+#
-+# CONFIG_USB_MUSB_HOST is not set
-+CONFIG_USB_MUSB_PERIPHERAL=y
-+# CONFIG_USB_MUSB_OTG is not set
-+CONFIG_USB_GADGET_MUSB_HDRC=y
-+# CONFIG_MUSB_PIO_ONLY is not set
-+CONFIG_USB_INVENTRA_DMA=y
-+# CONFIG_USB_TI_CPPI_DMA is not set
-+# CONFIG_USB_MUSB_DEBUG is not set
-+
-+#
-+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
-+#
-+CONFIG_USB_GADGET=y
-+# CONFIG_USB_GADGET_DEBUG is not set
-+# CONFIG_USB_GADGET_DEBUG_FILES is not set
-+# CONFIG_USB_GADGET_DEBUG_FS is not set
-+CONFIG_USB_GADGET_VBUS_DRAW=2
-+CONFIG_USB_GADGET_SELECTED=y
-+# CONFIG_USB_GADGET_AT91 is not set
-+# CONFIG_USB_GADGET_ATMEL_USBA is not set
-+# CONFIG_USB_GADGET_FSL_USB2 is not set
-+# CONFIG_USB_GADGET_LH7A40X is not set
-+# CONFIG_USB_GADGET_OMAP is not set
-+# CONFIG_USB_GADGET_PXA25X is not set
-+# CONFIG_USB_GADGET_PXA27X is not set
-+# CONFIG_USB_GADGET_S3C2410 is not set
-+# CONFIG_USB_GADGET_IMX is not set
-+# CONFIG_USB_GADGET_M66592 is not set
-+# CONFIG_USB_GADGET_AMD5536UDC is not set
-+# CONFIG_USB_GADGET_FSL_QE is not set
-+# CONFIG_USB_GADGET_CI13XXX is not set
-+# CONFIG_USB_GADGET_NET2280 is not set
-+# CONFIG_USB_GADGET_GOKU is not set
-+# CONFIG_USB_GADGET_DUMMY_HCD is not set
-+CONFIG_USB_GADGET_DUALSPEED=y
-+# CONFIG_USB_ZERO is not set
-+CONFIG_USB_ETH=y
-+CONFIG_USB_ETH_RNDIS=y
-+# CONFIG_USB_GADGETFS is not set
-+# CONFIG_USB_FILE_STORAGE is not set
-+# CONFIG_USB_G_SERIAL is not set
-+# CONFIG_USB_MIDI_GADGET is not set
-+# CONFIG_USB_G_PRINTER is not set
-+# CONFIG_USB_CDC_COMPOSITE is not set
-+
-+#
-+# OTG and related infrastructure
-+#
-+CONFIG_USB_OTG_UTILS=y
-+# CONFIG_USB_GPIO_VBUS is not set
-+# CONFIG_ISP1301_OMAP is not set
-+CONFIG_TWL4030_USB=y
-+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+# CONFIG_MMC_UNSAFE_RESUME is not set
-+
-+#
-+# MMC/SD/SDIO Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+CONFIG_MMC_BLOCK_BOUNCE=y
-+# CONFIG_SDIO_UART is not set
-+# CONFIG_MMC_TEST is not set
-+
-+#
-+# MMC/SD/SDIO Host Controller Drivers
-+#
-+# CONFIG_MMC_SDHCI is not set
-+CONFIG_MMC_OMAP_HS=y
-+# CONFIG_MEMSTICK is not set
-+# CONFIG_ACCESSIBILITY is not set
-+# CONFIG_NEW_LEDS is not set
-+CONFIG_RTC_LIB=y
-+CONFIG_RTC_CLASS=y
-+CONFIG_RTC_HCTOSYS=y
-+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-+# CONFIG_RTC_DEBUG is not set
-+
-+#
-+# RTC interfaces
-+#
-+CONFIG_RTC_INTF_SYSFS=y
-+CONFIG_RTC_INTF_PROC=y
-+CONFIG_RTC_INTF_DEV=y
-+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-+# CONFIG_RTC_DRV_TEST is not set
-+
-+#
-+# I2C RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
-+CONFIG_RTC_DRV_TWL4030=y
-+# CONFIG_RTC_DRV_S35390A is not set
-+# CONFIG_RTC_DRV_FM3130 is not set
-+# CONFIG_RTC_DRV_RX8581 is not set
-+
-+#
-+# SPI RTC drivers
-+#
-+
-+#
-+# Platform RTC drivers
-+#
-+# CONFIG_RTC_DRV_CMOS is not set
-+# CONFIG_RTC_DRV_DS1286 is not set
-+# CONFIG_RTC_DRV_DS1511 is not set
-+# CONFIG_RTC_DRV_DS1553 is not set
-+# CONFIG_RTC_DRV_DS1742 is not set
-+# CONFIG_RTC_DRV_STK17TA8 is not set
-+# CONFIG_RTC_DRV_M48T86 is not set
-+# CONFIG_RTC_DRV_M48T35 is not set
-+# CONFIG_RTC_DRV_M48T59 is not set
-+# CONFIG_RTC_DRV_BQ4802 is not set
-+# CONFIG_RTC_DRV_V3020 is not set
-+
-+#
-+# on-CPU RTC drivers
-+#
-+# CONFIG_DMADEVICES is not set
-+CONFIG_REGULATOR=y
-+# CONFIG_REGULATOR_DEBUG is not set
-+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-+# CONFIG_REGULATOR_BQ24022 is not set
-+CONFIG_REGULATOR_TWL4030=y
-+# CONFIG_UIO is not set
-+# CONFIG_STAGING is not set
-+
-+#
-+# CBUS support
-+#
-+# CONFIG_CBUS is not set
-+
-+#
-+# File systems
-+#
-+CONFIG_EXT2_FS=y
-+# CONFIG_EXT2_FS_XATTR is not set
-+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=y
-+# CONFIG_EXT3_FS_XATTR is not set
-+# CONFIG_EXT4_FS is not set
-+CONFIG_JBD=y
-+# CONFIG_JBD_DEBUG is not set
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+# CONFIG_FS_POSIX_ACL is not set
-+CONFIG_FILE_LOCKING=y
-+# CONFIG_XFS_FS is not set
-+# CONFIG_OCFS2_FS is not set
-+# CONFIG_BTRFS_FS is not set
-+CONFIG_DNOTIFY=y
-+CONFIG_INOTIFY=y
-+CONFIG_INOTIFY_USER=y
-+CONFIG_QUOTA=y
-+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
-+CONFIG_PRINT_QUOTA_WARNING=y
-+CONFIG_QUOTA_TREE=y
-+# CONFIG_QFMT_V1 is not set
-+CONFIG_QFMT_V2=y
-+CONFIG_QUOTACTL=y
-+# CONFIG_AUTOFS_FS is not set
-+# CONFIG_AUTOFS4_FS is not set
-+# CONFIG_FUSE_FS is not set
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=y
-+CONFIG_MSDOS_FS=y
-+CONFIG_VFAT_FS=y
-+CONFIG_FAT_DEFAULT_CODEPAGE=437
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+# CONFIG_NTFS_FS is not set
-+
-+#
-+# Pseudo filesystems
-+#
-+CONFIG_PROC_FS=y
-+CONFIG_PROC_SYSCTL=y
-+CONFIG_PROC_PAGE_MONITOR=y
-+CONFIG_SYSFS=y
-+CONFIG_TMPFS=y
-+# CONFIG_TMPFS_POSIX_ACL is not set
-+# CONFIG_HUGETLB_PAGE is not set
-+# CONFIG_CONFIGFS_FS is not set
-+CONFIG_MISC_FILESYSTEMS=y
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
-+CONFIG_JFFS2_FS=y
-+CONFIG_JFFS2_FS_DEBUG=0
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-+# CONFIG_JFFS2_SUMMARY is not set
-+# CONFIG_JFFS2_FS_XATTR is not set
-+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-+CONFIG_JFFS2_ZLIB=y
-+# CONFIG_JFFS2_LZO is not set
-+CONFIG_JFFS2_RTIME=y
-+# CONFIG_JFFS2_RUBIN is not set
-+# CONFIG_CRAMFS is not set
-+# CONFIG_SQUASHFS is not set
-+# CONFIG_VXFS_FS is not set
-+# CONFIG_MINIX_FS is not set
-+# CONFIG_OMFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+CONFIG_NFS_V4=y
-+CONFIG_ROOT_NFS=y
-+# CONFIG_NFSD is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+CONFIG_SUNRPC_GSS=y
-+# CONFIG_SUNRPC_REGISTER_V4 is not set
-+CONFIG_RPCSEC_GSS_KRB5=y
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+# CONFIG_SMB_FS is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+
-+#
-+# Partition Types
-+#
-+CONFIG_PARTITION_ADVANCED=y
-+# CONFIG_ACORN_PARTITION is not set
-+# CONFIG_OSF_PARTITION is not set
-+# CONFIG_AMIGA_PARTITION is not set
-+# CONFIG_ATARI_PARTITION is not set
-+# CONFIG_MAC_PARTITION is not set
-+CONFIG_MSDOS_PARTITION=y
-+# CONFIG_BSD_DISKLABEL is not set
-+# CONFIG_MINIX_SUBPARTITION is not set
-+# CONFIG_SOLARIS_X86_PARTITION is not set
-+# CONFIG_UNIXWARE_DISKLABEL is not set
-+# CONFIG_LDM_PARTITION is not set
-+# CONFIG_SGI_PARTITION is not set
-+# CONFIG_ULTRIX_PARTITION is not set
-+# CONFIG_SUN_PARTITION is not set
-+# CONFIG_KARMA_PARTITION is not set
-+# CONFIG_EFI_PARTITION is not set
-+# CONFIG_SYSV68_PARTITION is not set
-+CONFIG_NLS=y
-+CONFIG_NLS_DEFAULT="iso8859-1"
-+CONFIG_NLS_CODEPAGE_437=y
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+# CONFIG_NLS_CODEPAGE_850 is not set
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+# CONFIG_NLS_ASCII is not set
-+CONFIG_NLS_ISO8859_1=y
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+# CONFIG_NLS_UTF8 is not set
-+# CONFIG_DLM is not set
-+
-+#
-+# Kernel hacking
-+#
-+# CONFIG_PRINTK_TIME is not set
-+CONFIG_ENABLE_WARN_DEPRECATED=y
-+CONFIG_ENABLE_MUST_CHECK=y
-+CONFIG_FRAME_WARN=1024
-+CONFIG_MAGIC_SYSRQ=y
-+# CONFIG_UNUSED_SYMBOLS is not set
-+CONFIG_DEBUG_FS=y
-+# CONFIG_HEADERS_CHECK is not set
-+CONFIG_DEBUG_KERNEL=y
-+# CONFIG_DEBUG_SHIRQ is not set
-+CONFIG_DETECT_SOFTLOCKUP=y
-+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-+CONFIG_SCHED_DEBUG=y
-+# CONFIG_SCHEDSTATS is not set
-+# CONFIG_TIMER_STATS is not set
-+# CONFIG_DEBUG_OBJECTS is not set
-+# CONFIG_DEBUG_SLAB is not set
-+# CONFIG_DEBUG_RT_MUTEXES is not set
-+# CONFIG_RT_MUTEX_TESTER is not set
-+# CONFIG_DEBUG_SPINLOCK is not set
-+CONFIG_DEBUG_MUTEXES=y
-+# CONFIG_DEBUG_LOCK_ALLOC is not set
-+# CONFIG_PROVE_LOCKING is not set
-+# CONFIG_LOCK_STAT is not set
-+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-+# CONFIG_DEBUG_KOBJECT is not set
-+CONFIG_DEBUG_BUGVERBOSE=y
-+CONFIG_DEBUG_INFO=y
-+# CONFIG_DEBUG_VM is not set
-+# CONFIG_DEBUG_WRITECOUNT is not set
-+# CONFIG_DEBUG_MEMORY_INIT is not set
-+# CONFIG_DEBUG_LIST is not set
-+# CONFIG_DEBUG_SG is not set
-+# CONFIG_DEBUG_NOTIFIERS is not set
-+CONFIG_FRAME_POINTER=y
-+# CONFIG_BOOT_PRINTK_DELAY is not set
-+# CONFIG_RCU_TORTURE_TEST is not set
-+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-+# CONFIG_BACKTRACE_SELF_TEST is not set
-+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-+# CONFIG_FAULT_INJECTION is not set
-+# CONFIG_LATENCYTOP is not set
-+CONFIG_HAVE_FUNCTION_TRACER=y
-+
-+#
-+# Tracers
-+#
-+# CONFIG_FUNCTION_TRACER is not set
-+# CONFIG_IRQSOFF_TRACER is not set
-+# CONFIG_SCHED_TRACER is not set
-+# CONFIG_CONTEXT_SWITCH_TRACER is not set
-+# CONFIG_BOOT_TRACER is not set
-+# CONFIG_TRACE_BRANCH_PROFILING is not set
-+# CONFIG_STACK_TRACER is not set
-+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
-+# CONFIG_SAMPLES is not set
-+CONFIG_HAVE_ARCH_KGDB=y
-+# CONFIG_KGDB is not set
-+CONFIG_DEBUG_USER=y
-+CONFIG_DEBUG_ERRORS=y
-+# CONFIG_DEBUG_STACK_USAGE is not set
-+# CONFIG_DEBUG_LL is not set
-+
-+#
-+# Security options
-+#
-+# CONFIG_KEYS is not set
-+# CONFIG_SECURITY is not set
-+# CONFIG_SECURITYFS is not set
-+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+# CONFIG_CRYPTO_FIPS is not set
-+CONFIG_CRYPTO_ALGAPI=y
-+CONFIG_CRYPTO_ALGAPI2=y
-+CONFIG_CRYPTO_AEAD2=y
-+CONFIG_CRYPTO_BLKCIPHER=y
-+CONFIG_CRYPTO_BLKCIPHER2=y
-+CONFIG_CRYPTO_HASH=y
-+CONFIG_CRYPTO_HASH2=y
-+CONFIG_CRYPTO_RNG2=y
-+CONFIG_CRYPTO_MANAGER=y
-+CONFIG_CRYPTO_MANAGER2=y
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_CRYPTD is not set
-+# CONFIG_CRYPTO_AUTHENC is not set
-+# CONFIG_CRYPTO_TEST is not set
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=y
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+CONFIG_CRYPTO_ECB=m
-+# CONFIG_CRYPTO_LRW is not set
-+CONFIG_CRYPTO_PCBC=m
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+# CONFIG_CRYPTO_HMAC is not set
-+# CONFIG_CRYPTO_XCBC is not set
-+
-+#
-+# Digest
-+#
-+CONFIG_CRYPTO_CRC32C=y
-+# CONFIG_CRYPTO_MD4 is not set
-+CONFIG_CRYPTO_MD5=y
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+# CONFIG_CRYPTO_SHA1 is not set
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+# CONFIG_CRYPTO_ARC4 is not set
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+CONFIG_CRYPTO_DES=y
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+# CONFIG_CRYPTO_DEFLATE is not set
-+# CONFIG_CRYPTO_LZO is not set
-+
-+#
-+# Random Number Generation
-+#
-+# CONFIG_CRYPTO_ANSI_CPRNG is not set
-+CONFIG_CRYPTO_HW=y
-+
-+#
-+# Library routines
-+#
-+CONFIG_BITREVERSE=y
-+CONFIG_GENERIC_FIND_LAST_BIT=y
-+CONFIG_CRC_CCITT=y
-+# CONFIG_CRC16 is not set
-+# CONFIG_CRC_T10DIF is not set
-+# CONFIG_CRC_ITU_T is not set
-+CONFIG_CRC32=y
-+# CONFIG_CRC7 is not set
-+CONFIG_LIBCRC32C=y
-+CONFIG_ZLIB_INFLATE=y
-+CONFIG_ZLIB_DEFLATE=y
-+CONFIG_PLIST=y
-+CONFIG_HAS_IOMEM=y
-+CONFIG_HAS_IOPORT=y
-+CONFIG_HAS_DMA=y
-diff --git a/arch/arm/configs/dss_omap_3430sdp_defconfig b/arch/arm/configs/dss_omap_3430sdp_defconfig
-new file mode 100644
-index 0000000..dc30dce
---- /dev/null
-+++ b/arch/arm/configs/dss_omap_3430sdp_defconfig
-@@ -0,0 +1,1634 @@
-+#
-+# Automatically generated make config: don't edit
-+# Linux kernel version: 2.6.29-omap1
-+# Thu Apr 2 11:11:24 2009
-+#
-+CONFIG_ARM=y
-+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-+CONFIG_GENERIC_GPIO=y
-+CONFIG_GENERIC_TIME=y
-+CONFIG_GENERIC_CLOCKEVENTS=y
-+CONFIG_MMU=y
-+# CONFIG_NO_IOPORT is not set
-+CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_STACKTRACE_SUPPORT=y
-+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-+CONFIG_LOCKDEP_SUPPORT=y
-+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-+CONFIG_HARDIRQS_SW_RESEND=y
-+CONFIG_GENERIC_IRQ_PROBE=y
-+CONFIG_RWSEM_GENERIC_SPINLOCK=y
-+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-+CONFIG_GENERIC_HWEIGHT=y
-+CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-+CONFIG_VECTORS_BASE=0xffff0000
-+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-+
-+#
-+# General setup
-+#
-+CONFIG_EXPERIMENTAL=y
-+CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-+CONFIG_LOCALVERSION=""
-+CONFIG_LOCALVERSION_AUTO=y
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_SYSVIPC_SYSCTL=y
-+# CONFIG_POSIX_MQUEUE is not set
-+CONFIG_BSD_PROCESS_ACCT=y
-+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_AUDIT is not set
-+
-+#
-+# RCU Subsystem
-+#
-+CONFIG_CLASSIC_RCU=y
-+# CONFIG_TREE_RCU is not set
-+# CONFIG_PREEMPT_RCU is not set
-+# CONFIG_TREE_RCU_TRACE is not set
-+# CONFIG_PREEMPT_RCU_TRACE is not set
-+# CONFIG_IKCONFIG is not set
-+CONFIG_LOG_BUF_SHIFT=14
-+CONFIG_GROUP_SCHED=y
-+CONFIG_FAIR_GROUP_SCHED=y
-+# CONFIG_RT_GROUP_SCHED is not set
-+CONFIG_USER_SCHED=y
-+# CONFIG_CGROUP_SCHED is not set
-+# CONFIG_CGROUPS is not set
-+CONFIG_SYSFS_DEPRECATED=y
-+CONFIG_SYSFS_DEPRECATED_V2=y
-+# CONFIG_RELAY is not set
-+# CONFIG_NAMESPACES is not set
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE=""
-+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-+CONFIG_SYSCTL=y
-+CONFIG_ANON_INODES=y
-+CONFIG_EMBEDDED=y
-+CONFIG_UID16=y
-+# CONFIG_SYSCTL_SYSCALL is not set
-+CONFIG_KALLSYMS=y
-+# CONFIG_KALLSYMS_ALL is not set
-+CONFIG_KALLSYMS_EXTRA_PASS=y
-+CONFIG_HOTPLUG=y
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_ELF_CORE=y
-+CONFIG_BASE_FULL=y
-+CONFIG_FUTEX=y
-+CONFIG_EPOLL=y
-+CONFIG_SIGNALFD=y
-+CONFIG_TIMERFD=y
-+CONFIG_EVENTFD=y
-+CONFIG_SHMEM=y
-+CONFIG_AIO=y
-+CONFIG_VM_EVENT_COUNTERS=y
-+CONFIG_COMPAT_BRK=y
-+CONFIG_SLAB=y
-+# CONFIG_SLUB is not set
-+# CONFIG_SLOB is not set
-+# CONFIG_PROFILING is not set
-+CONFIG_HAVE_OPROFILE=y
-+# CONFIG_KPROBES is not set
-+CONFIG_HAVE_KPROBES=y
-+CONFIG_HAVE_KRETPROBES=y
-+CONFIG_HAVE_CLK=y
-+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-+CONFIG_SLABINFO=y
-+CONFIG_RT_MUTEXES=y
-+CONFIG_BASE_SMALL=0
-+CONFIG_MODULES=y
-+# CONFIG_MODULE_FORCE_LOAD is not set
-+CONFIG_MODULE_UNLOAD=y
-+# CONFIG_MODULE_FORCE_UNLOAD is not set
-+CONFIG_MODVERSIONS=y
-+CONFIG_MODULE_SRCVERSION_ALL=y
-+CONFIG_BLOCK=y
-+# CONFIG_LBD is not set
-+# CONFIG_BLK_DEV_IO_TRACE is not set
-+# CONFIG_BLK_DEV_BSG is not set
-+# CONFIG_BLK_DEV_INTEGRITY is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+CONFIG_IOSCHED_AS=y
-+CONFIG_IOSCHED_DEADLINE=y
-+CONFIG_IOSCHED_CFQ=y
-+CONFIG_DEFAULT_AS=y
-+# CONFIG_DEFAULT_DEADLINE is not set
-+# CONFIG_DEFAULT_CFQ is not set
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="anticipatory"
-+CONFIG_FREEZER=y
-+
-+#
-+# System Type
-+#
-+# CONFIG_ARCH_AAEC2000 is not set
-+# CONFIG_ARCH_INTEGRATOR is not set
-+# CONFIG_ARCH_REALVIEW is not set
-+# CONFIG_ARCH_VERSATILE is not set
-+# CONFIG_ARCH_AT91 is not set
-+# CONFIG_ARCH_CLPS711X is not set
-+# CONFIG_ARCH_EBSA110 is not set
-+# CONFIG_ARCH_EP93XX is not set
-+# CONFIG_ARCH_FOOTBRIDGE is not set
-+# CONFIG_ARCH_NETX is not set
-+# CONFIG_ARCH_H720X is not set
-+# CONFIG_ARCH_IMX is not set
-+# CONFIG_ARCH_IOP13XX is not set
-+# CONFIG_ARCH_IOP32X is not set
-+# CONFIG_ARCH_IOP33X is not set
-+# CONFIG_ARCH_IXP23XX is not set
-+# CONFIG_ARCH_IXP2000 is not set
-+# CONFIG_ARCH_IXP4XX is not set
-+# CONFIG_ARCH_L7200 is not set
-+# CONFIG_ARCH_KIRKWOOD is not set
-+# CONFIG_ARCH_KS8695 is not set
-+# CONFIG_ARCH_NS9XXX is not set
-+# CONFIG_ARCH_LOKI is not set
-+# CONFIG_ARCH_MV78XX0 is not set
-+# CONFIG_ARCH_MXC is not set
-+# CONFIG_ARCH_ORION5X is not set
-+# CONFIG_ARCH_PNX4008 is not set
-+# CONFIG_ARCH_PXA is not set
-+# CONFIG_ARCH_RPC is not set
-+# CONFIG_ARCH_SA1100 is not set
-+# CONFIG_ARCH_S3C2410 is not set
-+# CONFIG_ARCH_S3C64XX is not set
-+# CONFIG_ARCH_SHARK is not set
-+# CONFIG_ARCH_LH7A40X is not set
-+# CONFIG_ARCH_DAVINCI is not set
-+CONFIG_ARCH_OMAP=y
-+# CONFIG_ARCH_MSM is not set
-+# CONFIG_ARCH_W90X900 is not set
-+
-+#
-+# TI OMAP Implementations
-+#
-+CONFIG_ARCH_OMAP_OTG=y
-+# CONFIG_ARCH_OMAP1 is not set
-+# CONFIG_ARCH_OMAP2 is not set
-+CONFIG_ARCH_OMAP3=y
-+
-+#
-+# OMAP Feature Selections
-+#
-+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
-+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
-+CONFIG_OMAP_SMARTREFLEX=y
-+# CONFIG_OMAP_SMARTREFLEX_TESTING is not set
-+CONFIG_OMAP_RESET_CLOCKS=y
-+CONFIG_OMAP_BOOT_TAG=y
-+CONFIG_OMAP_BOOT_REASON=y
-+# CONFIG_OMAP_COMPONENT_VERSION is not set
-+# CONFIG_OMAP_GPIO_SWITCH is not set
-+CONFIG_OMAP_MUX=y
-+CONFIG_OMAP_MUX_DEBUG=y
-+CONFIG_OMAP_MUX_WARNINGS=y
-+# CONFIG_OMAP_MCBSP is not set
-+# CONFIG_OMAP_MBOX_FWK is not set
-+# CONFIG_OMAP_MPU_TIMER is not set
-+CONFIG_OMAP_32K_TIMER=y
-+CONFIG_OMAP_32K_TIMER_HZ=128
-+CONFIG_OMAP_TICK_GPTIMER=1
-+CONFIG_OMAP_DM_TIMER=y
-+CONFIG_OMAP_LL_DEBUG_UART1=y
-+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
-+# CONFIG_OMAP_LL_DEBUG_UART3 is not set
-+CONFIG_OMAP_SERIAL_WAKE=y
-+CONFIG_ARCH_OMAP34XX=y
-+CONFIG_ARCH_OMAP3430=y
-+
-+#
-+# OMAP Board Type
-+#
-+# CONFIG_MACH_NOKIA_RX51 is not set
-+# CONFIG_MACH_OMAP_LDP is not set
-+CONFIG_MACH_OMAP_3430SDP=y
-+# CONFIG_MACH_OMAP3EVM is not set
-+# CONFIG_MACH_OMAP3_BEAGLE is not set
-+# CONFIG_MACH_OVERO is not set
-+# CONFIG_MACH_OMAP3_PANDORA is not set
-+
-+#
-+# Processor Type
-+#
-+CONFIG_CPU_32=y
-+CONFIG_CPU_32v6K=y
-+CONFIG_CPU_V7=y
-+CONFIG_CPU_32v7=y
-+CONFIG_CPU_ABRT_EV7=y
-+CONFIG_CPU_PABRT_IFAR=y
-+CONFIG_CPU_CACHE_V7=y
-+CONFIG_CPU_CACHE_VIPT=y
-+CONFIG_CPU_COPY_V6=y
-+CONFIG_CPU_TLB_V7=y
-+CONFIG_CPU_HAS_ASID=y
-+CONFIG_CPU_CP15=y
-+CONFIG_CPU_CP15_MMU=y
-+
-+#
-+# Processor Features
-+#
-+CONFIG_ARM_THUMB=y
-+# CONFIG_ARM_THUMBEE is not set
-+# CONFIG_CPU_ICACHE_DISABLE is not set
-+# CONFIG_CPU_DCACHE_DISABLE is not set
-+# CONFIG_CPU_BPREDICT_DISABLE is not set
-+CONFIG_HAS_TLS_REG=y
-+# CONFIG_OUTER_CACHE is not set
-+
-+#
-+# Bus support
-+#
-+# CONFIG_PCI_SYSCALL is not set
-+# CONFIG_ARCH_SUPPORTS_MSI is not set
-+# CONFIG_PCCARD is not set
-+
-+#
-+# Kernel Features
-+#
-+CONFIG_TICK_ONESHOT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-+CONFIG_VMSPLIT_3G=y
-+# CONFIG_VMSPLIT_2G is not set
-+# CONFIG_VMSPLIT_1G is not set
-+CONFIG_PAGE_OFFSET=0xC0000000
-+# CONFIG_PREEMPT is not set
-+CONFIG_HZ=128
-+CONFIG_AEABI=y
-+CONFIG_OABI_COMPAT=y
-+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
-+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-+CONFIG_SELECT_MEMORY_MODEL=y
-+CONFIG_FLATMEM_MANUAL=y
-+# CONFIG_DISCONTIGMEM_MANUAL is not set
-+# CONFIG_SPARSEMEM_MANUAL is not set
-+CONFIG_FLATMEM=y
-+CONFIG_FLAT_NODE_MEM_MAP=y
-+CONFIG_PAGEFLAGS_EXTENDED=y
-+CONFIG_SPLIT_PTLOCK_CPUS=4
-+# CONFIG_PHYS_ADDR_T_64BIT is not set
-+CONFIG_ZONE_DMA_FLAG=0
-+CONFIG_VIRT_TO_BUS=y
-+CONFIG_UNEVICTABLE_LRU=y
-+# CONFIG_LEDS is not set
-+CONFIG_ALIGNMENT_TRAP=y
-+
-+#
-+# Boot options
-+#
-+CONFIG_ZBOOT_ROM_TEXT=0x0
-+CONFIG_ZBOOT_ROM_BSS=0x0
-+CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8"
-+# CONFIG_XIP_KERNEL is not set
-+# CONFIG_KEXEC is not set
-+
-+#
-+# CPU Power Management
-+#
-+# CONFIG_CPU_FREQ is not set
-+# CONFIG_CPU_IDLE is not set
-+
-+#
-+# Floating point emulation
-+#
-+
-+#
-+# At least one emulation must be selected
-+#
-+CONFIG_FPE_NWFPE=y
-+# CONFIG_FPE_NWFPE_XP is not set
-+# CONFIG_FPE_FASTFPE is not set
-+CONFIG_VFP=y
-+CONFIG_VFPv3=y
-+# CONFIG_NEON is not set
-+
-+#
-+# Userspace binary formats
-+#
-+CONFIG_BINFMT_ELF=y
-+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-+CONFIG_HAVE_AOUT=y
-+# CONFIG_BINFMT_AOUT is not set
-+CONFIG_BINFMT_MISC=y
-+
-+#
-+# Power management options
-+#
-+CONFIG_PM=y
-+# CONFIG_PM_DEBUG is not set
-+CONFIG_PM_SLEEP=y
-+CONFIG_SUSPEND=y
-+CONFIG_SUSPEND_FREEZER=y
-+# CONFIG_APM_EMULATION is not set
-+CONFIG_ARCH_SUSPEND_POSSIBLE=y
-+CONFIG_NET=y
-+
-+#
-+# Networking options
-+#
-+CONFIG_COMPAT_NET_DEV_OPS=y
-+CONFIG_PACKET=y
-+# CONFIG_PACKET_MMAP is not set
-+CONFIG_UNIX=y
-+CONFIG_XFRM=y
-+# CONFIG_XFRM_USER is not set
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+CONFIG_NET_KEY=y
-+# CONFIG_NET_KEY_MIGRATE is not set
-+CONFIG_INET=y
-+# CONFIG_IP_MULTICAST is not set
-+# CONFIG_IP_ADVANCED_ROUTER is not set
-+CONFIG_IP_FIB_HASH=y
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+CONFIG_IP_PNP_BOOTP=y
-+CONFIG_IP_PNP_RARP=y
-+# CONFIG_NET_IPIP is not set
-+# CONFIG_NET_IPGRE is not set
-+# CONFIG_ARPD is not set
-+# CONFIG_SYN_COOKIES is not set
-+# CONFIG_INET_AH is not set
-+# CONFIG_INET_ESP is not set
-+# CONFIG_INET_IPCOMP is not set
-+# CONFIG_INET_XFRM_TUNNEL is not set
-+# CONFIG_INET_TUNNEL is not set
-+CONFIG_INET_XFRM_MODE_TRANSPORT=y
-+CONFIG_INET_XFRM_MODE_TUNNEL=y
-+CONFIG_INET_XFRM_MODE_BEET=y
-+# CONFIG_INET_LRO is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
-+# CONFIG_TCP_CONG_ADVANCED is not set
-+CONFIG_TCP_CONG_CUBIC=y
-+CONFIG_DEFAULT_TCP_CONG="cubic"
-+# CONFIG_TCP_MD5SIG is not set
-+# CONFIG_IPV6 is not set
-+# CONFIG_NETWORK_SECMARK is not set
-+# CONFIG_NETFILTER is not set
-+# CONFIG_IP_DCCP is not set
-+# CONFIG_IP_SCTP is not set
-+# CONFIG_TIPC is not set
-+# CONFIG_ATM is not set
-+# CONFIG_BRIDGE is not set
-+# CONFIG_NET_DSA is not set
-+# CONFIG_VLAN_8021Q is not set
-+# CONFIG_DECNET is not set
-+# CONFIG_LLC2 is not set
-+# CONFIG_IPX is not set
-+# CONFIG_ATALK is not set
-+# CONFIG_X25 is not set
-+# CONFIG_LAPB is not set
-+# CONFIG_ECONET is not set
-+# CONFIG_WAN_ROUTER is not set
-+# CONFIG_NET_SCHED is not set
-+# CONFIG_DCB is not set
-+
-+#
-+# Network testing
-+#
-+# CONFIG_NET_PKTGEN is not set
-+# CONFIG_HAMRADIO is not set
-+# CONFIG_CAN is not set
-+# CONFIG_IRDA is not set
-+# CONFIG_BT is not set
-+# CONFIG_AF_RXRPC is not set
-+# CONFIG_PHONET is not set
-+CONFIG_WIRELESS=y
-+# CONFIG_CFG80211 is not set
-+CONFIG_WIRELESS_OLD_REGULATORY=y
-+# CONFIG_WIRELESS_EXT is not set
-+# CONFIG_LIB80211 is not set
-+# CONFIG_MAC80211 is not set
-+# CONFIG_WIMAX is not set
-+# CONFIG_RFKILL is not set
-+# CONFIG_NET_9P is not set
-+
-+#
-+# Device Drivers
-+#
-+
-+#
-+# Generic Driver Options
-+#
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-+CONFIG_STANDALONE=y
-+CONFIG_PREVENT_FIRMWARE_BUILD=y
-+# CONFIG_FW_LOADER is not set
-+# CONFIG_DEBUG_DRIVER is not set
-+# CONFIG_DEBUG_DEVRES is not set
-+# CONFIG_SYS_HYPERVISOR is not set
-+# CONFIG_CONNECTOR is not set
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+CONFIG_MTD_CONCAT=y
-+CONFIG_MTD_PARTITIONS=y
-+# CONFIG_MTD_TESTS is not set
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+CONFIG_MTD_CMDLINE_PARTS=y
-+# CONFIG_MTD_AFS_PARTS is not set
-+# CONFIG_MTD_AR7_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLKDEVS=y
-+CONFIG_MTD_BLOCK=y
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+# CONFIG_SSFDC is not set
-+# CONFIG_MTD_OOPS is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+CONFIG_MTD_CFI=y
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_GEN_PROBE=y
-+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+CONFIG_MTD_CFI_INTELEXT=y
-+# CONFIG_MTD_CFI_AMDSTD is not set
-+# CONFIG_MTD_CFI_STAA is not set
-+CONFIG_MTD_CFI_UTIL=y
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+# CONFIG_MTD_PHYSMAP is not set
-+# CONFIG_MTD_ARM_INTEGRATOR is not set
-+CONFIG_MTD_OMAP_NOR=y
-+# CONFIG_MTD_PLATRAM is not set
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+# CONFIG_MTD_DATAFLASH is not set
-+# CONFIG_MTD_M25P80 is not set
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+CONFIG_MTD_NAND=y
-+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
-+CONFIG_MTD_NAND_ECC_SMC=y
-+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-+# CONFIG_MTD_NAND_GPIO is not set
-+CONFIG_MTD_NAND_OMAP2=y
-+CONFIG_MTD_NAND_IDS=y
-+# CONFIG_MTD_NAND_DISKONCHIP is not set
-+# CONFIG_MTD_NAND_NANDSIM is not set
-+# CONFIG_MTD_NAND_PLATFORM is not set
-+# CONFIG_MTD_ALAUDA is not set
-+CONFIG_MTD_ONENAND=y
-+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
-+# CONFIG_MTD_ONENAND_GENERIC is not set
-+CONFIG_MTD_ONENAND_OMAP2=y
-+# CONFIG_MTD_ONENAND_OTP is not set
-+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
-+# CONFIG_MTD_ONENAND_SIM is not set
-+
-+#
-+# LPDDR flash memory drivers
-+#
-+# CONFIG_MTD_LPDDR is not set
-+
-+#
-+# UBI - Unsorted block images
-+#
-+# CONFIG_MTD_UBI is not set
-+# CONFIG_PARPORT is not set
-+CONFIG_BLK_DEV=y
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+CONFIG_BLK_DEV_LOOP=y
-+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-+# CONFIG_BLK_DEV_NBD is not set
-+# CONFIG_BLK_DEV_UB is not set
-+CONFIG_BLK_DEV_RAM=y
-+CONFIG_BLK_DEV_RAM_COUNT=16
-+CONFIG_BLK_DEV_RAM_SIZE=16384
-+# CONFIG_BLK_DEV_XIP is not set
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+CONFIG_MISC_DEVICES=y
-+# CONFIG_ICS932S401 is not set
-+# CONFIG_OMAP_STI is not set
-+# CONFIG_ENCLOSURE_SERVICES is not set
-+# CONFIG_C2PORT is not set
-+
-+#
-+# EEPROM support
-+#
-+# CONFIG_EEPROM_AT24 is not set
-+# CONFIG_EEPROM_AT25 is not set
-+# CONFIG_EEPROM_LEGACY is not set
-+# CONFIG_EEPROM_93CX6 is not set
-+CONFIG_HAVE_IDE=y
-+# CONFIG_IDE is not set
-+
-+#
-+# SCSI device support
-+#
-+# CONFIG_RAID_ATTRS is not set
-+CONFIG_SCSI=y
-+CONFIG_SCSI_DMA=y
-+# CONFIG_SCSI_TGT is not set
-+# CONFIG_SCSI_NETLINK is not set
-+CONFIG_SCSI_PROC_FS=y
-+
-+#
-+# SCSI support type (disk, tape, CD-ROM)
-+#
-+CONFIG_BLK_DEV_SD=y
-+# CONFIG_CHR_DEV_ST is not set
-+# CONFIG_CHR_DEV_OSST is not set
-+# CONFIG_BLK_DEV_SR is not set
-+# CONFIG_CHR_DEV_SG is not set
-+# CONFIG_CHR_DEV_SCH is not set
-+
-+#
-+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-+#
-+# CONFIG_SCSI_MULTI_LUN is not set
-+# CONFIG_SCSI_CONSTANTS is not set
-+# CONFIG_SCSI_LOGGING is not set
-+# CONFIG_SCSI_SCAN_ASYNC is not set
-+CONFIG_SCSI_WAIT_SCAN=m
-+
-+#
-+# SCSI Transports
-+#
-+# CONFIG_SCSI_SPI_ATTRS is not set
-+# CONFIG_SCSI_FC_ATTRS is not set
-+# CONFIG_SCSI_ISCSI_ATTRS is not set
-+# CONFIG_SCSI_SAS_LIBSAS is not set
-+# CONFIG_SCSI_SRP_ATTRS is not set
-+CONFIG_SCSI_LOWLEVEL=y
-+# CONFIG_ISCSI_TCP is not set
-+# CONFIG_LIBFC is not set
-+# CONFIG_SCSI_DEBUG is not set
-+# CONFIG_SCSI_DH is not set
-+# CONFIG_ATA is not set
-+# CONFIG_MD is not set
-+CONFIG_NETDEVICES=y
-+# CONFIG_DUMMY is not set
-+# CONFIG_BONDING is not set
-+# CONFIG_MACVLAN is not set
-+# CONFIG_EQUALIZER is not set
-+# CONFIG_TUN is not set
-+# CONFIG_VETH is not set
-+# CONFIG_PHYLIB is not set
-+CONFIG_NET_ETHERNET=y
-+CONFIG_MII=y
-+# CONFIG_AX88796 is not set
-+CONFIG_SMC91X=y
-+# CONFIG_DM9000 is not set
-+# CONFIG_ENC28J60 is not set
-+# CONFIG_SMC911X is not set
-+# CONFIG_SMSC911X is not set
-+# CONFIG_DNET is not set
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-+# CONFIG_B44 is not set
-+CONFIG_NETDEV_1000=y
-+CONFIG_NETDEV_10000=y
-+
-+#
-+# Wireless LAN
-+#
-+# CONFIG_WLAN_PRE80211 is not set
-+# CONFIG_WLAN_80211 is not set
-+# CONFIG_IWLWIFI_LEDS is not set
-+
-+#
-+# Enable WiMAX (Networking options) to see the WiMAX drivers
-+#
-+
-+#
-+# USB Network Adapters
-+#
-+# CONFIG_USB_CATC is not set
-+# CONFIG_USB_KAWETH is not set
-+# CONFIG_USB_PEGASUS is not set
-+# CONFIG_USB_RTL8150 is not set
-+# CONFIG_USB_USBNET is not set
-+# CONFIG_WAN is not set
-+# CONFIG_PPP is not set
-+# CONFIG_SLIP is not set
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
-+# CONFIG_ISDN is not set
-+
-+#
-+# Input device support
-+#
-+CONFIG_INPUT=y
-+# CONFIG_INPUT_FF_MEMLESS is not set
-+# CONFIG_INPUT_POLLDEV is not set
-+
-+#
-+# Userland interfaces
-+#
-+# CONFIG_INPUT_MOUSEDEV is not set
-+# CONFIG_INPUT_JOYDEV is not set
-+CONFIG_INPUT_EVDEV=y
-+# CONFIG_INPUT_EVBUG is not set
-+
-+#
-+# Input Device Drivers
-+#
-+CONFIG_INPUT_KEYBOARD=y
-+# CONFIG_KEYBOARD_ATKBD is not set
-+# CONFIG_KEYBOARD_SUNKBD is not set
-+# CONFIG_KEYBOARD_LKKBD is not set
-+# CONFIG_KEYBOARD_XTKBD is not set
-+# CONFIG_KEYBOARD_NEWTON is not set
-+# CONFIG_KEYBOARD_STOWAWAY is not set
-+CONFIG_KEYBOARD_TWL4030=y
-+# CONFIG_KEYBOARD_GPIO is not set
-+# CONFIG_INPUT_MOUSE is not set
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TABLET is not set
-+CONFIG_INPUT_TOUCHSCREEN=y
-+CONFIG_TOUCHSCREEN_ADS7846=y
-+# CONFIG_TOUCHSCREEN_FUJITSU is not set
-+# CONFIG_TOUCHSCREEN_GUNZE is not set
-+# CONFIG_TOUCHSCREEN_ELO is not set
-+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-+# CONFIG_TOUCHSCREEN_MTOUCH is not set
-+# CONFIG_TOUCHSCREEN_INEXIO is not set
-+# CONFIG_TOUCHSCREEN_MK712 is not set
-+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-+# CONFIG_TOUCHSCREEN_TSC2005 is not set
-+# CONFIG_TOUCHSCREEN_TSC210X is not set
-+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-+# CONFIG_TOUCHSCREEN_TSC2007 is not set
-+# CONFIG_INPUT_MISC is not set
-+
-+#
-+# Hardware I/O ports
-+#
-+# CONFIG_SERIO is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
-+# Character devices
-+#
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+CONFIG_DEVKMEM=y
-+# CONFIG_SERIAL_NONSTANDARD is not set
-+
-+#
-+# Serial drivers
-+#
-+CONFIG_SERIAL_8250=y
-+CONFIG_SERIAL_8250_CONSOLE=y
-+CONFIG_SERIAL_8250_NR_UARTS=32
-+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-+CONFIG_SERIAL_8250_EXTENDED=y
-+CONFIG_SERIAL_8250_MANY_PORTS=y
-+CONFIG_SERIAL_8250_SHARE_IRQ=y
-+CONFIG_SERIAL_8250_DETECT_IRQ=y
-+CONFIG_SERIAL_8250_RSA=y
-+
-+#
-+# Non-8250 serial port support
-+#
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+CONFIG_UNIX98_PTYS=y
-+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_IPMI_HANDLER is not set
-+CONFIG_HW_RANDOM=y
-+# CONFIG_R3964 is not set
-+# CONFIG_RAW_DRIVER is not set
-+# CONFIG_TCG_TPM is not set
-+CONFIG_I2C=y
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_CHARDEV=y
-+CONFIG_I2C_HELPER_AUTO=y
-+
-+#
-+# I2C Hardware Bus support
-+#
-+
-+#
-+# I2C system bus drivers (mostly embedded / system-on-chip)
-+#
-+# CONFIG_I2C_GPIO is not set
-+# CONFIG_I2C_OCORES is not set
-+CONFIG_I2C_OMAP=y
-+# CONFIG_I2C_SIMTEC is not set
-+
-+#
-+# External I2C/SMBus adapter drivers
-+#
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+# CONFIG_I2C_TINY_USB is not set
-+
-+#
-+# Other I2C/SMBus bus drivers
-+#
-+# CONFIG_I2C_PCA_PLATFORM is not set
-+# CONFIG_I2C_STUB is not set
-+
-+#
-+# Miscellaneous I2C Chip support
-+#
-+# CONFIG_DS1682 is not set
-+# CONFIG_SENSORS_PCF8574 is not set
-+# CONFIG_PCF8575 is not set
-+# CONFIG_SENSORS_PCA9539 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+# CONFIG_TWL4030_MADC is not set
-+# CONFIG_TWL4030_POWEROFF is not set
-+# CONFIG_SENSORS_MAX6875 is not set
-+# CONFIG_SENSORS_TSL2550 is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+# CONFIG_I2C_DEBUG_CHIP is not set
-+CONFIG_SPI=y
-+# CONFIG_SPI_DEBUG is not set
-+CONFIG_SPI_MASTER=y
-+
-+#
-+# SPI Master Controller Drivers
-+#
-+# CONFIG_SPI_BITBANG is not set
-+# CONFIG_SPI_GPIO is not set
-+CONFIG_SPI_OMAP24XX=y
-+
-+#
-+# SPI Protocol Masters
-+#
-+# CONFIG_SPI_TSC210X is not set
-+# CONFIG_SPI_TSC2301 is not set
-+# CONFIG_SPI_SPIDEV is not set
-+# CONFIG_SPI_TLE62X0 is not set
-+CONFIG_ARCH_REQUIRE_GPIOLIB=y
-+CONFIG_GPIOLIB=y
-+# CONFIG_DEBUG_GPIO is not set
-+# CONFIG_GPIO_SYSFS is not set
-+
-+#
-+# Memory mapped GPIO expanders:
-+#
-+
-+#
-+# I2C GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX732X is not set
-+# CONFIG_GPIO_PCA953X is not set
-+# CONFIG_GPIO_PCF857X is not set
-+CONFIG_GPIO_TWL4030=y
-+
-+#
-+# PCI GPIO expanders:
-+#
-+
-+#
-+# SPI GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX7301 is not set
-+# CONFIG_GPIO_MCP23S08 is not set
-+# CONFIG_W1 is not set
-+# CONFIG_POWER_SUPPLY is not set
-+# CONFIG_HWMON is not set
-+# CONFIG_THERMAL is not set
-+# CONFIG_THERMAL_HWMON is not set
-+CONFIG_WATCHDOG=y
-+CONFIG_WATCHDOG_NOWAYOUT=y
-+
-+#
-+# Watchdog Device Drivers
-+#
-+# CONFIG_SOFT_WATCHDOG is not set
-+CONFIG_OMAP_WATCHDOG=y
-+
-+#
-+# USB-based Watchdog Cards
-+#
-+# CONFIG_USBPCWATCHDOG is not set
-+CONFIG_SSB_POSSIBLE=y
-+
-+#
-+# Sonics Silicon Backplane
-+#
-+# CONFIG_SSB is not set
-+
-+#
-+# Multifunction device drivers
-+#
-+# CONFIG_MFD_CORE is not set
-+# CONFIG_MFD_SM501 is not set
-+# CONFIG_MFD_ASIC3 is not set
-+# CONFIG_HTC_EGPIO is not set
-+# CONFIG_HTC_PASIC3 is not set
-+# CONFIG_TPS65010 is not set
-+CONFIG_TWL4030_CORE=y
-+# CONFIG_TWL4030_POWER is not set
-+# CONFIG_MFD_TMIO is not set
-+# CONFIG_MFD_T7L66XB is not set
-+# CONFIG_MFD_TC6387XB is not set
-+# CONFIG_MFD_TC6393XB is not set
-+# CONFIG_PMIC_DA903X is not set
-+# CONFIG_MFD_WM8400 is not set
-+# CONFIG_MFD_WM8350_I2C is not set
-+# CONFIG_MFD_PCF50633 is not set
-+
-+#
-+# Multimedia devices
-+#
-+
-+#
-+# Multimedia core support
-+#
-+# CONFIG_VIDEO_DEV is not set
-+# CONFIG_DVB_CORE is not set
-+# CONFIG_VIDEO_MEDIA is not set
-+
-+#
-+# Multimedia drivers
-+#
-+CONFIG_DAB=y
-+# CONFIG_USB_DABUSB is not set
-+
-+#
-+# Graphics support
-+#
-+# CONFIG_VGASTATE is not set
-+CONFIG_VIDEO_OUTPUT_CONTROL=m
-+CONFIG_FB=y
-+# CONFIG_FIRMWARE_EDID is not set
-+# CONFIG_FB_DDC is not set
-+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-+CONFIG_FB_CFB_FILLRECT=m
-+CONFIG_FB_CFB_COPYAREA=m
-+CONFIG_FB_CFB_IMAGEBLIT=m
-+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-+# CONFIG_FB_SYS_FILLRECT is not set
-+# CONFIG_FB_SYS_COPYAREA is not set
-+# CONFIG_FB_SYS_IMAGEBLIT is not set
-+# CONFIG_FB_FOREIGN_ENDIAN is not set
-+# CONFIG_FB_SYS_FOPS is not set
-+# CONFIG_FB_SVGALIB is not set
-+# CONFIG_FB_MACMODES is not set
-+# CONFIG_FB_BACKLIGHT is not set
-+# CONFIG_FB_MODE_HELPERS is not set
-+# CONFIG_FB_TILEBLITTING is not set
-+
-+#
-+# Frame buffer hardware drivers
-+#
-+# CONFIG_FB_S1D13XXX is not set
-+# CONFIG_FB_VIRTUAL is not set
-+# CONFIG_FB_METRONOME is not set
-+# CONFIG_FB_MB862XX is not set
-+# CONFIG_FB_OMAP_LCD_VGA is not set
-+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
-+CONFIG_OMAP2_DSS=m
-+CONFIG_OMAP2_DSS_VRAM_SIZE=8
-+CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
-+# CONFIG_OMAP2_DSS_RFBI is not set
-+CONFIG_OMAP2_DSS_VENC=y
-+# CONFIG_OMAP2_DSS_SDI is not set
-+# CONFIG_OMAP2_DSS_DSI is not set
-+# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
-+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
-+
-+#
-+# OMAP2/3 Display Device Drivers
-+#
-+CONFIG_PANEL_GENERIC=m
-+# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set
-+CONFIG_PANEL_SHARP_LS037V7DW01=m
-+# CONFIG_PANEL_N800 is not set
-+# CONFIG_CTRL_BLIZZARD is not set
-+CONFIG_FB_OMAP2=m
-+CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
-+# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
-+CONFIG_FB_OMAP2_NUM_FBS=3
-+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-+
-+#
-+# Display device support
-+#
-+# CONFIG_DISPLAY_SUPPORT is not set
-+
-+#
-+# Console display driver support
-+#
-+# CONFIG_VGA_CONSOLE is not set
-+CONFIG_DUMMY_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE is not set
-+# CONFIG_LOGO is not set
-+# CONFIG_SOUND is not set
-+CONFIG_HID_SUPPORT=y
-+CONFIG_HID=y
-+# CONFIG_HID_DEBUG is not set
-+# CONFIG_HIDRAW is not set
-+
-+#
-+# USB Input Devices
-+#
-+CONFIG_USB_HID=y
-+# CONFIG_HID_PID is not set
-+# CONFIG_USB_HIDDEV is not set
-+
-+#
-+# Special HID drivers
-+#
-+CONFIG_HID_COMPAT=y
-+# CONFIG_HID_A4TECH is not set
-+# CONFIG_HID_APPLE is not set
-+# CONFIG_HID_BELKIN is not set
-+# CONFIG_HID_CHERRY is not set
-+# CONFIG_HID_CHICONY is not set
-+# CONFIG_HID_CYPRESS is not set
-+# CONFIG_HID_EZKEY is not set
-+# CONFIG_HID_GYRATION is not set
-+# CONFIG_HID_LOGITECH is not set
-+# CONFIG_HID_MICROSOFT is not set
-+# CONFIG_HID_MONTEREY is not set
-+# CONFIG_HID_NTRIG is not set
-+# CONFIG_HID_PANTHERLORD is not set
-+# CONFIG_HID_PETALYNX is not set
-+# CONFIG_HID_SAMSUNG is not set
-+# CONFIG_HID_SONY is not set
-+# CONFIG_HID_SUNPLUS is not set
-+# CONFIG_GREENASIA_FF is not set
-+# CONFIG_HID_TOPSEED is not set
-+# CONFIG_THRUSTMASTER_FF is not set
-+# CONFIG_ZEROPLUS_FF is not set
-+CONFIG_USB_SUPPORT=y
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+CONFIG_USB=y
-+CONFIG_USB_DEBUG=y
-+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-+
-+#
-+# Miscellaneous USB options
-+#
-+CONFIG_USB_DEVICEFS=y
-+# CONFIG_USB_DEVICE_CLASS is not set
-+# CONFIG_USB_DYNAMIC_MINORS is not set
-+CONFIG_USB_SUSPEND=y
-+CONFIG_USB_OTG=y
-+# CONFIG_USB_OTG_WHITELIST is not set
-+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+CONFIG_USB_MON=y
-+# CONFIG_USB_WUSB is not set
-+# CONFIG_USB_WUSB_CBAF is not set
-+
-+#
-+# USB Host Controller Drivers
-+#
-+# CONFIG_USB_C67X00_HCD is not set
-+CONFIG_USB_EHCI_HCD=m
-+CONFIG_OMAP_EHCI_PHY_MODE=y
-+# CONFIG_OMAP_EHCI_TLL_MODE is not set
-+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
-+# CONFIG_USB_OXU210HP_HCD is not set
-+# CONFIG_USB_ISP116X_HCD is not set
-+# CONFIG_USB_OHCI_HCD is not set
-+# CONFIG_USB_SL811_HCD is not set
-+# CONFIG_USB_R8A66597_HCD is not set
-+# CONFIG_USB_HWA_HCD is not set
-+CONFIG_USB_MUSB_HDRC=y
-+CONFIG_USB_MUSB_SOC=y
-+
-+#
-+# OMAP 343x high speed USB support
-+#
-+# CONFIG_USB_MUSB_HOST is not set
-+# CONFIG_USB_MUSB_PERIPHERAL is not set
-+CONFIG_USB_MUSB_OTG=y
-+CONFIG_USB_GADGET_MUSB_HDRC=y
-+CONFIG_USB_MUSB_HDRC_HCD=y
-+# CONFIG_MUSB_PIO_ONLY is not set
-+CONFIG_USB_INVENTRA_DMA=y
-+# CONFIG_USB_TI_CPPI_DMA is not set
-+# CONFIG_USB_MUSB_DEBUG is not set
-+
-+#
-+# USB Device Class drivers
-+#
-+# CONFIG_USB_ACM is not set
-+# CONFIG_USB_PRINTER is not set
-+# CONFIG_USB_WDM is not set
-+# CONFIG_USB_TMC is not set
-+
-+#
-+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
-+#
-+
-+#
-+# see USB_STORAGE Help for more information
-+#
-+CONFIG_USB_STORAGE=y
-+CONFIG_USB_STORAGE_DEBUG=y
-+# CONFIG_USB_STORAGE_DATAFAB is not set
-+# CONFIG_USB_STORAGE_FREECOM is not set
-+# CONFIG_USB_STORAGE_ISD200 is not set
-+# CONFIG_USB_STORAGE_USBAT is not set
-+# CONFIG_USB_STORAGE_SDDR09 is not set
-+# CONFIG_USB_STORAGE_SDDR55 is not set
-+# CONFIG_USB_STORAGE_JUMPSHOT is not set
-+# CONFIG_USB_STORAGE_ALAUDA is not set
-+# CONFIG_USB_STORAGE_ONETOUCH is not set
-+# CONFIG_USB_STORAGE_KARMA is not set
-+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-+# CONFIG_USB_LIBUSUAL is not set
-+
-+#
-+# USB Imaging devices
-+#
-+# CONFIG_USB_MDC800 is not set
-+# CONFIG_USB_MICROTEK is not set
-+
-+#
-+# USB port drivers
-+#
-+# CONFIG_USB_SERIAL is not set
-+
-+#
-+# USB Miscellaneous drivers
-+#
-+# CONFIG_USB_EMI62 is not set
-+# CONFIG_USB_EMI26 is not set
-+# CONFIG_USB_ADUTUX is not set
-+# CONFIG_USB_SEVSEG is not set
-+# CONFIG_USB_RIO500 is not set
-+# CONFIG_USB_LEGOTOWER is not set
-+# CONFIG_USB_LCD is not set
-+# CONFIG_USB_BERRY_CHARGE is not set
-+# CONFIG_USB_LED is not set
-+# CONFIG_USB_CYPRESS_CY7C63 is not set
-+# CONFIG_USB_CYTHERM is not set
-+# CONFIG_USB_PHIDGET is not set
-+# CONFIG_USB_IDMOUSE is not set
-+# CONFIG_USB_FTDI_ELAN is not set
-+# CONFIG_USB_APPLEDISPLAY is not set
-+# CONFIG_USB_SISUSBVGA is not set
-+# CONFIG_USB_LD is not set
-+# CONFIG_USB_TRANCEVIBRATOR is not set
-+# CONFIG_USB_IOWARRIOR is not set
-+CONFIG_USB_TEST=y
-+# CONFIG_USB_ISIGHTFW is not set
-+# CONFIG_USB_VST is not set
-+CONFIG_USB_GADGET=y
-+CONFIG_USB_GADGET_DEBUG=y
-+CONFIG_USB_GADGET_DEBUG_FILES=y
-+# CONFIG_USB_GADGET_DEBUG_FS is not set
-+CONFIG_USB_GADGET_VBUS_DRAW=2
-+CONFIG_USB_GADGET_SELECTED=y
-+# CONFIG_USB_GADGET_AT91 is not set
-+# CONFIG_USB_GADGET_ATMEL_USBA is not set
-+# CONFIG_USB_GADGET_FSL_USB2 is not set
-+# CONFIG_USB_GADGET_LH7A40X is not set
-+# CONFIG_USB_GADGET_OMAP is not set
-+# CONFIG_USB_GADGET_PXA25X is not set
-+# CONFIG_USB_GADGET_PXA27X is not set
-+# CONFIG_USB_GADGET_S3C2410 is not set
-+# CONFIG_USB_GADGET_IMX is not set
-+# CONFIG_USB_GADGET_M66592 is not set
-+# CONFIG_USB_GADGET_AMD5536UDC is not set
-+# CONFIG_USB_GADGET_FSL_QE is not set
-+# CONFIG_USB_GADGET_CI13XXX is not set
-+# CONFIG_USB_GADGET_NET2280 is not set
-+# CONFIG_USB_GADGET_GOKU is not set
-+# CONFIG_USB_GADGET_DUMMY_HCD is not set
-+CONFIG_USB_GADGET_DUALSPEED=y
-+CONFIG_USB_ZERO=m
-+# CONFIG_USB_ZERO_HNPTEST is not set
-+# CONFIG_USB_ETH is not set
-+# CONFIG_USB_GADGETFS is not set
-+# CONFIG_USB_FILE_STORAGE is not set
-+# CONFIG_USB_G_SERIAL is not set
-+# CONFIG_USB_MIDI_GADGET is not set
-+# CONFIG_USB_G_PRINTER is not set
-+# CONFIG_USB_CDC_COMPOSITE is not set
-+
-+#
-+# OTG and related infrastructure
-+#
-+CONFIG_USB_OTG_UTILS=y
-+# CONFIG_USB_GPIO_VBUS is not set
-+# CONFIG_ISP1301_OMAP is not set
-+CONFIG_TWL4030_USB=y
-+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+# CONFIG_MMC_UNSAFE_RESUME is not set
-+
-+#
-+# MMC/SD/SDIO Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+CONFIG_MMC_BLOCK_BOUNCE=y
-+# CONFIG_SDIO_UART is not set
-+# CONFIG_MMC_TEST is not set
-+
-+#
-+# MMC/SD/SDIO Host Controller Drivers
-+#
-+# CONFIG_MMC_SDHCI is not set
-+CONFIG_MMC_OMAP_HS=m
-+# CONFIG_MMC_SPI is not set
-+# CONFIG_MEMSTICK is not set
-+# CONFIG_ACCESSIBILITY is not set
-+# CONFIG_NEW_LEDS is not set
-+CONFIG_RTC_LIB=y
-+CONFIG_RTC_CLASS=y
-+CONFIG_RTC_HCTOSYS=y
-+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-+# CONFIG_RTC_DEBUG is not set
-+
-+#
-+# RTC interfaces
-+#
-+CONFIG_RTC_INTF_SYSFS=y
-+CONFIG_RTC_INTF_PROC=y
-+CONFIG_RTC_INTF_DEV=y
-+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-+# CONFIG_RTC_DRV_TEST is not set
-+
-+#
-+# I2C RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
-+CONFIG_RTC_DRV_TWL4030=y
-+# CONFIG_RTC_DRV_S35390A is not set
-+# CONFIG_RTC_DRV_FM3130 is not set
-+# CONFIG_RTC_DRV_RX8581 is not set
-+
-+#
-+# SPI RTC drivers
-+#
-+# CONFIG_RTC_DRV_M41T94 is not set
-+# CONFIG_RTC_DRV_DS1305 is not set
-+# CONFIG_RTC_DRV_DS1390 is not set
-+# CONFIG_RTC_DRV_MAX6902 is not set
-+# CONFIG_RTC_DRV_R9701 is not set
-+# CONFIG_RTC_DRV_RS5C348 is not set
-+# CONFIG_RTC_DRV_DS3234 is not set
-+
-+#
-+# Platform RTC drivers
-+#
-+# CONFIG_RTC_DRV_CMOS is not set
-+# CONFIG_RTC_DRV_DS1286 is not set
-+# CONFIG_RTC_DRV_DS1511 is not set
-+# CONFIG_RTC_DRV_DS1553 is not set
-+# CONFIG_RTC_DRV_DS1742 is not set
-+# CONFIG_RTC_DRV_STK17TA8 is not set
-+# CONFIG_RTC_DRV_M48T86 is not set
-+# CONFIG_RTC_DRV_M48T35 is not set
-+# CONFIG_RTC_DRV_M48T59 is not set
-+# CONFIG_RTC_DRV_BQ4802 is not set
-+# CONFIG_RTC_DRV_V3020 is not set
-+
-+#
-+# on-CPU RTC drivers
-+#
-+# CONFIG_DMADEVICES is not set
-+CONFIG_REGULATOR=y
-+# CONFIG_REGULATOR_DEBUG is not set
-+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-+# CONFIG_REGULATOR_BQ24022 is not set
-+CONFIG_REGULATOR_TWL4030=y
-+# CONFIG_UIO is not set
-+# CONFIG_STAGING is not set
-+
-+#
-+# CBUS support
-+#
-+# CONFIG_CBUS is not set
-+
-+#
-+# File systems
-+#
-+CONFIG_EXT2_FS=y
-+# CONFIG_EXT2_FS_XATTR is not set
-+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=y
-+# CONFIG_EXT3_FS_XATTR is not set
-+# CONFIG_EXT4_FS is not set
-+CONFIG_JBD=y
-+# CONFIG_JBD_DEBUG is not set
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+# CONFIG_FS_POSIX_ACL is not set
-+CONFIG_FILE_LOCKING=y
-+# CONFIG_XFS_FS is not set
-+# CONFIG_OCFS2_FS is not set
-+# CONFIG_BTRFS_FS is not set
-+CONFIG_DNOTIFY=y
-+CONFIG_INOTIFY=y
-+CONFIG_INOTIFY_USER=y
-+CONFIG_QUOTA=y
-+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
-+CONFIG_PRINT_QUOTA_WARNING=y
-+CONFIG_QUOTA_TREE=y
-+# CONFIG_QFMT_V1 is not set
-+CONFIG_QFMT_V2=y
-+CONFIG_QUOTACTL=y
-+# CONFIG_AUTOFS_FS is not set
-+# CONFIG_AUTOFS4_FS is not set
-+# CONFIG_FUSE_FS is not set
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=y
-+CONFIG_MSDOS_FS=y
-+CONFIG_VFAT_FS=y
-+CONFIG_FAT_DEFAULT_CODEPAGE=437
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+# CONFIG_NTFS_FS is not set
-+
-+#
-+# Pseudo filesystems
-+#
-+CONFIG_PROC_FS=y
-+CONFIG_PROC_SYSCTL=y
-+CONFIG_PROC_PAGE_MONITOR=y
-+CONFIG_SYSFS=y
-+CONFIG_TMPFS=y
-+# CONFIG_TMPFS_POSIX_ACL is not set
-+# CONFIG_HUGETLB_PAGE is not set
-+# CONFIG_CONFIGFS_FS is not set
-+CONFIG_MISC_FILESYSTEMS=y
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
-+CONFIG_JFFS2_FS=y
-+CONFIG_JFFS2_FS_DEBUG=0
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-+# CONFIG_JFFS2_SUMMARY is not set
-+# CONFIG_JFFS2_FS_XATTR is not set
-+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-+CONFIG_JFFS2_ZLIB=y
-+# CONFIG_JFFS2_LZO is not set
-+CONFIG_JFFS2_RTIME=y
-+# CONFIG_JFFS2_RUBIN is not set
-+# CONFIG_JFFS2_CMODE_NONE is not set
-+CONFIG_JFFS2_CMODE_PRIORITY=y
-+# CONFIG_JFFS2_CMODE_SIZE is not set
-+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
-+# CONFIG_CRAMFS is not set
-+# CONFIG_SQUASHFS is not set
-+# CONFIG_VXFS_FS is not set
-+# CONFIG_MINIX_FS is not set
-+# CONFIG_OMFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+CONFIG_NFS_V4=y
-+CONFIG_ROOT_NFS=y
-+# CONFIG_NFSD is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+CONFIG_SUNRPC_GSS=y
-+# CONFIG_SUNRPC_REGISTER_V4 is not set
-+CONFIG_RPCSEC_GSS_KRB5=y
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+# CONFIG_SMB_FS is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+
-+#
-+# Partition Types
-+#
-+CONFIG_PARTITION_ADVANCED=y
-+# CONFIG_ACORN_PARTITION is not set
-+# CONFIG_OSF_PARTITION is not set
-+# CONFIG_AMIGA_PARTITION is not set
-+# CONFIG_ATARI_PARTITION is not set
-+# CONFIG_MAC_PARTITION is not set
-+CONFIG_MSDOS_PARTITION=y
-+# CONFIG_BSD_DISKLABEL is not set
-+# CONFIG_MINIX_SUBPARTITION is not set
-+# CONFIG_SOLARIS_X86_PARTITION is not set
-+# CONFIG_UNIXWARE_DISKLABEL is not set
-+# CONFIG_LDM_PARTITION is not set
-+# CONFIG_SGI_PARTITION is not set
-+# CONFIG_ULTRIX_PARTITION is not set
-+# CONFIG_SUN_PARTITION is not set
-+# CONFIG_KARMA_PARTITION is not set
-+# CONFIG_EFI_PARTITION is not set
-+# CONFIG_SYSV68_PARTITION is not set
-+CONFIG_NLS=y
-+CONFIG_NLS_DEFAULT="iso8859-1"
-+CONFIG_NLS_CODEPAGE_437=y
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+# CONFIG_NLS_CODEPAGE_850 is not set
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+# CONFIG_NLS_ASCII is not set
-+CONFIG_NLS_ISO8859_1=y
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+# CONFIG_NLS_UTF8 is not set
-+# CONFIG_DLM is not set
-+
-+#
-+# Kernel hacking
-+#
-+# CONFIG_PRINTK_TIME is not set
-+CONFIG_ENABLE_WARN_DEPRECATED=y
-+CONFIG_ENABLE_MUST_CHECK=y
-+CONFIG_FRAME_WARN=1024
-+CONFIG_MAGIC_SYSRQ=y
-+# CONFIG_UNUSED_SYMBOLS is not set
-+CONFIG_DEBUG_FS=y
-+# CONFIG_HEADERS_CHECK is not set
-+CONFIG_DEBUG_KERNEL=y
-+# CONFIG_DEBUG_SHIRQ is not set
-+CONFIG_DETECT_SOFTLOCKUP=y
-+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-+CONFIG_SCHED_DEBUG=y
-+# CONFIG_SCHEDSTATS is not set
-+# CONFIG_TIMER_STATS is not set
-+# CONFIG_DEBUG_OBJECTS is not set
-+# CONFIG_DEBUG_SLAB is not set
-+# CONFIG_DEBUG_RT_MUTEXES is not set
-+# CONFIG_RT_MUTEX_TESTER is not set
-+# CONFIG_DEBUG_SPINLOCK is not set
-+CONFIG_DEBUG_MUTEXES=y
-+# CONFIG_DEBUG_LOCK_ALLOC is not set
-+# CONFIG_PROVE_LOCKING is not set
-+# CONFIG_LOCK_STAT is not set
-+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-+# CONFIG_DEBUG_KOBJECT is not set
-+CONFIG_DEBUG_BUGVERBOSE=y
-+CONFIG_DEBUG_INFO=y
-+# CONFIG_DEBUG_VM is not set
-+# CONFIG_DEBUG_WRITECOUNT is not set
-+# CONFIG_DEBUG_MEMORY_INIT is not set
-+# CONFIG_DEBUG_LIST is not set
-+# CONFIG_DEBUG_SG is not set
-+# CONFIG_DEBUG_NOTIFIERS is not set
-+CONFIG_FRAME_POINTER=y
-+# CONFIG_BOOT_PRINTK_DELAY is not set
-+# CONFIG_RCU_TORTURE_TEST is not set
-+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-+# CONFIG_BACKTRACE_SELF_TEST is not set
-+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-+# CONFIG_FAULT_INJECTION is not set
-+# CONFIG_LATENCYTOP is not set
-+CONFIG_HAVE_FUNCTION_TRACER=y
-+
-+#
-+# Tracers
-+#
-+# CONFIG_FUNCTION_TRACER is not set
-+# CONFIG_IRQSOFF_TRACER is not set
-+# CONFIG_SCHED_TRACER is not set
-+# CONFIG_CONTEXT_SWITCH_TRACER is not set
-+# CONFIG_BOOT_TRACER is not set
-+# CONFIG_TRACE_BRANCH_PROFILING is not set
-+# CONFIG_STACK_TRACER is not set
-+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
-+# CONFIG_SAMPLES is not set
-+CONFIG_HAVE_ARCH_KGDB=y
-+# CONFIG_KGDB is not set
-+CONFIG_DEBUG_USER=y
-+CONFIG_DEBUG_ERRORS=y
-+# CONFIG_DEBUG_STACK_USAGE is not set
-+# CONFIG_DEBUG_LL is not set
-+
-+#
-+# Security options
-+#
-+# CONFIG_KEYS is not set
-+# CONFIG_SECURITY is not set
-+# CONFIG_SECURITYFS is not set
-+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+# CONFIG_CRYPTO_FIPS is not set
-+CONFIG_CRYPTO_ALGAPI=y
-+CONFIG_CRYPTO_ALGAPI2=y
-+CONFIG_CRYPTO_AEAD2=y
-+CONFIG_CRYPTO_BLKCIPHER=y
-+CONFIG_CRYPTO_BLKCIPHER2=y
-+CONFIG_CRYPTO_HASH=y
-+CONFIG_CRYPTO_HASH2=y
-+CONFIG_CRYPTO_RNG2=y
-+CONFIG_CRYPTO_MANAGER=y
-+CONFIG_CRYPTO_MANAGER2=y
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_CRYPTD is not set
-+# CONFIG_CRYPTO_AUTHENC is not set
-+# CONFIG_CRYPTO_TEST is not set
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=y
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+CONFIG_CRYPTO_ECB=m
-+# CONFIG_CRYPTO_LRW is not set
-+CONFIG_CRYPTO_PCBC=m
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+# CONFIG_CRYPTO_HMAC is not set
-+# CONFIG_CRYPTO_XCBC is not set
-+
-+#
-+# Digest
-+#
-+CONFIG_CRYPTO_CRC32C=y
-+# CONFIG_CRYPTO_MD4 is not set
-+CONFIG_CRYPTO_MD5=y
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+# CONFIG_CRYPTO_SHA1 is not set
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+# CONFIG_CRYPTO_ARC4 is not set
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+CONFIG_CRYPTO_DES=y
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+# CONFIG_CRYPTO_DEFLATE is not set
-+# CONFIG_CRYPTO_LZO is not set
-+
-+#
-+# Random Number Generation
-+#
-+# CONFIG_CRYPTO_ANSI_CPRNG is not set
-+CONFIG_CRYPTO_HW=y
-+
-+#
-+# Library routines
-+#
-+CONFIG_BITREVERSE=y
-+CONFIG_GENERIC_FIND_LAST_BIT=y
-+CONFIG_CRC_CCITT=y
-+# CONFIG_CRC16 is not set
-+# CONFIG_CRC_T10DIF is not set
-+# CONFIG_CRC_ITU_T is not set
-+CONFIG_CRC32=y
-+# CONFIG_CRC7 is not set
-+CONFIG_LIBCRC32C=y
-+CONFIG_ZLIB_INFLATE=y
-+CONFIG_ZLIB_DEFLATE=y
-+CONFIG_PLIST=y
-+CONFIG_HAS_IOMEM=y
-+CONFIG_HAS_IOPORT=y
-+CONFIG_HAS_DMA=y
-diff --git a/arch/arm/configs/dss_overo_defconfig b/arch/arm/configs/dss_overo_defconfig
-new file mode 100644
-index 0000000..755a1b6
---- /dev/null
-+++ b/arch/arm/configs/dss_overo_defconfig
-@@ -0,0 +1,1862 @@
-+#
-+# Automatically generated make config: don't edit
-+# Linux kernel version: 2.6.29-omap1
-+# Thu Apr 2 11:30:57 2009
-+#
-+CONFIG_ARM=y
-+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-+CONFIG_GENERIC_GPIO=y
-+CONFIG_GENERIC_TIME=y
-+CONFIG_GENERIC_CLOCKEVENTS=y
-+CONFIG_MMU=y
-+# CONFIG_NO_IOPORT is not set
-+CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_STACKTRACE_SUPPORT=y
-+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-+CONFIG_LOCKDEP_SUPPORT=y
-+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-+CONFIG_HARDIRQS_SW_RESEND=y
-+CONFIG_GENERIC_IRQ_PROBE=y
-+CONFIG_RWSEM_GENERIC_SPINLOCK=y
-+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-+CONFIG_GENERIC_HWEIGHT=y
-+CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-+CONFIG_OPROFILE_ARMV7=y
-+CONFIG_VECTORS_BASE=0xffff0000
-+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-+
-+#
-+# General setup
-+#
-+CONFIG_EXPERIMENTAL=y
-+CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-+CONFIG_LOCALVERSION=""
-+CONFIG_LOCALVERSION_AUTO=y
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_SYSVIPC_SYSCTL=y
-+# CONFIG_POSIX_MQUEUE is not set
-+CONFIG_BSD_PROCESS_ACCT=y
-+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_AUDIT is not set
-+
-+#
-+# RCU Subsystem
-+#
-+CONFIG_CLASSIC_RCU=y
-+# CONFIG_TREE_RCU is not set
-+# CONFIG_PREEMPT_RCU is not set
-+# CONFIG_TREE_RCU_TRACE is not set
-+# CONFIG_PREEMPT_RCU_TRACE is not set
-+CONFIG_IKCONFIG=y
-+CONFIG_IKCONFIG_PROC=y
-+CONFIG_LOG_BUF_SHIFT=14
-+CONFIG_GROUP_SCHED=y
-+CONFIG_FAIR_GROUP_SCHED=y
-+# CONFIG_RT_GROUP_SCHED is not set
-+CONFIG_USER_SCHED=y
-+# CONFIG_CGROUP_SCHED is not set
-+# CONFIG_CGROUPS is not set
-+CONFIG_SYSFS_DEPRECATED=y
-+CONFIG_SYSFS_DEPRECATED_V2=y
-+# CONFIG_RELAY is not set
-+# CONFIG_NAMESPACES is not set
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE=""
-+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-+CONFIG_SYSCTL=y
-+CONFIG_ANON_INODES=y
-+CONFIG_EMBEDDED=y
-+CONFIG_UID16=y
-+# CONFIG_SYSCTL_SYSCALL is not set
-+CONFIG_KALLSYMS=y
-+# CONFIG_KALLSYMS_ALL is not set
-+# CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_HOTPLUG=y
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+# CONFIG_ELF_CORE is not set
-+CONFIG_BASE_FULL=y
-+CONFIG_FUTEX=y
-+CONFIG_EPOLL=y
-+CONFIG_SIGNALFD=y
-+CONFIG_TIMERFD=y
-+CONFIG_EVENTFD=y
-+CONFIG_SHMEM=y
-+CONFIG_AIO=y
-+CONFIG_VM_EVENT_COUNTERS=y
-+CONFIG_SLUB_DEBUG=y
-+# CONFIG_COMPAT_BRK is not set
-+# CONFIG_SLAB is not set
-+CONFIG_SLUB=y
-+# CONFIG_SLOB is not set
-+CONFIG_PROFILING=y
-+CONFIG_TRACEPOINTS=y
-+# CONFIG_MARKERS is not set
-+CONFIG_OPROFILE=y
-+CONFIG_HAVE_OPROFILE=y
-+# CONFIG_KPROBES is not set
-+CONFIG_HAVE_KPROBES=y
-+CONFIG_HAVE_KRETPROBES=y
-+CONFIG_HAVE_CLK=y
-+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-+CONFIG_SLABINFO=y
-+CONFIG_RT_MUTEXES=y
-+CONFIG_BASE_SMALL=0
-+CONFIG_MODULES=y
-+# CONFIG_MODULE_FORCE_LOAD is not set
-+CONFIG_MODULE_UNLOAD=y
-+CONFIG_MODULE_FORCE_UNLOAD=y
-+CONFIG_MODVERSIONS=y
-+CONFIG_MODULE_SRCVERSION_ALL=y
-+CONFIG_BLOCK=y
-+CONFIG_LBD=y
-+# CONFIG_BLK_DEV_IO_TRACE is not set
-+# CONFIG_BLK_DEV_BSG is not set
-+# CONFIG_BLK_DEV_INTEGRITY is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+CONFIG_IOSCHED_AS=y
-+CONFIG_IOSCHED_DEADLINE=y
-+CONFIG_IOSCHED_CFQ=y
-+# CONFIG_DEFAULT_AS is not set
-+# CONFIG_DEFAULT_DEADLINE is not set
-+CONFIG_DEFAULT_CFQ=y
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="cfq"
-+CONFIG_FREEZER=y
-+
-+#
-+# System Type
-+#
-+# CONFIG_ARCH_AAEC2000 is not set
-+# CONFIG_ARCH_INTEGRATOR is not set
-+# CONFIG_ARCH_REALVIEW is not set
-+# CONFIG_ARCH_VERSATILE is not set
-+# CONFIG_ARCH_AT91 is not set
-+# CONFIG_ARCH_CLPS711X is not set
-+# CONFIG_ARCH_EBSA110 is not set
-+# CONFIG_ARCH_EP93XX is not set
-+# CONFIG_ARCH_FOOTBRIDGE is not set
-+# CONFIG_ARCH_NETX is not set
-+# CONFIG_ARCH_H720X is not set
-+# CONFIG_ARCH_IMX is not set
-+# CONFIG_ARCH_IOP13XX is not set
-+# CONFIG_ARCH_IOP32X is not set
-+# CONFIG_ARCH_IOP33X is not set
-+# CONFIG_ARCH_IXP23XX is not set
-+# CONFIG_ARCH_IXP2000 is not set
-+# CONFIG_ARCH_IXP4XX is not set
-+# CONFIG_ARCH_L7200 is not set
-+# CONFIG_ARCH_KIRKWOOD is not set
-+# CONFIG_ARCH_KS8695 is not set
-+# CONFIG_ARCH_NS9XXX is not set
-+# CONFIG_ARCH_LOKI is not set
-+# CONFIG_ARCH_MV78XX0 is not set
-+# CONFIG_ARCH_MXC is not set
-+# CONFIG_ARCH_ORION5X is not set
-+# CONFIG_ARCH_PNX4008 is not set
-+# CONFIG_ARCH_PXA is not set
-+# CONFIG_ARCH_RPC is not set
-+# CONFIG_ARCH_SA1100 is not set
-+# CONFIG_ARCH_S3C2410 is not set
-+# CONFIG_ARCH_S3C64XX is not set
-+# CONFIG_ARCH_SHARK is not set
-+# CONFIG_ARCH_LH7A40X is not set
-+# CONFIG_ARCH_DAVINCI is not set
-+CONFIG_ARCH_OMAP=y
-+# CONFIG_ARCH_MSM is not set
-+# CONFIG_ARCH_W90X900 is not set
-+
-+#
-+# TI OMAP Implementations
-+#
-+CONFIG_ARCH_OMAP_OTG=y
-+# CONFIG_ARCH_OMAP1 is not set
-+# CONFIG_ARCH_OMAP2 is not set
-+CONFIG_ARCH_OMAP3=y
-+
-+#
-+# OMAP Feature Selections
-+#
-+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
-+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
-+CONFIG_OMAP_SMARTREFLEX=y
-+# CONFIG_OMAP_SMARTREFLEX_TESTING is not set
-+# CONFIG_OMAP_RESET_CLOCKS is not set
-+CONFIG_OMAP_BOOT_TAG=y
-+CONFIG_OMAP_BOOT_REASON=y
-+# CONFIG_OMAP_COMPONENT_VERSION is not set
-+# CONFIG_OMAP_GPIO_SWITCH is not set
-+# CONFIG_OMAP_MUX is not set
-+CONFIG_OMAP_MCBSP=y
-+# CONFIG_OMAP_MBOX_FWK is not set
-+# CONFIG_OMAP_MPU_TIMER is not set
-+CONFIG_OMAP_32K_TIMER=y
-+CONFIG_OMAP_32K_TIMER_HZ=128
-+CONFIG_OMAP_TICK_GPTIMER=1
-+CONFIG_OMAP_DM_TIMER=y
-+# CONFIG_OMAP_LL_DEBUG_UART1 is not set
-+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
-+CONFIG_OMAP_LL_DEBUG_UART3=y
-+CONFIG_ARCH_OMAP34XX=y
-+CONFIG_ARCH_OMAP3430=y
-+
-+#
-+# OMAP Board Type
-+#
-+# CONFIG_MACH_NOKIA_RX51 is not set
-+# CONFIG_MACH_OMAP_LDP is not set
-+# CONFIG_MACH_OMAP_3430SDP is not set
-+# CONFIG_MACH_OMAP3EVM is not set
-+# CONFIG_MACH_OMAP3_BEAGLE is not set
-+CONFIG_MACH_OVERO=y
-+# CONFIG_MACH_OMAP3_PANDORA is not set
-+
-+#
-+# Processor Type
-+#
-+CONFIG_CPU_32=y
-+CONFIG_CPU_32v6K=y
-+CONFIG_CPU_V7=y
-+CONFIG_CPU_32v7=y
-+CONFIG_CPU_ABRT_EV7=y
-+CONFIG_CPU_PABRT_IFAR=y
-+CONFIG_CPU_CACHE_V7=y
-+CONFIG_CPU_CACHE_VIPT=y
-+CONFIG_CPU_COPY_V6=y
-+CONFIG_CPU_TLB_V7=y
-+CONFIG_CPU_HAS_ASID=y
-+CONFIG_CPU_CP15=y
-+CONFIG_CPU_CP15_MMU=y
-+
-+#
-+# Processor Features
-+#
-+CONFIG_ARM_THUMB=y
-+CONFIG_ARM_THUMBEE=y
-+# CONFIG_CPU_ICACHE_DISABLE is not set
-+# CONFIG_CPU_DCACHE_DISABLE is not set
-+# CONFIG_CPU_BPREDICT_DISABLE is not set
-+CONFIG_HAS_TLS_REG=y
-+# CONFIG_OUTER_CACHE is not set
-+
-+#
-+# Bus support
-+#
-+# CONFIG_PCI_SYSCALL is not set
-+# CONFIG_ARCH_SUPPORTS_MSI is not set
-+# CONFIG_PCCARD is not set
-+
-+#
-+# Kernel Features
-+#
-+CONFIG_TICK_ONESHOT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-+CONFIG_VMSPLIT_3G=y
-+# CONFIG_VMSPLIT_2G is not set
-+# CONFIG_VMSPLIT_1G is not set
-+CONFIG_PAGE_OFFSET=0xC0000000
-+# CONFIG_PREEMPT is not set
-+CONFIG_HZ=128
-+CONFIG_AEABI=y
-+# CONFIG_OABI_COMPAT is not set
-+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
-+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-+CONFIG_SELECT_MEMORY_MODEL=y
-+CONFIG_FLATMEM_MANUAL=y
-+# CONFIG_DISCONTIGMEM_MANUAL is not set
-+# CONFIG_SPARSEMEM_MANUAL is not set
-+CONFIG_FLATMEM=y
-+CONFIG_FLAT_NODE_MEM_MAP=y
-+CONFIG_PAGEFLAGS_EXTENDED=y
-+CONFIG_SPLIT_PTLOCK_CPUS=4
-+# CONFIG_PHYS_ADDR_T_64BIT is not set
-+CONFIG_ZONE_DMA_FLAG=0
-+CONFIG_VIRT_TO_BUS=y
-+CONFIG_UNEVICTABLE_LRU=y
-+CONFIG_LEDS=y
-+CONFIG_ALIGNMENT_TRAP=y
-+
-+#
-+# Boot options
-+#
-+CONFIG_ZBOOT_ROM_TEXT=0x0
-+CONFIG_ZBOOT_ROM_BSS=0x0
-+CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.2.14:/tftpboot/rootfs ip=192.168.2.15 nolock,rsize=1024,wsize=1024 rw"
-+# CONFIG_XIP_KERNEL is not set
-+CONFIG_KEXEC=y
-+CONFIG_ATAGS_PROC=y
-+
-+#
-+# CPU Power Management
-+#
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_TABLE=y
-+# CONFIG_CPU_FREQ_DEBUG is not set
-+CONFIG_CPU_FREQ_STAT=y
-+CONFIG_CPU_FREQ_STAT_DETAILS=y
-+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-+# CONFIG_CPU_IDLE is not set
-+
-+#
-+# Floating point emulation
-+#
-+
-+#
-+# At least one emulation must be selected
-+#
-+CONFIG_VFP=y
-+CONFIG_VFPv3=y
-+CONFIG_NEON=y
-+
-+#
-+# Userspace binary formats
-+#
-+CONFIG_BINFMT_ELF=y
-+CONFIG_HAVE_AOUT=y
-+CONFIG_BINFMT_AOUT=m
-+CONFIG_BINFMT_MISC=y
-+
-+#
-+# Power management options
-+#
-+CONFIG_PM=y
-+# CONFIG_PM_DEBUG is not set
-+CONFIG_PM_SLEEP=y
-+CONFIG_SUSPEND=y
-+CONFIG_SUSPEND_FREEZER=y
-+# CONFIG_APM_EMULATION is not set
-+CONFIG_ARCH_SUSPEND_POSSIBLE=y
-+CONFIG_NET=y
-+
-+#
-+# Networking options
-+#
-+CONFIG_COMPAT_NET_DEV_OPS=y
-+CONFIG_PACKET=y
-+CONFIG_PACKET_MMAP=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM=y
-+# CONFIG_XFRM_USER is not set
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+CONFIG_NET_KEY=y
-+# CONFIG_NET_KEY_MIGRATE is not set
-+CONFIG_INET=y
-+# CONFIG_IP_MULTICAST is not set
-+# CONFIG_IP_ADVANCED_ROUTER is not set
-+CONFIG_IP_FIB_HASH=y
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+CONFIG_IP_PNP_BOOTP=y
-+CONFIG_IP_PNP_RARP=y
-+# CONFIG_NET_IPIP is not set
-+# CONFIG_NET_IPGRE is not set
-+# CONFIG_ARPD is not set
-+# CONFIG_SYN_COOKIES is not set
-+# CONFIG_INET_AH is not set
-+# CONFIG_INET_ESP is not set
-+# CONFIG_INET_IPCOMP is not set
-+# CONFIG_INET_XFRM_TUNNEL is not set
-+CONFIG_INET_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_TRANSPORT=y
-+CONFIG_INET_XFRM_MODE_TUNNEL=y
-+CONFIG_INET_XFRM_MODE_BEET=y
-+# CONFIG_INET_LRO is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
-+# CONFIG_TCP_CONG_ADVANCED is not set
-+CONFIG_TCP_CONG_CUBIC=y
-+CONFIG_DEFAULT_TCP_CONG="cubic"
-+# CONFIG_TCP_MD5SIG is not set
-+CONFIG_IPV6=m
-+# CONFIG_IPV6_PRIVACY is not set
-+# CONFIG_IPV6_ROUTER_PREF is not set
-+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-+# CONFIG_INET6_AH is not set
-+# CONFIG_INET6_ESP is not set
-+# CONFIG_INET6_IPCOMP is not set
-+# CONFIG_IPV6_MIP6 is not set
-+# CONFIG_INET6_XFRM_TUNNEL is not set
-+# CONFIG_INET6_TUNNEL is not set
-+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET6_XFRM_MODE_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_BEET=m
-+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-+CONFIG_IPV6_SIT=m
-+CONFIG_IPV6_NDISC_NODETYPE=y
-+# CONFIG_IPV6_TUNNEL is not set
-+# CONFIG_IPV6_MULTIPLE_TABLES is not set
-+# CONFIG_IPV6_MROUTE is not set
-+# CONFIG_NETWORK_SECMARK is not set
-+# CONFIG_NETFILTER is not set
-+# CONFIG_IP_DCCP is not set
-+# CONFIG_IP_SCTP is not set
-+# CONFIG_TIPC is not set
-+# CONFIG_ATM is not set
-+# CONFIG_BRIDGE is not set
-+# CONFIG_NET_DSA is not set
-+# CONFIG_VLAN_8021Q is not set
-+# CONFIG_DECNET is not set
-+# CONFIG_LLC2 is not set
-+# CONFIG_IPX is not set
-+# CONFIG_ATALK is not set
-+# CONFIG_X25 is not set
-+# CONFIG_LAPB is not set
-+# CONFIG_ECONET is not set
-+# CONFIG_WAN_ROUTER is not set
-+# CONFIG_NET_SCHED is not set
-+# CONFIG_DCB is not set
-+
-+#
-+# Network testing
-+#
-+# CONFIG_NET_PKTGEN is not set
-+# CONFIG_HAMRADIO is not set
-+# CONFIG_CAN is not set
-+# CONFIG_IRDA is not set
-+CONFIG_BT=y
-+CONFIG_BT_L2CAP=y
-+CONFIG_BT_SCO=y
-+CONFIG_BT_RFCOMM=y
-+CONFIG_BT_RFCOMM_TTY=y
-+CONFIG_BT_BNEP=y
-+CONFIG_BT_BNEP_MC_FILTER=y
-+CONFIG_BT_BNEP_PROTO_FILTER=y
-+CONFIG_BT_HIDP=y
-+
-+#
-+# Bluetooth device drivers
-+#
-+# CONFIG_BT_HCIBTSDIO is not set
-+CONFIG_BT_HCIUART=y
-+CONFIG_BT_HCIUART_H4=y
-+CONFIG_BT_HCIUART_BCSP=y
-+# CONFIG_BT_HCIUART_LL is not set
-+# CONFIG_BT_HCIBRF6150 is not set
-+# CONFIG_BT_HCIH4P is not set
-+# CONFIG_BT_HCIVHCI is not set
-+# CONFIG_AF_RXRPC is not set
-+# CONFIG_PHONET is not set
-+CONFIG_WIRELESS=y
-+CONFIG_CFG80211=y
-+# CONFIG_CFG80211_REG_DEBUG is not set
-+CONFIG_NL80211=y
-+CONFIG_WIRELESS_OLD_REGULATORY=y
-+CONFIG_WIRELESS_EXT=y
-+CONFIG_WIRELESS_EXT_SYSFS=y
-+CONFIG_LIB80211=y
-+CONFIG_LIB80211_CRYPT_WEP=m
-+CONFIG_LIB80211_CRYPT_CCMP=m
-+CONFIG_LIB80211_CRYPT_TKIP=m
-+# CONFIG_LIB80211_DEBUG is not set
-+CONFIG_MAC80211=y
-+
-+#
-+# Rate control algorithm selection
-+#
-+CONFIG_MAC80211_RC_PID=y
-+CONFIG_MAC80211_RC_MINSTREL=y
-+CONFIG_MAC80211_RC_DEFAULT_PID=y
-+# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
-+CONFIG_MAC80211_RC_DEFAULT="pid"
-+# CONFIG_MAC80211_MESH is not set
-+CONFIG_MAC80211_LEDS=y
-+# CONFIG_MAC80211_DEBUGFS is not set
-+# CONFIG_MAC80211_DEBUG_MENU is not set
-+# CONFIG_WIMAX is not set
-+# CONFIG_RFKILL is not set
-+# CONFIG_NET_9P is not set
-+
-+#
-+# Device Drivers
-+#
-+
-+#
-+# Generic Driver Options
-+#
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-+CONFIG_STANDALONE=y
-+CONFIG_PREVENT_FIRMWARE_BUILD=y
-+CONFIG_FW_LOADER=y
-+CONFIG_FIRMWARE_IN_KERNEL=y
-+CONFIG_EXTRA_FIRMWARE=""
-+# CONFIG_DEBUG_DRIVER is not set
-+# CONFIG_DEBUG_DEVRES is not set
-+# CONFIG_SYS_HYPERVISOR is not set
-+# CONFIG_CONNECTOR is not set
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+CONFIG_MTD_CONCAT=y
-+CONFIG_MTD_PARTITIONS=y
-+# CONFIG_MTD_TESTS is not set
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+# CONFIG_MTD_CMDLINE_PARTS is not set
-+# CONFIG_MTD_AFS_PARTS is not set
-+# CONFIG_MTD_AR7_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLKDEVS=y
-+CONFIG_MTD_BLOCK=y
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+# CONFIG_SSFDC is not set
-+# CONFIG_MTD_OOPS is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+# CONFIG_MTD_CFI is not set
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+# CONFIG_MTD_PLATRAM is not set
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+# CONFIG_MTD_DATAFLASH is not set
-+# CONFIG_MTD_M25P80 is not set
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+CONFIG_MTD_NAND=y
-+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
-+# CONFIG_MTD_NAND_ECC_SMC is not set
-+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-+# CONFIG_MTD_NAND_GPIO is not set
-+CONFIG_MTD_NAND_OMAP2=y
-+CONFIG_MTD_NAND_IDS=y
-+# CONFIG_MTD_NAND_DISKONCHIP is not set
-+# CONFIG_MTD_NAND_NANDSIM is not set
-+# CONFIG_MTD_NAND_PLATFORM is not set
-+# CONFIG_MTD_ONENAND is not set
-+
-+#
-+# LPDDR flash memory drivers
-+#
-+# CONFIG_MTD_LPDDR is not set
-+
-+#
-+# UBI - Unsorted block images
-+#
-+# CONFIG_MTD_UBI is not set
-+# CONFIG_PARPORT is not set
-+CONFIG_BLK_DEV=y
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+CONFIG_BLK_DEV_LOOP=y
-+CONFIG_BLK_DEV_CRYPTOLOOP=m
-+# CONFIG_BLK_DEV_NBD is not set
-+CONFIG_BLK_DEV_RAM=y
-+CONFIG_BLK_DEV_RAM_COUNT=16
-+CONFIG_BLK_DEV_RAM_SIZE=16384
-+# CONFIG_BLK_DEV_XIP is not set
-+CONFIG_CDROM_PKTCDVD=m
-+CONFIG_CDROM_PKTCDVD_BUFFERS=8
-+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+CONFIG_MISC_DEVICES=y
-+# CONFIG_ICS932S401 is not set
-+# CONFIG_OMAP_STI is not set
-+# CONFIG_ENCLOSURE_SERVICES is not set
-+# CONFIG_C2PORT is not set
-+
-+#
-+# EEPROM support
-+#
-+# CONFIG_EEPROM_AT24 is not set
-+# CONFIG_EEPROM_AT25 is not set
-+# CONFIG_EEPROM_LEGACY is not set
-+CONFIG_EEPROM_93CX6=m
-+CONFIG_HAVE_IDE=y
-+# CONFIG_IDE is not set
-+
-+#
-+# SCSI device support
-+#
-+CONFIG_RAID_ATTRS=m
-+CONFIG_SCSI=y
-+CONFIG_SCSI_DMA=y
-+# CONFIG_SCSI_TGT is not set
-+# CONFIG_SCSI_NETLINK is not set
-+CONFIG_SCSI_PROC_FS=y
-+
-+#
-+# SCSI support type (disk, tape, CD-ROM)
-+#
-+CONFIG_BLK_DEV_SD=y
-+# CONFIG_CHR_DEV_ST is not set
-+# CONFIG_CHR_DEV_OSST is not set
-+# CONFIG_BLK_DEV_SR is not set
-+CONFIG_CHR_DEV_SG=m
-+# CONFIG_CHR_DEV_SCH is not set
-+
-+#
-+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-+#
-+CONFIG_SCSI_MULTI_LUN=y
-+# CONFIG_SCSI_CONSTANTS is not set
-+# CONFIG_SCSI_LOGGING is not set
-+# CONFIG_SCSI_SCAN_ASYNC is not set
-+CONFIG_SCSI_WAIT_SCAN=m
-+
-+#
-+# SCSI Transports
-+#
-+# CONFIG_SCSI_SPI_ATTRS is not set
-+# CONFIG_SCSI_FC_ATTRS is not set
-+# CONFIG_SCSI_ISCSI_ATTRS is not set
-+# CONFIG_SCSI_SAS_LIBSAS is not set
-+# CONFIG_SCSI_SRP_ATTRS is not set
-+CONFIG_SCSI_LOWLEVEL=y
-+# CONFIG_ISCSI_TCP is not set
-+# CONFIG_LIBFC is not set
-+# CONFIG_SCSI_DEBUG is not set
-+# CONFIG_SCSI_DH is not set
-+# CONFIG_ATA is not set
-+CONFIG_MD=y
-+CONFIG_BLK_DEV_MD=m
-+CONFIG_MD_LINEAR=m
-+CONFIG_MD_RAID0=m
-+CONFIG_MD_RAID1=m
-+CONFIG_MD_RAID10=m
-+CONFIG_MD_RAID456=m
-+CONFIG_MD_RAID5_RESHAPE=y
-+CONFIG_MD_MULTIPATH=m
-+CONFIG_MD_FAULTY=m
-+CONFIG_BLK_DEV_DM=m
-+# CONFIG_DM_DEBUG is not set
-+CONFIG_DM_CRYPT=m
-+CONFIG_DM_SNAPSHOT=m
-+CONFIG_DM_MIRROR=m
-+CONFIG_DM_ZERO=m
-+CONFIG_DM_MULTIPATH=m
-+CONFIG_DM_DELAY=m
-+# CONFIG_DM_UEVENT is not set
-+CONFIG_NETDEVICES=y
-+CONFIG_DUMMY=m
-+# CONFIG_BONDING is not set
-+# CONFIG_MACVLAN is not set
-+# CONFIG_EQUALIZER is not set
-+CONFIG_TUN=m
-+# CONFIG_VETH is not set
-+# CONFIG_NET_ETHERNET is not set
-+# CONFIG_NETDEV_1000 is not set
-+# CONFIG_NETDEV_10000 is not set
-+
-+#
-+# Wireless LAN
-+#
-+# CONFIG_WLAN_PRE80211 is not set
-+CONFIG_WLAN_80211=y
-+CONFIG_LIBERTAS=y
-+CONFIG_LIBERTAS_SDIO=y
-+CONFIG_LIBERTAS_DEBUG=y
-+# CONFIG_LIBERTAS_THINFIRM is not set
-+# CONFIG_MAC80211_HWSIM is not set
-+CONFIG_P54_COMMON=m
-+# CONFIG_IWLWIFI_LEDS is not set
-+CONFIG_HOSTAP=m
-+CONFIG_HOSTAP_FIRMWARE=y
-+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
-+# CONFIG_B43 is not set
-+# CONFIG_B43LEGACY is not set
-+# CONFIG_RT2X00 is not set
-+
-+#
-+# Enable WiMAX (Networking options) to see the WiMAX drivers
-+#
-+# CONFIG_WAN is not set
-+CONFIG_PPP=m
-+# CONFIG_PPP_MULTILINK is not set
-+# CONFIG_PPP_FILTER is not set
-+CONFIG_PPP_ASYNC=m
-+CONFIG_PPP_SYNC_TTY=m
-+CONFIG_PPP_DEFLATE=m
-+CONFIG_PPP_BSDCOMP=m
-+CONFIG_PPP_MPPE=m
-+CONFIG_PPPOE=m
-+# CONFIG_PPPOL2TP is not set
-+# CONFIG_SLIP is not set
-+CONFIG_SLHC=m
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
-+# CONFIG_ISDN is not set
-+
-+#
-+# Input device support
-+#
-+CONFIG_INPUT=y
-+# CONFIG_INPUT_FF_MEMLESS is not set
-+# CONFIG_INPUT_POLLDEV is not set
-+
-+#
-+# Userland interfaces
-+#
-+CONFIG_INPUT_MOUSEDEV=y
-+CONFIG_INPUT_MOUSEDEV_PSAUX=y
-+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-+# CONFIG_INPUT_JOYDEV is not set
-+CONFIG_INPUT_EVDEV=y
-+# CONFIG_INPUT_EVBUG is not set
-+
-+#
-+# Input Device Drivers
-+#
-+CONFIG_INPUT_KEYBOARD=y
-+# CONFIG_KEYBOARD_ATKBD is not set
-+# CONFIG_KEYBOARD_SUNKBD is not set
-+# CONFIG_KEYBOARD_LKKBD is not set
-+# CONFIG_KEYBOARD_XTKBD is not set
-+# CONFIG_KEYBOARD_NEWTON is not set
-+# CONFIG_KEYBOARD_STOWAWAY is not set
-+# CONFIG_KEYBOARD_TWL4030 is not set
-+# CONFIG_KEYBOARD_LM8323 is not set
-+# CONFIG_KEYBOARD_GPIO is not set
-+CONFIG_INPUT_MOUSE=y
-+CONFIG_MOUSE_PS2=y
-+CONFIG_MOUSE_PS2_ALPS=y
-+CONFIG_MOUSE_PS2_LOGIPS2PP=y
-+CONFIG_MOUSE_PS2_SYNAPTICS=y
-+CONFIG_MOUSE_PS2_TRACKPOINT=y
-+# CONFIG_MOUSE_PS2_ELANTECH is not set
-+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
-+# CONFIG_MOUSE_SERIAL is not set
-+# CONFIG_MOUSE_APPLETOUCH is not set
-+# CONFIG_MOUSE_BCM5974 is not set
-+# CONFIG_MOUSE_VSXXXAA is not set
-+# CONFIG_MOUSE_GPIO is not set
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TABLET is not set
-+# CONFIG_INPUT_TOUCHSCREEN is not set
-+# CONFIG_INPUT_MISC is not set
-+
-+#
-+# Hardware I/O ports
-+#
-+CONFIG_SERIO=y
-+CONFIG_SERIO_SERPORT=y
-+CONFIG_SERIO_LIBPS2=y
-+# CONFIG_SERIO_RAW is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
-+# Character devices
-+#
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+CONFIG_VT_HW_CONSOLE_BINDING=y
-+CONFIG_DEVKMEM=y
-+# CONFIG_SERIAL_NONSTANDARD is not set
-+
-+#
-+# Serial drivers
-+#
-+CONFIG_SERIAL_8250=y
-+CONFIG_SERIAL_8250_CONSOLE=y
-+CONFIG_SERIAL_8250_NR_UARTS=32
-+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-+CONFIG_SERIAL_8250_EXTENDED=y
-+CONFIG_SERIAL_8250_MANY_PORTS=y
-+CONFIG_SERIAL_8250_SHARE_IRQ=y
-+CONFIG_SERIAL_8250_DETECT_IRQ=y
-+CONFIG_SERIAL_8250_RSA=y
-+
-+#
-+# Non-8250 serial port support
-+#
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+CONFIG_UNIX98_PTYS=y
-+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_IPMI_HANDLER is not set
-+CONFIG_HW_RANDOM=y
-+# CONFIG_R3964 is not set
-+# CONFIG_RAW_DRIVER is not set
-+# CONFIG_TCG_TPM is not set
-+CONFIG_I2C=y
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_CHARDEV=y
-+CONFIG_I2C_HELPER_AUTO=y
-+
-+#
-+# I2C Hardware Bus support
-+#
-+
-+#
-+# I2C system bus drivers (mostly embedded / system-on-chip)
-+#
-+# CONFIG_I2C_GPIO is not set
-+# CONFIG_I2C_OCORES is not set
-+CONFIG_I2C_OMAP=y
-+# CONFIG_I2C_SIMTEC is not set
-+
-+#
-+# External I2C/SMBus adapter drivers
-+#
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+
-+#
-+# Other I2C/SMBus bus drivers
-+#
-+# CONFIG_I2C_PCA_PLATFORM is not set
-+# CONFIG_I2C_STUB is not set
-+
-+#
-+# Miscellaneous I2C Chip support
-+#
-+# CONFIG_DS1682 is not set
-+# CONFIG_SENSORS_PCF8574 is not set
-+# CONFIG_PCF8575 is not set
-+# CONFIG_SENSORS_PCA9539 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+CONFIG_TWL4030_MADC=m
-+CONFIG_TWL4030_POWEROFF=y
-+# CONFIG_SENSORS_MAX6875 is not set
-+# CONFIG_SENSORS_TSL2550 is not set
-+# CONFIG_SENSORS_TSL2563 is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+# CONFIG_I2C_DEBUG_CHIP is not set
-+CONFIG_SPI=y
-+# CONFIG_SPI_DEBUG is not set
-+CONFIG_SPI_MASTER=y
-+
-+#
-+# SPI Master Controller Drivers
-+#
-+# CONFIG_SPI_BITBANG is not set
-+# CONFIG_SPI_GPIO is not set
-+CONFIG_SPI_OMAP24XX=y
-+
-+#
-+# SPI Protocol Masters
-+#
-+# CONFIG_SPI_TSC210X is not set
-+# CONFIG_SPI_TSC2301 is not set
-+# CONFIG_SPI_SPIDEV is not set
-+# CONFIG_SPI_TLE62X0 is not set
-+CONFIG_ARCH_REQUIRE_GPIOLIB=y
-+CONFIG_GPIOLIB=y
-+CONFIG_DEBUG_GPIO=y
-+CONFIG_GPIO_SYSFS=y
-+
-+#
-+# Memory mapped GPIO expanders:
-+#
-+
-+#
-+# I2C GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX732X is not set
-+# CONFIG_GPIO_PCA953X is not set
-+# CONFIG_GPIO_PCF857X is not set
-+CONFIG_GPIO_TWL4030=y
-+
-+#
-+# PCI GPIO expanders:
-+#
-+
-+#
-+# SPI GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX7301 is not set
-+# CONFIG_GPIO_MCP23S08 is not set
-+# CONFIG_W1 is not set
-+CONFIG_POWER_SUPPLY=m
-+# CONFIG_POWER_SUPPLY_DEBUG is not set
-+# CONFIG_PDA_POWER is not set
-+# CONFIG_BATTERY_DS2760 is not set
-+# CONFIG_TWL4030_BCI_BATTERY is not set
-+# CONFIG_BATTERY_BQ27x00 is not set
-+CONFIG_HWMON=y
-+# CONFIG_HWMON_VID is not set
-+# CONFIG_SENSORS_AD7414 is not set
-+# CONFIG_SENSORS_AD7418 is not set
-+# CONFIG_SENSORS_ADCXX is not set
-+# CONFIG_SENSORS_ADM1021 is not set
-+# CONFIG_SENSORS_ADM1025 is not set
-+# CONFIG_SENSORS_ADM1026 is not set
-+# CONFIG_SENSORS_ADM1029 is not set
-+# CONFIG_SENSORS_ADM1031 is not set
-+# CONFIG_SENSORS_ADM9240 is not set
-+# CONFIG_SENSORS_ADT7462 is not set
-+# CONFIG_SENSORS_ADT7470 is not set
-+# CONFIG_SENSORS_ADT7473 is not set
-+# CONFIG_SENSORS_ADT7475 is not set
-+# CONFIG_SENSORS_ATXP1 is not set
-+# CONFIG_SENSORS_DS1621 is not set
-+# CONFIG_SENSORS_F71805F is not set
-+# CONFIG_SENSORS_F71882FG is not set
-+# CONFIG_SENSORS_F75375S is not set
-+# CONFIG_SENSORS_GL518SM is not set
-+# CONFIG_SENSORS_GL520SM is not set
-+# CONFIG_SENSORS_IT87 is not set
-+# CONFIG_SENSORS_LM63 is not set
-+# CONFIG_SENSORS_LM70 is not set
-+# CONFIG_SENSORS_LM75 is not set
-+# CONFIG_SENSORS_LM77 is not set
-+# CONFIG_SENSORS_LM78 is not set
-+# CONFIG_SENSORS_LM80 is not set
-+# CONFIG_SENSORS_LM83 is not set
-+# CONFIG_SENSORS_LM85 is not set
-+# CONFIG_SENSORS_LM87 is not set
-+# CONFIG_SENSORS_LM90 is not set
-+# CONFIG_SENSORS_LM92 is not set
-+# CONFIG_SENSORS_LM93 is not set
-+# CONFIG_SENSORS_LTC4245 is not set
-+# CONFIG_SENSORS_MAX1111 is not set
-+# CONFIG_SENSORS_MAX1619 is not set
-+# CONFIG_SENSORS_MAX6650 is not set
-+# CONFIG_SENSORS_PC87360 is not set
-+# CONFIG_SENSORS_PC87427 is not set
-+# CONFIG_SENSORS_DME1737 is not set
-+# CONFIG_SENSORS_SMSC47M1 is not set
-+# CONFIG_SENSORS_SMSC47M192 is not set
-+# CONFIG_SENSORS_SMSC47B397 is not set
-+# CONFIG_SENSORS_ADS7828 is not set
-+# CONFIG_SENSORS_THMC50 is not set
-+# CONFIG_SENSORS_VT1211 is not set
-+# CONFIG_SENSORS_W83781D is not set
-+# CONFIG_SENSORS_W83791D is not set
-+# CONFIG_SENSORS_W83792D is not set
-+# CONFIG_SENSORS_W83793 is not set
-+# CONFIG_SENSORS_W83L785TS is not set
-+# CONFIG_SENSORS_W83L786NG is not set
-+# CONFIG_SENSORS_W83627HF is not set
-+# CONFIG_SENSORS_W83627EHF is not set
-+# CONFIG_SENSORS_TSC210X is not set
-+CONFIG_SENSORS_OMAP34XX=y
-+# CONFIG_HWMON_DEBUG_CHIP is not set
-+# CONFIG_THERMAL is not set
-+# CONFIG_THERMAL_HWMON is not set
-+CONFIG_WATCHDOG=y
-+CONFIG_WATCHDOG_NOWAYOUT=y
-+
-+#
-+# Watchdog Device Drivers
-+#
-+# CONFIG_SOFT_WATCHDOG is not set
-+CONFIG_OMAP_WATCHDOG=y
-+CONFIG_SSB_POSSIBLE=y
-+
-+#
-+# Sonics Silicon Backplane
-+#
-+# CONFIG_SSB is not set
-+
-+#
-+# Multifunction device drivers
-+#
-+# CONFIG_MFD_CORE is not set
-+# CONFIG_MFD_SM501 is not set
-+# CONFIG_MFD_ASIC3 is not set
-+# CONFIG_HTC_EGPIO is not set
-+# CONFIG_HTC_PASIC3 is not set
-+# CONFIG_TPS65010 is not set
-+CONFIG_TWL4030_CORE=y
-+# CONFIG_TWL4030_POWER is not set
-+# CONFIG_MFD_TMIO is not set
-+# CONFIG_MFD_T7L66XB is not set
-+# CONFIG_MFD_TC6387XB is not set
-+# CONFIG_MFD_TC6393XB is not set
-+# CONFIG_PMIC_DA903X is not set
-+# CONFIG_MFD_WM8400 is not set
-+# CONFIG_MFD_WM8350_I2C is not set
-+# CONFIG_MFD_PCF50633 is not set
-+
-+#
-+# Multimedia devices
-+#
-+
-+#
-+# Multimedia core support
-+#
-+CONFIG_VIDEO_DEV=m
-+CONFIG_VIDEO_V4L2_COMMON=m
-+CONFIG_VIDEO_ALLOW_V4L1=y
-+CONFIG_VIDEO_V4L1_COMPAT=y
-+CONFIG_DVB_CORE=m
-+CONFIG_VIDEO_MEDIA=m
-+
-+#
-+# Multimedia drivers
-+#
-+CONFIG_MEDIA_ATTACH=y
-+CONFIG_MEDIA_TUNER=m
-+# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
-+CONFIG_MEDIA_TUNER_SIMPLE=m
-+CONFIG_MEDIA_TUNER_TDA8290=m
-+CONFIG_MEDIA_TUNER_TDA9887=m
-+CONFIG_MEDIA_TUNER_TEA5761=m
-+CONFIG_MEDIA_TUNER_TEA5767=m
-+CONFIG_MEDIA_TUNER_MT20XX=m
-+CONFIG_MEDIA_TUNER_XC2028=m
-+CONFIG_MEDIA_TUNER_XC5000=m
-+CONFIG_VIDEO_V4L2=m
-+CONFIG_VIDEO_V4L1=m
-+CONFIG_VIDEO_CAPTURE_DRIVERS=y
-+# CONFIG_VIDEO_ADV_DEBUG is not set
-+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-+# CONFIG_VIDEO_VIVI is not set
-+# CONFIG_VIDEO_CPIA is not set
-+# CONFIG_VIDEO_SAA5246A is not set
-+# CONFIG_VIDEO_SAA5249 is not set
-+# CONFIG_SOC_CAMERA is not set
-+CONFIG_RADIO_ADAPTERS=y
-+# CONFIG_RADIO_TEA5764 is not set
-+# CONFIG_DVB_DYNAMIC_MINORS is not set
-+CONFIG_DVB_CAPTURE_DRIVERS=y
-+# CONFIG_TTPCI_EEPROM is not set
-+# CONFIG_DVB_B2C2_FLEXCOP is not set
-+
-+#
-+# Supported DVB Frontends
-+#
-+
-+#
-+# Customise DVB Frontends
-+#
-+# CONFIG_DVB_FE_CUSTOMISE is not set
-+
-+#
-+# Multistandard (satellite) frontends
-+#
-+# CONFIG_DVB_STB0899 is not set
-+# CONFIG_DVB_STB6100 is not set
-+
-+#
-+# DVB-S (satellite) frontends
-+#
-+CONFIG_DVB_CX24110=m
-+CONFIG_DVB_CX24123=m
-+CONFIG_DVB_MT312=m
-+CONFIG_DVB_S5H1420=m
-+# CONFIG_DVB_STV0288 is not set
-+# CONFIG_DVB_STB6000 is not set
-+CONFIG_DVB_STV0299=m
-+CONFIG_DVB_TDA8083=m
-+CONFIG_DVB_TDA10086=m
-+# CONFIG_DVB_TDA8261 is not set
-+CONFIG_DVB_VES1X93=m
-+CONFIG_DVB_TUNER_ITD1000=m
-+# CONFIG_DVB_TUNER_CX24113 is not set
-+CONFIG_DVB_TDA826X=m
-+CONFIG_DVB_TUA6100=m
-+# CONFIG_DVB_CX24116 is not set
-+# CONFIG_DVB_SI21XX is not set
-+
-+#
-+# DVB-T (terrestrial) frontends
-+#
-+CONFIG_DVB_SP8870=m
-+CONFIG_DVB_SP887X=m
-+CONFIG_DVB_CX22700=m
-+CONFIG_DVB_CX22702=m
-+# CONFIG_DVB_DRX397XD is not set
-+CONFIG_DVB_L64781=m
-+CONFIG_DVB_TDA1004X=m
-+CONFIG_DVB_NXT6000=m
-+CONFIG_DVB_MT352=m
-+CONFIG_DVB_ZL10353=m
-+CONFIG_DVB_DIB3000MB=m
-+CONFIG_DVB_DIB3000MC=m
-+CONFIG_DVB_DIB7000M=m
-+CONFIG_DVB_DIB7000P=m
-+CONFIG_DVB_TDA10048=m
-+
-+#
-+# DVB-C (cable) frontends
-+#
-+CONFIG_DVB_VES1820=m
-+CONFIG_DVB_TDA10021=m
-+CONFIG_DVB_TDA10023=m
-+CONFIG_DVB_STV0297=m
-+
-+#
-+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
-+#
-+CONFIG_DVB_NXT200X=m
-+# CONFIG_DVB_OR51211 is not set
-+# CONFIG_DVB_OR51132 is not set
-+CONFIG_DVB_BCM3510=m
-+CONFIG_DVB_LGDT330X=m
-+# CONFIG_DVB_LGDT3304 is not set
-+CONFIG_DVB_S5H1409=m
-+CONFIG_DVB_AU8522=m
-+CONFIG_DVB_S5H1411=m
-+
-+#
-+# ISDB-T (terrestrial) frontends
-+#
-+# CONFIG_DVB_S921 is not set
-+
-+#
-+# Digital terrestrial only tuners/PLL
-+#
-+CONFIG_DVB_PLL=m
-+CONFIG_DVB_TUNER_DIB0070=m
-+
-+#
-+# SEC control devices for DVB-S
-+#
-+CONFIG_DVB_LNBP21=m
-+# CONFIG_DVB_ISL6405 is not set
-+CONFIG_DVB_ISL6421=m
-+# CONFIG_DVB_LGS8GL5 is not set
-+
-+#
-+# Tools to develop new frontends
-+#
-+# CONFIG_DVB_DUMMY_FE is not set
-+# CONFIG_DVB_AF9013 is not set
-+# CONFIG_DAB is not set
-+
-+#
-+# Graphics support
-+#
-+# CONFIG_VGASTATE is not set
-+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-+CONFIG_FB=y
-+# CONFIG_FIRMWARE_EDID is not set
-+# CONFIG_FB_DDC is not set
-+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-+CONFIG_FB_CFB_FILLRECT=m
-+CONFIG_FB_CFB_COPYAREA=m
-+CONFIG_FB_CFB_IMAGEBLIT=m
-+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-+# CONFIG_FB_SYS_FILLRECT is not set
-+# CONFIG_FB_SYS_COPYAREA is not set
-+# CONFIG_FB_SYS_IMAGEBLIT is not set
-+# CONFIG_FB_FOREIGN_ENDIAN is not set
-+# CONFIG_FB_SYS_FOPS is not set
-+# CONFIG_FB_SVGALIB is not set
-+# CONFIG_FB_MACMODES is not set
-+# CONFIG_FB_BACKLIGHT is not set
-+# CONFIG_FB_MODE_HELPERS is not set
-+# CONFIG_FB_TILEBLITTING is not set
-+
-+#
-+# Frame buffer hardware drivers
-+#
-+# CONFIG_FB_S1D13XXX is not set
-+# CONFIG_FB_VIRTUAL is not set
-+# CONFIG_FB_METRONOME is not set
-+# CONFIG_FB_MB862XX is not set
-+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
-+CONFIG_OMAP2_DSS=m
-+CONFIG_OMAP2_DSS_VRAM_SIZE=12
-+CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
-+# CONFIG_OMAP2_DSS_RFBI is not set
-+CONFIG_OMAP2_DSS_VENC=y
-+# CONFIG_OMAP2_DSS_SDI is not set
-+# CONFIG_OMAP2_DSS_DSI is not set
-+# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
-+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
-+
-+#
-+# OMAP2/3 Display Device Drivers
-+#
-+CONFIG_PANEL_GENERIC=m
-+CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C=m
-+# CONFIG_PANEL_SHARP_LS037V7DW01 is not set
-+# CONFIG_PANEL_N800 is not set
-+# CONFIG_CTRL_BLIZZARD is not set
-+CONFIG_FB_OMAP2=m
-+CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
-+# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
-+CONFIG_FB_OMAP2_NUM_FBS=3
-+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-+
-+#
-+# Display device support
-+#
-+CONFIG_DISPLAY_SUPPORT=y
-+
-+#
-+# Display hardware drivers
-+#
-+
-+#
-+# Console display driver support
-+#
-+# CONFIG_VGA_CONSOLE is not set
-+CONFIG_DUMMY_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE is not set
-+# CONFIG_LOGO is not set
-+CONFIG_SOUND=y
-+CONFIG_SOUND_OSS_CORE=y
-+CONFIG_SND=y
-+CONFIG_SND_TIMER=y
-+CONFIG_SND_PCM=y
-+CONFIG_SND_SEQUENCER=m
-+# CONFIG_SND_SEQ_DUMMY is not set
-+CONFIG_SND_OSSEMUL=y
-+CONFIG_SND_MIXER_OSS=y
-+CONFIG_SND_PCM_OSS=y
-+CONFIG_SND_PCM_OSS_PLUGINS=y
-+CONFIG_SND_SEQUENCER_OSS=y
-+# CONFIG_SND_HRTIMER is not set
-+# CONFIG_SND_DYNAMIC_MINORS is not set
-+CONFIG_SND_SUPPORT_OLD_API=y
-+CONFIG_SND_VERBOSE_PROCFS=y
-+CONFIG_SND_VERBOSE_PRINTK=y
-+CONFIG_SND_DEBUG=y
-+# CONFIG_SND_DEBUG_VERBOSE is not set
-+# CONFIG_SND_PCM_XRUN_DEBUG is not set
-+CONFIG_SND_DRIVERS=y
-+# CONFIG_SND_DUMMY is not set
-+# CONFIG_SND_VIRMIDI is not set
-+# CONFIG_SND_MTPAV is not set
-+# CONFIG_SND_SERIAL_U16550 is not set
-+# CONFIG_SND_MPU401 is not set
-+CONFIG_SND_ARM=y
-+CONFIG_SND_SPI=y
-+CONFIG_SND_SOC=y
-+CONFIG_SND_OMAP_SOC=y
-+CONFIG_SND_OMAP_SOC_MCBSP=y
-+CONFIG_SND_OMAP_SOC_OVERO=y
-+CONFIG_SND_SOC_I2C_AND_SPI=y
-+# CONFIG_SND_SOC_ALL_CODECS is not set
-+CONFIG_SND_SOC_TWL4030=y
-+# CONFIG_SOUND_PRIME is not set
-+CONFIG_HID_SUPPORT=y
-+CONFIG_HID=y
-+CONFIG_HID_DEBUG=y
-+# CONFIG_HIDRAW is not set
-+# CONFIG_HID_PID is not set
-+
-+#
-+# Special HID drivers
-+#
-+CONFIG_HID_COMPAT=y
-+# CONFIG_HID_APPLE is not set
-+CONFIG_USB_SUPPORT=y
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB is not set
-+# CONFIG_USB_OTG_WHITELIST is not set
-+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+CONFIG_USB_MUSB_HDRC=y
-+CONFIG_USB_MUSB_SOC=y
-+
-+#
-+# OMAP 343x high speed USB support
-+#
-+# CONFIG_USB_MUSB_HOST is not set
-+CONFIG_USB_MUSB_PERIPHERAL=y
-+# CONFIG_USB_MUSB_OTG is not set
-+CONFIG_USB_GADGET_MUSB_HDRC=y
-+# CONFIG_MUSB_PIO_ONLY is not set
-+CONFIG_USB_INVENTRA_DMA=y
-+# CONFIG_USB_TI_CPPI_DMA is not set
-+# CONFIG_USB_MUSB_DEBUG is not set
-+
-+#
-+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
-+#
-+CONFIG_USB_GADGET=y
-+# CONFIG_USB_GADGET_DEBUG is not set
-+# CONFIG_USB_GADGET_DEBUG_FILES is not set
-+# CONFIG_USB_GADGET_DEBUG_FS is not set
-+CONFIG_USB_GADGET_VBUS_DRAW=2
-+CONFIG_USB_GADGET_SELECTED=y
-+# CONFIG_USB_GADGET_AT91 is not set
-+# CONFIG_USB_GADGET_ATMEL_USBA is not set
-+# CONFIG_USB_GADGET_FSL_USB2 is not set
-+# CONFIG_USB_GADGET_LH7A40X is not set
-+# CONFIG_USB_GADGET_OMAP is not set
-+# CONFIG_USB_GADGET_PXA25X is not set
-+# CONFIG_USB_GADGET_PXA27X is not set
-+# CONFIG_USB_GADGET_S3C2410 is not set
-+# CONFIG_USB_GADGET_IMX is not set
-+# CONFIG_USB_GADGET_M66592 is not set
-+# CONFIG_USB_GADGET_AMD5536UDC is not set
-+# CONFIG_USB_GADGET_FSL_QE is not set
-+# CONFIG_USB_GADGET_CI13XXX is not set
-+# CONFIG_USB_GADGET_NET2280 is not set
-+# CONFIG_USB_GADGET_GOKU is not set
-+# CONFIG_USB_GADGET_DUMMY_HCD is not set
-+CONFIG_USB_GADGET_DUALSPEED=y
-+# CONFIG_USB_ZERO is not set
-+CONFIG_USB_ETH=y
-+CONFIG_USB_ETH_RNDIS=y
-+# CONFIG_USB_GADGETFS is not set
-+# CONFIG_USB_FILE_STORAGE is not set
-+# CONFIG_USB_G_SERIAL is not set
-+# CONFIG_USB_MIDI_GADGET is not set
-+# CONFIG_USB_G_PRINTER is not set
-+# CONFIG_USB_CDC_COMPOSITE is not set
-+
-+#
-+# OTG and related infrastructure
-+#
-+CONFIG_USB_OTG_UTILS=y
-+# CONFIG_USB_GPIO_VBUS is not set
-+# CONFIG_ISP1301_OMAP is not set
-+CONFIG_TWL4030_USB=y
-+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+CONFIG_MMC_UNSAFE_RESUME=y
-+
-+#
-+# MMC/SD/SDIO Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+CONFIG_MMC_BLOCK_BOUNCE=y
-+CONFIG_SDIO_UART=y
-+# CONFIG_MMC_TEST is not set
-+
-+#
-+# MMC/SD/SDIO Host Controller Drivers
-+#
-+# CONFIG_MMC_SDHCI is not set
-+CONFIG_MMC_OMAP_HS=y
-+# CONFIG_MMC_SPI is not set
-+# CONFIG_MEMSTICK is not set
-+# CONFIG_ACCESSIBILITY is not set
-+CONFIG_NEW_LEDS=y
-+CONFIG_LEDS_CLASS=y
-+
-+#
-+# LED drivers
-+#
-+# CONFIG_LEDS_OMAP_DEBUG is not set
-+# CONFIG_LEDS_OMAP is not set
-+# CONFIG_LEDS_OMAP_PWM is not set
-+# CONFIG_LEDS_PCA9532 is not set
-+CONFIG_LEDS_GPIO=y
-+# CONFIG_LEDS_LP5521 is not set
-+# CONFIG_LEDS_PCA955X is not set
-+
-+#
-+# LED Triggers
-+#
-+CONFIG_LEDS_TRIGGERS=y
-+CONFIG_LEDS_TRIGGER_TIMER=y
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
-+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
-+CONFIG_RTC_LIB=y
-+CONFIG_RTC_CLASS=y
-+CONFIG_RTC_HCTOSYS=y
-+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-+# CONFIG_RTC_DEBUG is not set
-+
-+#
-+# RTC interfaces
-+#
-+CONFIG_RTC_INTF_SYSFS=y
-+CONFIG_RTC_INTF_PROC=y
-+CONFIG_RTC_INTF_DEV=y
-+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-+# CONFIG_RTC_DRV_TEST is not set
-+
-+#
-+# I2C RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
-+CONFIG_RTC_DRV_TWL4030=y
-+# CONFIG_RTC_DRV_S35390A is not set
-+# CONFIG_RTC_DRV_FM3130 is not set
-+# CONFIG_RTC_DRV_RX8581 is not set
-+
-+#
-+# SPI RTC drivers
-+#
-+# CONFIG_RTC_DRV_M41T94 is not set
-+# CONFIG_RTC_DRV_DS1305 is not set
-+# CONFIG_RTC_DRV_DS1390 is not set
-+# CONFIG_RTC_DRV_MAX6902 is not set
-+# CONFIG_RTC_DRV_R9701 is not set
-+# CONFIG_RTC_DRV_RS5C348 is not set
-+# CONFIG_RTC_DRV_DS3234 is not set
-+
-+#
-+# Platform RTC drivers
-+#
-+# CONFIG_RTC_DRV_CMOS is not set
-+# CONFIG_RTC_DRV_DS1286 is not set
-+# CONFIG_RTC_DRV_DS1511 is not set
-+# CONFIG_RTC_DRV_DS1553 is not set
-+# CONFIG_RTC_DRV_DS1742 is not set
-+# CONFIG_RTC_DRV_STK17TA8 is not set
-+# CONFIG_RTC_DRV_M48T86 is not set
-+# CONFIG_RTC_DRV_M48T35 is not set
-+# CONFIG_RTC_DRV_M48T59 is not set
-+# CONFIG_RTC_DRV_BQ4802 is not set
-+# CONFIG_RTC_DRV_V3020 is not set
-+
-+#
-+# on-CPU RTC drivers
-+#
-+# CONFIG_DMADEVICES is not set
-+CONFIG_REGULATOR=y
-+# CONFIG_REGULATOR_DEBUG is not set
-+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-+# CONFIG_REGULATOR_BQ24022 is not set
-+CONFIG_REGULATOR_TWL4030=y
-+# CONFIG_UIO is not set
-+# CONFIG_STAGING is not set
-+
-+#
-+# CBUS support
-+#
-+# CONFIG_CBUS is not set
-+
-+#
-+# File systems
-+#
-+CONFIG_EXT2_FS=y
-+# CONFIG_EXT2_FS_XATTR is not set
-+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=y
-+# CONFIG_EXT3_FS_XATTR is not set
-+# CONFIG_EXT4_FS is not set
-+CONFIG_JBD=y
-+# CONFIG_JBD_DEBUG is not set
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+CONFIG_FS_POSIX_ACL=y
-+CONFIG_FILE_LOCKING=y
-+CONFIG_XFS_FS=m
-+# CONFIG_XFS_QUOTA is not set
-+# CONFIG_XFS_POSIX_ACL is not set
-+# CONFIG_XFS_RT is not set
-+# CONFIG_XFS_DEBUG is not set
-+# CONFIG_GFS2_FS is not set
-+# CONFIG_OCFS2_FS is not set
-+# CONFIG_BTRFS_FS is not set
-+CONFIG_DNOTIFY=y
-+CONFIG_INOTIFY=y
-+CONFIG_INOTIFY_USER=y
-+CONFIG_QUOTA=y
-+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
-+CONFIG_PRINT_QUOTA_WARNING=y
-+CONFIG_QUOTA_TREE=y
-+# CONFIG_QFMT_V1 is not set
-+CONFIG_QFMT_V2=y
-+CONFIG_QUOTACTL=y
-+# CONFIG_AUTOFS_FS is not set
-+# CONFIG_AUTOFS4_FS is not set
-+CONFIG_FUSE_FS=m
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+CONFIG_ISO9660_FS=m
-+CONFIG_JOLIET=y
-+CONFIG_ZISOFS=y
-+CONFIG_UDF_FS=m
-+CONFIG_UDF_NLS=y
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=y
-+CONFIG_MSDOS_FS=y
-+CONFIG_VFAT_FS=y
-+CONFIG_FAT_DEFAULT_CODEPAGE=437
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+# CONFIG_NTFS_FS is not set
-+
-+#
-+# Pseudo filesystems
-+#
-+CONFIG_PROC_FS=y
-+CONFIG_PROC_SYSCTL=y
-+CONFIG_PROC_PAGE_MONITOR=y
-+CONFIG_SYSFS=y
-+CONFIG_TMPFS=y
-+# CONFIG_TMPFS_POSIX_ACL is not set
-+# CONFIG_HUGETLB_PAGE is not set
-+# CONFIG_CONFIGFS_FS is not set
-+CONFIG_MISC_FILESYSTEMS=y
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
-+CONFIG_JFFS2_FS=y
-+CONFIG_JFFS2_FS_DEBUG=0
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-+CONFIG_JFFS2_SUMMARY=y
-+CONFIG_JFFS2_FS_XATTR=y
-+CONFIG_JFFS2_FS_POSIX_ACL=y
-+CONFIG_JFFS2_FS_SECURITY=y
-+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-+CONFIG_JFFS2_ZLIB=y
-+CONFIG_JFFS2_LZO=y
-+CONFIG_JFFS2_RTIME=y
-+CONFIG_JFFS2_RUBIN=y
-+# CONFIG_JFFS2_CMODE_NONE is not set
-+CONFIG_JFFS2_CMODE_PRIORITY=y
-+# CONFIG_JFFS2_CMODE_SIZE is not set
-+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
-+# CONFIG_CRAMFS is not set
-+# CONFIG_SQUASHFS is not set
-+# CONFIG_VXFS_FS is not set
-+# CONFIG_MINIX_FS is not set
-+# CONFIG_OMFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+CONFIG_NFS_V4=y
-+CONFIG_ROOT_NFS=y
-+# CONFIG_NFSD is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_EXPORTFS=m
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+CONFIG_SUNRPC_GSS=y
-+# CONFIG_SUNRPC_REGISTER_V4 is not set
-+CONFIG_RPCSEC_GSS_KRB5=y
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+# CONFIG_SMB_FS is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+
-+#
-+# Partition Types
-+#
-+CONFIG_PARTITION_ADVANCED=y
-+# CONFIG_ACORN_PARTITION is not set
-+# CONFIG_OSF_PARTITION is not set
-+# CONFIG_AMIGA_PARTITION is not set
-+# CONFIG_ATARI_PARTITION is not set
-+# CONFIG_MAC_PARTITION is not set
-+CONFIG_MSDOS_PARTITION=y
-+# CONFIG_BSD_DISKLABEL is not set
-+# CONFIG_MINIX_SUBPARTITION is not set
-+# CONFIG_SOLARIS_X86_PARTITION is not set
-+# CONFIG_UNIXWARE_DISKLABEL is not set
-+# CONFIG_LDM_PARTITION is not set
-+# CONFIG_SGI_PARTITION is not set
-+# CONFIG_ULTRIX_PARTITION is not set
-+# CONFIG_SUN_PARTITION is not set
-+# CONFIG_KARMA_PARTITION is not set
-+# CONFIG_EFI_PARTITION is not set
-+# CONFIG_SYSV68_PARTITION is not set
-+CONFIG_NLS=y
-+CONFIG_NLS_DEFAULT="iso8859-1"
-+CONFIG_NLS_CODEPAGE_437=y
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+# CONFIG_NLS_CODEPAGE_850 is not set
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+# CONFIG_NLS_ASCII is not set
-+CONFIG_NLS_ISO8859_1=y
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+# CONFIG_NLS_UTF8 is not set
-+# CONFIG_DLM is not set
-+
-+#
-+# Kernel hacking
-+#
-+# CONFIG_PRINTK_TIME is not set
-+CONFIG_ENABLE_WARN_DEPRECATED=y
-+CONFIG_ENABLE_MUST_CHECK=y
-+CONFIG_FRAME_WARN=1024
-+CONFIG_MAGIC_SYSRQ=y
-+# CONFIG_UNUSED_SYMBOLS is not set
-+CONFIG_DEBUG_FS=y
-+# CONFIG_HEADERS_CHECK is not set
-+CONFIG_DEBUG_KERNEL=y
-+# CONFIG_DEBUG_SHIRQ is not set
-+CONFIG_DETECT_SOFTLOCKUP=y
-+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-+CONFIG_SCHED_DEBUG=y
-+CONFIG_SCHEDSTATS=y
-+CONFIG_TIMER_STATS=y
-+# CONFIG_DEBUG_OBJECTS is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
-+# CONFIG_SLUB_STATS is not set
-+# CONFIG_DEBUG_RT_MUTEXES is not set
-+# CONFIG_RT_MUTEX_TESTER is not set
-+# CONFIG_DEBUG_SPINLOCK is not set
-+CONFIG_DEBUG_MUTEXES=y
-+# CONFIG_DEBUG_LOCK_ALLOC is not set
-+# CONFIG_PROVE_LOCKING is not set
-+# CONFIG_LOCK_STAT is not set
-+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-+CONFIG_STACKTRACE=y
-+# CONFIG_DEBUG_KOBJECT is not set
-+CONFIG_DEBUG_BUGVERBOSE=y
-+# CONFIG_DEBUG_INFO is not set
-+# CONFIG_DEBUG_VM is not set
-+# CONFIG_DEBUG_WRITECOUNT is not set
-+# CONFIG_DEBUG_MEMORY_INIT is not set
-+# CONFIG_DEBUG_LIST is not set
-+# CONFIG_DEBUG_SG is not set
-+# CONFIG_DEBUG_NOTIFIERS is not set
-+CONFIG_FRAME_POINTER=y
-+# CONFIG_BOOT_PRINTK_DELAY is not set
-+# CONFIG_RCU_TORTURE_TEST is not set
-+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-+# CONFIG_BACKTRACE_SELF_TEST is not set
-+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-+# CONFIG_FAULT_INJECTION is not set
-+# CONFIG_LATENCYTOP is not set
-+CONFIG_NOP_TRACER=y
-+CONFIG_HAVE_FUNCTION_TRACER=y
-+CONFIG_RING_BUFFER=y
-+CONFIG_TRACING=y
-+
-+#
-+# Tracers
-+#
-+# CONFIG_FUNCTION_TRACER is not set
-+# CONFIG_IRQSOFF_TRACER is not set
-+# CONFIG_SCHED_TRACER is not set
-+# CONFIG_CONTEXT_SWITCH_TRACER is not set
-+# CONFIG_BOOT_TRACER is not set
-+# CONFIG_TRACE_BRANCH_PROFILING is not set
-+# CONFIG_STACK_TRACER is not set
-+# CONFIG_FTRACE_STARTUP_TEST is not set
-+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
-+# CONFIG_SAMPLES is not set
-+CONFIG_HAVE_ARCH_KGDB=y
-+# CONFIG_KGDB is not set
-+CONFIG_DEBUG_USER=y
-+CONFIG_DEBUG_ERRORS=y
-+# CONFIG_DEBUG_STACK_USAGE is not set
-+# CONFIG_DEBUG_LL is not set
-+
-+#
-+# Security options
-+#
-+# CONFIG_KEYS is not set
-+# CONFIG_SECURITY is not set
-+# CONFIG_SECURITYFS is not set
-+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-+CONFIG_XOR_BLOCKS=m
-+CONFIG_ASYNC_CORE=m
-+CONFIG_ASYNC_MEMCPY=m
-+CONFIG_ASYNC_XOR=m
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+# CONFIG_CRYPTO_FIPS is not set
-+CONFIG_CRYPTO_ALGAPI=y
-+CONFIG_CRYPTO_ALGAPI2=y
-+CONFIG_CRYPTO_AEAD2=y
-+CONFIG_CRYPTO_BLKCIPHER=y
-+CONFIG_CRYPTO_BLKCIPHER2=y
-+CONFIG_CRYPTO_HASH=y
-+CONFIG_CRYPTO_HASH2=y
-+CONFIG_CRYPTO_RNG2=y
-+CONFIG_CRYPTO_MANAGER=y
-+CONFIG_CRYPTO_MANAGER2=y
-+CONFIG_CRYPTO_GF128MUL=m
-+CONFIG_CRYPTO_NULL=m
-+CONFIG_CRYPTO_CRYPTD=m
-+# CONFIG_CRYPTO_AUTHENC is not set
-+CONFIG_CRYPTO_TEST=m
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=y
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+CONFIG_CRYPTO_ECB=y
-+CONFIG_CRYPTO_LRW=m
-+CONFIG_CRYPTO_PCBC=m
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+CONFIG_CRYPTO_HMAC=m
-+CONFIG_CRYPTO_XCBC=m
-+
-+#
-+# Digest
-+#
-+CONFIG_CRYPTO_CRC32C=y
-+CONFIG_CRYPTO_MD4=m
-+CONFIG_CRYPTO_MD5=y
-+CONFIG_CRYPTO_MICHAEL_MIC=y
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+CONFIG_CRYPTO_SHA1=m
-+CONFIG_CRYPTO_SHA256=m
-+CONFIG_CRYPTO_SHA512=m
-+CONFIG_CRYPTO_TGR192=m
-+CONFIG_CRYPTO_WP512=m
-+
-+#
-+# Ciphers
-+#
-+CONFIG_CRYPTO_AES=y
-+CONFIG_CRYPTO_ANUBIS=m
-+CONFIG_CRYPTO_ARC4=y
-+CONFIG_CRYPTO_BLOWFISH=m
-+CONFIG_CRYPTO_CAMELLIA=m
-+CONFIG_CRYPTO_CAST5=m
-+CONFIG_CRYPTO_CAST6=m
-+CONFIG_CRYPTO_DES=y
-+CONFIG_CRYPTO_FCRYPT=m
-+CONFIG_CRYPTO_KHAZAD=m
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+CONFIG_CRYPTO_SERPENT=m
-+CONFIG_CRYPTO_TEA=m
-+CONFIG_CRYPTO_TWOFISH=m
-+CONFIG_CRYPTO_TWOFISH_COMMON=m
-+
-+#
-+# Compression
-+#
-+CONFIG_CRYPTO_DEFLATE=m
-+# CONFIG_CRYPTO_LZO is not set
-+
-+#
-+# Random Number Generation
-+#
-+# CONFIG_CRYPTO_ANSI_CPRNG is not set
-+CONFIG_CRYPTO_HW=y
-+
-+#
-+# Library routines
-+#
-+CONFIG_BITREVERSE=y
-+CONFIG_GENERIC_FIND_LAST_BIT=y
-+CONFIG_CRC_CCITT=y
-+CONFIG_CRC16=m
-+CONFIG_CRC_T10DIF=y
-+CONFIG_CRC_ITU_T=y
-+CONFIG_CRC32=y
-+CONFIG_CRC7=y
-+CONFIG_LIBCRC32C=y
-+CONFIG_ZLIB_INFLATE=y
-+CONFIG_ZLIB_DEFLATE=y
-+CONFIG_LZO_COMPRESS=y
-+CONFIG_LZO_DECOMPRESS=y
-+CONFIG_PLIST=y
-+CONFIG_HAS_IOMEM=y
-+CONFIG_HAS_IOPORT=y
-+CONFIG_HAS_DMA=y
-diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
-index 0a1099e..3c664a9 100644
---- a/arch/arm/mach-omap2/board-3430sdp.c
-+++ b/arch/arm/mach-omap2/board-3430sdp.c
-@@ -242,6 +243,35 @@ static struct spi_board_info sdp3430_spi_board_info[] __initdata = {
- },
- };
-
-+
-+#define SDP2430_LCD_PANEL_BACKLIGHT_GPIO 91
-+#define SDP2430_LCD_PANEL_ENABLE_GPIO 154
-+#if 0
-+#define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 24
-+#define SDP3430_LCD_PANEL_ENABLE_GPIO 28
-+#else
-+#define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 8
-+#define SDP3430_LCD_PANEL_ENABLE_GPIO 5
-+#endif
-+
-+#define PM_RECEIVER TWL4030_MODULE_PM_RECEIVER
-+#define ENABLE_VAUX2_DEDICATED 0x09
-+#define ENABLE_VAUX2_DEV_GRP 0x20
-+#define ENABLE_VAUX3_DEDICATED 0x03
-+#define ENABLE_VAUX3_DEV_GRP 0x20
-+
-+#define ENABLE_VPLL2_DEDICATED 0x05
-+#define ENABLE_VPLL2_DEV_GRP 0xE0
-+#define TWL4030_VPLL2_DEV_GRP 0x33
-+#define TWL4030_VPLL2_DEDICATED 0x36
-+
-+#define t2_out(c, r, v) twl4030_i2c_write_u8(c, r, v)
-+
-+static unsigned backlight_gpio;
-+static unsigned enable_gpio;
-+static int lcd_enabled;
-+static int dvi_enabled;
-+
- static struct platform_device sdp3430_lcd_device = {
- .name = "sdp2430_lcd",
- .id = -1,
-@@ -257,9 +287,198 @@ static struct regulator_consumer_supply sdp3430_vdvi_supply = {
- .dev = &sdp3430_lcd_device.dev,
- };
-
-+static void enable_vpll2(int enable)
-+{
-+ u8 ded_val, grp_val;
-+
-+ if (enable) {
-+ ded_val = ENABLE_VPLL2_DEDICATED;
-+ grp_val = ENABLE_VPLL2_DEV_GRP;
-+ } else {
-+ ded_val = 0;
-+ grp_val = 0;
-+ }
-+
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
-+ ded_val, TWL4030_VPLL2_DEDICATED);
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
-+ grp_val, TWL4030_VPLL2_DEV_GRP);
-+}
-+
-+static int sdp3430_dsi_power_up(void)
-+{
-+ if (omap_rev() > OMAP3430_REV_ES1_0)
-+ enable_vpll2(1);
-+ return 0;
-+}
-+
-+static void sdp3430_dsi_power_down(void)
-+{
-+ if (omap_rev() > OMAP3430_REV_ES1_0)
-+ enable_vpll2(0);
-+}
-+
-+static void __init sdp3430_display_init(void)
-+{
-+ int r;
-+
-+ enable_gpio = SDP3430_LCD_PANEL_ENABLE_GPIO;
-+ backlight_gpio = SDP3430_LCD_PANEL_BACKLIGHT_GPIO;
-+
-+ r = gpio_request(enable_gpio, "LCD reset");
-+ if (r) {
-+ printk(KERN_ERR "failed to get LCD reset GPIO\n");
-+ goto err0;
-+ }
-+
-+ r = gpio_request(backlight_gpio, "LCD Backlight");
-+ if (r) {
-+ printk(KERN_ERR "failed to get LCD backlight GPIO\n");
-+ goto err1;
-+ }
-+
-+ gpio_direction_output(enable_gpio, 0);
-+ gpio_direction_output(backlight_gpio, 0);
-+
-+ return;
-+err1:
-+ gpio_free(enable_gpio);
-+err0:
-+ return;
-+}
-+
-+static int sdp3430_panel_enable_lcd(struct omap_display *display)
-+{
-+ u8 ded_val, ded_reg;
-+ u8 grp_val, grp_reg;
-+
-+ if (dvi_enabled) {
-+ printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
-+ return -EINVAL;
-+ }
-+
-+ ded_reg = TWL4030_VAUX3_DEDICATED;
-+ ded_val = ENABLE_VAUX3_DEDICATED;
-+ grp_reg = TWL4030_VAUX3_DEV_GRP;
-+ grp_val = ENABLE_VAUX3_DEV_GRP;
-+
-+ gpio_direction_output(enable_gpio, 1);
-+ gpio_direction_output(backlight_gpio, 1);
-+
-+ if (0 != t2_out(PM_RECEIVER, ded_val, ded_reg))
-+ return -EIO;
-+ if (0 != t2_out(PM_RECEIVER, grp_val, grp_reg))
-+ return -EIO;
-+
-+ sdp3430_dsi_power_up();
-+
-+ lcd_enabled = 1;
-+
-+ return 0;
-+}
-+
-+static void sdp3430_panel_disable_lcd(struct omap_display *display)
-+{
-+ lcd_enabled = 0;
-+
-+ sdp3430_dsi_power_down();
-+
-+ gpio_direction_output(enable_gpio, 0);
-+ gpio_direction_output(backlight_gpio, 0);
-+}
-+
-+static struct omap_dss_display_config sdp3430_display_data = {
-+ .type = OMAP_DISPLAY_TYPE_DPI,
-+ .name = "lcd",
-+ .panel_name = "sharp-ls037v7dw01",
-+ .u.dpi.data_lines = 16,
-+ .panel_enable = sdp3430_panel_enable_lcd,
-+ .panel_disable = sdp3430_panel_disable_lcd,
-+};
-+
-+static int sdp3430_panel_enable_dvi(struct omap_display *display)
-+{
-+ if (lcd_enabled) {
-+ printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
-+ return -EINVAL;
-+ }
-+
-+ sdp3430_dsi_power_up();
-+
-+ dvi_enabled = 1;
-+
-+ return 0;
-+}
-+
-+static void sdp3430_panel_disable_dvi(struct omap_display *display)
-+{
-+ sdp3430_dsi_power_down();
-+
-+ dvi_enabled = 0;
-+}
-+
-+
-+static struct omap_dss_display_config sdp3430_display_data_dvi = {
-+ .type = OMAP_DISPLAY_TYPE_DPI,
-+ .name = "dvi",
-+ .panel_name = "panel-generic",
-+ .u.dpi.data_lines = 24,
-+ .panel_enable = sdp3430_panel_enable_dvi,
-+ .panel_disable = sdp3430_panel_disable_dvi,
-+};
-+
-+static int sdp3430_panel_enable_tv(struct omap_display *display)
-+{
-+#define ENABLE_VDAC_DEDICATED 0x03
-+#define ENABLE_VDAC_DEV_GRP 0x20
-+
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
-+ ENABLE_VDAC_DEDICATED,
-+ TWL4030_VDAC_DEDICATED);
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
-+ ENABLE_VDAC_DEV_GRP, TWL4030_VDAC_DEV_GRP);
-+
-+ return 0;
-+}
-+
-+static void sdp3430_panel_disable_tv(struct omap_display *display)
-+{
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
-+ TWL4030_VDAC_DEDICATED);
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
-+ TWL4030_VDAC_DEV_GRP);
-+}
-+
-+static struct omap_dss_display_config sdp3430_display_data_tv = {
-+ .type = OMAP_DISPLAY_TYPE_VENC,
-+ .name = "tv",
-+ .u.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
-+ .panel_enable = sdp3430_panel_enable_tv,
-+ .panel_disable = sdp3430_panel_disable_tv,
-+};
-+
-+static struct omap_dss_board_info sdp3430_dss_data = {
-+ .dsi_power_up = sdp3430_dsi_power_up,
-+ .dsi_power_down = sdp3430_dsi_power_down,
-+ .num_displays = 3,
-+ .displays = {
-+ &sdp3430_display_data,
-+ &sdp3430_display_data_dvi,
-+ &sdp3430_display_data_tv,
-+ }
-+};
-+
-+static struct platform_device sdp3430_dss_device = {
-+ .name = "omapdss",
-+ .id = -1,
-+ .dev = {
-+ .platform_data = &sdp3430_dss_data,
-+ },
-+};
-+
- static struct platform_device *sdp3430_devices[] __initdata = {
- &sdp3430_smc91x_device,
-- &sdp3430_lcd_device,
-+ &sdp3430_dss_device,
- };
-
- static inline void __init sdp3430_init_smc91x(void)
-@@ -306,13 +525,8 @@ static struct omap_uart_config sdp3430_uart_config __initdata = {
- .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
- };
-
--static struct omap_lcd_config sdp3430_lcd_config __initdata = {
-- .ctrl_name = "internal",
--};
--
- static struct omap_board_config_kernel sdp3430_config[] __initdata = {
- { OMAP_TAG_UART, &sdp3430_uart_config },
-- { OMAP_TAG_LCD, &sdp3430_lcd_config },
- };
-
- static int sdp3430_batt_table[] = {
-@@ -681,6 +895,7 @@ static void __init omap_3430sdp_init(void)
- omap_serial_init();
- usb_musb_init();
- usb_ehci_init();
-+ sdp3430_display_init();
- }
-
- static void __init omap_3430sdp_map_io(void)
-diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
-index 346351e..b67e7a5 100644
---- a/arch/arm/mach-omap2/board-omap3beagle.c
-+++ b/arch/arm/mach-omap2/board-omap3beagle.c
-@@ -30,6 +30,7 @@
-
- #include <linux/regulator/machine.h>
- #include <linux/i2c/twl4030.h>
-+#include <linux/omapfb.h>
-
- #include <mach/hardware.h>
- #include <asm/mach-types.h>
-@@ -312,10 +314,6 @@ static void __init omap3_beagle_init_irq(void)
- omap_gpio_init();
- }
-
--static struct omap_lcd_config omap3_beagle_lcd_config __initdata = {
-- .ctrl_name = "internal",
--};
--
- static struct gpio_led gpio_leds[] = {
- {
- .name = "beagleboard::usr0",
-@@ -369,13 +367,94 @@ static struct platform_device keys_gpio = {
- },
- };
-
-+/* DSS */
-+
-+static int beagle_enable_dvi(struct omap_display *display)
-+{
-+ if (display->hw_config.panel_reset_gpio != -1)
-+ gpio_direction_output(display->hw_config.panel_reset_gpio, 1);
-+
-+ return 0;
-+}
-+
-+static void beagle_disable_dvi(struct omap_display *display)
-+{
-+ if (display->hw_config.panel_reset_gpio != -1)
-+ gpio_direction_output(display->hw_config.panel_reset_gpio, 0);
-+}
-+
-+static struct omap_dss_display_config beagle_display_data_dvi = {
-+ .type = OMAP_DISPLAY_TYPE_DPI,
-+ .name = "dvi",
-+ .panel_name = "panel-generic",
-+ .u.dpi.data_lines = 24,
-+ .panel_reset_gpio = 170,
-+ .panel_enable = beagle_enable_dvi,
-+ .panel_disable = beagle_disable_dvi,
-+};
-+
-+
-+static int beagle_panel_enable_tv(struct omap_display *display)
-+{
-+#define ENABLE_VDAC_DEDICATED 0x03
-+#define ENABLE_VDAC_DEV_GRP 0x20
-+
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
-+ ENABLE_VDAC_DEDICATED,
-+ TWL4030_VDAC_DEDICATED);
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
-+ ENABLE_VDAC_DEV_GRP, TWL4030_VDAC_DEV_GRP);
-+
-+ return 0;
-+}
-+
-+static void beagle_panel_disable_tv(struct omap_display *display)
-+{
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
-+ TWL4030_VDAC_DEDICATED);
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
-+ TWL4030_VDAC_DEV_GRP);
-+}
-+
-+static struct omap_dss_display_config beagle_display_data_tv = {
-+ .type = OMAP_DISPLAY_TYPE_VENC,
-+ .name = "tv",
-+ .u.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
-+ .panel_enable = beagle_panel_enable_tv,
-+ .panel_disable = beagle_panel_disable_tv,
-+};
-+
-+static struct omap_dss_board_info beagle_dss_data = {
-+ .num_displays = 2,
-+ .displays = {
-+ &beagle_display_data_dvi,
-+ &beagle_display_data_tv,
-+ }
-+};
-+
-+static struct platform_device beagle_dss_device = {
-+ .name = "omapdss",
-+ .id = -1,
-+ .dev = {
-+ .platform_data = &beagle_dss_data,
-+ },
-+};
-+
-+static void __init beagle_display_init(void)
-+{
-+ int r;
-+
-+ r = gpio_request(beagle_display_data_dvi.panel_reset_gpio, "DVI reset");
-+ if (r < 0)
-+ printk(KERN_ERR "Unable to get DVI reset GPIO\n");
-+}
-+
- static struct omap_board_config_kernel omap3_beagle_config[] __initdata = {
- { OMAP_TAG_UART, &omap3_beagle_uart_config },
-- { OMAP_TAG_LCD, &omap3_beagle_lcd_config },
- };
-
- static struct platform_device *omap3_beagle_devices[] __initdata = {
-- &omap3_beagle_lcd_device,
-+ &beagle_dss_device,
- &leds_gpio,
- &keys_gpio,
- };
-@@ -428,13 +507,11 @@ static void __init omap3_beagle_init(void)
- omap_serial_init();
-
- omap_cfg_reg(J25_34XX_GPIO170);
-- gpio_request(170, "DVI_nPD");
-- /* REVISIT leave DVI powered down until it's needed ... */
-- gpio_direction_output(170, true);
-
- usb_musb_init();
- usb_ehci_init();
- omap3beagle_flash_init();
-+ beagle_display_init();
- }
-
- static void __init omap3_beagle_map_io(void)
-diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
-index 024d7c4..6f5a866 100644
---- a/arch/arm/mach-omap2/board-omap3evm.c
-+++ b/arch/arm/mach-omap2/board-omap3evm.c
-@@ -216,13 +217,215 @@ static int __init omap3_evm_i2c_init(void)
- return 0;
- }
-
--static struct platform_device omap3_evm_lcd_device = {
-- .name = "omap3evm_lcd",
-- .id = -1,
-+#define LCD_PANEL_LR 2
-+#define LCD_PANEL_UD 3
-+#define LCD_PANEL_INI 152
-+#define LCD_PANEL_ENABLE_GPIO 153
-+#define LCD_PANEL_QVGA 154
-+#define LCD_PANEL_RESB 155
-+
-+#define ENABLE_VDAC_DEDICATED 0x03
-+#define ENABLE_VDAC_DEV_GRP 0x20
-+#define ENABLE_VPLL2_DEDICATED 0x05
-+#define ENABLE_VPLL2_DEV_GRP 0xE0
-+
-+#define TWL4030_GPIODATA_IN3 0x03
-+#define TWL4030_GPIODATA_DIR3 0x06
-+#define TWL4030_VPLL2_DEV_GRP 0x33
-+#define TWL4030_VPLL2_DEDICATED 0x36
-+
-+static int lcd_enabled;
-+static int dvi_enabled;
-+
-+static void __init omap3_evm_display_init(void)
-+{
-+ int r;
-+ r = gpio_request(LCD_PANEL_LR, "lcd_panel_lr");
-+ if (r) {
-+ printk(KERN_ERR "failed to get LCD_PANEL_LR\n");
-+ return;
-+ }
-+ r = gpio_request(LCD_PANEL_UD, "lcd_panel_ud");
-+ if (r) {
-+ printk(KERN_ERR "failed to get LCD_PANEL_UD\n");
-+ goto err_1;
-+ }
-+
-+ r = gpio_request(LCD_PANEL_INI, "lcd_panel_ini");
-+ if (r) {
-+ printk(KERN_ERR "failed to get LCD_PANEL_INI\n");
-+ goto err_2;
-+ }
-+ r = gpio_request(LCD_PANEL_RESB, "lcd_panel_resb");
-+ if (r) {
-+ printk(KERN_ERR "failed to get LCD_PANEL_RESB\n");
-+ goto err_3;
-+ }
-+ r = gpio_request(LCD_PANEL_QVGA, "lcd_panel_qvga");
-+ if (r) {
-+ printk(KERN_ERR "failed to get LCD_PANEL_QVGA\n");
-+ goto err_4;
-+ }
-+
-+ gpio_direction_output(LCD_PANEL_LR, 0);
-+ gpio_direction_output(LCD_PANEL_UD, 0);
-+ gpio_direction_output(LCD_PANEL_INI, 0);
-+ gpio_direction_output(LCD_PANEL_RESB, 0);
-+ gpio_direction_output(LCD_PANEL_QVGA, 0);
-+
-+#define TWL_LED_LEDEN 0x00
-+#define TWL_PWMA_PWMAON 0x00
-+#define TWL_PWMA_PWMAOFF 0x01
-+
-+ twl4030_i2c_write_u8(TWL4030_MODULE_LED, 0x11, TWL_LED_LEDEN);
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PWMA, 0x01, TWL_PWMA_PWMAON);
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PWMA, 0x02, TWL_PWMA_PWMAOFF);
-+
-+ gpio_direction_output(LCD_PANEL_RESB, 1);
-+ gpio_direction_output(LCD_PANEL_INI, 1);
-+ gpio_direction_output(LCD_PANEL_QVGA, 0);
-+ gpio_direction_output(LCD_PANEL_LR, 1);
-+ gpio_direction_output(LCD_PANEL_UD, 1);
-+
-+ return;
-+
-+err_4:
-+ gpio_free(LCD_PANEL_RESB);
-+err_3:
-+ gpio_free(LCD_PANEL_INI);
-+err_2:
-+ gpio_free(LCD_PANEL_UD);
-+err_1:
-+ gpio_free(LCD_PANEL_LR);
-+
-+}
-+
-+static int omap3_evm_panel_enable_lcd(struct omap_display *display)
-+{
-+ if (dvi_enabled) {
-+ printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
-+ return -EINVAL;
-+ }
-+ if (omap_rev() > OMAP3430_REV_ES1_0) {
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
-+ ENABLE_VPLL2_DEDICATED, TWL4030_VPLL2_DEDICATED);
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
-+ ENABLE_VPLL2_DEV_GRP, TWL4030_VPLL2_DEV_GRP);
-+ }
-+ gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 0);
-+ lcd_enabled = 1;
-+ return 0;
-+}
-+
-+static void omap3_evm_panel_disable_lcd(struct omap_display *display)
-+{
-+ if (omap_rev() > OMAP3430_REV_ES1_0) {
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
-+ TWL4030_VPLL2_DEDICATED);
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
-+ TWL4030_VPLL2_DEV_GRP);
-+ }
-+ gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 1);
-+ lcd_enabled = 0;
-+}
-+
-+static struct omap_dss_display_config omap3_evm_display_data = {
-+ .type = OMAP_DISPLAY_TYPE_DPI,
-+ .name = "lcd",
-+ .panel_name = "sharp-ls037v7dw01",
-+ .u.dpi.data_lines = 18,
-+ .panel_enable = omap3_evm_panel_enable_lcd,
-+ .panel_disable = omap3_evm_panel_disable_lcd,
- };
-
--static struct omap_lcd_config omap3_evm_lcd_config __initdata = {
-- .ctrl_name = "internal",
-+static int omap3_evm_panel_enable_tv(struct omap_display *display)
-+{
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
-+ ENABLE_VDAC_DEDICATED, TWL4030_VDAC_DEDICATED);
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
-+ ENABLE_VDAC_DEV_GRP, TWL4030_VDAC_DEV_GRP);
-+ return 0;
-+}
-+
-+static void omap3_evm_panel_disable_tv(struct omap_display *display)
-+{
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
-+ TWL4030_VDAC_DEDICATED);
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00,
-+ TWL4030_VDAC_DEV_GRP);
-+}
-+
-+static struct omap_dss_display_config omap3_evm_display_data_tv = {
-+ .type = OMAP_DISPLAY_TYPE_VENC,
-+ .name = "tv",
-+ .u.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
-+ .panel_enable = omap3_evm_panel_enable_tv,
-+ .panel_disable = omap3_evm_panel_disable_tv,
-+};
-+
-+
-+static int omap3_evm_panel_enable_dvi(struct omap_display *display)
-+{
-+ if (lcd_enabled) {
-+ printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
-+ return -EINVAL;
-+ }
-+ if (omap_rev() > OMAP3430_REV_ES1_0) {
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
-+ ENABLE_VPLL2_DEDICATED, TWL4030_VPLL2_DEDICATED);
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
-+ ENABLE_VPLL2_DEV_GRP, TWL4030_VPLL2_DEV_GRP);
-+ }
-+
-+ twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80,
-+ TWL4030_GPIODATA_IN3);
-+ twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80,
-+ TWL4030_GPIODATA_DIR3);
-+ dvi_enabled = 1;
-+
-+ return 0;
-+}
-+
-+static void omap3_evm_panel_disable_dvi(struct omap_display *display)
-+{
-+ if (omap_rev() > OMAP3430_REV_ES1_0) {
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
-+ TWL4030_VPLL2_DEDICATED);
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
-+ TWL4030_VPLL2_DEV_GRP);
-+ }
-+
-+ twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x00,
-+ TWL4030_GPIODATA_IN3);
-+ twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x00,
-+ TWL4030_GPIODATA_DIR3);
-+ dvi_enabled = 0;
-+}
-+
-+
-+static struct omap_dss_display_config omap3_evm_display_data_dvi = {
-+ .type = OMAP_DISPLAY_TYPE_DPI,
-+ .name = "dvi",
-+ .panel_name = "panel-generic",
-+ .u.dpi.data_lines = 24,
-+ .panel_enable = omap3_evm_panel_enable_dvi,
-+ .panel_disable = omap3_evm_panel_disable_dvi,
-+};
-+
-+static struct omap_dss_board_info omap3_evm_dss_data = {
-+ .num_displays = 3,
-+ .displays = {
-+ &omap3_evm_display_data,
-+ &omap3_evm_display_data_dvi,
-+ &omap3_evm_display_data_tv,
-+ }
-+};
-+static struct platform_device omap3_evm_dss_device = {
-+ .name = "omapdss",
-+ .id = -1,
-+ .dev = {
-+ .platform_data = &omap3_evm_dss_data,
-+ },
- };
-
- static void ads7846_dev_init(void)
-@@ -281,11 +484,10 @@ static void __init omap3_evm_init_irq(void)
-
- static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
- { OMAP_TAG_UART, &omap3_evm_uart_config },
-- { OMAP_TAG_LCD, &omap3_evm_lcd_config },
- };
-
- static struct platform_device *omap3_evm_devices[] __initdata = {
-- &omap3_evm_lcd_device,
-+ &omap3_evm_dss_device,
- &omap3evm_smc911x_device,
- };
-
-@@ -305,6 +507,7 @@ static void __init omap3_evm_init(void)
- usb_ehci_init();
- omap3evm_flash_init();
- ads7846_dev_init();
-+ omap3_evm_display_init();
- }
-
- static void __init omap3_evm_map_io(void)
-diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
-index 071f4b0..267bb6b 100644
---- a/arch/arm/mach-omap2/board-overo.c
-+++ b/arch/arm/mach-omap2/board-overo.c
-@@ -41,6 +41,7 @@
- #include <mach/board-overo.h>
- #include <mach/board.h>
- #include <mach/common.h>
-+#include <mach/display.h>
- #include <mach/gpio.h>
- #include <mach/gpmc.h>
- #include <mach/hardware.h>
-@@ -176,6 +177,9 @@ static void __init overo_ads7846_init(void)
- static inline void __init overo_ads7846_init(void) { return; }
- #endif
-
-+static int lcd_enabled;
-+static int dvi_enabled;
-+
- static struct mtd_partition overo_nand_partitions[] = {
- {
- .name = "xloader",
-@@ -360,22 +364,101 @@ static void __init overo_init_irq(void)
- omap_gpio_init();
- }
-
--static struct platform_device overo_lcd_device = {
-- .name = "overo_lcd",
-- .id = -1,
-+/* DSS */
-+
-+#define OVERO_GPIO_LCD_EN 144
-+
-+static void __init overo_display_init(void)
-+{
-+ int r;
-+
-+ r = gpio_request(OVERO_GPIO_LCD_EN, "display enable");
-+ if (r)
-+ printk("fail1\n");
-+ r = gpio_direction_output(OVERO_GPIO_LCD_EN, 1);
-+ if (r)
-+ printk("fail2\n");
-+ gpio_export(OVERO_GPIO_LCD_EN, 0);
-+}
-+
-+static int overo_panel_enable_dvi(struct omap_display *display)
-+{
-+ if (lcd_enabled) {
-+ printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
-+ return -EINVAL;
-+ }
-+ dvi_enabled = 1;
-+
-+ gpio_set_value(OVERO_GPIO_LCD_EN, 1);
-+
-+ return 0;
-+}
-+
-+static void overo_panel_disable_dvi(struct omap_display *display)
-+{
-+ gpio_set_value(OVERO_GPIO_LCD_EN, 0);
-+
-+ dvi_enabled = 0;
-+}
-+
-+static struct omap_dss_display_config overo_display_data_dvi = {
-+ .type = OMAP_DISPLAY_TYPE_DPI,
-+ .name = "dvi",
-+ .panel_name = "panel-generic",
-+ .u.dpi.data_lines = 24,
-+ .panel_enable = overo_panel_enable_dvi,
-+ .panel_disable = overo_panel_disable_dvi,
- };
-
--static struct omap_lcd_config overo_lcd_config __initdata = {
-- .ctrl_name = "internal",
-+static int overo_panel_enable_lcd(struct omap_display *display)
-+{
-+ if (dvi_enabled) {
-+ printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
-+ return -EINVAL;
-+ }
-+
-+ gpio_set_value(OVERO_GPIO_LCD_EN, 1);
-+ lcd_enabled = 1;
-+ return 0;
-+}
-+
-+static void overo_panel_disable_lcd(struct omap_display *display)
-+{
-+ gpio_set_value(OVERO_GPIO_LCD_EN, 0);
-+ lcd_enabled = 0;
-+}
-+
-+static struct omap_dss_display_config overo_display_data_lcd = {
-+ .type = OMAP_DISPLAY_TYPE_DPI,
-+ .name = "lcd43",
-+ .panel_name = "samsung-lte430wq-f0c",
-+ .u.dpi.data_lines = 24,
-+ .panel_enable = overo_panel_enable_lcd,
-+ .panel_disable = overo_panel_disable_lcd,
-+ };
-+
-+static struct omap_dss_board_info overo_dss_data = {
-+ .num_displays = 2,
-+ .displays = {
-+ &overo_display_data_dvi,
-+ &overo_display_data_lcd,
-+ }
-+};
-+
-+static struct platform_device overo_dss_device = {
-+ .name = "omapdss",
-+ .id = -1,
-+ .dev = {
-+ .platform_data = &overo_dss_data,
-+ },
- };
-
- static struct omap_board_config_kernel overo_config[] __initdata = {
- { OMAP_TAG_UART, &overo_uart_config },
-- { OMAP_TAG_LCD, &overo_lcd_config },
- };
-
- static struct platform_device *overo_devices[] __initdata = {
-- &overo_lcd_device,
-+ &overo_dss_device,
- };
-
- static void __init overo_init(void)
-@@ -390,6 +473,7 @@ static void __init overo_init(void)
- overo_flash_init();
- overo_init_smsc911x();
- overo_ads7846_init();
-+ overo_display_init();
-
- if ((gpio_request(OVERO_GPIO_W2W_NRESET,
- "OVERO_GPIO_W2W_NRESET") == 0) &&
---
-1.5.6.5
-
+++ /dev/null
-From 4741076cae4f4284e1fff9a03f35475b8455af54 Mon Sep 17 00:00:00 2001
-From: Imre Deak <imre.deak@nokia.com>
-Date: Wed, 1 Apr 2009 14:36:39 +0200
-Subject: [PATCH 08/69] DSS2: Add function to display object to get the backlight level
-
-This is needed by an upcoming patch that changes the backlight
-initialization to use the backlight level set by the bootloader.
-
-Also add a field for the maximum backlight level.
-
-Signed-off-by: Imre Deak <imre.deak@nokia.com>
----
- arch/arm/plat-omap/include/mach/display.h | 3 +++
- 1 files changed, 3 insertions(+), 0 deletions(-)
-
-diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
-index 6288353..6b702c7 100644
---- a/arch/arm/plat-omap/include/mach/display.h
-+++ b/arch/arm/plat-omap/include/mach/display.h
-@@ -211,6 +211,8 @@ struct omap_dss_display_config {
- int panel_reset_gpio;
- int ctrl_reset_gpio;
-
-+ int max_backlight_level;
-+
- const char *name; /* for debug */
- const char *ctrl_name;
- const char *panel_name;
-@@ -225,6 +227,7 @@ struct omap_dss_display_config {
- void (*ctrl_disable)(struct omap_display *display);
- int (*set_backlight)(struct omap_display *display,
- int level);
-+ int (*get_backlight)(struct omap_display *display);
- };
-
- struct device;
---
-1.6.2.4
-
+++ /dev/null
-From 66e16f86d3f4c5b34b37e965c65102b7192371de Mon Sep 17 00:00:00 2001
-From: Imre Deak <imre.deak@nokia.com>
-Date: Thu, 2 Apr 2009 11:47:13 +0300
-Subject: [PATCH 09/69] DSS2: Add acx565akm panel
-
-Signed-off-by: Imre Deak <imre.deak@nokia.com>
----
- drivers/video/omap2/displays/Kconfig | 8 +
- drivers/video/omap2/displays/Makefile | 2 +
- drivers/video/omap2/displays/panel-acx565akm.c | 712 ++++++++++++++++++++++++
- drivers/video/omap2/displays/panel-acx565akm.h | 9 +
- 4 files changed, 731 insertions(+), 0 deletions(-)
- create mode 100644 drivers/video/omap2/displays/panel-acx565akm.c
- create mode 100644 drivers/video/omap2/displays/panel-acx565akm.h
-
-diff --git a/drivers/video/omap2/displays/Kconfig b/drivers/video/omap2/displays/Kconfig
-index 356ceb1..3feecee 100644
---- a/drivers/video/omap2/displays/Kconfig
-+++ b/drivers/video/omap2/displays/Kconfig
-@@ -28,4 +28,12 @@ config CTRL_BLIZZARD
- tristate "Blizzard Controller"
- help
- Blizzard Controller (hack)
-+
-+config PANEL_ACX565AKM
-+ tristate "ACX565AKM LCD Panel"
-+ depends on OMAP2_DSS_SDI
-+ select BACKLIGHT_CLASS_DEVICE
-+ help
-+ LCD Panel used in RX51
-+
- endmenu
-diff --git a/drivers/video/omap2/displays/Makefile b/drivers/video/omap2/displays/Makefile
-index 1b74b7e..9bafcb6 100644
---- a/drivers/video/omap2/displays/Makefile
-+++ b/drivers/video/omap2/displays/Makefile
-@@ -4,3 +4,5 @@ obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o
-
- obj-$(CONFIG_CTRL_BLIZZARD) += ctrl-blizzard.o
- obj-$(CONFIG_PANEL_N800) += panel-n800.o
-+
-+obj-$(CONFIG_PANEL_ACX565AKM) += panel-acx565akm.o
-diff --git a/drivers/video/omap2/displays/panel-acx565akm.c b/drivers/video/omap2/displays/panel-acx565akm.c
-new file mode 100644
-index 0000000..2679d6c
---- /dev/null
-+++ b/drivers/video/omap2/displays/panel-acx565akm.c
-@@ -0,0 +1,712 @@
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/clk.h>
-+#include <linux/platform_device.h>
-+#include <linux/delay.h>
-+#include <linux/spi/spi.h>
-+#include <linux/jiffies.h>
-+#include <linux/sched.h>
-+#include <linux/backlight.h>
-+#include <linux/fb.h>
-+
-+#include <mach/display.h>
-+#include <mach/dma.h>
-+
-+#include "panel-acx565akm.h"
-+
-+#define MIPID_CMD_READ_DISP_ID 0x04
-+#define MIPID_CMD_READ_RED 0x06
-+#define MIPID_CMD_READ_GREEN 0x07
-+#define MIPID_CMD_READ_BLUE 0x08
-+#define MIPID_CMD_READ_DISP_STATUS 0x09
-+#define MIPID_CMD_RDDSDR 0x0F
-+#define MIPID_CMD_SLEEP_IN 0x10
-+#define MIPID_CMD_SLEEP_OUT 0x11
-+#define MIPID_CMD_DISP_OFF 0x28
-+#define MIPID_CMD_DISP_ON 0x29
-+#define MIPID_CMD_WRITE_DISP_BRIGHTNESS 0x51
-+#define MIPID_CMD_READ_DISP_BRIGHTNESS 0x52
-+#define MIPID_CMD_WRITE_CTRL_DISP 0x53
-+
-+#define CTRL_DISP_BRIGHTNESS_CTRL_ON (1 << 5)
-+#define CTRL_DISP_AMBIENT_LIGHT_CTRL_ON (1 << 4)
-+#define CTRL_DISP_BACKLIGHT_ON (1 << 2)
-+#define CTRL_DISP_AUTO_BRIGHTNESS_ON (1 << 1)
-+
-+#define MIPID_CMD_READ_CTRL_DISP 0x54
-+#define MIPID_CMD_WRITE_CABC 0x55
-+#define MIPID_CMD_READ_CABC 0x56
-+
-+#define MIPID_VER_LPH8923 3
-+#define MIPID_VER_LS041Y3 4
-+#define MIPID_VER_L4F00311 8
-+#define MIPID_VER_ACX565AKM 9
-+
-+struct acx565akm_device {
-+ struct backlight_device *bl_dev;
-+ int enabled;
-+ int model;
-+ int revision;
-+ u8 display_id[3];
-+ int has_bc:1;
-+ int has_cabc:1;
-+ unsigned int saved_bklight_level;
-+ unsigned long hw_guard_end; /* next value of jiffies
-+ when we can issue the
-+ next sleep in/out command */
-+ unsigned long hw_guard_wait; /* max guard time in jiffies */
-+
-+ struct spi_device *spi;
-+ struct mutex mutex;
-+ struct omap_panel panel;
-+ struct omap_display *display;
-+};
-+
-+static int acx565akm_bl_update_status(struct backlight_device *dev);
-+
-+static void acx565akm_transfer(struct acx565akm_device *md, int cmd,
-+ const u8 *wbuf, int wlen, u8 *rbuf, int rlen)
-+{
-+ struct spi_message m;
-+ struct spi_transfer *x, xfer[5];
-+ int r;
-+
-+ BUG_ON(md->spi == NULL);
-+
-+ spi_message_init(&m);
-+
-+ memset(xfer, 0, sizeof(xfer));
-+ x = &xfer[0];
-+
-+ cmd &= 0xff;
-+ x->tx_buf = &cmd;
-+ x->bits_per_word = 9;
-+ x->len = 2;
-+
-+ if (rlen > 1 && wlen == 0) {
-+ /*
-+ * Between the command and the response data there is a
-+ * dummy clock cycle. Add an extra bit after the command
-+ * word to account for this.
-+ */
-+ x->bits_per_word = 10;
-+ cmd <<= 1;
-+ }
-+ spi_message_add_tail(x, &m);
-+
-+ if (wlen) {
-+ x++;
-+ x->tx_buf = wbuf;
-+ x->len = wlen;
-+ x->bits_per_word = 9;
-+ spi_message_add_tail(x, &m);
-+ }
-+
-+ if (rlen) {
-+ x++;
-+ x->rx_buf = rbuf;
-+ x->len = rlen;
-+ spi_message_add_tail(x, &m);
-+ }
-+
-+ r = spi_sync(md->spi, &m);
-+ if (r < 0)
-+ dev_dbg(&md->spi->dev, "spi_sync %d\n", r);
-+}
-+
-+static inline void acx565akm_cmd(struct acx565akm_device *md, int cmd)
-+{
-+ acx565akm_transfer(md, cmd, NULL, 0, NULL, 0);
-+}
-+
-+static inline void acx565akm_write(struct acx565akm_device *md,
-+ int reg, const u8 *buf, int len)
-+{
-+ acx565akm_transfer(md, reg, buf, len, NULL, 0);
-+}
-+
-+static inline void acx565akm_read(struct acx565akm_device *md,
-+ int reg, u8 *buf, int len)
-+{
-+ acx565akm_transfer(md, reg, NULL, 0, buf, len);
-+}
-+
-+static void hw_guard_start(struct acx565akm_device *md, int guard_msec)
-+{
-+ md->hw_guard_wait = msecs_to_jiffies(guard_msec);
-+ md->hw_guard_end = jiffies + md->hw_guard_wait;
-+}
-+
-+static void hw_guard_wait(struct acx565akm_device *md)
-+{
-+ unsigned long wait = md->hw_guard_end - jiffies;
-+
-+ if ((long)wait > 0 && wait <= md->hw_guard_wait) {
-+ set_current_state(TASK_UNINTERRUPTIBLE);
-+ schedule_timeout(wait);
-+ }
-+}
-+
-+static void set_sleep_mode(struct acx565akm_device *md, int on)
-+{
-+ int cmd, sleep_time = 50;
-+
-+ if (on)
-+ cmd = MIPID_CMD_SLEEP_IN;
-+ else
-+ cmd = MIPID_CMD_SLEEP_OUT;
-+ hw_guard_wait(md);
-+ acx565akm_cmd(md, cmd);
-+ hw_guard_start(md, 120);
-+ /*
-+ * When we enable the panel, it seems we _have_ to sleep
-+ * 120 ms before sending the init string. When disabling the
-+ * panel we'll sleep for the duration of 2 frames, so that the
-+ * controller can still provide the PCLK,HS,VS signals. */
-+ if (!on)
-+ sleep_time = 120;
-+ msleep(sleep_time);
-+}
-+
-+static void set_display_state(struct acx565akm_device *md, int enabled)
-+{
-+ int cmd = enabled ? MIPID_CMD_DISP_ON : MIPID_CMD_DISP_OFF;
-+
-+ acx565akm_cmd(md, cmd);
-+}
-+
-+static int panel_enabled(struct acx565akm_device *md)
-+{
-+ u32 disp_status;
-+ int enabled;
-+
-+ acx565akm_read(md, MIPID_CMD_READ_DISP_STATUS, (u8 *)&disp_status, 4);
-+ disp_status = __be32_to_cpu(disp_status);
-+ enabled = (disp_status & (1 << 17)) && (disp_status & (1 << 10));
-+ dev_dbg(&md->spi->dev,
-+ "LCD panel %senabled by bootloader (status 0x%04x)\n",
-+ enabled ? "" : "not ", disp_status);
-+ return enabled;
-+}
-+
-+static void enable_backlight_ctrl(struct acx565akm_device *md, int enable)
-+{
-+ u16 ctrl;
-+
-+ acx565akm_read(md, MIPID_CMD_READ_CTRL_DISP, (u8 *)&ctrl, 1);
-+ if (enable) {
-+ ctrl |= CTRL_DISP_BRIGHTNESS_CTRL_ON |
-+ CTRL_DISP_BACKLIGHT_ON;
-+ } else {
-+ ctrl &= ~(CTRL_DISP_BRIGHTNESS_CTRL_ON |
-+ CTRL_DISP_BACKLIGHT_ON);
-+ }
-+
-+ ctrl |= 1 << 8;
-+ acx565akm_write(md, MIPID_CMD_WRITE_CTRL_DISP, (u8 *)&ctrl, 2);
-+}
-+
-+static void set_cabc_mode(struct acx565akm_device *md, int mode)
-+{
-+ u16 cabc_ctrl;
-+
-+ cabc_ctrl = 0;
-+ acx565akm_read(md, MIPID_CMD_READ_CABC, (u8 *)&cabc_ctrl, 1);
-+ cabc_ctrl &= ~3;
-+ cabc_ctrl |= (1 << 8) | (mode & 3);
-+ acx565akm_write(md, MIPID_CMD_WRITE_CABC, (u8 *)&cabc_ctrl, 2);
-+}
-+
-+static int get_cabc_mode(struct acx565akm_device *md)
-+{
-+ u8 cabc_ctrl;
-+
-+ acx565akm_read(md, MIPID_CMD_READ_CABC, &cabc_ctrl, 1);
-+ return cabc_ctrl & 3;
-+}
-+
-+static int panel_detect(struct acx565akm_device *md)
-+{
-+ acx565akm_read(md, MIPID_CMD_READ_DISP_ID, md->display_id, 3);
-+ dev_dbg(&md->spi->dev, "MIPI display ID: %02x%02x%02x\n",
-+ md->display_id[0], md->display_id[1], md->display_id[2]);
-+
-+ switch (md->display_id[0]) {
-+ case 0x10:
-+ md->model = MIPID_VER_ACX565AKM;
-+ md->panel.name = "acx565akm";
-+ md->has_bc = 1;
-+ md->has_cabc = 1;
-+ break;
-+ case 0x29:
-+ md->model = MIPID_VER_L4F00311;
-+ md->panel.name = "l4f00311";
-+ break;
-+ case 0x45:
-+ md->model = MIPID_VER_LPH8923;
-+ md->panel.name = "lph8923";
-+ break;
-+ case 0x83:
-+ md->model = MIPID_VER_LS041Y3;
-+ md->panel.name = "ls041y3";
-+ break;
-+ default:
-+ md->panel.name = "unknown";
-+ dev_err(&md->spi->dev, "invalid display ID\n");
-+ return -ENODEV;
-+ }
-+
-+ md->revision = md->display_id[1];
-+
-+ pr_info("omapfb: %s rev %02x LCD detected\n",
-+ md->panel.name, md->revision);
-+
-+ return 0;
-+}
-+
-+static int acx565akm_panel_enable(struct omap_display *display)
-+{
-+ struct acx565akm_device *md =
-+ (struct acx565akm_device *)display->panel->priv;
-+
-+ dev_dbg(&md->spi->dev, "%s\n", __func__);
-+
-+ mutex_lock(&md->mutex);
-+
-+ if (display->hw_config.panel_enable)
-+ display->hw_config.panel_enable(display);
-+
-+ md->enabled = panel_enabled(md);
-+
-+ if (md->enabled) {
-+ dev_dbg(&md->spi->dev, "panel already enabled\n");
-+ mutex_unlock(&md->mutex);
-+ return 0;
-+ }
-+
-+ set_sleep_mode(md, 0);
-+ md->enabled = 1;
-+ set_display_state(md, 1);
-+
-+ mutex_unlock(&md->mutex);
-+
-+ return acx565akm_bl_update_status(md->bl_dev);
-+}
-+
-+static void acx565akm_panel_disable(struct omap_display *display)
-+{
-+ struct acx565akm_device *md =
-+ (struct acx565akm_device *)display->panel->priv;
-+
-+ dev_dbg(&md->spi->dev, "%s\n", __func__);
-+
-+ mutex_lock(&md->mutex);
-+
-+ if (!md->enabled) {
-+ mutex_unlock(&md->mutex);
-+ return;
-+ }
-+ set_display_state(md, 0);
-+ set_sleep_mode(md, 1);
-+ md->enabled = 0;
-+
-+ if (display->hw_config.panel_disable)
-+ display->hw_config.panel_disable(display);
-+
-+ mutex_unlock(&md->mutex);
-+}
-+
-+#if 0
-+static void acx565akm_set_mode(struct omap_display *display,
-+ int x_res, int y_res, int bpp)
-+{
-+ struct acx565akm_device *md =
-+ (struct acx565akm_device *)display->panel->priv;
-+ u16 par;
-+
-+ switch (bpp) {
-+ case 16:
-+ par = 0x150;
-+ break;
-+ case 18:
-+ par = 0x160;
-+ break;
-+ case 24:
-+ par = 0x170;
-+ break;
-+ }
-+
-+ acx565akm_write(md, 0x3a, (u8 *)&par, 2);
-+}
-+#endif
-+
-+static int acx565akm_panel_suspend(struct omap_display *display)
-+{
-+ acx565akm_panel_disable(display);
-+ return 0;
-+}
-+
-+static int acx565akm_panel_resume(struct omap_display *display)
-+{
-+ return acx565akm_panel_enable(display);
-+}
-+
-+static void acx565akm_set_brightness(struct acx565akm_device *md, int level)
-+{
-+ int bv;
-+
-+ bv = level | (1 << 8);
-+ acx565akm_write(md, MIPID_CMD_WRITE_DISP_BRIGHTNESS, (u8 *)&bv, 2);
-+
-+ if (level)
-+ enable_backlight_ctrl(md, 1);
-+ else
-+ enable_backlight_ctrl(md, 0);
-+}
-+
-+static int acx565akm_get_actual_brightness(struct acx565akm_device *md)
-+{
-+ u8 bv;
-+
-+ acx565akm_read(md, MIPID_CMD_READ_DISP_BRIGHTNESS, &bv, 1);
-+
-+ return bv;
-+}
-+
-+static int acx565akm_bl_update_status(struct backlight_device *dev)
-+{
-+ struct acx565akm_device *md = dev_get_drvdata(&dev->dev);
-+ struct omap_display *display = md->display;
-+ int r;
-+ int level;
-+
-+ dev_dbg(&md->spi->dev, "%s\n", __func__);
-+
-+ if (display->hw_config.set_backlight == NULL)
-+ return -ENODEV;
-+
-+ mutex_lock(&md->mutex);
-+
-+ if (dev->props.fb_blank == FB_BLANK_UNBLANK &&
-+ dev->props.power == FB_BLANK_UNBLANK)
-+ level = dev->props.brightness;
-+ else
-+ level = 0;
-+
-+ r = 0;
-+ if (md->has_bc)
-+ acx565akm_set_brightness(md, level);
-+ else
-+ if (display->hw_config.set_backlight != NULL)
-+ r = display->hw_config.set_backlight(display, level);
-+ else
-+ r = -ENODEV;
-+
-+ mutex_unlock(&md->mutex);
-+
-+ return r;
-+}
-+
-+static int acx565akm_bl_get_intensity(struct backlight_device *dev)
-+{
-+ struct acx565akm_device *md = dev_get_drvdata(&dev->dev);
-+ struct omap_display *display = md->display;
-+
-+ dev_dbg(&dev->dev, "%s\n", __func__);
-+
-+ if (md->has_bc && display->hw_config.set_backlight == NULL)
-+ return -ENODEV;
-+
-+ if (dev->props.fb_blank == FB_BLANK_UNBLANK &&
-+ dev->props.power == FB_BLANK_UNBLANK) {
-+ if (md->has_bc)
-+ return acx565akm_get_actual_brightness(md);
-+ else
-+ return dev->props.brightness;
-+ }
-+
-+ return 0;
-+}
-+
-+static struct backlight_ops acx565akm_bl_ops = {
-+ .get_brightness = acx565akm_bl_get_intensity,
-+ .update_status = acx565akm_bl_update_status,
-+};
-+
-+static const char *cabc_modes[] = {
-+ "off", /* used also always when CABC is not supported */
-+ "ui",
-+ "still-image",
-+ "moving-image",
-+};
-+
-+static ssize_t show_cabc_mode(struct device *dev,
-+ struct device_attribute *attr,
-+ char *buf)
-+{
-+ struct acx565akm_device *md = dev_get_drvdata(dev);
-+ const char *mode_str;
-+ int mode;
-+ int len;
-+
-+ if (!md->has_cabc)
-+ mode = 0;
-+ else
-+ mode = get_cabc_mode(md);
-+ mode_str = "unknown";
-+ if (mode >= 0 && mode < ARRAY_SIZE(cabc_modes))
-+ mode_str = cabc_modes[mode];
-+ len = snprintf(buf, PAGE_SIZE, "%s\n", mode_str);
-+
-+ return len < PAGE_SIZE - 1 ? len : PAGE_SIZE - 1;
-+}
-+
-+static ssize_t store_cabc_mode(struct device *dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ struct acx565akm_device *md = dev_get_drvdata(dev);
-+ int i;
-+
-+ for (i = 0; i < ARRAY_SIZE(cabc_modes); i++) {
-+ const char *mode_str = cabc_modes[i];
-+ int cmp_len = strlen(mode_str);
-+
-+ if (count > 0 && buf[count - 1] == '\n')
-+ count--;
-+ if (count != cmp_len)
-+ continue;
-+
-+ if (strncmp(buf, mode_str, cmp_len) == 0)
-+ break;
-+ }
-+
-+ if (i == ARRAY_SIZE(cabc_modes))
-+ return -EINVAL;
-+
-+ if (!md->has_cabc && i != 0)
-+ return -EINVAL;
-+
-+ mutex_lock(&md->mutex);
-+ set_cabc_mode(md, i);
-+ mutex_unlock(&md->mutex);
-+
-+ return count;
-+}
-+
-+static ssize_t show_cabc_available_modes(struct device *dev,
-+ struct device_attribute *attr,
-+ char *buf)
-+{
-+ struct acx565akm_device *md = dev_get_drvdata(dev);
-+ int len;
-+ int i;
-+
-+ if (!md->has_cabc)
-+ return snprintf(buf, PAGE_SIZE, "%s\n", cabc_modes[0]);
-+
-+ for (i = 0, len = 0;
-+ len < PAGE_SIZE && i < ARRAY_SIZE(cabc_modes); i++)
-+ len += snprintf(&buf[len], PAGE_SIZE - len, "%s%s%s",
-+ i ? " " : "", cabc_modes[i],
-+ i == ARRAY_SIZE(cabc_modes) - 1 ? "\n" : "");
-+
-+ return len < PAGE_SIZE ? len : PAGE_SIZE - 1;
-+}
-+
-+static DEVICE_ATTR(cabc_mode, S_IRUGO | S_IWUSR,
-+ show_cabc_mode, store_cabc_mode);
-+static DEVICE_ATTR(cabc_available_modes, S_IRUGO,
-+ show_cabc_available_modes, NULL);
-+
-+static struct attribute *bldev_attrs[] = {
-+ &dev_attr_cabc_mode.attr,
-+ &dev_attr_cabc_available_modes.attr,
-+ NULL,
-+};
-+
-+static struct attribute_group bldev_attr_group = {
-+ .attrs = bldev_attrs,
-+};
-+
-+static int acx565akm_panel_init(struct omap_display *display)
-+{
-+ struct omap_panel *panel = display->panel;
-+ struct acx565akm_panel_data *panel_data = display->hw_config.panel_data;
-+ struct acx565akm_device *md = (struct acx565akm_device *)panel->priv;
-+
-+ struct backlight_device *bldev;
-+ int brightness;
-+ int max_brightness;
-+ int r;
-+
-+ dev_dbg(&md->spi->dev, "%s\n", __func__);
-+
-+ if (!panel_data) {
-+ dev_err(&md->spi->dev, "no panel data\n");
-+ return -ENODEV;
-+ }
-+
-+ mutex_init(&md->mutex);
-+ md->display = display;
-+
-+ if (display->hw_config.panel_enable)
-+ display->hw_config.panel_enable(display);
-+
-+ md->enabled = panel_enabled(md);
-+
-+ r = panel_detect(md);
-+ if (r) {
-+ if (!md->enabled && display->hw_config.panel_disable)
-+ display->hw_config.panel_disable(display);
-+ mutex_unlock(&md->mutex);
-+ return r;
-+ }
-+
-+ if (!panel_data->bc_connected) {
-+ md->has_bc = 0;
-+ md->has_cabc = 0;
-+ }
-+
-+#if 0
-+ acx565akm_set_mode(display, panel->timings.x_res, panel->timings.y_res,
-+ panel->bpp);
-+#endif
-+
-+ if (!md->enabled)
-+ display->hw_config.panel_disable(display);
-+
-+ bldev = backlight_device_register("acx565akm", &md->spi->dev,
-+ md, &acx565akm_bl_ops);
-+ md->bl_dev = bldev;
-+
-+ if (md->has_cabc) {
-+ r = sysfs_create_group(&bldev->dev.kobj, &bldev_attr_group);
-+ if (r) {
-+ dev_err(&bldev->dev, "failed to create sysfs files\n");
-+ backlight_device_unregister(bldev);
-+ return r;
-+ }
-+ }
-+
-+ bldev->props.fb_blank = FB_BLANK_UNBLANK;
-+ bldev->props.power = FB_BLANK_UNBLANK;
-+
-+ if (md->has_bc)
-+ max_brightness = 255;
-+ else
-+ max_brightness = display->hw_config.max_backlight_level;
-+
-+ if (md->has_bc)
-+ brightness = acx565akm_get_actual_brightness(md);
-+ else {
-+ if (display->hw_config.get_backlight != NULL)
-+ brightness = display->hw_config.get_backlight(display);
-+ else
-+ brightness = 0;
-+ }
-+
-+ bldev->props.max_brightness = max_brightness;
-+ bldev->props.brightness = brightness;
-+ acx565akm_bl_update_status(bldev);
-+
-+ return 0;
-+}
-+
-+static struct omap_panel acx565akm_panel = {
-+ .name = "panel-acx565akm",
-+ .init = acx565akm_panel_init,
-+ .suspend = acx565akm_panel_suspend,
-+ .resume = acx565akm_panel_resume,
-+ .enable = acx565akm_panel_enable,
-+ .disable = acx565akm_panel_disable,
-+
-+ .timings = {
-+ .x_res = 800,
-+ .y_res = 480,
-+
-+ .pixel_clock = 24000,
-+
-+ .hsw = 4,
-+ .hfp = 16,
-+ .hbp = 12,
-+
-+ .vsw = 3,
-+ .vfp = 3,
-+ .vbp = 3,
-+ },
-+
-+ .config = OMAP_DSS_LCD_TFT,
-+
-+ .recommended_bpp = 16,
-+
-+ /*
-+ * supported modes: 12bpp(444), 16bpp(565), 18bpp(666), 24bpp(888)
-+ * resolutions.
-+ */
-+};
-+
-+static int acx565akm_spi_probe(struct spi_device *spi)
-+{
-+ struct acx565akm_device *md;
-+
-+ dev_dbg(&md->spi->dev, "%s\n", __func__);
-+
-+ md = kzalloc(sizeof(*md), GFP_KERNEL);
-+ if (md == NULL) {
-+ dev_err(&spi->dev, "out of memory\n");
-+ return -ENOMEM;
-+ }
-+
-+ spi->mode = SPI_MODE_3;
-+ md->spi = spi;
-+ dev_set_drvdata(&spi->dev, md);
-+ md->panel = acx565akm_panel;
-+ acx565akm_panel.priv = md;
-+
-+ omap_dss_register_panel(&acx565akm_panel);
-+
-+ return 0;
-+}
-+
-+static int acx565akm_spi_remove(struct spi_device *spi)
-+{
-+ struct acx565akm_device *md = dev_get_drvdata(&spi->dev);
-+
-+ dev_dbg(&md->spi->dev, "%s\n", __func__);
-+
-+ sysfs_remove_group(&md->bl_dev->dev.kobj, &bldev_attr_group);
-+ backlight_device_unregister(md->bl_dev);
-+ omap_dss_unregister_panel(&acx565akm_panel);
-+
-+ kfree(md);
-+
-+ return 0;
-+}
-+
-+static struct spi_driver acx565akm_spi_driver = {
-+ .driver = {
-+ .name = "acx565akm",
-+ .bus = &spi_bus_type,
-+ .owner = THIS_MODULE,
-+ },
-+ .probe = acx565akm_spi_probe,
-+ .remove = __devexit_p(acx565akm_spi_remove),
-+};
-+
-+static int __init acx565akm_init(void)
-+{
-+ return spi_register_driver(&acx565akm_spi_driver);
-+}
-+
-+static void __exit acx565akm_exit(void)
-+{
-+ spi_unregister_driver(&acx565akm_spi_driver);
-+}
-+
-+module_init(acx565akm_init);
-+module_exit(acx565akm_exit);
-+
-+MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
-+MODULE_DESCRIPTION("acx565akm LCD Driver");
-+MODULE_LICENSE("GPL");
-diff --git a/drivers/video/omap2/displays/panel-acx565akm.h b/drivers/video/omap2/displays/panel-acx565akm.h
-new file mode 100644
-index 0000000..6d3727b
---- /dev/null
-+++ b/drivers/video/omap2/displays/panel-acx565akm.h
-@@ -0,0 +1,9 @@
-+#ifndef __DRIVERS_VIDEO_OMAP2_DISPLAYS_PANEL_ACX565AKM_H
-+#define __DRIVERS_VIDEO_OMAP2_DISPLAYS_PANEL_ACX565AKM_H
-+
-+struct acx565akm_panel_data {
-+ unsigned bc_connected:1;
-+};
-+
-+#endif
-+
---
-1.6.2.4
-
+++ /dev/null
-From 370510e24ddbf539392ebb6a1e43280965fcb19b Mon Sep 17 00:00:00 2001
-From: Vaibhav Hiremath <hvaibhav@ti.com>
-Date: Tue, 31 Mar 2009 18:47:32 +0530
-Subject: [PATCH 10/69] DSS2: Small VRFB context allocation bug fixed
-
-This is minor bug while requesting and mapping memory for
-VRFB space.
-
-Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
----
- drivers/video/omap2/omapfb/omapfb-main.c | 1 +
- 1 files changed, 1 insertions(+), 0 deletions(-)
-
-diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
-index 852abe5..44febef 100644
---- a/drivers/video/omap2/omapfb/omapfb-main.c
-+++ b/drivers/video/omap2/omapfb/omapfb-main.c
-@@ -1193,6 +1193,7 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
-
- if(!va) {
- printk(KERN_ERR "vrfb: ioremap failed\n");
-+ omap_vrfb_release_ctx(&rg->vrfb);
- return -ENOMEM;
- }
-
---
-1.6.2.4
-
+++ /dev/null
-From 370d1f93a32e8fcaeac5c16574417e354af21d08 Mon Sep 17 00:00:00 2001
-From: Vaibhav Hiremath <hvaibhav@ti.com>
-Date: Tue, 31 Mar 2009 18:38:31 +0530
-Subject: [PATCH 11/69] DSS2: Allocated memory for Color Look-up-table
-
-We were not allocating memory for CMAP buffer and due to that
-G_CMAP was failing, since it does check for size of CMAP buffer.
-
-Called "fb_alloc_cmap" for llocating memory for CMAP.
-
-We are currently not supporting 1,2,4,8 bpp, so meaning less
-for us as of now. But for completeness this is required.
-
-Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
----
- drivers/video/omap2/omapfb/omapfb-main.c | 5 +++++
- 1 files changed, 5 insertions(+), 0 deletions(-)
-
-diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
-index 44febef..afe40a9 100644
---- a/drivers/video/omap2/omapfb/omapfb-main.c
-+++ b/drivers/video/omap2/omapfb/omapfb-main.c
-@@ -1525,6 +1525,11 @@ int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi)
- goto err;
-
- set_fb_fix(fbi);
-+
-+ r = fb_alloc_cmap(&fbi->cmap, 256, 0);
-+ if (r)
-+ dev_err(fbdev->dev, "unable to allocate color map memory\n");
-+
- err:
- return r;
- }
---
-1.6.2.4
-
+++ /dev/null
-From 9c93bcab724b5935d745604773ed43825efefd87 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Thu, 2 Apr 2009 13:47:11 +0300
-Subject: [PATCH 12/69] DSS2: Fix DMA rotation
-
-u16 was not a good type for offsets. First, they need to be signed,
-and second, 16 bits is not enough.
----
- drivers/video/omap2/dss/dispc.c | 12 ++++++------
- 1 files changed, 6 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-index ffb5648..6cea545 100644
---- a/drivers/video/omap2/dss/dispc.c
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -778,7 +778,7 @@ static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
- dispc_write_reg(vsi_reg[plane-1], val);
- }
-
--static void _dispc_set_pix_inc(enum omap_plane plane, u16 inc)
-+static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
- {
- const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
- DISPC_VID_PIXEL_INC(0),
-@@ -787,7 +787,7 @@ static void _dispc_set_pix_inc(enum omap_plane plane, u16 inc)
- dispc_write_reg(ri_reg[plane], inc);
- }
-
--static void _dispc_set_row_inc(enum omap_plane plane, u16 inc)
-+static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
- {
- const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
- DISPC_VID_ROW_INC(0),
-@@ -1123,7 +1123,7 @@ static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
- }
- }
-
--static int pixinc(int pixels, u8 ps)
-+static s32 pixinc(int pixels, u8 ps)
- {
- if (pixels == 1)
- return 1;
-@@ -1140,7 +1140,7 @@ static void calc_rotation_offset(u8 rotation, bool mirror,
- u16 width, u16 height,
- enum omap_color_mode color_mode, bool fieldmode,
- unsigned *offset0, unsigned *offset1,
-- u16 *row_inc, u16 *pix_inc)
-+ s32 *row_inc, s32 *pix_inc)
- {
- u8 ps;
- u16 fbw, fbh;
-@@ -1298,8 +1298,8 @@ static int _dispc_setup_plane(enum omap_plane plane,
- bool fieldmode = 0;
- int cconv = 0;
- unsigned offset0, offset1;
-- u16 row_inc;
-- u16 pix_inc;
-+ s32 row_inc;
-+ s32 pix_inc;
-
- if (plane == OMAP_DSS_GFX) {
- if (width != out_width || height != out_height)
---
-1.6.2.4
-
+++ /dev/null
-From 360a55ddd309e3a45b227a4a905ae7120dd16169 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Thu, 2 Apr 2009 14:21:12 +0300
-Subject: [PATCH 13/69] DSS2: Verify that overlay paddr != 0
-
----
- drivers/video/omap2/dss/dispc.c | 3 +++
- drivers/video/omap2/dss/overlay.c | 3 +++
- 2 files changed, 6 insertions(+), 0 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-index 6cea545..2480a03 100644
---- a/drivers/video/omap2/dss/dispc.c
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -1301,6 +1301,9 @@ static int _dispc_setup_plane(enum omap_plane plane,
- s32 row_inc;
- s32 pix_inc;
-
-+ if (paddr == 0)
-+ return -EINVAL;
-+
- if (plane == OMAP_DSS_GFX) {
- if (width != out_width || height != out_height)
- return -EINVAL;
-diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c
-index 968edbe..9209acf 100644
---- a/drivers/video/omap2/dss/overlay.c
-+++ b/drivers/video/omap2/dss/overlay.c
-@@ -331,6 +331,9 @@ static int dss_ovl_set_overlay_info(struct omap_overlay *ovl,
- int r;
- struct omap_overlay_info old_info;
-
-+ if (info->paddr == 0)
-+ return -EINVAL;
-+
- old_info = ovl->info;
- ovl->info = *info;
-
---
-1.6.2.4
-
+++ /dev/null
-From 832b763db235da8e62f7b6ab02bcb8ad6bcb7a01 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Thu, 2 Apr 2009 16:48:41 +0300
-Subject: [PATCH 14/69] DSS2: Add function to get DSS logic clock rate
-
----
- drivers/video/omap2/dss/dispc.c | 15 +++++++++++++++
- drivers/video/omap2/dss/dss.h | 1 +
- 2 files changed, 16 insertions(+), 0 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-index 2480a03..1bc23f7 100644
---- a/drivers/video/omap2/dss/dispc.c
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -1850,6 +1850,21 @@ unsigned long dispc_fclk_rate(void)
- return r;
- }
-
-+unsigned long dispc_lclk_rate(void)
-+{
-+ int lcd;
-+ unsigned long r;
-+ u32 l;
-+
-+ l = dispc_read_reg(DISPC_DIVISOR);
-+
-+ lcd = FLD_GET(l, 23, 16);
-+
-+ r = dispc_fclk_rate();
-+
-+ return r / lcd;
-+}
-+
- unsigned long dispc_pclk_rate(void)
- {
- int lcd, pcd;
-diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
-index bac5ece..0be42b6 100644
---- a/drivers/video/omap2/dss/dss.h
-+++ b/drivers/video/omap2/dss/dss.h
-@@ -294,6 +294,7 @@ bool dispc_trans_key_enabled(enum omap_channel ch);
-
- void dispc_set_lcd_timings(struct omap_video_timings *timings);
- unsigned long dispc_fclk_rate(void);
-+unsigned long dispc_lclk_rate(void);
- unsigned long dispc_pclk_rate(void);
- void dispc_set_pol_freq(struct omap_panel *panel);
- void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
---
-1.6.2.4
-
+++ /dev/null
-From a5c235a6f0094494ae1fc1a1ba4728e0d33dfd3b Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Thu, 2 Apr 2009 16:49:27 +0300
-Subject: [PATCH 15/69] DSS2: DSI: calculate VP_CLK_RATIO properly
-
----
- drivers/video/omap2/dss/dsi.c | 17 +++++++++++------
- 1 files changed, 11 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
-index 4442931..aecb89d 100644
---- a/drivers/video/omap2/dss/dsi.c
-+++ b/drivers/video/omap2/dss/dsi.c
-@@ -1104,7 +1104,10 @@ int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
- enable_clocks(1);
- dsi_enable_pll_clock(1);
-
-- /* configure dispc fck and pixel clock to something sane */
-+ /* XXX this should be calculated depending on the screen size,
-+ * required framerate and DSI speed.
-+ * For now 48MHz is enough for 864x480@60 with 360Mbps/lane
-+ * with two lanes */
- r = dispc_calc_clock_div(1, 48 * 1000 * 1000, &cinfo);
- if (r)
- goto err0;
-@@ -1119,7 +1122,7 @@ int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
- if (r)
- goto err0;
-
-- /* PLL does not come out of reset without this... */
-+ /* XXX PLL does not come out of reset without this... */
- dispc_pck_free_enable(1);
-
- if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
-@@ -1128,8 +1131,8 @@ int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
- goto err1;
- }
-
-- /* ... but if left on, we get problems when planes do not
-- * fill the whole display. No idea about this XXX */
-+ /* XXX ... but if left on, we get problems when planes do not
-+ * fill the whole display. No idea about this */
- dispc_pck_free_enable(0);
-
- if (enable_hsclk && enable_hsdiv)
-@@ -2214,6 +2217,7 @@ static int dsi_proto_config(struct omap_display *display)
- {
- u32 r;
- int buswidth = 0;
-+ int div;
-
- dsi_config_tx_fifo(DSI_FIFO_SIZE_128,
- DSI_FIFO_SIZE_0,
-@@ -2254,8 +2258,9 @@ static int dsi_proto_config(struct omap_display *display)
- r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
- r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
- r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
-- /* XXX what should the ratio be */
-- r = FLD_MOD(r, 0, 4, 4); /* VP_CLK_RATIO, VP_PCLK = VP_CLK/2 */
-+
-+ div = dispc_lclk_rate() / dispc_pclk_rate();
-+ r = FLD_MOD(r, div == 2 ? 0 : 1, 4, 4); /* VP_CLK_RATIO */
- r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
- r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
- r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
---
-1.6.2.4
-
+++ /dev/null
-From 6b2c9d84c7accdfe1067fcdc8a00e50674aab4bb Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Thu, 2 Apr 2009 17:42:26 +0300
-Subject: [PATCH 16/69] DSS2: DSI: improve packet len calculation
-
----
- drivers/video/omap2/dss/dsi.c | 21 ++++++++++++++++-----
- 1 files changed, 16 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
-index aecb89d..66ac6ea 100644
---- a/drivers/video/omap2/dss/dsi.c
-+++ b/drivers/video/omap2/dss/dsi.c
-@@ -2624,17 +2624,28 @@ static void dsi_update_screen_dispc(struct omap_display *display,
- u16 x, u16 y, u16 w, u16 h)
- {
- int bytespp = 3;
-+ int len;
- int total_len;
-- int line_packet_len;
-+ int packet_payload;
-+ int packet_len;
- u32 l;
-
- if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
- DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
- x, y, w, h);
-
-- /* TODO: one packet could be longer, I think? Max is the line buffer */
-- line_packet_len = w * bytespp + 1; /* 1 byte for DCS cmd */
-- total_len = line_packet_len * h;
-+ len = w * h * bytespp;
-+
-+ /* XXX: one packet could be longer, I think? Line buffer is
-+ * 1024 x 24bits, but we have to put DCS cmd there also.
-+ * 1023 * 3 should work, but causes strange color effects. */
-+ packet_payload = min(w, (u16)1020) * bytespp;
-+
-+ packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
-+ total_len = (len / packet_payload) * packet_len;
-+
-+ if (len % packet_payload)
-+ total_len += (len % packet_payload) + 1;
-
- display->ctrl->setup_update(display, x, y, w, h);
-
-@@ -2646,7 +2657,7 @@ static void dsi_update_screen_dispc(struct omap_display *display,
- l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
- dsi_write_reg(DSI_VC_TE(1), l);
-
-- dsi_vc_write_long_header(1, DSI_DT_DCS_LONG_WRITE, line_packet_len, 0);
-+ dsi_vc_write_long_header(1, DSI_DT_DCS_LONG_WRITE, packet_len, 0);
-
- if (dsi.use_te)
- l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
---
-1.6.2.4
-
+++ /dev/null
-From 85848d329ca3a2d6ee6841cdc11cc5951d187931 Mon Sep 17 00:00:00 2001
-From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
-Date: Fri, 3 Apr 2009 19:09:20 +0200
-Subject: [PATCH 17/69] DSS2: Disable video planes on sync lost error
-MIME-Version: 1.0
-Content-Type: text/plain; charset=utf-8
-Content-Transfer-Encoding: 8bit
-
-When encountering the sync lost error disable the display and all video
-planes on the affected manager. Afterwards re-enable the display.
-
-Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
----
- drivers/video/omap2/dss/dispc.c | 50 +++++++++++++++++++++++++++++++++++++++
- 1 files changed, 50 insertions(+), 0 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-index 1bc23f7..41734f3 100644
---- a/drivers/video/omap2/dss/dispc.c
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -2518,29 +2518,79 @@ static void dispc_error_worker(struct work_struct *work)
- }
-
- if (errors & DISPC_IRQ_SYNC_LOST) {
-+ struct omap_overlay_manager *manager = NULL;
-+ bool enable = false;
-+
- DSSERR("SYNC_LOST, disabling LCD\n");
-+
- for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
- struct omap_overlay_manager *mgr;
- mgr = omap_dss_get_overlay_manager(i);
-
- if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
-+ manager = mgr;
-+ enable = mgr->display->state ==
-+ OMAP_DSS_DISPLAY_ACTIVE;
- mgr->display->disable(mgr->display);
- break;
- }
- }
-+
-+ if (manager) {
-+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
-+ struct omap_overlay *ovl;
-+ ovl = omap_dss_get_overlay(i);
-+
-+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
-+ continue;
-+
-+ if (ovl->id != 0 && ovl->manager == manager)
-+ dispc_enable_plane(ovl->id, 0);
-+ }
-+
-+ dispc_go(manager->id);
-+ mdelay(50);
-+ if (enable)
-+ manager->display->enable(manager->display);
-+ }
- }
-
- if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
-+ struct omap_overlay_manager *manager = NULL;
-+ bool enable = false;
-+
- DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
-+
- for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
- struct omap_overlay_manager *mgr;
- mgr = omap_dss_get_overlay_manager(i);
-
- if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
-+ manager = mgr;
-+ enable = mgr->display->state ==
-+ OMAP_DSS_DISPLAY_ACTIVE;
- mgr->display->disable(mgr->display);
- break;
- }
- }
-+
-+ if (manager) {
-+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
-+ struct omap_overlay *ovl;
-+ ovl = omap_dss_get_overlay(i);
-+
-+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
-+ continue;
-+
-+ if (ovl->id != 0 && ovl->manager == manager)
-+ dispc_enable_plane(ovl->id, 0);
-+ }
-+
-+ dispc_go(manager->id);
-+ mdelay(50);
-+ if (enable)
-+ manager->display->enable(manager->display);
-+ }
- }
-
- if (errors & DISPC_IRQ_OCP_ERR) {
---
-1.6.2.4
-
+++ /dev/null
-From 63e15ba8d5f95b13d3abf359da718537d769f112 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Tue, 7 Apr 2009 10:01:58 +0300
-Subject: [PATCH 18/69] DSS2: check for ovl paddr only when enabling
-
-It seems Xvideo uses SETUP_PLANE ioctl even when
-the fb memory has not been allocated. Sigh.
----
- drivers/video/omap2/dss/overlay.c | 8 +++++---
- 1 files changed, 5 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c
-index 9209acf..c047206 100644
---- a/drivers/video/omap2/dss/overlay.c
-+++ b/drivers/video/omap2/dss/overlay.c
-@@ -281,6 +281,11 @@ int dss_check_overlay(struct omap_overlay *ovl, struct omap_display *display)
-
- info = &ovl->info;
-
-+ if (info->paddr == 0) {
-+ DSSDBG("check_overlay failed: paddr 0\n");
-+ return -EINVAL;
-+ }
-+
- display->get_resolution(display, &dw, &dh);
-
- DSSDBG("check_overlay %d: (%d,%d %dx%d -> %dx%d) disp (%dx%d)\n",
-@@ -331,9 +336,6 @@ static int dss_ovl_set_overlay_info(struct omap_overlay *ovl,
- int r;
- struct omap_overlay_info old_info;
-
-- if (info->paddr == 0)
-- return -EINVAL;
--
- old_info = ovl->info;
- ovl->info = *info;
-
---
-1.6.2.4
-
+++ /dev/null
-From 67f3fc050ab4e2006d5b7ec6ec341896627181ab Mon Sep 17 00:00:00 2001
-From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
-Date: Mon, 6 Apr 2009 17:32:04 +0200
-Subject: [PATCH 19/69] DSS2: Check fclk limits when configuring video planes
-MIME-Version: 1.0
-Content-Type: text/plain; charset=utf-8
-Content-Transfer-Encoding: 8bit
-
-Check that the currect functional clock is fast enough to support
-the requested scaling ratios. Also check if 5-tap filtering can be
-used even though the downscaling ratio is less than 1:2 since the
-functional clock rate required for 5-tap filtering can be less than
-the requirement for 3-tap filtering, and 5-tap filtering should look
-better.
-
-Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
----
- drivers/video/omap2/dss/dispc.c | 104 ++++++++++++++++++++++++++++++++++++---
- 1 files changed, 97 insertions(+), 7 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-index 41734f3..61861d8 100644
---- a/drivers/video/omap2/dss/dispc.c
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -1026,11 +1026,11 @@ static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
- static void _dispc_set_scaling(enum omap_plane plane,
- u16 orig_width, u16 orig_height,
- u16 out_width, u16 out_height,
-- bool ilace)
-+ bool ilace, bool five_taps)
- {
- int fir_hinc;
- int fir_vinc;
-- int hscaleup, vscaleup, five_taps;
-+ int hscaleup, vscaleup;
- int fieldmode = 0;
- int accu0 = 0;
- int accu1 = 0;
-@@ -1040,7 +1040,6 @@ static void _dispc_set_scaling(enum omap_plane plane,
-
- hscaleup = orig_width <= out_width;
- vscaleup = orig_height <= out_height;
-- five_taps = orig_height > out_height * 2;
-
- _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
-
-@@ -1283,6 +1282,73 @@ static void calc_rotation_offset(u8 rotation, bool mirror,
- }
- }
-
-+static unsigned long calc_fclk_five_taps(u16 width, u16 height,
-+ u16 out_width, u16 out_height, enum omap_color_mode color_mode)
-+{
-+ u32 fclk = 0;
-+ /* FIXME venc pclk? */
-+ u64 tmp, pclk = dispc_pclk_rate();
-+
-+ if (height > out_height) {
-+ /* FIXME get real display PPL */
-+ unsigned int ppl = 800;
-+
-+ tmp = pclk * height * out_width;
-+ do_div(tmp, 2 * out_height * ppl);
-+ fclk = tmp;
-+
-+ if (height > 2 * out_height) {
-+ tmp = pclk * (height - 2 * out_height) * out_width;
-+ do_div(tmp, 2 * out_height * (ppl - out_width));
-+ fclk = max(fclk, (u32) tmp);
-+ }
-+ }
-+
-+ if (width > out_width) {
-+ tmp = pclk * width;
-+ do_div(tmp, out_width);
-+ fclk = max(fclk, (u32) tmp);
-+
-+ if (color_mode == OMAP_DSS_COLOR_RGB24U)
-+ fclk <<= 1;
-+ }
-+
-+ return fclk;
-+}
-+
-+static unsigned long calc_fclk(u16 width, u16 height,
-+ u16 out_width, u16 out_height,
-+ enum omap_color_mode color_mode, bool five_taps)
-+{
-+ unsigned int hf, vf;
-+
-+ if (five_taps)
-+ return calc_fclk_five_taps(width, height,
-+ out_width, out_height, color_mode);
-+
-+ /*
-+ * FIXME how to determine the 'A' factor
-+ * for the no downscaling case ?
-+ */
-+
-+ if (width > 3 * out_width)
-+ hf = 4;
-+ else if (width > 2 * out_width)
-+ hf = 3;
-+ else if (width > out_width)
-+ hf = 2;
-+ else
-+ hf = 1;
-+
-+ if (height > out_height)
-+ vf = 2;
-+ else
-+ vf = 1;
-+
-+ /* FIXME venc pclk? */
-+ return dispc_pclk_rate() * vf * hf;
-+}
-+
- static int _dispc_setup_plane(enum omap_plane plane,
- enum omap_channel channel_out,
- u32 paddr, u16 screen_width,
-@@ -1294,7 +1360,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
- u8 rotation, int mirror)
- {
- const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
-- bool five_taps = height > out_height * 2;
-+ bool five_taps = 0;
- bool fieldmode = 0;
- int cconv = 0;
- unsigned offset0, offset1;
-@@ -1323,8 +1389,8 @@ static int _dispc_setup_plane(enum omap_plane plane,
- }
- } else {
- /* video plane */
-- if (width > (2048 >> five_taps))
-- return -EINVAL;
-+
-+ unsigned long fclk;
-
- if (out_width < width / maxdownscale ||
- out_width > width * 8)
-@@ -1356,6 +1422,30 @@ static int _dispc_setup_plane(enum omap_plane plane,
- default:
- return -EINVAL;
- }
-+
-+ /* Must use 5-tap filter? */
-+ five_taps = height > out_height * 2;
-+
-+ /* Try to use 5-tap filter whenever possible. */
-+ if (cpu_is_omap34xx() && !five_taps &&
-+ height > out_height && width <= 1024) {
-+ fclk = calc_fclk_five_taps(width, height,
-+ out_width, out_height, color_mode);
-+ if (fclk <= dispc_fclk_rate())
-+ five_taps = true;
-+ }
-+
-+ if (width > (2048 >> five_taps))
-+ return -EINVAL;
-+
-+ fclk = calc_fclk(width, height, out_width, out_height,
-+ color_mode, five_taps);
-+
-+ DSSDBG("required fclk rate = %lu Hz\n", fclk);
-+ DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
-+
-+ if (fclk > dispc_fclk_rate())
-+ return -EINVAL;
- }
-
- if (ilace && height >= out_height)
-@@ -1399,7 +1489,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
- if (plane != OMAP_DSS_GFX) {
- _dispc_set_scaling(plane, width, height,
- out_width, out_height,
-- ilace);
-+ ilace, five_taps);
- _dispc_set_vid_size(plane, out_width, out_height);
- _dispc_set_vid_color_conv(plane, cconv);
- }
---
-1.6.2.4
-
+++ /dev/null
-From 9f8f1613253656f155b3844c8255a560f86e0acd Mon Sep 17 00:00:00 2001
-From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
-Date: Mon, 6 Apr 2009 17:32:05 +0200
-Subject: [PATCH 20/69] DSS2: Check scaling limits against proper values
-MIME-Version: 1.0
-Content-Type: text/plain; charset=utf-8
-Content-Transfer-Encoding: 8bit
-
-Move the ilace and fieldmode related height adjustments to be performed
-before checking the scaling limits.
-
-Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
----
- drivers/video/omap2/dss/dispc.c | 31 ++++++++++++++++---------------
- 1 files changed, 16 insertions(+), 15 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-index 61861d8..ae7be3d 100644
---- a/drivers/video/omap2/dss/dispc.c
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -1366,10 +1366,25 @@ static int _dispc_setup_plane(enum omap_plane plane,
- unsigned offset0, offset1;
- s32 row_inc;
- s32 pix_inc;
-+ u16 frame_height = height;
-
- if (paddr == 0)
- return -EINVAL;
-
-+ if (ilace && height >= out_height)
-+ fieldmode = 1;
-+
-+ if (ilace) {
-+ if (fieldmode)
-+ height /= 2;
-+ pos_y /= 2;
-+ out_height /= 2;
-+
-+ DSSDBG("adjusting for ilace: height %d, pos_y %d, "
-+ "out_height %d\n",
-+ height, pos_y, out_height);
-+ }
-+
- if (plane == OMAP_DSS_GFX) {
- if (width != out_width || height != out_height)
- return -EINVAL;
-@@ -1448,28 +1463,14 @@ static int _dispc_setup_plane(enum omap_plane plane,
- return -EINVAL;
- }
-
-- if (ilace && height >= out_height)
-- fieldmode = 1;
--
- calc_rotation_offset(rotation, mirror,
-- screen_width, width, height, color_mode,
-+ screen_width, width, frame_height, color_mode,
- fieldmode,
- &offset0, &offset1, &row_inc, &pix_inc);
-
- DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
- offset0, offset1, row_inc, pix_inc);
-
-- if (ilace) {
-- if (fieldmode)
-- height /= 2;
-- pos_y /= 2;
-- out_height /= 2;
--
-- DSSDBG("adjusting for ilace: height %d, pos_y %d, "
-- "out_height %d\n",
-- height, pos_y, out_height);
-- }
--
- _dispc_set_channel_out(plane, channel_out);
- _dispc_set_color_mode(plane, color_mode);
-
---
-1.6.2.4
-
+++ /dev/null
-From c5e71be877e71c7df329205307e830f158c403bf Mon Sep 17 00:00:00 2001
-From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
-Date: Mon, 6 Apr 2009 17:32:06 +0200
-Subject: [PATCH 21/69] DSS2: Add venc register dump
-MIME-Version: 1.0
-Content-Type: text/plain; charset=utf-8
-Content-Transfer-Encoding: 8bit
-
-Add a new file to debugfs to dump the VENC registers. The function
-prototype was already there but the implementation was missing.
-
-Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
----
- drivers/video/omap2/dss/venc.c | 55 ++++++++++++++++++++++++++++++++++++++++
- 1 files changed, 55 insertions(+), 0 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c
-index aceed9f..b655df4 100644
---- a/drivers/video/omap2/dss/venc.c
-+++ b/drivers/video/omap2/dss/venc.c
-@@ -30,6 +30,7 @@
- #include <linux/completion.h>
- #include <linux/delay.h>
- #include <linux/string.h>
-+#include <linux/seq_file.h>
-
- #include <mach/display.h>
- #include <mach/cpu.h>
-@@ -81,6 +82,7 @@
- #define VENC_TVDETGP_INT_START_STOP_Y 0xB4
- #define VENC_GEN_CTRL 0xB8
- #define VENC_OUTPUT_CONTROL 0xC4
-+#define VENC_OUTPUT_TEST 0xC8
- #define VENC_DAC_B__DAC_C 0xC8
-
- struct venc_config {
-@@ -598,3 +600,56 @@ void venc_init_display(struct omap_display *display)
- display->set_timings = venc_set_timings;
- display->check_timings = venc_check_timings;
- }
-+
-+void venc_dump_regs(struct seq_file *s)
-+{
-+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
-+
-+ venc_enable_clocks(1);
-+
-+ DUMPREG(VENC_F_CONTROL);
-+ DUMPREG(VENC_VIDOUT_CTRL);
-+ DUMPREG(VENC_SYNC_CTRL);
-+ DUMPREG(VENC_LLEN);
-+ DUMPREG(VENC_FLENS);
-+ DUMPREG(VENC_HFLTR_CTRL);
-+ DUMPREG(VENC_CC_CARR_WSS_CARR);
-+ DUMPREG(VENC_C_PHASE);
-+ DUMPREG(VENC_GAIN_U);
-+ DUMPREG(VENC_GAIN_V);
-+ DUMPREG(VENC_GAIN_Y);
-+ DUMPREG(VENC_BLACK_LEVEL);
-+ DUMPREG(VENC_BLANK_LEVEL);
-+ DUMPREG(VENC_X_COLOR);
-+ DUMPREG(VENC_M_CONTROL);
-+ DUMPREG(VENC_BSTAMP_WSS_DATA);
-+ DUMPREG(VENC_S_CARR);
-+ DUMPREG(VENC_LINE21);
-+ DUMPREG(VENC_LN_SEL);
-+ DUMPREG(VENC_L21__WC_CTL);
-+ DUMPREG(VENC_HTRIGGER_VTRIGGER);
-+ DUMPREG(VENC_SAVID__EAVID);
-+ DUMPREG(VENC_FLEN__FAL);
-+ DUMPREG(VENC_LAL__PHASE_RESET);
-+ DUMPREG(VENC_HS_INT_START_STOP_X);
-+ DUMPREG(VENC_HS_EXT_START_STOP_X);
-+ DUMPREG(VENC_VS_INT_START_X);
-+ DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
-+ DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
-+ DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
-+ DUMPREG(VENC_VS_EXT_STOP_Y);
-+ DUMPREG(VENC_AVID_START_STOP_X);
-+ DUMPREG(VENC_AVID_START_STOP_Y);
-+ DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
-+ DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
-+ DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
-+ DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
-+ DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
-+ DUMPREG(VENC_GEN_CTRL);
-+ DUMPREG(VENC_OUTPUT_CONTROL);
-+ DUMPREG(VENC_OUTPUT_TEST);
-+
-+ venc_enable_clocks(0);
-+
-+#undef DUMPREG
-+}
---
-1.6.2.4
-
+++ /dev/null
-From facfd479bb6efad76eec1e74048cb7a31da7287d Mon Sep 17 00:00:00 2001
-From: Imre Deak <imre.deak@nokia.com>
-Date: Mon, 6 Apr 2009 22:26:04 +0200
-Subject: [PATCH 22/69] DSS2: FB: remove unused var warning
-
-Signed-off-by: Imre Deak <imre.deak@nokia.com>
----
- drivers/video/omap2/omapfb/omapfb-main.c | 2 ++
- 1 files changed, 2 insertions(+), 0 deletions(-)
-
-diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
-index afe40a9..12ce0c3 100644
---- a/drivers/video/omap2/omapfb/omapfb-main.c
-+++ b/drivers/video/omap2/omapfb/omapfb-main.c
-@@ -1246,7 +1246,9 @@ static int omapfb_alloc_fbmem_display(struct fb_info *fbi, unsigned long size,
- display->get_resolution(display, &w, &h);
-
- if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
-+#ifdef DEBUG
- int oldw = w, oldh = h;
-+#endif
-
- omap_vrfb_adjust_size(&w, &h, bytespp);
-
---
-1.6.2.4
-
+++ /dev/null
-From c02b843c2732bc7b15a3e35b5dd715d68225bbd1 Mon Sep 17 00:00:00 2001
-From: Imre Deak <imre.deak@nokia.com>
-Date: Wed, 8 Apr 2009 12:51:46 +0200
-Subject: [PATCH 23/69] DSS2: pass the default FB color format through board info
-
-Add a field to the FB memory region platform data, so that board
-init code can pass a default color format to the driver. Set this
-format as an initial setting for the given FB.
-
-This is needed for an upcoming patch that adds detection of the
-color format set by the bootloader.
-
-Signed-off-by: Imre Deak <imre.deak@nokia.com>
----
- drivers/video/omap2/omapfb/omapfb-main.c | 121 +++++++++++++++++++++++++++---
- drivers/video/omap2/omapfb/omapfb.h | 2 +
- include/linux/omapfb.h | 5 +
- 3 files changed, 117 insertions(+), 11 deletions(-)
-
-diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
-index 12ce0c3..67c67c2 100644
---- a/drivers/video/omap2/omapfb/omapfb-main.c
-+++ b/drivers/video/omap2/omapfb/omapfb-main.c
-@@ -370,6 +370,21 @@ static enum omap_color_mode fb_mode_to_dss_mode(struct fb_var_screeninfo *var)
- return -EINVAL;
- }
-
-+static int dss_mode_to_fb_mode(enum omap_color_mode dssmode,
-+ struct fb_var_screeninfo *var)
-+{
-+ int i;
-+
-+ for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) {
-+ struct omapfb_colormode *mode = &omapfb_colormodes[i];
-+ if (dssmode == mode->dssmode) {
-+ assign_colormode_to_var(var, mode);
-+ return 0;
-+ }
-+ }
-+ return -ENOENT;
-+}
-+
- void set_fb_fix(struct fb_info *fbi)
- {
- struct fb_fix_screeninfo *fix = &fbi->fix;
-@@ -1267,6 +1282,60 @@ static int omapfb_alloc_fbmem_display(struct fb_info *fbi, unsigned long size,
- return omapfb_alloc_fbmem(fbi, size, paddr);
- }
-
-+static enum omap_color_mode fb_format_to_dss_mode(enum omapfb_color_format format)
-+{
-+ enum omap_color_mode mode;
-+
-+ switch (format) {
-+ case OMAPFB_COLOR_RGB565:
-+ mode = OMAP_DSS_COLOR_RGB16;
-+ break;
-+ case OMAPFB_COLOR_YUV422:
-+ mode = OMAP_DSS_COLOR_YUV2;
-+ break;
-+ case OMAPFB_COLOR_CLUT_8BPP:
-+ mode = OMAP_DSS_COLOR_CLUT8;
-+ break;
-+ case OMAPFB_COLOR_CLUT_4BPP:
-+ mode = OMAP_DSS_COLOR_CLUT4;
-+ break;
-+ case OMAPFB_COLOR_CLUT_2BPP:
-+ mode = OMAP_DSS_COLOR_CLUT2;
-+ break;
-+ case OMAPFB_COLOR_CLUT_1BPP:
-+ mode = OMAP_DSS_COLOR_CLUT1;
-+ break;
-+ case OMAPFB_COLOR_RGB444:
-+ mode = OMAP_DSS_COLOR_RGB12U;
-+ break;
-+ case OMAPFB_COLOR_YUY422:
-+ mode = OMAP_DSS_COLOR_UYVY;
-+ break;
-+ case OMAPFB_COLOR_ARGB16:
-+ mode = OMAP_DSS_COLOR_ARGB16;
-+ break;
-+ case OMAPFB_COLOR_RGB24U:
-+ mode = OMAP_DSS_COLOR_RGB24U;
-+ break;
-+ case OMAPFB_COLOR_RGB24P:
-+ mode = OMAP_DSS_COLOR_RGB24P;
-+ break;
-+ case OMAPFB_COLOR_ARGB32:
-+ mode = OMAP_DSS_COLOR_ARGB32;
-+ break;
-+ case OMAPFB_COLOR_RGBA32:
-+ mode = OMAP_DSS_COLOR_RGBA32;
-+ break;
-+ case OMAPFB_COLOR_RGBX32:
-+ mode = OMAP_DSS_COLOR_RGBX32;
-+ break;
-+ default:
-+ mode = -EINVAL;
-+ }
-+
-+ return mode;
-+}
-+
- static int omapfb_parse_vram_param(const char *param, int max_entries,
- unsigned long *sizes, unsigned long *paddrs)
- {
-@@ -1483,9 +1552,36 @@ int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi)
- }
-
- var->nonstd = 0;
-+ var->bits_per_pixel = 0;
-
- var->rotate = ofbi->rotation;
-
-+ /*
-+ * Check if there is a default color format set in the board file,
-+ * and use this format instead the default deducted from the
-+ * display bpp.
-+ */
-+ if (fbdev->dev->platform_data) {
-+ struct omapfb_platform_data *opd;
-+ int id = ofbi->id;
-+
-+ opd = fbdev->dev->platform_data;
-+ if (opd->mem_desc.region[id].format_used) {
-+ enum omap_color_mode mode;
-+ enum omapfb_color_format format;
-+
-+ format = opd->mem_desc.region[id].format;
-+ mode = fb_format_to_dss_mode(format);
-+ if (mode < 0) {
-+ r = mode;
-+ goto err;
-+ }
-+ r = dss_mode_to_fb_mode(mode, var);
-+ if (r < 0)
-+ goto err;
-+ }
-+ }
-+
- if (display) {
- u16 w, h;
- display->get_resolution(display, &w, &h);
-@@ -1502,16 +1598,18 @@ int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi)
- var->xres_virtual = var->xres;
- var->yres_virtual = var->yres;
-
-- switch (display->get_recommended_bpp(display)) {
-- case 16:
-- var->bits_per_pixel = 16;
-- break;
-- case 24:
-- var->bits_per_pixel = 32;
-- break;
-- default:
-- dev_err(fbdev->dev, "illegal display bpp\n");
-- return -EINVAL;
-+ if (!var->bits_per_pixel) {
-+ switch (display->get_recommended_bpp(display)) {
-+ case 16:
-+ var->bits_per_pixel = 16;
-+ break;
-+ case 24:
-+ var->bits_per_pixel = 32;
-+ break;
-+ default:
-+ dev_err(fbdev->dev, "illegal display bpp\n");
-+ return -EINVAL;
-+ }
- }
- } else {
- /* if there's no display, let's just guess some basic values */
-@@ -1519,7 +1617,8 @@ int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi)
- var->yres = 240;
- var->xres_virtual = var->xres;
- var->yres_virtual = var->yres;
-- var->bits_per_pixel = 16;
-+ if (!var->bits_per_pixel)
-+ var->bits_per_pixel = 16;
- }
-
- r = check_fb_var(fbi, var);
-diff --git a/drivers/video/omap2/omapfb/omapfb.h b/drivers/video/omap2/omapfb/omapfb.h
-index 65e9e6e..2607def 100644
---- a/drivers/video/omap2/omapfb/omapfb.h
-+++ b/drivers/video/omap2/omapfb/omapfb.h
-@@ -27,6 +27,8 @@
- #define DEBUG
- #endif
-
-+#include <mach/display.h>
-+
- #ifdef DEBUG
- extern unsigned int omapfb_debug;
- #define DBG(format, ...) \
-diff --git a/include/linux/omapfb.h b/include/linux/omapfb.h
-index 96190b2..7a34f22 100644
---- a/include/linux/omapfb.h
-+++ b/include/linux/omapfb.h
-@@ -298,6 +298,11 @@ struct omapfb_mem_region {
- void __iomem *vaddr;
- unsigned long size;
- u8 type; /* OMAPFB_PLANE_MEM_* */
-+ enum omapfb_color_format format;/* OMAPFB_COLOR_* */
-+ unsigned format_used:1; /* Must be set when format is set.
-+ * Needed b/c of the badly chosen 0
-+ * base for OMAPFB_COLOR_* values
-+ */
- unsigned alloc:1; /* allocated by the driver */
- unsigned map:1; /* kernel mapped by the driver */
- };
---
-1.6.2.4
-
+++ /dev/null
-From 2710416c43572652cb5355a5eaf68038c95659e8 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Thu, 9 Apr 2009 12:10:46 +0300
-Subject: [PATCH 24/69] DSS2: Beagle: Use gpio_set_value
-
----
- arch/arm/mach-omap2/board-omap3beagle.c | 10 +++++++---
- 1 files changed, 7 insertions(+), 3 deletions(-)
-
-diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
-index b67e7a5..8c1961d 100644
---- a/arch/arm/mach-omap2/board-omap3beagle.c
-+++ b/arch/arm/mach-omap2/board-omap3beagle.c
-@@ -372,7 +372,7 @@ static struct platform_device keys_gpio = {
- static int beagle_enable_dvi(struct omap_display *display)
- {
- if (display->hw_config.panel_reset_gpio != -1)
-- gpio_direction_output(display->hw_config.panel_reset_gpio, 1);
-+ gpio_set_value(display->hw_config.panel_reset_gpio, 1);
-
- return 0;
- }
-@@ -380,7 +380,7 @@ static int beagle_enable_dvi(struct omap_display *display)
- static void beagle_disable_dvi(struct omap_display *display)
- {
- if (display->hw_config.panel_reset_gpio != -1)
-- gpio_direction_output(display->hw_config.panel_reset_gpio, 0);
-+ gpio_set_value(display->hw_config.panel_reset_gpio, 0);
- }
-
- static struct omap_dss_display_config beagle_display_data_dvi = {
-@@ -445,8 +445,12 @@ static void __init beagle_display_init(void)
- int r;
-
- r = gpio_request(beagle_display_data_dvi.panel_reset_gpio, "DVI reset");
-- if (r < 0)
-+ if (r < 0) {
- printk(KERN_ERR "Unable to get DVI reset GPIO\n");
-+ return;
-+ }
-+
-+ gpio_direction_output(beagle_display_data_dvi.panel_reset_gpio, 0);
- }
-
- static struct omap_board_config_kernel omap3_beagle_config[] __initdata = {
---
-1.6.2.4
-
+++ /dev/null
-From 990f3160d33361c135ee72e91f202e05a8c378fc Mon Sep 17 00:00:00 2001
-From: Hardik Shah <hardik.shah@ti.com>
-Date: Mon, 13 Apr 2009 18:50:24 +0530
-Subject: [PATCH 25/69] DSS2: VRFB: Macro for calculating base address of the VRFB context was faulty
-
-Signed-off-by: Hardik Shah <hardik.shah@ti.com>
----
- arch/arm/plat-omap/vrfb.c | 4 ++--
- 1 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
-index 7e0f8fc..d68065f 100644
---- a/arch/arm/plat-omap/vrfb.c
-+++ b/arch/arm/plat-omap/vrfb.c
-@@ -16,8 +16,8 @@
-
- #define SMS_ROT_VIRT_BASE(context, rot) \
- (((context >= 4) ? 0xD0000000 : 0x70000000) \
-- | 0x4000000 * (context) \
-- | 0x1000000 * (rot))
-+ + (0x4000000 * (context)) \
-+ + (0x1000000 * (rot)))
-
- #define OMAP_VRFB_SIZE (2048 * 2048 * 4)
-
---
-1.6.2.4
-
+++ /dev/null
-From a1e8018c0806a1a0579eda4b93b7d6764a2ff643 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Wed, 15 Apr 2009 14:06:54 +0300
-Subject: [PATCH 26/69] DSS2: DSI: sidlemode to noidle while sending frame
-
-DISPC interrupts are not wake-up capable. Smart-idle in DISPC_SIDLEMODE
-causes DSS interface to go to idle at the end of the frame, and the
-FRAMEDONE interrupt is then delayed until something wakes up the DSS
-interface.
-
-So we set SIDLEMODE to no-idle when we start sending the frame, and
-set it back to smart-idle after receiving FRAMEDONE.
----
- drivers/video/omap2/dss/dispc.c | 10 ++++++++++
- drivers/video/omap2/dss/dsi.c | 4 ++++
- drivers/video/omap2/dss/dss.h | 3 +++
- 3 files changed, 17 insertions(+), 0 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-index ae7be3d..16c68b8 100644
---- a/drivers/video/omap2/dss/dispc.c
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -2791,6 +2791,16 @@ static void _omap_dispc_initialize_irq(void)
- omap_dispc_set_irqs();
- }
-
-+void dispc_enable_sidle(void)
-+{
-+ REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
-+}
-+
-+void dispc_disable_sidle(void)
-+{
-+ REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
-+}
-+
- static void _omap_dispc_initial_config(void)
- {
- u32 l;
-diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
-index 66ac6ea..50af925 100644
---- a/drivers/video/omap2/dss/dsi.c
-+++ b/drivers/video/omap2/dss/dsi.c
-@@ -2665,6 +2665,8 @@ static void dsi_update_screen_dispc(struct omap_display *display,
- l = FLD_MOD(l, 1, 31, 31); /* TE_START */
- dsi_write_reg(DSI_VC_TE(1), l);
-
-+ dispc_disable_sidle();
-+
- dispc_enable_lcd_out(1);
-
- if (dsi.use_te)
-@@ -2678,6 +2680,8 @@ static void framedone_callback(void *data, u32 mask)
- return;
- }
-
-+ dispc_enable_sidle();
-+
- dsi.framedone_scheduled = 1;
-
- /* We get FRAMEDONE when DISPC has finished sending pixels and turns
-diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
-index 0be42b6..d0917a8 100644
---- a/drivers/video/omap2/dss/dss.h
-+++ b/drivers/video/omap2/dss/dss.h
-@@ -244,6 +244,9 @@ void dispc_fake_vsync_irq(void);
- void dispc_save_context(void);
- void dispc_restore_context(void);
-
-+void dispc_enable_sidle(void);
-+void dispc_disable_sidle(void);
-+
- void dispc_lcd_enable_signal_polarity(bool act_high);
- void dispc_lcd_enable_signal(bool enable);
- void dispc_pck_free_enable(bool enable);
---
-1.6.2.4
-
+++ /dev/null
-From 77e848eeba461e9b55b09d39fd0d640caea13e19 Mon Sep 17 00:00:00 2001
-From: Hardik Shah <hardik.shah@ti.com>
-Date: Thu, 9 Apr 2009 12:09:44 +0530
-Subject: [PATCH 27/69] DSS2: VRFB rotation and mirroring implemented.
-
-DSS2 modified to accept the rotation_type input
-to get the dma or VRFB rotation.
-
-DSS2: VRFB: Changed to pass DSS mode to vrfb_setup instead of Bpp.
-
-VRFB size registers requires the width to be halved when the
-mode is YUV or UYVY. So modifed to pass the mode to omap_vrfb_setup
-function.
-
-Code added by Tim Yamin for few bug fixes
-
-Signed-off-by: Tim Yamin <plasm@roo.me.uk>
-Signed-off-by: Hardik Shah <hardik.shah@ti.com>
----
- arch/arm/plat-omap/include/mach/display.h | 6 ++
- arch/arm/plat-omap/include/mach/vrfb.h | 3 +-
- arch/arm/plat-omap/vrfb.c | 36 +++++++++-
- drivers/video/omap2/dss/dispc.c | 109 +++++++++++++++++++++++++++--
- drivers/video/omap2/dss/dss.h | 1 +
- drivers/video/omap2/dss/manager.c | 1 +
- 6 files changed, 144 insertions(+), 12 deletions(-)
-
-diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
-index 6b702c7..b0a6272 100644
---- a/arch/arm/plat-omap/include/mach/display.h
-+++ b/arch/arm/plat-omap/include/mach/display.h
-@@ -341,6 +341,11 @@ enum omap_dss_overlay_managers {
-
- struct omap_overlay_manager;
-
-+enum omap_dss_rotation_type {
-+ OMAP_DSS_ROT_DMA = 0,
-+ OMAP_DSS_ROT_VRFB = 1,
-+};
-+
- struct omap_overlay_info {
- bool enabled;
-
-@@ -351,6 +356,7 @@ struct omap_overlay_info {
- u16 height;
- enum omap_color_mode color_mode;
- u8 rotation;
-+ enum omap_dss_rotation_type rotation_type;
- bool mirror;
-
- u16 pos_x;
-diff --git a/arch/arm/plat-omap/include/mach/vrfb.h b/arch/arm/plat-omap/include/mach/vrfb.h
-index 2047862..12c7fab 100644
---- a/arch/arm/plat-omap/include/mach/vrfb.h
-+++ b/arch/arm/plat-omap/include/mach/vrfb.h
-@@ -24,6 +24,7 @@
- #ifndef __VRFB_H
- #define __VRFB_H
-
-+#include <mach/display.h>
- #define OMAP_VRFB_LINE_LEN 2048
-
- struct vrfb
-@@ -42,6 +43,6 @@ extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
- u8 bytespp);
- extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
- u16 width, u16 height,
-- u8 bytespp);
-+ enum omap_color_mode color_mode);
-
- #endif /* __VRFB_H */
-diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
-index d68065f..2f08f6d 100644
---- a/arch/arm/plat-omap/vrfb.c
-+++ b/arch/arm/plat-omap/vrfb.c
-@@ -5,7 +5,6 @@
-
- #include <mach/io.h>
- #include <mach/vrfb.h>
--
- /*#define DEBUG*/
-
- #ifdef DEBUG
-@@ -50,19 +49,48 @@ EXPORT_SYMBOL(omap_vrfb_adjust_size);
-
- void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
- u16 width, u16 height,
-- u8 bytespp)
-+ enum omap_color_mode color_mode)
- {
- unsigned pixel_size_exp;
- u16 vrfb_width;
- u16 vrfb_height;
- u8 ctx = vrfb->context;
-+ u8 bytespp;
-
- DBG("omapfb_set_vrfb(%d, %lx, %dx%d, %d)\n", ctx, paddr,
- width, height, bytespp);
-
-- if (bytespp == 4)
-+ switch (color_mode) {
-+ case OMAP_DSS_COLOR_RGB16:
-+ case OMAP_DSS_COLOR_ARGB16:
-+ bytespp = 2;
-+ break;
-+
-+ case OMAP_DSS_COLOR_RGB24P:
-+ bytespp = 3;
-+ break;
-+
-+ case OMAP_DSS_COLOR_RGB24U:
-+ case OMAP_DSS_COLOR_ARGB32:
-+ case OMAP_DSS_COLOR_RGBA32:
-+ case OMAP_DSS_COLOR_RGBX32:
-+ case OMAP_DSS_COLOR_YUV2:
-+ case OMAP_DSS_COLOR_UYVY:
-+ bytespp = 4;
-+ break;
-+
-+ default:
-+ BUG();
-+ return;
-+ }
-+
-+ if (color_mode == OMAP_DSS_COLOR_YUV2 ||
-+ color_mode == OMAP_DSS_COLOR_UYVY)
-+ width >>= 1;
-+
-+ if (bytespp == 4) {
- pixel_size_exp = 2;
-- else if (bytespp == 2)
-+ } else if (bytespp == 2)
- pixel_size_exp = 1;
- else
- BUG();
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-index 16c68b8..23a8155 100644
---- a/drivers/video/omap2/dss/dispc.c
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -1106,7 +1106,7 @@ static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
- case 0: vidrot = 0; break;
- case 1: vidrot = 1; break;
- case 2: vidrot = 2; break;
-- case 3: vidrot = 1; break;
-+ case 3: vidrot = 3; break;
- }
- }
-
-@@ -1134,7 +1134,92 @@ static s32 pixinc(int pixels, u8 ps)
- BUG();
- }
-
--static void calc_rotation_offset(u8 rotation, bool mirror,
-+static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
-+ u16 screen_width,
-+ u16 width, u16 height,
-+ enum omap_color_mode color_mode, bool fieldmode,
-+ unsigned *offset0, unsigned *offset1,
-+ s32 *row_inc, s32 *pix_inc)
-+{
-+ u8 ps;
-+
-+ switch (color_mode) {
-+ case OMAP_DSS_COLOR_RGB16:
-+ case OMAP_DSS_COLOR_ARGB16:
-+ ps = 2;
-+ break;
-+
-+ case OMAP_DSS_COLOR_RGB24P:
-+ ps = 3;
-+ break;
-+
-+ case OMAP_DSS_COLOR_RGB24U:
-+ case OMAP_DSS_COLOR_ARGB32:
-+ case OMAP_DSS_COLOR_RGBA32:
-+ case OMAP_DSS_COLOR_RGBX32:
-+ case OMAP_DSS_COLOR_YUV2:
-+ case OMAP_DSS_COLOR_UYVY:
-+ ps = 4;
-+ break;
-+
-+ default:
-+ BUG();
-+ return;
-+ }
-+
-+ DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
-+ width, height);
-+ switch (rotation + mirror * 4) {
-+ case 0:
-+ case 2:
-+ /*
-+ * If the pixel format is YUV or UYVY divide the width
-+ * of the image by 2 for 0 and 180 degree rotation.
-+ */
-+ if (color_mode == OMAP_DSS_COLOR_YUV2 ||
-+ color_mode == OMAP_DSS_COLOR_UYVY)
-+ width = width >> 1;
-+ case 1:
-+ case 3:
-+ *offset0 = 0;
-+ if (fieldmode)
-+ *offset1 = screen_width * ps;
-+ else
-+ *offset1 = 0;
-+
-+ *row_inc = pixinc(1 + (screen_width - width) +
-+ (fieldmode ? screen_width : 0),
-+ ps);
-+ *pix_inc = pixinc(1, ps);
-+ break;
-+
-+ case 4:
-+ case 6:
-+ /* If the pixel format is YUV or UYVY divide the width
-+ * of the image by 2 for 0 degree and 180 degree
-+ */
-+ if (color_mode == OMAP_DSS_COLOR_YUV2 ||
-+ color_mode == OMAP_DSS_COLOR_UYVY)
-+ width = width >> 1;
-+ case 5:
-+ case 7:
-+ *offset0 = 0;
-+ if (fieldmode)
-+ *offset1 = screen_width * ps;
-+ else
-+ *offset1 = 0;
-+ *row_inc = pixinc(1 - (screen_width + width) -
-+ (fieldmode ? screen_width : 0),
-+ ps);
-+ *pix_inc = pixinc(1, ps);
-+ break;
-+
-+ default:
-+ BUG();
-+ }
-+}
-+
-+static void calc_dma_rotation_offset(u8 rotation, bool mirror,
- u16 screen_width,
- u16 width, u16 height,
- enum omap_color_mode color_mode, bool fieldmode,
-@@ -1357,6 +1442,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
- u16 out_width, u16 out_height,
- enum omap_color_mode color_mode,
- bool ilace,
-+ enum omap_dss_rotation_type rotation_type,
- u8 rotation, int mirror)
- {
- const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
-@@ -1463,10 +1549,16 @@ static int _dispc_setup_plane(enum omap_plane plane,
- return -EINVAL;
- }
-
-- calc_rotation_offset(rotation, mirror,
-- screen_width, width, frame_height, color_mode,
-- fieldmode,
-- &offset0, &offset1, &row_inc, &pix_inc);
-+ if (rotation_type == OMAP_DSS_ROT_DMA)
-+ calc_dma_rotation_offset(rotation, mirror,
-+ screen_width, width, frame_height, color_mode,
-+ fieldmode,
-+ &offset0, &offset1, &row_inc, &pix_inc);
-+ else
-+ calc_vrfb_rotation_offset(rotation, mirror,
-+ screen_width, width, frame_height, color_mode,
-+ fieldmode,
-+ &offset0, &offset1, &row_inc, &pix_inc);
-
- DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
- offset0, offset1, row_inc, pix_inc);
-@@ -2889,6 +2981,7 @@ int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
- u16 out_width, u16 out_height,
- enum omap_color_mode color_mode,
- bool ilace,
-+ enum omap_dss_rotation_type rotation_type,
- u8 rotation, bool mirror)
- {
- int r = 0;
-@@ -2909,6 +3002,7 @@ int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
- width, height,
- out_width, out_height,
- color_mode, ilace,
-+ rotation_type,
- rotation, mirror);
-
- enable_clocks(0);
-@@ -3122,7 +3216,8 @@ void dispc_setup_partial_planes(struct omap_display *display,
- pw, ph,
- pow, poh,
- pi->color_mode, 0,
-- pi->rotation, // XXX rotation probably wrong
-+ pi->rotation_type,
-+ pi->rotation,
- pi->mirror);
-
- dispc_enable_plane(ovl->id, 1);
-diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
-index d0917a8..584dce6 100644
---- a/drivers/video/omap2/dss/dss.h
-+++ b/drivers/video/omap2/dss/dss.h
-@@ -272,6 +272,7 @@ int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
- u16 out_width, u16 out_height,
- enum omap_color_mode color_mode,
- bool ilace,
-+ enum omap_dss_rotation_type rotation_type,
- u8 rotation, bool mirror);
-
- void dispc_go(enum omap_channel channel);
-diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
-index b0fee80..8ca0bbb 100644
---- a/drivers/video/omap2/dss/manager.c
-+++ b/drivers/video/omap2/dss/manager.c
-@@ -395,6 +395,7 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
- outh,
- ovl->info.color_mode,
- ilace,
-+ ovl->info.rotation_type,
- ovl->info.rotation,
- ovl->info.mirror);
-
---
-1.6.2.4
-
+++ /dev/null
-From c09f1a0642fd58a1b081594ea36dfd1bf71aec52 Mon Sep 17 00:00:00 2001
-From: Hardik Shah <hardik.shah@ti.com>
-Date: Thu, 9 Apr 2009 12:13:07 +0530
-Subject: [PATCH 28/69] DSS2: OMAPFB: Added support for the YUV VRFB rotation and mirroring.
-
-DSS2 now requires roatation_type to be specified by driver.
-Added support for that.
-DSS2 OMAPFB: Modified to pass the dss mode to omap_vrfb_setup function.
-
-VRFB size register requires the width to be halved when the
-mode is YUV or UYVY. So VRFB is modifed to pass the mode to omap_vrfb_setup
-function.
-
-Few changes done by Tim Yamin
-Signed-off-by: Tim Yamin <plasm@roo.me.uk>
-Signed-off-by: Hardik Shah <hardik.shah@ti.com>
----
- arch/arm/plat-omap/vrfb.c | 4 +-
- drivers/video/omap2/omapfb/omapfb-main.c | 59 ++++++++++++++----------------
- drivers/video/omap2/omapfb/omapfb.h | 7 +---
- 3 files changed, 30 insertions(+), 40 deletions(-)
-
-diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
-index 2f08f6d..2ae0d68 100644
---- a/arch/arm/plat-omap/vrfb.c
-+++ b/arch/arm/plat-omap/vrfb.c
-@@ -88,9 +88,9 @@ void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
- color_mode == OMAP_DSS_COLOR_UYVY)
- width >>= 1;
-
-- if (bytespp == 4) {
-+ if (bytespp == 4)
- pixel_size_exp = 2;
-- } else if (bytespp == 2)
-+ else if (bytespp == 2)
- pixel_size_exp = 1;
- else
- BUG();
-diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
-index 67c67c2..57f5900 100644
---- a/drivers/video/omap2/omapfb/omapfb-main.c
-+++ b/drivers/video/omap2/omapfb/omapfb-main.c
-@@ -176,15 +176,9 @@ static unsigned omapfb_get_vrfb_offset(struct omapfb_info *ofbi, int rot)
-
- static u32 omapfb_get_region_rot_paddr(struct omapfb_info *ofbi)
- {
-- if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
-- unsigned offset;
-- int rot;
--
-- rot = ofbi->rotation;
--
-- offset = omapfb_get_vrfb_offset(ofbi, rot);
--
-- return ofbi->region.vrfb.paddr[rot] + offset;
-+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
-+ return ofbi->region.vrfb.paddr[ofbi->rotation]
-+ + omapfb_get_vrfb_offset(ofbi, ofbi->rotation);
- } else {
- return ofbi->region.paddr;
- }
-@@ -192,7 +186,7 @@ static u32 omapfb_get_region_rot_paddr(struct omapfb_info *ofbi)
-
- u32 omapfb_get_region_paddr(struct omapfb_info *ofbi)
- {
-- if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
-+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
- return ofbi->region.vrfb.paddr[0];
- else
- return ofbi->region.paddr;
-@@ -200,7 +194,7 @@ u32 omapfb_get_region_paddr(struct omapfb_info *ofbi)
-
- void __iomem *omapfb_get_region_vaddr(struct omapfb_info *ofbi)
- {
-- if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
-+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
- return ofbi->region.vrfb.vaddr[0];
- else
- return ofbi->region.vaddr;
-@@ -398,7 +392,7 @@ void set_fb_fix(struct fb_info *fbi)
- fbi->screen_base = (char __iomem *)omapfb_get_region_vaddr(ofbi);
-
- /* used by mmap in fbmem.c */
-- if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
-+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
- fix->line_length =
- (OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 3;
- else
-@@ -434,11 +428,14 @@ void set_fb_fix(struct fb_info *fbi)
- fix->xpanstep = 1;
- fix->ypanstep = 1;
-
-- if (rg->size) {
-- if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
-- omap_vrfb_setup(&rg->vrfb, rg->paddr,
-- var->xres_virtual, var->yres_virtual,
-- var->bits_per_pixel >> 3);
-+ if (rg->size && ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
-+ enum omap_color_mode mode = 0;
-+ mode = fb_mode_to_dss_mode(var);
-+
-+ omap_vrfb_setup(&rg->vrfb, rg->paddr,
-+ var->xres_virtual,
-+ var->yres_virtual,
-+ mode);
- }
- }
-
-@@ -527,7 +524,7 @@ int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var)
- if (var->yres > var->yres_virtual)
- var->yres = var->yres_virtual;
-
-- if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
-+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
- line_size = OMAP_VRFB_LINE_LEN * bytespp;
- else
- line_size = var->xres_virtual * bytespp;
-@@ -549,7 +546,7 @@ int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var)
-
- if (line_size * var->yres_virtual > max_frame_size) {
- DBG("can't fit FB into memory, reducing x\n");
-- if (ofbi->rotation_type == OMAPFB_ROT_VRFB)
-+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
- return -EINVAL;
-
- var->xres_virtual = max_frame_size / var->yres_virtual /
-@@ -672,7 +669,7 @@ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
- struct omap_overlay_info info;
- int xres, yres;
- int screen_width;
-- int rot, mirror;
-+ int mirror;
-
- DBG("setup_overlay %d, posx %d, posy %d, outw %d, outh %d\n", ofbi->id,
- posx, posy, outw, outh);
-@@ -688,7 +685,7 @@ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
- offset = ((var->yoffset * var->xres_virtual +
- var->xoffset) * var->bits_per_pixel) >> 3;
-
-- if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
-+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
- data_start_p = omapfb_get_region_rot_paddr(ofbi);
- data_start_v = NULL;
- } else {
-@@ -711,13 +708,10 @@ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
-
- ovl->get_overlay_info(ovl, &info);
-
-- if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
-- rot = 0;
-+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
- mirror = 0;
-- } else {
-- rot = ofbi->rotation;
-+ else
- mirror = ofbi->mirror;
-- }
-
- info.paddr = data_start_p;
- info.vaddr = data_start_v;
-@@ -725,7 +719,8 @@ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
- info.width = xres;
- info.height = yres;
- info.color_mode = mode;
-- info.rotation = rot;
-+ info.rotation_type = ofbi->rotation_type;
-+ info.rotation = ofbi->rotation;
- info.mirror = mirror;
-
- info.pos_x = posx;
-@@ -1121,7 +1116,7 @@ static void omapfb_free_fbmem(struct fb_info *fbi)
- if (rg->vaddr)
- iounmap(rg->vaddr);
-
-- if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
-+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
- /* unmap the 0 angle rotation */
- if (rg->vrfb.vaddr[0]) {
- iounmap(rg->vrfb.vaddr[0]);
-@@ -1181,7 +1176,7 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
- return -ENOMEM;
- }
-
-- if (ofbi->rotation_type != OMAPFB_ROT_VRFB) {
-+ if (ofbi->rotation_type != OMAP_DSS_ROT_VRFB) {
- vaddr = ioremap_wc(paddr, size);
-
- if (!vaddr) {
-@@ -1260,7 +1255,7 @@ static int omapfb_alloc_fbmem_display(struct fb_info *fbi, unsigned long size,
-
- display->get_resolution(display, &w, &h);
-
-- if (ofbi->rotation_type == OMAPFB_ROT_VRFB) {
-+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
- #ifdef DEBUG
- int oldw = w, oldh = h;
- #endif
-@@ -1701,8 +1696,8 @@ static int omapfb_create_framebuffers(struct omapfb2_device *fbdev)
- ofbi->id = i;
-
- /* assign these early, so that fb alloc can use them */
-- ofbi->rotation_type = def_vrfb ? OMAPFB_ROT_VRFB :
-- OMAPFB_ROT_DMA;
-+ ofbi->rotation_type = def_vrfb ? OMAP_DSS_ROT_VRFB :
-+ OMAP_DSS_ROT_DMA;
- ofbi->rotation = def_rotate;
- ofbi->mirror = def_mirror;
-
-diff --git a/drivers/video/omap2/omapfb/omapfb.h b/drivers/video/omap2/omapfb/omapfb.h
-index 2607def..43f6922 100644
---- a/drivers/video/omap2/omapfb/omapfb.h
-+++ b/drivers/video/omap2/omapfb/omapfb.h
-@@ -53,11 +53,6 @@ struct omapfb2_mem_region {
- bool map; /* kernel mapped by the driver */
- };
-
--enum omapfb_rotation_type {
-- OMAPFB_ROT_DMA = 0,
-- OMAPFB_ROT_VRFB = 1,
--};
--
- /* appended to fb_info */
- struct omapfb_info {
- int id;
-@@ -66,7 +61,7 @@ struct omapfb_info {
- int num_overlays;
- struct omap_overlay *overlays[OMAPFB_MAX_OVL_PER_FB];
- struct omapfb2_device *fbdev;
-- enum omapfb_rotation_type rotation_type;
-+ enum omap_dss_rotation_type rotation_type;
- u8 rotation;
- bool mirror;
- };
---
-1.6.2.4
-
+++ /dev/null
-From a8a37babe4856170f4cba86c425a8f21975d9e9e Mon Sep 17 00:00:00 2001
-From: Tim Yamin <plasm@roo.me.uk>
-Date: Mon, 13 Apr 2009 13:57:42 -0700
-Subject: [PATCH 29/69] DSS2: OMAPFB: Set line_length correctly for YUV with VRFB.
-
-Signed-off-by: Tim Yamin <plasm@roo.me.uk>
----
- drivers/video/omap2/omapfb/omapfb-main.c | 30 +++++++++++++++++++++++++-----
- 1 files changed, 25 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
-index 57f5900..cd63740 100644
---- a/drivers/video/omap2/omapfb/omapfb-main.c
-+++ b/drivers/video/omap2/omapfb/omapfb-main.c
-@@ -392,10 +392,19 @@ void set_fb_fix(struct fb_info *fbi)
- fbi->screen_base = (char __iomem *)omapfb_get_region_vaddr(ofbi);
-
- /* used by mmap in fbmem.c */
-- if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
-- fix->line_length =
-- (OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 3;
-- else
-+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
-+ switch (var->nonstd) {
-+ case OMAPFB_COLOR_YUV422:
-+ case OMAPFB_COLOR_YUY422:
-+ fix->line_length =
-+ (OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 2;
-+ break;
-+ default:
-+ fix->line_length =
-+ (OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 3;
-+ break;
-+ }
-+ } else
- fix->line_length =
- (var->xres_virtual * var->bits_per_pixel) >> 3;
- fix->smem_start = omapfb_get_region_paddr(ofbi);
-@@ -704,7 +713,18 @@ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
- goto err;
- }
-
-- screen_width = fix->line_length / (var->bits_per_pixel >> 3);
-+ switch (var->nonstd) {
-+ case OMAPFB_COLOR_YUV422:
-+ case OMAPFB_COLOR_YUY422:
-+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
-+ screen_width = fix->line_length
-+ / (var->bits_per_pixel >> 2);
-+ break;
-+ }
-+ default:
-+ screen_width = fix->line_length / (var->bits_per_pixel >> 3);
-+ break;
-+ }
-
- ovl->get_overlay_info(ovl, &info);
-
---
-1.6.2.4
-
+++ /dev/null
-From bda19b9359d9dc60f8b0beb5685e173e236ee30f Mon Sep 17 00:00:00 2001
-From: Hardik Shah <hardik.shah@ti.com>
-Date: Wed, 15 Apr 2009 17:05:18 +0530
-Subject: [PATCH 30/69] DSS2: dispc_get_trans_key was returning wrong key type
-
-Signed-off-by: Hardik Shah <hardik.shah@ti.com>
----
- drivers/video/omap2/dss/dispc.c | 4 ++--
- 1 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-index 23a8155..076d3d4 100644
---- a/drivers/video/omap2/dss/dispc.c
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -1826,9 +1826,9 @@ void dispc_get_trans_key(enum omap_channel ch,
- enable_clocks(1);
- if (type) {
- if (ch == OMAP_DSS_CHANNEL_LCD)
-- *type = REG_GET(DISPC_CONFIG, 11, 11) >> 11;
-+ *type = REG_GET(DISPC_CONFIG, 11, 11);
- else if (ch == OMAP_DSS_CHANNEL_DIGIT)
-- *type = REG_GET(DISPC_CONFIG, 13, 13) >> 13;
-+ *type = REG_GET(DISPC_CONFIG, 13, 13);
- else
- BUG();
- }
---
-1.6.2.4
-
+++ /dev/null
-From 30c40f5e6b1794430f678bf23d3319354321cab7 Mon Sep 17 00:00:00 2001
-From: Imre Deak <imre.deak@nokia.com>
-Date: Tue, 14 Apr 2009 14:50:11 +0200
-Subject: [PATCH 31/69] DSS2: do bootmem reserve for exclusive access
-
-BOOTMEM_DEFAULT would allow multiple reservations for the same location,
-we need to reserve the region for our exclusive use. Also check if the
-reserve succeeded.
-
-Signed-off-by: Imre Deak <imre.deak@nokia.com>
----
- arch/arm/plat-omap/vram.c | 5 ++++-
- 1 files changed, 4 insertions(+), 1 deletions(-)
-
-diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
-index f24a110..520f260 100644
---- a/arch/arm/plat-omap/vram.c
-+++ b/arch/arm/plat-omap/vram.c
-@@ -524,7 +524,10 @@ void __init omapfb_reserve_sdram(void)
- return;
- }
-
-- reserve_bootmem(paddr, size, BOOTMEM_DEFAULT);
-+ if (reserve_bootmem(paddr, size, BOOTMEM_EXCLUSIVE) < 0) {
-+ pr_err("FB: failed to reserve VRAM\n");
-+ return;
-+ }
- } else {
- if (size > sdram_size) {
- printk(KERN_ERR "Illegal SDRAM size for VRAM\n");
---
-1.6.2.4
-
+++ /dev/null
-From ed7a9223f6785be03951c55f3b0695b0d5635c80 Mon Sep 17 00:00:00 2001
-From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
-Date: Thu, 9 Apr 2009 15:04:44 +0200
-Subject: [PATCH 32/69] DSS2: Fix DISPC_VID_FIR value for omap34xx
-MIME-Version: 1.0
-Content-Type: text/plain; charset=utf-8
-Content-Transfer-Encoding: 8bit
-
-The msbs of the DISPC_VID_FIR fields were incorrectly masked out on
-omap34xx and thus 4:1 downscale did not work correctly.
-
-Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
----
- drivers/video/omap2/dss/dispc.c | 5 ++++-
- 1 files changed, 4 insertions(+), 1 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-index 076d3d4..b8a3329 100644
---- a/drivers/video/omap2/dss/dispc.c
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -994,7 +994,10 @@ static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
-
- BUG_ON(plane == OMAP_DSS_GFX);
-
-- val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
-+ if (cpu_is_omap24xx())
-+ val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
-+ else
-+ val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
- dispc_write_reg(fir_reg[plane-1], val);
- }
-
---
-1.6.2.4
-
+++ /dev/null
-From 5390230ed12585a79683733209db34e9130b8e3b Mon Sep 17 00:00:00 2001
-From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
-Date: Thu, 9 Apr 2009 15:04:43 +0200
-Subject: [PATCH 33/69] DSS2: Prefer 3-tap filter
-MIME-Version: 1.0
-Content-Type: text/plain; charset=utf-8
-Content-Transfer-Encoding: 8bit
-
-The 5-tap filter seems rather unstable. With some scaling settings it
-works and with some it doesn't even though the functional clock remains
-within the TRM limits. So prefer the 3-tap filter unless the functional
-clock required for it is too high.
-
-Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
----
- drivers/video/omap2/dss/dispc.c | 27 ++++++++++++---------------
- 1 files changed, 12 insertions(+), 15 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-index b8a3329..b631dd8 100644
---- a/drivers/video/omap2/dss/dispc.c
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -1405,15 +1405,10 @@ static unsigned long calc_fclk_five_taps(u16 width, u16 height,
- }
-
- static unsigned long calc_fclk(u16 width, u16 height,
-- u16 out_width, u16 out_height,
-- enum omap_color_mode color_mode, bool five_taps)
-+ u16 out_width, u16 out_height)
- {
- unsigned int hf, vf;
-
-- if (five_taps)
-- return calc_fclk_five_taps(width, height,
-- out_width, out_height, color_mode);
--
- /*
- * FIXME how to determine the 'A' factor
- * for the no downscaling case ?
-@@ -1494,7 +1489,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
- } else {
- /* video plane */
-
-- unsigned long fclk;
-+ unsigned long fclk = 0;
-
- if (out_width < width / maxdownscale ||
- out_width > width * 8)
-@@ -1530,20 +1525,22 @@ static int _dispc_setup_plane(enum omap_plane plane,
- /* Must use 5-tap filter? */
- five_taps = height > out_height * 2;
-
-- /* Try to use 5-tap filter whenever possible. */
-- if (cpu_is_omap34xx() && !five_taps &&
-- height > out_height && width <= 1024) {
-- fclk = calc_fclk_five_taps(width, height,
-- out_width, out_height, color_mode);
-- if (fclk <= dispc_fclk_rate())
-+ if (!five_taps) {
-+ fclk = calc_fclk(width, height,
-+ out_width, out_height);
-+
-+ /* Try 5-tap filter if 3-tap fclk is too high */
-+ if (cpu_is_omap34xx() && height > out_height &&
-+ fclk > dispc_fclk_rate())
- five_taps = true;
- }
-
- if (width > (2048 >> five_taps))
- return -EINVAL;
-
-- fclk = calc_fclk(width, height, out_width, out_height,
-- color_mode, five_taps);
-+ if (five_taps)
-+ fclk = calc_fclk_five_taps(width, height,
-+ out_width, out_height, color_mode);
-
- DSSDBG("required fclk rate = %lu Hz\n", fclk);
- DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
---
-1.6.2.4
-
+++ /dev/null
-From 946eb774e95cdc2f2fa5cdc24aa69229f82814b8 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Thu, 16 Apr 2009 17:56:00 +0300
-Subject: [PATCH 34/69] DSS2: VRAM: improve omap_vram_add_region()
-
-Combine postponed and non-posponed versions of omap_vram_add_region.
-Make the func non-static, so it can be called from board files.
----
- arch/arm/plat-omap/include/mach/vram.h | 1 +
- arch/arm/plat-omap/vram.c | 54 +++++++++++++------------------
- 2 files changed, 24 insertions(+), 31 deletions(-)
-
-diff --git a/arch/arm/plat-omap/include/mach/vram.h b/arch/arm/plat-omap/include/mach/vram.h
-index f176562..8639e08 100644
---- a/arch/arm/plat-omap/include/mach/vram.h
-+++ b/arch/arm/plat-omap/include/mach/vram.h
-@@ -24,6 +24,7 @@
-
- #include <asm/types.h>
-
-+extern int omap_vram_add_region(unsigned long paddr, size_t size);
- extern int omap_vram_free(unsigned long paddr, size_t size);
- extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr);
- extern int omap_vram_reserve(unsigned long paddr, size_t size);
-diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
-index 520f260..8e9fe77 100644
---- a/arch/arm/plat-omap/vram.c
-+++ b/arch/arm/plat-omap/vram.c
-@@ -60,6 +60,7 @@
- * time when we cannot yet allocate the region list */
- #define MAX_POSTPONED_REGIONS 10
-
-+static bool vram_initialized;
- static int postponed_cnt __initdata;
- static struct {
- unsigned long paddr;
-@@ -145,39 +146,32 @@ static void omap_vram_free_allocation(struct vram_alloc *va)
- kfree(va);
- }
-
--static __init int omap_vram_add_region_postponed(unsigned long paddr,
-- size_t size)
--{
-- if (postponed_cnt == MAX_POSTPONED_REGIONS)
-- return -ENOMEM;
--
-- postponed_regions[postponed_cnt].paddr = paddr;
-- postponed_regions[postponed_cnt].size = size;
--
-- ++postponed_cnt;
--
-- return 0;
--}
--
--/* add/remove_region can be exported if there's need to add/remove regions
-- * runtime */
--static int omap_vram_add_region(unsigned long paddr, size_t size)
-+int omap_vram_add_region(unsigned long paddr, size_t size)
- {
- struct vram_region *rm;
- unsigned pages;
-
-- DBG("adding region paddr %08lx size %d\n",
-- paddr, size);
-+ if (vram_initialized) {
-+ DBG("adding region paddr %08lx size %d\n",
-+ paddr, size);
-
-- size &= PAGE_MASK;
-- pages = size >> PAGE_SHIFT;
-+ size &= PAGE_MASK;
-+ pages = size >> PAGE_SHIFT;
-
-- rm = omap_vram_create_region(paddr, pages);
-- if (rm == NULL)
-- return -ENOMEM;
-+ rm = omap_vram_create_region(paddr, pages);
-+ if (rm == NULL)
-+ return -ENOMEM;
-+
-+ list_add(&rm->list, ®ion_list);
-+ } else {
-+ if (postponed_cnt == MAX_POSTPONED_REGIONS)
-+ return -ENOMEM;
-
-- list_add(&rm->list, ®ion_list);
-+ postponed_regions[postponed_cnt].paddr = paddr;
-+ postponed_regions[postponed_cnt].size = size;
-
-+ ++postponed_cnt;
-+ }
- return 0;
- }
-
-@@ -438,6 +432,8 @@ static __init int omap_vram_init(void)
- {
- int i, r;
-
-+ vram_initialized = 1;
-+
- for (i = 0; i < postponed_cnt; i++)
- omap_vram_add_region(postponed_regions[i].paddr,
- postponed_regions[i].size);
-@@ -472,10 +468,6 @@ static void __init omapfb_early_vram(char **p)
- omapfb_def_sdram_vram_size = memparse(*p, p);
- if (**p == ',')
- omapfb_def_sdram_vram_start = simple_strtoul((*p) + 1, p, 16);
--
-- printk("omapfb_early_vram, %d, 0x%x\n",
-- omapfb_def_sdram_vram_size,
-- omapfb_def_sdram_vram_start);
- }
- __early_param("vram=", omapfb_early_vram);
-
-@@ -538,7 +530,7 @@ void __init omapfb_reserve_sdram(void)
- BUG_ON(paddr & ~PAGE_MASK);
- }
-
-- omap_vram_add_region_postponed(paddr, size);
-+ omap_vram_add_region(paddr, size);
-
- pr_info("Reserving %u bytes SDRAM for VRAM\n", size);
- }
-@@ -594,7 +586,7 @@ unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
- reserved = pend_avail - paddr;
- size_avail = pend_avail - reserved - pstart_avail;
-
-- omap_vram_add_region_postponed(paddr, size);
-+ omap_vram_add_region(paddr, size);
-
- if (reserved)
- pr_info("Reserving %lu bytes SRAM for VRAM\n", reserved);
---
-1.6.2.4
-
+++ /dev/null
-From f825cafd5ee5c600218740507f85594c825b0c00 Mon Sep 17 00:00:00 2001
-From: Hardik Shah <hardik.shah@ti.com>
-Date: Thu, 16 Apr 2009 18:47:49 +0530
-Subject: [PATCH 35/69] DSS2: Added the function pointer for getting default color.
-
-V4L2 Framework has a CID for getting/setting default color.
-So added the function pointer for doing same.
-SYSFS based getting the default color will remain same
-
-Signed-off-by: Hardik Shah <hardik.shah@ti.com>
----
- arch/arm/plat-omap/include/mach/display.h | 1 +
- drivers/video/omap2/dss/manager.c | 11 +++++++----
- 2 files changed, 8 insertions(+), 4 deletions(-)
-
-diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
-index b0a6272..073cdda 100644
---- a/arch/arm/plat-omap/include/mach/display.h
-+++ b/arch/arm/plat-omap/include/mach/display.h
-@@ -414,6 +414,7 @@ struct omap_overlay_manager {
- int (*apply)(struct omap_overlay_manager *mgr);
-
- void (*set_default_color)(struct omap_overlay_manager *mgr, u32 color);
-+ u32 (*get_default_color)(struct omap_overlay_manager *mgr);
- void (*set_trans_key)(struct omap_overlay_manager *mgr,
- enum omap_dss_color_key_type type,
- u32 trans_key);
-diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
-index 8ca0bbb..12cf7b0 100644
---- a/drivers/video/omap2/dss/manager.c
-+++ b/drivers/video/omap2/dss/manager.c
-@@ -98,10 +98,8 @@ static ssize_t manager_display_store(struct omap_overlay_manager *mgr, const cha
- static ssize_t manager_default_color_show(struct omap_overlay_manager *mgr,
- char *buf)
- {
-- u32 default_color;
--
-- default_color = dispc_get_default_color(mgr->id);
-- return snprintf(buf, PAGE_SIZE, "%d", default_color);
-+ return snprintf(buf, PAGE_SIZE, "%d",
-+ mgr->get_default_color(mgr));
- }
-
- static ssize_t manager_default_color_store(struct omap_overlay_manager *mgr,
-@@ -470,6 +468,10 @@ static void omap_dss_mgr_enable_trans_key(struct omap_overlay_manager *mgr,
- {
- dispc_enable_trans_key(mgr->id, enable);
- }
-+static u32 omap_dss_mgr_get_default_color(struct omap_overlay_manager *mgr)
-+{
-+ return dispc_get_default_color(mgr->id);
-+}
-
- static void omap_dss_add_overlay_manager(struct omap_overlay_manager *manager)
- {
-@@ -512,6 +514,7 @@ int dss_init_overlay_managers(struct platform_device *pdev)
- mgr->set_default_color = &omap_dss_mgr_set_def_color,
- mgr->set_trans_key = &omap_dss_mgr_set_trans_key,
- mgr->enable_trans_key = &omap_dss_mgr_enable_trans_key,
-+ mgr->get_default_color = &omap_dss_mgr_get_default_color;
- mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC,
-
- dss_overlay_setup_dispc_manager(mgr);
---
-1.6.2.4
-
+++ /dev/null
-From 6c56dc10226c84f41917ac2117b0e654fa080d40 Mon Sep 17 00:00:00 2001
-From: Hardik Shah <hardik.shah@ti.com>
-Date: Thu, 16 Apr 2009 19:00:11 +0530
-Subject: [PATCH 36/69] DSS2: Added support for setting and querying alpha blending.
-
-Signed-off-by: Hardik Shah <hardik.shah@ti.com>
----
- arch/arm/plat-omap/include/mach/display.h | 3 +++
- drivers/video/omap2/dss/dispc.c | 26 ++++++++++++++++++++++++++
- drivers/video/omap2/dss/dss.h | 2 ++
- drivers/video/omap2/dss/manager.c | 14 ++++++++++++++
- 4 files changed, 45 insertions(+), 0 deletions(-)
-
-diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
-index 073cdda..e1f615a 100644
---- a/arch/arm/plat-omap/include/mach/display.h
-+++ b/arch/arm/plat-omap/include/mach/display.h
-@@ -415,11 +415,14 @@ struct omap_overlay_manager {
-
- void (*set_default_color)(struct omap_overlay_manager *mgr, u32 color);
- u32 (*get_default_color)(struct omap_overlay_manager *mgr);
-+ bool (*get_alpha_blending_status)(struct omap_overlay_manager *mgr);
- void (*set_trans_key)(struct omap_overlay_manager *mgr,
- enum omap_dss_color_key_type type,
- u32 trans_key);
- void (*enable_trans_key)(struct omap_overlay_manager *mgr,
- bool enable);
-+ void (*enable_alpha_blending)(struct omap_overlay_manager *mgr,
-+ bool enable);
- };
-
- enum omap_display_caps {
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-index b631dd8..7e551c2 100644
---- a/drivers/video/omap2/dss/dispc.c
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -1847,6 +1847,32 @@ void dispc_enable_trans_key(enum omap_channel ch, bool enable)
- REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
- enable_clocks(0);
- }
-+void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
-+{
-+ enable_clocks(1);
-+ if (ch == OMAP_DSS_CHANNEL_LCD)
-+ REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
-+ else /* OMAP_DSS_CHANNEL_DIGIT */
-+ REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
-+ enable_clocks(0);
-+}
-+bool dispc_alpha_blending_enabled(enum omap_channel ch)
-+{
-+ bool enabled;
-+
-+ enable_clocks(1);
-+ if (ch == OMAP_DSS_CHANNEL_LCD)
-+ enabled = REG_GET(DISPC_CONFIG, 18, 18);
-+ else if (ch == OMAP_DSS_CHANNEL_DIGIT)
-+ enabled = REG_GET(DISPC_CONFIG, 18, 18);
-+ else
-+ BUG();
-+ enable_clocks(0);
-+
-+ return enabled;
-+
-+}
-+
-
- bool dispc_trans_key_enabled(enum omap_channel ch)
- {
-diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
-index 584dce6..1d01ff6 100644
---- a/drivers/video/omap2/dss/dss.h
-+++ b/drivers/video/omap2/dss/dss.h
-@@ -294,7 +294,9 @@ void dispc_get_trans_key(enum omap_channel ch,
- enum omap_dss_color_key_type *type,
- u32 *trans_key);
- void dispc_enable_trans_key(enum omap_channel ch, bool enable);
-+void dispc_enable_alpha_blending(enum omap_channel ch, bool enable);
- bool dispc_trans_key_enabled(enum omap_channel ch);
-+bool dispc_alpha_blending_enabled(enum omap_channel ch);
-
- void dispc_set_lcd_timings(struct omap_video_timings *timings);
- unsigned long dispc_fclk_rate(void);
-diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
-index 12cf7b0..90acd28 100644
---- a/drivers/video/omap2/dss/manager.c
-+++ b/drivers/video/omap2/dss/manager.c
-@@ -468,6 +468,16 @@ static void omap_dss_mgr_enable_trans_key(struct omap_overlay_manager *mgr,
- {
- dispc_enable_trans_key(mgr->id, enable);
- }
-+static void omap_dss_mgr_enable_alpha_blending(struct omap_overlay_manager *mgr,
-+ bool enable)
-+{
-+ dispc_enable_alpha_blending(mgr->id, enable);
-+}
-+static bool omap_dss_mgr_get_alpha_blending_status(
-+ struct omap_overlay_manager *mgr)
-+{
-+ return dispc_alpha_blending_enabled(mgr->id);
-+}
- static u32 omap_dss_mgr_get_default_color(struct omap_overlay_manager *mgr)
- {
- return dispc_get_default_color(mgr->id);
-@@ -514,6 +524,10 @@ int dss_init_overlay_managers(struct platform_device *pdev)
- mgr->set_default_color = &omap_dss_mgr_set_def_color,
- mgr->set_trans_key = &omap_dss_mgr_set_trans_key,
- mgr->enable_trans_key = &omap_dss_mgr_enable_trans_key,
-+ mgr->enable_alpha_blending =
-+ &omap_dss_mgr_enable_alpha_blending;
-+ mgr->get_alpha_blending_status =
-+ omap_dss_mgr_get_alpha_blending_status;
- mgr->get_default_color = &omap_dss_mgr_get_default_color;
- mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC,
-
---
-1.6.2.4
-
+++ /dev/null
-From 2c9edd6af31a812a9487dd8bc12322e105a29f44 Mon Sep 17 00:00:00 2001
-From: Hardik Shah <hardik.shah@ti.com>
-Date: Fri, 17 Apr 2009 09:42:36 +0530
-Subject: [PATCH 37/69] DSS2: Added support for querying color keying.
-
-V4L2 Framework has a ioctl for getting/setting color keying.
-So added the function manager pointers for doing same.
-
-Modifed the color keying sysfs entries to use manager
-function pointer. Earlier they were calling direcly
-dispc function to set/enable color keying.
-
-Some of color-keying function pointers in the overlay_manager
-structure re-named to be more specific.
-
-Signed-off-by: Hardik Shah <hardik.shah@ti.com>
----
- arch/arm/plat-omap/include/mach/display.h | 6 ++++-
- drivers/video/omap2/dss/manager.c | 36 +++++++++++++++++++++--------
- 2 files changed, 31 insertions(+), 11 deletions(-)
-
-diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
-index e1f615a..d0b4c83 100644
---- a/arch/arm/plat-omap/include/mach/display.h
-+++ b/arch/arm/plat-omap/include/mach/display.h
-@@ -416,7 +416,11 @@ struct omap_overlay_manager {
- void (*set_default_color)(struct omap_overlay_manager *mgr, u32 color);
- u32 (*get_default_color)(struct omap_overlay_manager *mgr);
- bool (*get_alpha_blending_status)(struct omap_overlay_manager *mgr);
-- void (*set_trans_key)(struct omap_overlay_manager *mgr,
-+ bool (*get_trans_key_status)(struct omap_overlay_manager *mgr);
-+ void (*get_trans_key_type_and_value)(struct omap_overlay_manager *mgr,
-+ enum omap_dss_color_key_type *type,
-+ u32 *trans_key);
-+ void (*set_trans_key_type_and_value)(struct omap_overlay_manager *mgr,
- enum omap_dss_color_key_type type,
- u32 trans_key);
- void (*enable_trans_key)(struct omap_overlay_manager *mgr,
-diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
-index 90acd28..e0501c4 100644
---- a/drivers/video/omap2/dss/manager.c
-+++ b/drivers/video/omap2/dss/manager.c
-@@ -124,7 +124,7 @@ static ssize_t manager_color_key_type_show(struct omap_overlay_manager *mgr,
- {
- enum omap_dss_color_key_type key_type;
-
-- dispc_get_trans_key(mgr->id, &key_type, NULL);
-+ mgr->get_trans_key_type_and_value(mgr, &key_type, NULL);
- BUG_ON(key_type >= ARRAY_SIZE(color_key_type_str));
-
- return snprintf(buf, PAGE_SIZE, "%s\n", color_key_type_str[key_type]);
-@@ -143,8 +143,8 @@ static ssize_t manager_color_key_type_store(struct omap_overlay_manager *mgr,
- }
- if (key_type == ARRAY_SIZE(color_key_type_str))
- return -EINVAL;
-- dispc_get_trans_key(mgr->id, NULL, &key_value);
-- dispc_set_trans_key(mgr->id, key_type, key_value);
-+ mgr->get_trans_key_type_and_value(mgr, NULL, &key_value);
-+ mgr->set_trans_key_type_and_value(mgr, key_type, key_value);
-
- return size;
- }
-@@ -154,7 +154,7 @@ static ssize_t manager_color_key_value_show(struct omap_overlay_manager *mgr,
- {
- u32 key_value;
-
-- dispc_get_trans_key(mgr->id, NULL, &key_value);
-+ mgr->get_trans_key_type_and_value(mgr, NULL, &key_value);
-
- return snprintf(buf, PAGE_SIZE, "%d\n", key_value);
- }
-@@ -167,8 +167,8 @@ static ssize_t manager_color_key_value_store(struct omap_overlay_manager *mgr,
-
- if (sscanf(buf, "%d", &key_value) != 1)
- return -EINVAL;
-- dispc_get_trans_key(mgr->id, &key_type, NULL);
-- dispc_set_trans_key(mgr->id, key_type, key_value);
-+ mgr->get_trans_key_type_and_value(mgr, &key_type, NULL);
-+ mgr->set_trans_key_type_and_value(mgr, key_type, key_value);
-
- return size;
- }
-@@ -177,7 +177,7 @@ static ssize_t manager_color_key_enabled_show(struct omap_overlay_manager *mgr,
- char *buf)
- {
- return snprintf(buf, PAGE_SIZE, "%d\n",
-- dispc_trans_key_enabled(mgr->id));
-+ mgr->get_trans_key_status(mgr));
- }
-
- static ssize_t manager_color_key_enabled_store(struct omap_overlay_manager *mgr,
-@@ -188,7 +188,7 @@ static ssize_t manager_color_key_enabled_store(struct omap_overlay_manager *mgr,
- if (sscanf(buf, "%d", &enable) != 1)
- return -EINVAL;
-
-- dispc_enable_trans_key(mgr->id, enable);
-+ mgr->enable_trans_key(mgr, enable);
-
- return size;
- }
-@@ -456,12 +456,20 @@ static void omap_dss_mgr_set_def_color(struct omap_overlay_manager *mgr,
- dispc_set_default_color(mgr->id, color);
- }
-
--static void omap_dss_mgr_set_trans_key(struct omap_overlay_manager *mgr,
-+static void omap_dss_mgr_set_trans_key_type_and_value(
-+ struct omap_overlay_manager *mgr,
- enum omap_dss_color_key_type type,
- u32 trans_key)
- {
- dispc_set_trans_key(mgr->id, type, trans_key);
- }
-+static void omap_dss_mgr_get_trans_key_type_and_value(
-+ struct omap_overlay_manager *mgr,
-+ enum omap_dss_color_key_type *type,
-+ u32 *trans_key)
-+{
-+ dispc_get_trans_key(mgr->id, type, trans_key);
-+}
-
- static void omap_dss_mgr_enable_trans_key(struct omap_overlay_manager *mgr,
- bool enable)
-@@ -482,6 +490,10 @@ static u32 omap_dss_mgr_get_default_color(struct omap_overlay_manager *mgr)
- {
- return dispc_get_default_color(mgr->id);
- }
-+static bool omap_dss_mgr_get_trans_key_status(struct omap_overlay_manager *mgr)
-+{
-+ return dispc_trans_key_enabled(mgr->id);
-+}
-
- static void omap_dss_add_overlay_manager(struct omap_overlay_manager *manager)
- {
-@@ -522,8 +534,12 @@ int dss_init_overlay_managers(struct platform_device *pdev)
- mgr->unset_display = &omap_dss_unset_display,
- mgr->apply = &omap_dss_mgr_apply,
- mgr->set_default_color = &omap_dss_mgr_set_def_color,
-- mgr->set_trans_key = &omap_dss_mgr_set_trans_key,
-+ mgr->set_trans_key_type_and_value =
-+ &omap_dss_mgr_set_trans_key_type_and_value,
-+ mgr->get_trans_key_type_and_value =
-+ &omap_dss_mgr_get_trans_key_type_and_value,
- mgr->enable_trans_key = &omap_dss_mgr_enable_trans_key,
-+ mgr->get_trans_key_status = &omap_dss_mgr_get_trans_key_status,
- mgr->enable_alpha_blending =
- &omap_dss_mgr_enable_alpha_blending;
- mgr->get_alpha_blending_status =
---
-1.6.2.4
-
+++ /dev/null
-From 9e8877f0e5b17d3ddd101d6a63aa86fdb14d35d5 Mon Sep 17 00:00:00 2001
-From: Hardik Shah <hardik.shah@ti.com>
-Date: Fri, 17 Apr 2009 09:51:25 +0530
-Subject: [PATCH 38/69] DSS2:OMAPFB: Some color keying pointerd renamed in DSS2. Replicated in FB
-
-Signed-off-by: Hardik Shah <hardik.shah@ti.com>
----
- drivers/video/omap2/omapfb/omapfb-ioctl.c | 11 +++++++----
- 1 files changed, 7 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/video/omap2/omapfb/omapfb-ioctl.c b/drivers/video/omap2/omapfb/omapfb-ioctl.c
-index 7f18d2a..79d8916 100644
---- a/drivers/video/omap2/omapfb/omapfb-ioctl.c
-+++ b/drivers/video/omap2/omapfb/omapfb-ioctl.c
-@@ -288,7 +288,8 @@ static int _omapfb_set_color_key(struct omap_overlay_manager *mgr,
- {
- enum omap_dss_color_key_type kt;
-
-- if(!mgr->set_default_color || !mgr->set_trans_key ||
-+ if (!mgr->set_default_color ||
-+ !mgr->set_trans_key_type_and_value ||
- !mgr->enable_trans_key)
- return 0;
-
-@@ -310,7 +311,7 @@ static int _omapfb_set_color_key(struct omap_overlay_manager *mgr,
- }
-
- mgr->set_default_color(mgr, ck->background);
-- mgr->set_trans_key(mgr, kt, ck->trans_key);
-+ mgr->set_trans_key_type_and_value(mgr, kt, ck->trans_key);
- mgr->enable_trans_key(mgr, 1);
-
- omapfb_color_keys[mgr->id] = *ck;
-@@ -341,7 +342,8 @@ static int omapfb_set_color_key(struct fb_info *fbi,
- goto err;
- }
-
-- if(!mgr->set_default_color || !mgr->set_trans_key ||
-+ if (!mgr->set_default_color ||
-+ !mgr->set_trans_key_type_and_value ||
- !mgr->enable_trans_key) {
- r = -ENODEV;
- goto err;
-@@ -377,7 +379,8 @@ static int omapfb_get_color_key(struct fb_info *fbi,
- goto err;
- }
-
-- if(!mgr->set_default_color || !mgr->set_trans_key ||
-+ if (!mgr->set_default_color ||
-+ !mgr->set_trans_key_type_and_value ||
- !mgr->enable_trans_key) {
- r = -ENODEV;
- goto err;
---
-1.6.2.4
-
+++ /dev/null
-From 6f1f0c7b19ecb468824b79f9d181ef0da41b7d7d Mon Sep 17 00:00:00 2001
-From: Hardik Shah <hardik.shah@ti.com>
-Date: Fri, 17 Apr 2009 13:58:21 +0530
-Subject: [PATCH 39/69] DSS2: Add sysfs entry to for the alpha blending support.
-
-Signed-off-by: Hardik Shah <hardik.shah@ti.com>
----
- drivers/video/omap2/dss/manager.c | 21 +++++++++++++++++++++
- 1 files changed, 21 insertions(+), 0 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
-index e0501c4..7965a84 100644
---- a/drivers/video/omap2/dss/manager.c
-+++ b/drivers/video/omap2/dss/manager.c
-@@ -192,6 +192,22 @@ static ssize_t manager_color_key_enabled_store(struct omap_overlay_manager *mgr,
-
- return size;
- }
-+static ssize_t manager_alpha_blending_enabled_show(
-+ struct omap_overlay_manager *mgr, char *buf)
-+{
-+ return snprintf(buf, PAGE_SIZE, "%d\n",
-+ mgr->get_alpha_blending_status(mgr));
-+}
-+static ssize_t manager_alpha_blending_enabled_store(
-+ struct omap_overlay_manager *mgr,
-+ const char *buf, size_t size)
-+{
-+ int enable;
-+ if (sscanf(buf, "%d", &enable) != 1)
-+ return -EINVAL;
-+ mgr->enable_alpha_blending(mgr, enable);
-+ return size;
-+}
-
-
- struct manager_attribute {
-@@ -215,6 +231,10 @@ static MANAGER_ATTR(color_key_value, S_IRUGO|S_IWUSR,
- manager_color_key_value_show, manager_color_key_value_store);
- static MANAGER_ATTR(color_key_enabled, S_IRUGO|S_IWUSR,
- manager_color_key_enabled_show, manager_color_key_enabled_store);
-+static MANAGER_ATTR(alpha_blending_enabled, S_IRUGO|S_IWUSR,
-+ manager_alpha_blending_enabled_show,
-+ manager_alpha_blending_enabled_store);
-+
-
- static struct attribute *manager_sysfs_attrs[] = {
- &manager_attr_name.attr,
-@@ -223,6 +243,7 @@ static struct attribute *manager_sysfs_attrs[] = {
- &manager_attr_color_key_type.attr,
- &manager_attr_color_key_value.attr,
- &manager_attr_color_key_enabled.attr,
-+ &manager_attr_alpha_blending_enabled.attr,
- NULL
- };
-
---
-1.6.2.4
-
+++ /dev/null
-From a5129f272a48aa22629137c9c31e60eddb8c3f5d Mon Sep 17 00:00:00 2001
-From: Hardik Shah <hardik.shah@ti.com>
-Date: Fri, 17 Apr 2009 14:24:46 +0530
-Subject: [PATCH 40/69] DSS2: Provided proper exclusion for destination color keying and alpha blending.
-
-OMAP does not support destination color key and alpha blending
-simultaneously. So this patch does not allow the user
-so set both at a time.
-
-Signed-off-by: Hardik Shah <hardik.shah@ti.com>
----
- drivers/video/omap2/dss/manager.c | 50 ++++++++++++++++++++++++++++++++++++-
- 1 files changed, 49 insertions(+), 1 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
-index 7965a84..108489c 100644
---- a/drivers/video/omap2/dss/manager.c
-+++ b/drivers/video/omap2/dss/manager.c
-@@ -137,12 +137,26 @@ static ssize_t manager_color_key_type_store(struct omap_overlay_manager *mgr,
- u32 key_value;
-
- for (key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
-- key_type < ARRAY_SIZE(color_key_type_str); key_type++) {
-+ key_type < ARRAY_SIZE(color_key_type_str); key_type++) {
- if (sysfs_streq(buf, color_key_type_str[key_type]))
- break;
- }
- if (key_type == ARRAY_SIZE(color_key_type_str))
- return -EINVAL;
-+ /* OMAP does not support destination color key and alpha blending
-+ * simultaneously. So if alpha blending and color keying both are
-+ * enabled then refrain from setting the color key type to
-+ * gfx-destination
-+ */
-+ if (!key_type) {
-+ bool color_key_enabled;
-+ bool alpha_blending_enabled;
-+ color_key_enabled = mgr->get_trans_key_status(mgr);
-+ alpha_blending_enabled = mgr->get_alpha_blending_status(mgr);
-+ if (color_key_enabled && alpha_blending_enabled)
-+ return -EINVAL;
-+ }
-+
- mgr->get_trans_key_type_and_value(mgr, NULL, &key_value);
- mgr->set_trans_key_type_and_value(mgr, key_type, key_value);
-
-@@ -188,6 +202,23 @@ static ssize_t manager_color_key_enabled_store(struct omap_overlay_manager *mgr,
- if (sscanf(buf, "%d", &enable) != 1)
- return -EINVAL;
-
-+ /* OMAP does not support destination color keying and
-+ * alpha blending simultaneously. so if alpha blending
-+ * is enabled refrain from enabling destination color
-+ * keying.
-+ */
-+ if (enable) {
-+ bool enabled;
-+ enabled = mgr->get_alpha_blending_status(mgr);
-+ if (enabled) {
-+ enum omap_dss_color_key_type key_type;
-+ mgr->get_trans_key_type_and_value(mgr,
-+ &key_type, NULL);
-+ if (!key_type)
-+ return -EINVAL;
-+ }
-+
-+ }
- mgr->enable_trans_key(mgr, enable);
-
- return size;
-@@ -205,6 +236,23 @@ static ssize_t manager_alpha_blending_enabled_store(
- int enable;
- if (sscanf(buf, "%d", &enable) != 1)
- return -EINVAL;
-+ /* OMAP does not support destination color keying and
-+ * alpha blending simultaneously. so if destination
-+ * color keying is enabled refrain from enabling
-+ * alpha blending
-+ */
-+ if (enable) {
-+ bool enabled;
-+ enabled = mgr->get_trans_key_status(mgr);
-+ if (enabled) {
-+ enum omap_dss_color_key_type key_type;
-+ mgr->get_trans_key_type_and_value(mgr, &key_type, NULL);
-+ if (!key_type)
-+ return -EINVAL;
-+
-+ }
-+
-+ }
- mgr->enable_alpha_blending(mgr, enable);
- return size;
- }
---
-1.6.2.4
-
+++ /dev/null
-From 9bcac9b9e678f476c83b5679b1215b6bc946130a Mon Sep 17 00:00:00 2001
-From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
-Date: Mon, 20 Apr 2009 16:26:18 +0200
-Subject: [PATCH 41/69] DSS2: Disable vertical offset with fieldmode
-MIME-Version: 1.0
-Content-Type: text/plain; charset=utf-8
-Content-Transfer-Encoding: 8bit
-
-When using fieldmode each field is basically a separate picture so the
-vertical filter should start at phase 0 for both fields.
-
-Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
----
- drivers/video/omap2/dss/dispc.c | 23 +++++++++--------------
- 1 files changed, 9 insertions(+), 14 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-index 7e551c2..f15614b 100644
---- a/drivers/video/omap2/dss/dispc.c
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -1029,12 +1029,12 @@ static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
- static void _dispc_set_scaling(enum omap_plane plane,
- u16 orig_width, u16 orig_height,
- u16 out_width, u16 out_height,
-- bool ilace, bool five_taps)
-+ bool ilace, bool five_taps,
-+ bool fieldmode)
- {
- int fir_hinc;
- int fir_vinc;
- int hscaleup, vscaleup;
-- int fieldmode = 0;
- int accu0 = 0;
- int accu1 = 0;
- u32 l;
-@@ -1072,17 +1072,12 @@ static void _dispc_set_scaling(enum omap_plane plane,
-
- dispc_write_reg(dispc_reg_att[plane], l);
-
-- if (ilace) {
-- if (fieldmode) {
-- accu0 = fir_vinc / 2;
-- accu1 = 0;
-- } else {
-- accu0 = 0;
-- accu1 = fir_vinc / 2;
-- if (accu1 >= 1024/2) {
-- accu0 = 1024/2;
-- accu1 -= accu0;
-- }
-+ if (ilace && !fieldmode) {
-+ accu0 = 0;
-+ accu1 = fir_vinc / 2;
-+ if (accu1 >= 1024/2) {
-+ accu0 = 1024/2;
-+ accu1 -= accu0;
- }
- }
-
-@@ -1582,7 +1577,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
- if (plane != OMAP_DSS_GFX) {
- _dispc_set_scaling(plane, width, height,
- out_width, out_height,
-- ilace, five_taps);
-+ ilace, five_taps, fieldmode);
- _dispc_set_vid_size(plane, out_width, out_height);
- _dispc_set_vid_color_conv(plane, cconv);
- }
---
-1.6.2.4
-
+++ /dev/null
-From 9c6de0fed6e8a598d026d348533fdf731b737d55 Mon Sep 17 00:00:00 2001
-From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
-Date: Mon, 20 Apr 2009 16:26:19 +0200
-Subject: [PATCH 42/69] DSS2: Don't enable fieldmode automatically
-MIME-Version: 1.0
-Content-Type: text/plain; charset=utf-8
-Content-Transfer-Encoding: 8bit
-
-The only case where enabling fieldmode automatically seems reasonable
-is when source and destination heights are equal. Some kind of user
-controllable knob should be added so the user could enable field mode
-when the source is interlaced.
-
-Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
----
- drivers/video/omap2/dss/dispc.c | 2 +-
- 1 files changed, 1 insertions(+), 1 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-index f15614b..1c036c1 100644
---- a/drivers/video/omap2/dss/dispc.c
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -1450,7 +1450,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
- if (paddr == 0)
- return -EINVAL;
-
-- if (ilace && height >= out_height)
-+ if (ilace && height == out_height)
- fieldmode = 1;
-
- if (ilace) {
---
-1.6.2.4
-
+++ /dev/null
-From 35e88797e93b107ba602dee1e2ac8ea761dccd4b Mon Sep 17 00:00:00 2001
-From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
-Date: Mon, 20 Apr 2009 16:26:20 +0200
-Subject: [PATCH 43/69] DSS2: Swap field 0 and field 1 registers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=utf-8
-Content-Transfer-Encoding: 8bit
-
-The values for the registers which have alternate values for each field
-were reveresed to what the hardware expects. For the hardware field 0
-is the even field or the bottom field, field 1 is the odd field or the
-top field. So simply swap the register values.
-
-Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
----
- drivers/video/omap2/dss/dispc.c | 66 ++++++++++++++++++++++-----------------
- 1 files changed, 37 insertions(+), 29 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-index 1c036c1..9bab6cf 100644
---- a/drivers/video/omap2/dss/dispc.c
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -1072,12 +1072,16 @@ static void _dispc_set_scaling(enum omap_plane plane,
-
- dispc_write_reg(dispc_reg_att[plane], l);
-
-+ /*
-+ * field 0 = even field = bottom field
-+ * field 1 = odd field = top field
-+ */
- if (ilace && !fieldmode) {
-- accu0 = 0;
-- accu1 = fir_vinc / 2;
-- if (accu1 >= 1024/2) {
-- accu0 = 1024/2;
-- accu1 -= accu0;
-+ accu1 = 0;
-+ accu0 = fir_vinc / 2;
-+ if (accu0 >= 1024/2) {
-+ accu1 = 1024/2;
-+ accu0 -= accu1;
- }
- }
-
-@@ -1266,34 +1270,38 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
- fbh = width;
- }
-
-+ /*
-+ * field 0 = even field = bottom field
-+ * field 1 = odd field = top field
-+ */
- switch (rotation + mirror * 4) {
- case 0:
-- *offset0 = 0;
-+ *offset1 = 0;
- if (fieldmode)
-- *offset1 = screen_width * ps;
-+ *offset0 = screen_width * ps;
- else
-- *offset1 = 0;
-+ *offset0 = 0;
- *row_inc = pixinc(1 + (screen_width - fbw) +
- (fieldmode ? screen_width : 0),
- ps);
- *pix_inc = pixinc(1, ps);
- break;
- case 1:
-- *offset0 = screen_width * (fbh - 1) * ps;
-+ *offset1 = screen_width * (fbh - 1) * ps;
- if (fieldmode)
-- *offset1 = *offset0 + ps;
-+ *offset0 = *offset1 + ps;
- else
-- *offset1 = *offset0;
-+ *offset0 = *offset1;
- *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
- (fieldmode ? 1 : 0), ps);
- *pix_inc = pixinc(-screen_width, ps);
- break;
- case 2:
-- *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
-+ *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
- if (fieldmode)
-- *offset1 = *offset0 - screen_width * ps;
-+ *offset0 = *offset1 - screen_width * ps;
- else
-- *offset1 = *offset0;
-+ *offset0 = *offset1;
- *row_inc = pixinc(-1 -
- (screen_width - fbw) -
- (fieldmode ? screen_width : 0),
-@@ -1301,11 +1309,11 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
- *pix_inc = pixinc(-1, ps);
- break;
- case 3:
-- *offset0 = (fbw - 1) * ps;
-+ *offset1 = (fbw - 1) * ps;
- if (fieldmode)
-- *offset1 = *offset0 - ps;
-+ *offset0 = *offset1 - ps;
- else
-- *offset1 = *offset0;
-+ *offset0 = *offset1;
- *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
- (fieldmode ? 1 : 0), ps);
- *pix_inc = pixinc(screen_width, ps);
-@@ -1313,11 +1321,11 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
-
- /* mirroring */
- case 0 + 4:
-- *offset0 = (fbw - 1) * ps;
-+ *offset1 = (fbw - 1) * ps;
- if (fieldmode)
-- *offset1 = *offset0 + screen_width * ps;
-+ *offset0 = *offset1 + screen_width * ps;
- else
-- *offset1 = *offset0;
-+ *offset0 = *offset1;
- *row_inc = pixinc(screen_width * 2 - 1 +
- (fieldmode ? screen_width : 0),
- ps);
-@@ -1325,11 +1333,11 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
- break;
-
- case 1 + 4:
-- *offset0 = 0;
-+ *offset1 = 0;
- if (fieldmode)
-- *offset1 = *offset0 + screen_width * ps;
-+ *offset0 = *offset1 + screen_width * ps;
- else
-- *offset1 = *offset0;
-+ *offset0 = *offset1;
- *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
- (fieldmode ? 1 : 0),
- ps);
-@@ -1337,11 +1345,11 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
- break;
-
- case 2 + 4:
-- *offset0 = screen_width * (fbh - 1) * ps;
-+ *offset1 = screen_width * (fbh - 1) * ps;
- if (fieldmode)
-- *offset1 = *offset0 + screen_width * ps;
-+ *offset0 = *offset1 + screen_width * ps;
- else
-- *offset1 = *offset0;
-+ *offset0 = *offset1;
- *row_inc = pixinc(1 - screen_width * 2 -
- (fieldmode ? screen_width : 0),
- ps);
-@@ -1349,11 +1357,11 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
- break;
-
- case 3 + 4:
-- *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
-+ *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
- if (fieldmode)
-- *offset1 = *offset0 + screen_width * ps;
-+ *offset0 = *offset1 + screen_width * ps;
- else
-- *offset1 = *offset0;
-+ *offset0 = *offset1;
- *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
- (fieldmode ? 1 : 0),
- ps);
---
-1.6.2.4
-
+++ /dev/null
-From a9b3500bd14609750a2337e866e1df62627c1bac Mon Sep 17 00:00:00 2001
-From: Imre Deak <imre.deak@nokia.com>
-Date: Mon, 20 Apr 2009 14:55:33 +0200
-Subject: [PATCH 44/69] DSS2: add sysfs entry for seting the rotate type
-
-This can help in utilizing VRAM memory better. Since with VRFB rotation
-we waste a lot of physical memory due to the VRFB HW design, provide the
-possibility to turn it off and free the extra memory for the use by other
-planes for example.
----
- drivers/video/omap2/omapfb/omapfb-sysfs.c | 42 ++++++++++++++++++++++++++++-
- 1 files changed, 41 insertions(+), 1 deletions(-)
-
-diff --git a/drivers/video/omap2/omapfb/omapfb-sysfs.c b/drivers/video/omap2/omapfb/omapfb-sysfs.c
-index 2c88718..4e3da42 100644
---- a/drivers/video/omap2/omapfb/omapfb-sysfs.c
-+++ b/drivers/video/omap2/omapfb/omapfb-sysfs.c
-@@ -43,6 +43,46 @@ static ssize_t show_rotate_type(struct device *dev,
- return snprintf(buf, PAGE_SIZE, "%d\n", ofbi->rotation_type);
- }
-
-+static ssize_t store_rotate_type(struct device *dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ struct fb_info *fbi = dev_get_drvdata(dev);
-+ struct omapfb_info *ofbi = FB2OFB(fbi);
-+ struct omapfb2_device *fbdev = ofbi->fbdev;
-+ enum omap_dss_rotation_type rot_type;
-+ int r;
-+
-+ rot_type = simple_strtoul(buf, NULL, 0);
-+
-+ if (rot_type != OMAP_DSS_ROT_DMA && rot_type != OMAP_DSS_ROT_VRFB)
-+ return -EINVAL;
-+
-+ omapfb_lock(fbdev);
-+
-+ r = 0;
-+ if (rot_type == ofbi->rotation_type)
-+ goto out;
-+
-+ r = -EBUSY;
-+ if (ofbi->region.size)
-+ goto out;
-+
-+ ofbi->rotation_type = rot_type;
-+
-+ /*
-+ * Since the VRAM for this FB is not allocated at the moment we don't need to
-+ * do any further parameter checking at this point.
-+ */
-+
-+ r = count;
-+out:
-+ omapfb_unlock(fbdev);
-+
-+ return r;
-+}
-+
-+
- static ssize_t show_mirror(struct device *dev,
- struct device_attribute *attr, char *buf)
- {
-@@ -327,7 +367,7 @@ static ssize_t show_virt(struct device *dev,
- }
-
- static struct device_attribute omapfb_attrs[] = {
-- __ATTR(rotate_type, S_IRUGO, show_rotate_type, NULL),
-+ __ATTR(rotate_type, S_IRUGO | S_IWUSR, show_rotate_type, store_rotate_type),
- __ATTR(mirror, S_IRUGO | S_IWUSR, show_mirror, store_mirror),
- __ATTR(size, S_IRUGO | S_IWUSR, show_size, store_size),
- __ATTR(overlays, S_IRUGO | S_IWUSR, show_overlays, store_overlays),
---
-1.6.2.4
-
+++ /dev/null
-From b0e081456a9b094109c04467d041ff693843ca47 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Tue, 21 Apr 2009 09:25:16 +0300
-Subject: [PATCH 45/69] DSS2: Fixed line endings from , to ;
-
----
- drivers/video/omap2/dss/manager.c | 18 +++++++++---------
- 1 files changed, 9 insertions(+), 9 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
-index 108489c..bf059e0 100644
---- a/drivers/video/omap2/dss/manager.c
-+++ b/drivers/video/omap2/dss/manager.c
-@@ -599,22 +599,22 @@ int dss_init_overlay_managers(struct platform_device *pdev)
- break;
- }
-
-- mgr->set_display = &omap_dss_set_display,
-- mgr->unset_display = &omap_dss_unset_display,
-- mgr->apply = &omap_dss_mgr_apply,
-- mgr->set_default_color = &omap_dss_mgr_set_def_color,
-+ mgr->set_display = &omap_dss_set_display;
-+ mgr->unset_display = &omap_dss_unset_display;
-+ mgr->apply = &omap_dss_mgr_apply;
-+ mgr->set_default_color = &omap_dss_mgr_set_def_color;
- mgr->set_trans_key_type_and_value =
-- &omap_dss_mgr_set_trans_key_type_and_value,
-+ &omap_dss_mgr_set_trans_key_type_and_value;
- mgr->get_trans_key_type_and_value =
-- &omap_dss_mgr_get_trans_key_type_and_value,
-- mgr->enable_trans_key = &omap_dss_mgr_enable_trans_key,
-- mgr->get_trans_key_status = &omap_dss_mgr_get_trans_key_status,
-+ &omap_dss_mgr_get_trans_key_type_and_value;
-+ mgr->enable_trans_key = &omap_dss_mgr_enable_trans_key;
-+ mgr->get_trans_key_status = &omap_dss_mgr_get_trans_key_status;
- mgr->enable_alpha_blending =
- &omap_dss_mgr_enable_alpha_blending;
- mgr->get_alpha_blending_status =
- omap_dss_mgr_get_alpha_blending_status;
- mgr->get_default_color = &omap_dss_mgr_get_default_color;
-- mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC,
-+ mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC;
-
- dss_overlay_setup_dispc_manager(mgr);
-
---
-1.6.2.4
-
+++ /dev/null
-From 0f88992b2681aed4f31dc7dd3926b357bbc95154 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Tue, 21 Apr 2009 10:11:55 +0300
-Subject: [PATCH 46/69] DSS2: DSI: decrease sync timeout from 60s to 2s
-
-The framedone-problem should be ok now, so we shouldn't get long waits.
----
- drivers/video/omap2/dss/dsi.c | 2 +-
- 1 files changed, 1 insertions(+), 1 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
-index 50af925..d59ad38 100644
---- a/drivers/video/omap2/dss/dsi.c
-+++ b/drivers/video/omap2/dss/dsi.c
-@@ -3216,7 +3216,7 @@ static void dsi_push_set_mirror(struct omap_display *display, int mirror)
-
- static int dsi_wait_sync(struct omap_display *display)
- {
-- long wait = msecs_to_jiffies(60000);
-+ long wait = msecs_to_jiffies(2000);
- struct completion compl;
-
- DSSDBGF("");
---
-1.6.2.4
-
+++ /dev/null
-From 7ddd5eaa7bc345c3719d613a46a95b7e8052ad2c Mon Sep 17 00:00:00 2001
-From: Imre Deak <imre.deak@nokia.com>
-Date: Tue, 21 Apr 2009 15:18:36 +0200
-Subject: [PATCH 47/69] DSS2: fix return value for rotate_type sysfs function
-
-Signed-off-by: Imre Deak <imre.deak@nokia.com>
----
- drivers/video/omap2/omapfb/omapfb-sysfs.c | 9 ++++-----
- 1 files changed, 4 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/video/omap2/omapfb/omapfb-sysfs.c b/drivers/video/omap2/omapfb/omapfb-sysfs.c
-index 4e3da42..13028ae 100644
---- a/drivers/video/omap2/omapfb/omapfb-sysfs.c
-+++ b/drivers/video/omap2/omapfb/omapfb-sysfs.c
-@@ -64,9 +64,10 @@ static ssize_t store_rotate_type(struct device *dev,
- if (rot_type == ofbi->rotation_type)
- goto out;
-
-- r = -EBUSY;
-- if (ofbi->region.size)
-+ if (ofbi->region.size) {
-+ r = -EBUSY;
- goto out;
-+ }
-
- ofbi->rotation_type = rot_type;
-
-@@ -74,12 +75,10 @@ static ssize_t store_rotate_type(struct device *dev,
- * Since the VRAM for this FB is not allocated at the moment we don't need to
- * do any further parameter checking at this point.
- */
--
-- r = count;
- out:
- omapfb_unlock(fbdev);
-
-- return r;
-+ return r ? r : count;
- }
-
-
---
-1.6.2.4
-
+++ /dev/null
-From e34564db95627ad20e918b240c45e2bd5555f7e8 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Wed, 22 Apr 2009 10:06:08 +0300
-Subject: [PATCH 48/69] OMAP2/3: DMA: implement trans copy and const fill
-
-Implement transparent copy and constant fill features for OMAP2/3.
-
-Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
----
- arch/arm/plat-omap/dma.c | 81 +++++++++++++++++++++------------
- arch/arm/plat-omap/include/mach/dma.h | 1 +
- 2 files changed, 52 insertions(+), 30 deletions(-)
-
-diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
-index 3fd0e77..060ac71 100755
---- a/arch/arm/plat-omap/dma.c
-+++ b/arch/arm/plat-omap/dma.c
-@@ -310,41 +310,62 @@ EXPORT_SYMBOL(omap_set_dma_transfer_params);
-
- void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
- {
-- u16 w;
--
- BUG_ON(omap_dma_in_1510_mode());
-
-- if (cpu_class_is_omap2()) {
-- REVISIT_24XX();
-- return;
-- }
-+ if (cpu_class_is_omap1()) {
-+ u16 w;
-
-- w = dma_read(CCR2(lch));
-- w &= ~0x03;
-+ w = dma_read(CCR2(lch));
-+ w &= ~0x03;
-
-- switch (mode) {
-- case OMAP_DMA_CONSTANT_FILL:
-- w |= 0x01;
-- break;
-- case OMAP_DMA_TRANSPARENT_COPY:
-- w |= 0x02;
-- break;
-- case OMAP_DMA_COLOR_DIS:
-- break;
-- default:
-- BUG();
-+ switch (mode) {
-+ case OMAP_DMA_CONSTANT_FILL:
-+ w |= 0x01;
-+ break;
-+ case OMAP_DMA_TRANSPARENT_COPY:
-+ w |= 0x02;
-+ break;
-+ case OMAP_DMA_COLOR_DIS:
-+ break;
-+ default:
-+ BUG();
-+ }
-+ dma_write(w, CCR2(lch));
-+
-+ w = dma_read(LCH_CTRL(lch));
-+ w &= ~0x0f;
-+ /* Default is channel type 2D */
-+ if (mode) {
-+ dma_write((u16)color, COLOR_L(lch));
-+ dma_write((u16)(color >> 16), COLOR_U(lch));
-+ w |= 1; /* Channel type G */
-+ }
-+ dma_write(w, LCH_CTRL(lch));
- }
-- dma_write(w, CCR2(lch));
-
-- w = dma_read(LCH_CTRL(lch));
-- w &= ~0x0f;
-- /* Default is channel type 2D */
-- if (mode) {
-- dma_write((u16)color, COLOR_L(lch));
-- dma_write((u16)(color >> 16), COLOR_U(lch));
-- w |= 1; /* Channel type G */
-+ if (cpu_class_is_omap2()) {
-+ u32 val;
-+
-+ val = dma_read(CCR(lch));
-+ val &= ~((1 << 17) | (1 << 16));
-+
-+ switch (mode) {
-+ case OMAP_DMA_CONSTANT_FILL:
-+ val |= 1 << 16;
-+ break;
-+ case OMAP_DMA_TRANSPARENT_COPY:
-+ val |= 1 << 17;
-+ break;
-+ case OMAP_DMA_COLOR_DIS:
-+ break;
-+ default:
-+ BUG();
-+ }
-+ dma_write(val, CCR(lch));
-+
-+ color &= 0xffffff;
-+ dma_write(color, COLOR(lch));
- }
-- dma_write(w, LCH_CTRL(lch));
- }
- EXPORT_SYMBOL(omap_set_dma_color_mode);
-
-diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/mach/dma.h
-index 224b077..4e34f47 100644
---- a/arch/arm/plat-omap/include/mach/dma.h
-+++ b/arch/arm/plat-omap/include/mach/dma.h
-@@ -144,6 +144,7 @@
- #define OMAP_DMA4_CSSA_U(n) 0
- #define OMAP_DMA4_CDSA_L(n) 0
- #define OMAP_DMA4_CDSA_U(n) 0
-+#define OMAP1_DMA_COLOR(n) 0
-
- /*----------------------------------------------------------------------------*/
-
---
-1.6.2.4
-
+++ /dev/null
-From 02034cc79f69512a6037f03ad1243c28f59fdd8a Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Wed, 22 Apr 2009 10:25:20 +0300
-Subject: [PATCH 49/69] DSS2: VRAM: clear allocated area with DMA
-
-Use DMA constant fill feature to clear VRAM area when
-someone allocates it.
----
- arch/arm/plat-omap/vram.c | 57 +++++++++++++++++++++++++++++++++++++++++++++
- 1 files changed, 57 insertions(+), 0 deletions(-)
-
-diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
-index 8e9fe77..90276ac 100644
---- a/arch/arm/plat-omap/vram.c
-+++ b/arch/arm/plat-omap/vram.c
-@@ -31,11 +31,13 @@
- #include <linux/seq_file.h>
- #include <linux/bootmem.h>
- #include <linux/omapfb.h>
-+#include <linux/completion.h>
-
- #include <asm/setup.h>
-
- #include <mach/sram.h>
- #include <mach/vram.h>
-+#include <mach/dma.h>
-
- #ifdef DEBUG
- #define DBG(format, ...) printk(KERN_DEBUG "VRAM: " format, ## __VA_ARGS__)
-@@ -276,6 +278,59 @@ int omap_vram_reserve(unsigned long paddr, size_t size)
- }
- EXPORT_SYMBOL(omap_vram_reserve);
-
-+static void _omap_vram_dma_cb(int lch, u16 ch_status, void *data)
-+{
-+ struct completion *compl = data;
-+ complete(compl);
-+}
-+
-+static int _omap_vram_clear(u32 paddr, unsigned pages)
-+{
-+ struct completion compl;
-+ unsigned elem_count;
-+ unsigned frame_count;
-+ int r;
-+ int lch;
-+
-+ init_completion(&compl);
-+
-+ r = omap_request_dma(OMAP_DMA_NO_DEVICE, "VRAM DMA",
-+ _omap_vram_dma_cb,
-+ &compl, &lch);
-+ if (r) {
-+ pr_err("VRAM: request_dma failed for memory clear\n");
-+ return -EBUSY;
-+ }
-+
-+ elem_count = pages * PAGE_SIZE / 4;
-+ frame_count = 1;
-+
-+ omap_set_dma_transfer_params(lch, OMAP_DMA_DATA_TYPE_S32,
-+ elem_count, frame_count,
-+ OMAP_DMA_SYNC_ELEMENT,
-+ 0, 0);
-+
-+ omap_set_dma_dest_params(lch, 0, OMAP_DMA_AMODE_POST_INC,
-+ paddr, 0, 0);
-+
-+ omap_set_dma_color_mode(lch, OMAP_DMA_CONSTANT_FILL, 0x000000);
-+
-+ omap_start_dma(lch);
-+
-+ if (wait_for_completion_timeout(&compl, msecs_to_jiffies(1000)) == 0) {
-+ omap_stop_dma(lch);
-+ pr_err("VRAM: dma timeout while clearing memory\n");
-+ r = -EIO;
-+ goto err;
-+ }
-+
-+ r = 0;
-+err:
-+ omap_free_dma(lch);
-+
-+ return r;
-+}
-+
- static int _omap_vram_alloc(int mtype, unsigned pages, unsigned long *paddr)
- {
- struct vram_region *rm;
-@@ -313,6 +368,8 @@ found:
-
- *paddr = start;
-
-+ _omap_vram_clear(start, pages);
-+
- return 0;
- }
-
---
-1.6.2.4
-
+++ /dev/null
-From 07482193cccdfe9ede1f47d72790dfbe54343505 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Wed, 22 Apr 2009 10:26:06 +0300
-Subject: [PATCH 50/69] DSS2: OMAPFB: remove fb clearing code
-
-VRAM manager does the clearing now when the area is allocated.
----
- drivers/video/omap2/omapfb/omapfb-main.c | 8 --------
- 1 files changed, 0 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
-index cd63740..76e7c6c 100644
---- a/drivers/video/omap2/omapfb/omapfb-main.c
-+++ b/drivers/video/omap2/omapfb/omapfb-main.c
-@@ -1174,7 +1174,6 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
- struct omapfb2_mem_region *rg;
- void __iomem *vaddr;
- int r;
-- int clear = 0;
-
- rg = &ofbi->region;
- memset(rg, 0, sizeof(*rg));
-@@ -1184,7 +1183,6 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
- if (!paddr) {
- DBG("allocating %lu bytes for fb %d\n", size, ofbi->id);
- r = omap_vram_alloc(OMAPFB_MEMTYPE_SDRAM, size, &paddr);
-- clear = 1;
- } else {
- DBG("reserving %lu bytes at %lx for fb %d\n", size, paddr,
- ofbi->id);
-@@ -1206,9 +1204,6 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
- }
-
- DBG("allocated VRAM paddr %lx, vaddr %p\n", paddr, vaddr);
--
-- if (clear)
-- memset_io(vaddr, 0, size);
- } else {
- void __iomem *va;
-
-@@ -1232,9 +1227,6 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
- rg->vrfb.vaddr[0] = va;
-
- vaddr = NULL;
--
-- if (clear)
-- memset_io(va, 0, size);
- }
-
- rg->paddr = paddr;
---
-1.6.2.4
-
+++ /dev/null
-From b47aef28536f3c276d232c41cd3084c69389dca4 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Wed, 22 Apr 2009 14:11:52 +0300
-Subject: [PATCH 51/69] DSS2: VRAM: use debugfs, not procfs
-
----
- arch/arm/plat-omap/vram.c | 103 +++++++++++++++------------------------------
- 1 files changed, 34 insertions(+), 69 deletions(-)
-
-diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
-index 90276ac..e847579 100644
---- a/arch/arm/plat-omap/vram.c
-+++ b/arch/arm/plat-omap/vram.c
-@@ -27,11 +27,11 @@
- #include <linux/mm.h>
- #include <linux/list.h>
- #include <linux/dma-mapping.h>
--#include <linux/proc_fs.h>
- #include <linux/seq_file.h>
- #include <linux/bootmem.h>
- #include <linux/omapfb.h>
- #include <linux/completion.h>
-+#include <linux/debugfs.h>
-
- #include <asm/setup.h>
-
-@@ -398,88 +398,54 @@ int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr)
- }
- EXPORT_SYMBOL(omap_vram_alloc);
-
--#ifdef CONFIG_PROC_FS
--static void *r_next(struct seq_file *m, void *v, loff_t *pos)
--{
-- struct list_head *l = v;
--
-- (*pos)++;
--
-- if (list_is_last(l, ®ion_list))
-- return NULL;
--
-- return l->next;
--}
--
--static void *r_start(struct seq_file *m, loff_t *pos)
--{
-- loff_t p = *pos;
-- struct list_head *l = ®ion_list;
--
-- mutex_lock(®ion_mutex);
--
-- do {
-- l = l->next;
-- if (l == ®ion_list)
-- return NULL;
-- } while (p--);
--
-- return l;
--}
--
--static void r_stop(struct seq_file *m, void *v)
--{
-- mutex_unlock(®ion_mutex);
--}
--
--static int r_show(struct seq_file *m, void *v)
-+#if defined(CONFIG_DEBUG_FS)
-+static int vram_debug_show(struct seq_file *s, void *unused)
- {
- struct vram_region *vr;
- struct vram_alloc *va;
- unsigned size;
-
-- vr = list_entry(v, struct vram_region, list);
--
-- size = vr->pages << PAGE_SHIFT;
--
-- seq_printf(m, "%08lx-%08lx (%d bytes)\n",
-- vr->paddr, vr->paddr + size - 1,
-- size);
-+ mutex_lock(®ion_mutex);
-
-- list_for_each_entry(va, &vr->alloc_list, list) {
-- size = va->pages << PAGE_SHIFT;
-- seq_printf(m, " %08lx-%08lx (%d bytes)\n",
-- va->paddr, va->paddr + size - 1,
-+ list_for_each_entry(vr, ®ion_list, list) {
-+ size = vr->pages << PAGE_SHIFT;
-+ seq_printf(s, "%08lx-%08lx (%d bytes)\n",
-+ vr->paddr, vr->paddr + size - 1,
- size);
-- }
-
-+ list_for_each_entry(va, &vr->alloc_list, list) {
-+ size = va->pages << PAGE_SHIFT;
-+ seq_printf(s, " %08lx-%08lx (%d bytes)\n",
-+ va->paddr, va->paddr + size - 1,
-+ size);
-+ }
-+ }
-
-+ mutex_unlock(®ion_mutex);
-
- return 0;
- }
-
--static const struct seq_operations resource_op = {
-- .start = r_start,
-- .next = r_next,
-- .stop = r_stop,
-- .show = r_show,
--};
--
--static int vram_open(struct inode *inode, struct file *file)
-+static int vram_debug_open(struct inode *inode, struct file *file)
- {
-- return seq_open(file, &resource_op);
-+ return single_open(file, vram_debug_show, inode->i_private);
- }
-
--static const struct file_operations proc_vram_operations = {
-- .open = vram_open,
-- .read = seq_read,
-- .llseek = seq_lseek,
-- .release = seq_release,
-+static const struct file_operations vram_debug_fops = {
-+ .open = vram_debug_open,
-+ .read = seq_read,
-+ .llseek = seq_lseek,
-+ .release = single_release,
- };
-
--static int __init omap_vram_create_proc(void)
-+static int __init omap_vram_create_debugfs(void)
- {
-- proc_create("omap-vram", 0, NULL, &proc_vram_operations);
-+ struct dentry *d;
-+
-+ d = debugfs_create_file("vram", S_IRUGO, NULL,
-+ NULL, &vram_debug_fops);
-+ if (IS_ERR(d))
-+ return PTR_ERR(d);
-
- return 0;
- }
-@@ -487,7 +453,7 @@ static int __init omap_vram_create_proc(void)
-
- static __init int omap_vram_init(void)
- {
-- int i, r;
-+ int i;
-
- vram_initialized = 1;
-
-@@ -495,10 +461,9 @@ static __init int omap_vram_init(void)
- omap_vram_add_region(postponed_regions[i].paddr,
- postponed_regions[i].size);
-
--#ifdef CONFIG_PROC_FS
-- r = omap_vram_create_proc();
-- if (r)
-- return -ENOMEM;
-+#ifdef CONFIG_DEBUG_FS
-+ if (omap_vram_create_debugfs())
-+ pr_err("VRAM: Failed to create debugfs file\n");
- #endif
-
- return 0;
---
-1.6.2.4
-
+++ /dev/null
-From 635fa66abe6e502c9b78b1dc66757bf67fd163e1 Mon Sep 17 00:00:00 2001
-From: Imre Deak <imre.deak@nokia.com>
-Date: Wed, 22 Apr 2009 14:40:48 +0200
-Subject: [PATCH 52/69] DSS2: VRAM: fix section mismatch warning
-
-postponed_regions are accessed from the non __init
-omap_vram_add_region().
-
-Signed-off-by: Imre Deak <imre.deak@nokia.com>
----
- arch/arm/plat-omap/vram.c | 4 ++--
- 1 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
-index e847579..b126a64 100644
---- a/arch/arm/plat-omap/vram.c
-+++ b/arch/arm/plat-omap/vram.c
-@@ -63,11 +63,11 @@
- #define MAX_POSTPONED_REGIONS 10
-
- static bool vram_initialized;
--static int postponed_cnt __initdata;
-+static int postponed_cnt;
- static struct {
- unsigned long paddr;
- size_t size;
--} postponed_regions[MAX_POSTPONED_REGIONS] __initdata;
-+} postponed_regions[MAX_POSTPONED_REGIONS];
-
- struct vram_alloc {
- struct list_head list;
---
-1.6.2.4
-
+++ /dev/null
-From c7ce3c5e9f7e28900b8ea9c3e1afe41dcdc0863d Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Thu, 23 Apr 2009 10:46:53 +0300
-Subject: [PATCH 53/69] DSS2: disable LCD & DIGIT before resetting DSS
-
-This seems to fix the synclost problem that we get, if the bootloader
-starts the DSS and the kernel resets it.
----
- drivers/video/omap2/dss/dss.c | 8 +++++---
- 1 files changed, 5 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
-index adc1f34..aab9758 100644
---- a/drivers/video/omap2/dss/dss.c
-+++ b/drivers/video/omap2/dss/dss.c
-@@ -285,6 +285,11 @@ int dss_init(bool skip_init)
- }
-
- if (!skip_init) {
-+ /* disable LCD and DIGIT output. This seems to fix the synclost
-+ * problem that we get, if the bootloader starts the DSS and
-+ * the kernel resets it */
-+ omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440);
-+
- /* We need to wait here a bit, otherwise we sometimes start to
- * get synclost errors, and after that only power cycle will
- * restore DSS functionality. I have no idea why this happens.
-@@ -294,10 +299,7 @@ int dss_init(bool skip_init)
- msleep(50);
-
- _omap_dss_reset();
--
- }
-- else
-- printk("DSS SKIP RESET\n");
-
- /* autoidle */
- REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
---
-1.6.2.4
-
+++ /dev/null
-From 3b27a3c4f6b84e46c84509f610dfe1456c0d72d3 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Mon, 27 Apr 2009 11:06:16 +0300
-Subject: [PATCH 54/69] DSS2: DSI: more error handling
-
----
- drivers/video/omap2/dss/dsi.c | 27 +++++++++++++++++++++++++++
- 1 files changed, 27 insertions(+), 0 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
-index d59ad38..d8df353 100644
---- a/drivers/video/omap2/dss/dsi.c
-+++ b/drivers/video/omap2/dss/dsi.c
-@@ -289,6 +289,8 @@ static struct
-
- bool autoupdate_setup;
-
-+ u32 errors;
-+ spinlock_t errors_lock;
- #ifdef DEBUG
- ktime_t perf_setup_time;
- ktime_t perf_start_time;
-@@ -541,6 +543,9 @@ void dsi_irq_handler(void)
- if (irqstatus & DSI_IRQ_ERROR_MASK) {
- DSSERR("DSI error, irqstatus %x\n", irqstatus);
- print_irq_status(irqstatus);
-+ spin_lock(&dsi.errors_lock);
-+ dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK;
-+ spin_unlock(&dsi.errors_lock);
- } else if (debug_irq) {
- print_irq_status(irqstatus);
- }
-@@ -616,6 +621,17 @@ static void _dsi_initialize_irq(void)
- -1 & (~DSI_CIO_IRQ_ERRCONTROL2));
- }
-
-+static u32 dsi_get_errors(void)
-+{
-+ unsigned long flags;
-+ u32 e;
-+ spin_lock_irqsave(&dsi.errors_lock, flags);
-+ e = dsi.errors;
-+ dsi.errors = 0;
-+ spin_unlock_irqrestore(&dsi.errors_lock, flags);
-+ return e;
-+}
-+
- static void dsi_vc_enable_bta_irq(int channel)
- {
- u32 l;
-@@ -1807,6 +1823,7 @@ static int dsi_vc_send_bta(int channel)
- static int dsi_vc_send_bta_sync(int channel)
- {
- int r = 0;
-+ u32 err;
-
- init_completion(&dsi.bta_completion);
-
-@@ -1822,6 +1839,13 @@ static int dsi_vc_send_bta_sync(int channel)
- r = -EIO;
- goto err;
- }
-+
-+ err = dsi_get_errors();
-+ if (err) {
-+ DSSERR("Error while sending BTA: %x\n", err);
-+ r = -EIO;
-+ goto err;
-+ }
- err:
- dsi_vc_disable_bta_irq(channel);
-
-@@ -3720,6 +3744,9 @@ int dsi_init(void)
- {
- u32 rev;
-
-+ spin_lock_init(&dsi.errors_lock);
-+ dsi.errors = 0;
-+
- spin_lock_init(&dsi.cmd_lock);
- dsi.cmd_fifo = kfifo_alloc(
- DSI_CMD_FIFO_LEN * sizeof(struct dsi_cmd_item),
---
-1.6.2.4
-
+++ /dev/null
-From c8588370442424ac31e2392b07891615629eb999 Mon Sep 17 00:00:00 2001
-From: Hardik Shah <hardik.shah@ti.com>
-Date: Fri, 24 Apr 2009 15:29:06 +0530
-Subject: [PATCH 55/69] DSS2: Added global alpha support.
-
-global_alpha sysfs entry for video1 plane will always show 255 as
-it does not support global_alpha.
-Initliazied the global alpha field for all the overlays
-to 255 (fully opaque).
-Documentation also updated.
-
-Signed-off-by: Hardik Shah <hardik.shah@ti.com>
----
- Documentation/arm/OMAP/DSS | 1 +
- arch/arm/plat-omap/include/mach/display.h | 1 +
- drivers/video/omap2/dss/dispc.c | 25 ++++++++++++++++---
- drivers/video/omap2/dss/dss.h | 3 +-
- drivers/video/omap2/dss/manager.c | 3 +-
- drivers/video/omap2/dss/overlay.c | 37 +++++++++++++++++++++++++++++
- 6 files changed, 64 insertions(+), 6 deletions(-)
-
-diff --git a/Documentation/arm/OMAP/DSS b/Documentation/arm/OMAP/DSS
-index 9e902a2..249e1a3 100644
---- a/Documentation/arm/OMAP/DSS
-+++ b/Documentation/arm/OMAP/DSS
-@@ -133,6 +133,7 @@ name
- output_size width,height
- position x,y
- screen_width width
-+global_alpha global alpha 0-255 0=transparent 255=opaque
-
- /sys/devices/platform/omapdss/manager? directory:
- display Destination display
-diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
-index d0b4c83..45b16ca 100644
---- a/arch/arm/plat-omap/include/mach/display.h
-+++ b/arch/arm/plat-omap/include/mach/display.h
-@@ -363,6 +363,7 @@ struct omap_overlay_info {
- u16 pos_y;
- u16 out_width; /* if 0, out_width == width */
- u16 out_height; /* if 0, out_height == height */
-+ u8 global_alpha;
- };
-
- enum omap_overlay_caps {
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-index 9bab6cf..b6a39f5 100644
---- a/drivers/video/omap2/dss/dispc.c
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -778,6 +778,17 @@ static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
- dispc_write_reg(vsi_reg[plane-1], val);
- }
-
-+static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
-+{
-+
-+ BUG_ON(plane == OMAP_DSS_VIDEO1);
-+
-+ if (plane == OMAP_DSS_GFX)
-+ REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
-+ else if (plane == OMAP_DSS_VIDEO2)
-+ REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
-+}
-+
- static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
- {
- const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
-@@ -1444,7 +1455,8 @@ static int _dispc_setup_plane(enum omap_plane plane,
- enum omap_color_mode color_mode,
- bool ilace,
- enum omap_dss_rotation_type rotation_type,
-- u8 rotation, int mirror)
-+ u8 rotation, int mirror,
-+ u8 global_alpha)
- {
- const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
- bool five_taps = 0;
-@@ -1592,6 +1604,9 @@ static int _dispc_setup_plane(enum omap_plane plane,
-
- _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
-
-+ if (plane != OMAP_DSS_VIDEO1)
-+ _dispc_setup_global_alpha(plane, global_alpha);
-+
- return 0;
- }
-
-@@ -3011,7 +3026,7 @@ int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
- enum omap_color_mode color_mode,
- bool ilace,
- enum omap_dss_rotation_type rotation_type,
-- u8 rotation, bool mirror)
-+ u8 rotation, bool mirror, u8 global_alpha)
- {
- int r = 0;
-
-@@ -3032,7 +3047,8 @@ int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
- out_width, out_height,
- color_mode, ilace,
- rotation_type,
-- rotation, mirror);
-+ rotation, mirror,
-+ global_alpha);
-
- enable_clocks(0);
-
-@@ -3247,7 +3263,8 @@ void dispc_setup_partial_planes(struct omap_display *display,
- pi->color_mode, 0,
- pi->rotation_type,
- pi->rotation,
-- pi->mirror);
-+ pi->mirror,
-+ pi->global_alpha);
-
- dispc_enable_plane(ovl->id, 1);
- }
-diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
-index 1d01ff6..20cef0a 100644
---- a/drivers/video/omap2/dss/dss.h
-+++ b/drivers/video/omap2/dss/dss.h
-@@ -273,7 +273,8 @@ int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
- enum omap_color_mode color_mode,
- bool ilace,
- enum omap_dss_rotation_type rotation_type,
-- u8 rotation, bool mirror);
-+ u8 rotation, bool mirror,
-+ u8 global_alpha);
-
- void dispc_go(enum omap_channel channel);
- void dispc_enable_lcd_out(bool enable);
-diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
-index bf059e0..1e6cd8d 100644
---- a/drivers/video/omap2/dss/manager.c
-+++ b/drivers/video/omap2/dss/manager.c
-@@ -464,7 +464,8 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
- ilace,
- ovl->info.rotation_type,
- ovl->info.rotation,
-- ovl->info.mirror);
-+ ovl->info.mirror,
-+ ovl->info.global_alpha);
-
- if (r) {
- DSSERR("dispc_setup_plane failed for ovl %d\n",
-diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c
-index c047206..035a57a 100644
---- a/drivers/video/omap2/dss/overlay.c
-+++ b/drivers/video/omap2/dss/overlay.c
-@@ -194,6 +194,37 @@ static ssize_t overlay_enabled_store(struct omap_overlay *ovl, const char *buf,
- return size;
- }
-
-+static ssize_t overlay_global_alpha_show(struct omap_overlay *ovl, char *buf)
-+{
-+ return snprintf(buf, PAGE_SIZE, "%d\n",
-+ ovl->info.global_alpha);
-+}
-+
-+static ssize_t overlay_global_alpha_store(struct omap_overlay *ovl,
-+ const char *buf, size_t size)
-+{
-+ int r;
-+ struct omap_overlay_info info;
-+
-+ ovl->get_overlay_info(ovl, &info);
-+
-+ /* Video1 plane does not support global alpha
-+ * to always make it 255 completely opaque
-+ */
-+ if (ovl->id == OMAP_DSS_VIDEO1)
-+ info.global_alpha = 255;
-+ else
-+ info.global_alpha = simple_strtoul(buf, NULL, 10);
-+
-+ if ((r = ovl->set_overlay_info(ovl, &info)))
-+ return r;
-+
-+ if (ovl->manager && (r = ovl->manager->apply(ovl->manager)))
-+ return r;
-+
-+ return size;
-+}
-+
- struct overlay_attribute {
- struct attribute attr;
- ssize_t (*show)(struct omap_overlay *, char *);
-@@ -215,6 +246,8 @@ static OVERLAY_ATTR(output_size, S_IRUGO|S_IWUSR,
- overlay_output_size_show, overlay_output_size_store);
- static OVERLAY_ATTR(enabled, S_IRUGO|S_IWUSR,
- overlay_enabled_show, overlay_enabled_store);
-+static OVERLAY_ATTR(global_alpha, S_IRUGO|S_IWUSR,
-+ overlay_global_alpha_show, overlay_global_alpha_store);
-
- static struct attribute *overlay_sysfs_attrs[] = {
- &overlay_attr_name.attr,
-@@ -224,6 +257,7 @@ static struct attribute *overlay_sysfs_attrs[] = {
- &overlay_attr_position.attr,
- &overlay_attr_output_size.attr,
- &overlay_attr_enabled.attr,
-+ &overlay_attr_global_alpha.attr,
- NULL
- };
-
-@@ -444,6 +478,7 @@ void dss_init_overlays(struct platform_device *pdev, const char *def_disp_name)
- ovl->id = OMAP_DSS_GFX;
- ovl->supported_modes = OMAP_DSS_COLOR_GFX_OMAP3;
- ovl->caps = OMAP_DSS_OVL_CAP_DISPC;
-+ ovl->info.global_alpha = 255;
- break;
- case 1:
- ovl->name = "vid1";
-@@ -451,6 +486,7 @@ void dss_init_overlays(struct platform_device *pdev, const char *def_disp_name)
- ovl->supported_modes = OMAP_DSS_COLOR_VID_OMAP3;
- ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
- OMAP_DSS_OVL_CAP_DISPC;
-+ ovl->info.global_alpha = 255;
- break;
- case 2:
- ovl->name = "vid2";
-@@ -458,6 +494,7 @@ void dss_init_overlays(struct platform_device *pdev, const char *def_disp_name)
- ovl->supported_modes = OMAP_DSS_COLOR_VID_OMAP3;
- ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
- OMAP_DSS_OVL_CAP_DISPC;
-+ ovl->info.global_alpha = 255;
- break;
- }
-
---
-1.6.2.4
-
+++ /dev/null
-From 32cf39c92dfd28e18936c31eea90b4d43a3c0968 Mon Sep 17 00:00:00 2001
-From: Hardik Shah <hardik.shah@ti.com>
-Date: Fri, 24 Apr 2009 14:33:48 +0530
-Subject: [PATCH 56/69] DSS2: Rotation attrs for YUV need not to be reversed for 90 and 270
-
-DSS2 supports horizontal mirroing. so only 180 and 0 degree attributes needs
-to be reversed for mirroring.
-Slight corrupt image is seen with 90 ad 270 degree rotation with mirroring
-when the image height and widht is not 32-pixels aligned. To be specific
-resolution is 168X192.
-
-Signed-off-by: Hardik Shah <hardik.shah@ti.com>
----
- drivers/video/omap2/dss/dispc.c | 4 ++--
- 1 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-index b6a39f5..f79decb 100644
---- a/drivers/video/omap2/dss/dispc.c
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -1110,9 +1110,9 @@ static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
- if (mirroring) {
- switch (rotation) {
- case 0: vidrot = 2; break;
-- case 1: vidrot = 3; break;
-+ case 1: vidrot = 1; break;
- case 2: vidrot = 0; break;
-- case 3: vidrot = 1; break;
-+ case 3: vidrot = 3; break;
- }
- } else {
- switch (rotation) {
---
-1.6.2.4
-
+++ /dev/null
-From bc67f1fce4472087014fdacd3f44ea732200533e Mon Sep 17 00:00:00 2001
-From: Hardik Shah <hardik.shah@ti.com>
-Date: Mon, 27 Apr 2009 13:15:07 +0530
-Subject: [PATCH 57/69] DSS2: Documentation update for new sysfs entries in omapdss/manager
-
-Signed-off-by: Hardik Shah <hardik.shah@ti.com>
----
- Documentation/arm/OMAP/DSS | 7 ++++++-
- 1 files changed, 6 insertions(+), 1 deletions(-)
-
-diff --git a/Documentation/arm/OMAP/DSS b/Documentation/arm/OMAP/DSS
-index 249e1a3..751000b 100644
---- a/Documentation/arm/OMAP/DSS
-+++ b/Documentation/arm/OMAP/DSS
-@@ -136,8 +136,13 @@ screen_width width
- global_alpha global alpha 0-255 0=transparent 255=opaque
-
- /sys/devices/platform/omapdss/manager? directory:
--display Destination display
-+display Destination display
- name
-+alpha_blending_enabled 0=off 1=on
-+color_key_enabled 0=off 1=on
-+color_key_type gfx-destination video-source
-+color_key_value 0 to 2^24
-+default_color default background color RGB24 0 to 2^24
-
- /sys/devices/platform/omapdss/display? directory:
- ctrl_name Controller name
---
-1.6.2.4
-
+++ /dev/null
-From 9500c899f05048d17ced4340ecfd377656a23934 Mon Sep 17 00:00:00 2001
-From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
-Date: Fri, 17 Apr 2009 18:34:33 +0200
-Subject: [PATCH 58/69] DSS2: Don't touch plane coordinates when changing fb->ovl mapping
-MIME-Version: 1.0
-Content-Type: text/plain; charset=utf-8
-Content-Transfer-Encoding: 8bit
-
-When attaching overlays to a framebuffer via the 'overlays' sysfs file
-do not touch the planes' coordinates. Without this change attaching
-VID2 to a framebuffer which already has VID1 attached would cause VID1
-to be reset to position 0,0 and scaled to 1:1 size. Also call
-omapfb_apply_changes() only once after all the overlays have been
-attached to avoid fiddling with all the overlays several times.
-
-Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
----
- drivers/video/omap2/omapfb/omapfb-sysfs.c | 13 ++++++-------
- 1 files changed, 6 insertions(+), 7 deletions(-)
-
-diff --git a/drivers/video/omap2/omapfb/omapfb-sysfs.c b/drivers/video/omap2/omapfb/omapfb-sysfs.c
-index 13028ae..702199d 100644
---- a/drivers/video/omap2/omapfb/omapfb-sysfs.c
-+++ b/drivers/video/omap2/omapfb/omapfb-sysfs.c
-@@ -183,6 +183,7 @@ static ssize_t store_overlays(struct device *dev, struct device_attribute *attr,
- struct omap_overlay *ovl;
- int num_ovls, r, i;
- int len;
-+ bool added = false;
-
- num_ovls = 0;
-
-@@ -284,15 +285,13 @@ static ssize_t store_overlays(struct device *dev, struct device_attribute *attr,
-
- ofbi->overlays[ofbi->num_overlays++] = ovl;
-
-- r = omapfb_apply_changes(fbi, 1);
-+ added = true;
-+ }
-+
-+ if (added) {
-+ r = omapfb_apply_changes(fbi, 0);
- if (r)
- goto out;
--
-- if (ovl->manager) {
-- r = ovl->manager->apply(ovl->manager);
-- if (r)
-- goto out;
-- }
- }
-
- r = count;
---
-1.6.2.4
-
+++ /dev/null
-From 750f7ddc0881834f3400c40e9a59d11f9427cf99 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Wed, 29 Apr 2009 17:26:30 +0300
-Subject: [PATCH 59/69] DSS2: DSI: configure ENTER/EXIT_HS_MODE_LATENCY
-
----
- drivers/video/omap2/dss/dsi.c | 49 ++++++++++++++++++++++++++++++++--------
- 1 files changed, 39 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
-index d8df353..5225ed6 100644
---- a/drivers/video/omap2/dss/dsi.c
-+++ b/drivers/video/omap2/dss/dsi.c
-@@ -2309,15 +2309,26 @@ static int dsi_proto_config(struct omap_display *display)
- return 0;
- }
-
--static void dsi_proto_timings(void)
--{
-- int tlpx_half, tclk_zero, tclk_prepare, tclk_trail;
-- int tclk_pre, tclk_post;
-- int ddr_clk_pre, ddr_clk_post;
-+static void dsi_proto_timings(struct omap_display *display)
-+{
-+ unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
-+ unsigned tclk_pre, tclk_post;
-+ unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
-+ unsigned ths_trail, ths_exit;
-+ unsigned ddr_clk_pre, ddr_clk_post;
-+ unsigned enter_hs_mode_lat, exit_hs_mode_lat;
-+ unsigned ths_eot;
- u32 r;
-
-+ r = dsi_read_reg(DSI_DSIPHY_CFG0);
-+ ths_prepare = FLD_GET(r, 31, 24);
-+ ths_prepare_ths_zero = FLD_GET(r, 23, 16);
-+ ths_zero = ths_prepare_ths_zero - ths_prepare;
-+ ths_trail = FLD_GET(r, 15, 8);
-+ ths_exit = FLD_GET(r, 7, 0);
-+
- r = dsi_read_reg(DSI_DSIPHY_CFG1);
-- tlpx_half = FLD_GET(r, 22, 16);
-+ tlpx = FLD_GET(r, 22, 16) * 2;
- tclk_trail = FLD_GET(r, 15, 8);
- tclk_zero = FLD_GET(r, 7, 0);
-
-@@ -2329,17 +2340,35 @@ static void dsi_proto_timings(void)
- /* min 60ns + 52*UI */
- tclk_post = ns2ddr(60) + 26;
-
-- ddr_clk_pre = (tclk_pre + tlpx_half*2 + tclk_zero + tclk_prepare) / 4;
-- ddr_clk_post = (tclk_post + tclk_trail) / 4;
-+ ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
-+ 4);
-+ ddr_clk_post = DIV_ROUND_UP(tclk_post + tclk_trail, 4);
-
- r = dsi_read_reg(DSI_CLK_TIMING);
- r = FLD_MOD(r, ddr_clk_pre, 15, 8);
- r = FLD_MOD(r, ddr_clk_post, 7, 0);
- dsi_write_reg(DSI_CLK_TIMING, r);
-
-- DSSDBG("ddr_clk_pre %d, ddr_clk_post %d\n",
-+ DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
- ddr_clk_pre,
- ddr_clk_post);
-+
-+ /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
-+ if (display->hw_config.u.dsi.data1_lane != 0 &&
-+ display->hw_config.u.dsi.data2_lane != 0)
-+ ths_eot = 2;
-+ else
-+ ths_eot = 4;
-+
-+ enter_hs_mode_lat = DIV_ROUND_UP(tlpx + ths_prepare + ths_zero, 4) + 4;
-+ exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
-+
-+ r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
-+ FLD_VAL(exit_hs_mode_lat, 15, 0);
-+ dsi_write_reg(DSI_VM_TIMING7, r);
-+
-+ DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
-+ enter_hs_mode_lat, exit_hs_mode_lat);
- }
-
-
-@@ -3340,7 +3369,7 @@ static int dsi_display_init_dsi(struct omap_display *display)
-
- _dsi_print_reset_status();
-
-- dsi_proto_timings();
-+ dsi_proto_timings(display);
- dsi_set_lp_clk_divisor();
-
- if (1)
---
-1.6.2.4
-
+++ /dev/null
-From 233a6e4f4ccaf5827f04ab38c590397755e61ecb Mon Sep 17 00:00:00 2001
-From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
-Date: Mon, 4 May 2009 16:18:30 +0200
-Subject: [PATCH 60/69] DSS2: Avoid div by zero when calculating required fclk
-MIME-Version: 1.0
-Content-Type: text/plain; charset=utf-8
-Content-Transfer-Encoding: 8bit
-
-When calculating the required fclk rate for five tap filtering if the
-display width and output width are equal div by zero could occur. The
-TRM doesn't actually specify how this case should be handled but for
-now just skip the calculation which would trigger the div by zero.
-
-Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
----
- drivers/video/omap2/dss/dispc.c | 2 +-
- 1 files changed, 1 insertions(+), 1 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-index f79decb..5fc9457 100644
---- a/drivers/video/omap2/dss/dispc.c
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -1399,7 +1399,7 @@ static unsigned long calc_fclk_five_taps(u16 width, u16 height,
- do_div(tmp, 2 * out_height * ppl);
- fclk = tmp;
-
-- if (height > 2 * out_height) {
-+ if (height > 2 * out_height && ppl != out_width) {
- tmp = pclk * (height - 2 * out_height) * out_width;
- do_div(tmp, 2 * out_height * (ppl - out_width));
- fclk = max(fclk, (u32) tmp);
---
-1.6.2.4
-
+++ /dev/null
-From e58576ceca922bfe4c793e6f77a873c4ea14f768 Mon Sep 17 00:00:00 2001
-From: Imre Deak <imre.deak@nokia.com>
-Date: Tue, 5 May 2009 09:05:12 +0300
-Subject: [PATCH 61/69] DSS2: VRFB: save / restore context
-
-The VRFB is part of the SMS and supplied by the core power domain; do
-the context saving while VRFB is configured and restore it along with
-the rest of the domain context.
-
-This patch only implements the restore functionality, but not the
-actual call to the restore. That belongs to PM functionality.
----
- arch/arm/plat-omap/include/mach/vrfb.h | 1 +
- arch/arm/plat-omap/vrfb.c | 50 ++++++++++++++++++++++++++-----
- 2 files changed, 43 insertions(+), 8 deletions(-)
-
-diff --git a/arch/arm/plat-omap/include/mach/vrfb.h b/arch/arm/plat-omap/include/mach/vrfb.h
-index 12c7fab..ee6c062 100644
---- a/arch/arm/plat-omap/include/mach/vrfb.h
-+++ b/arch/arm/plat-omap/include/mach/vrfb.h
-@@ -44,5 +44,6 @@ extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
- extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
- u16 width, u16 height,
- enum omap_color_mode color_mode);
-+extern void omap_vrfb_restore_context(void);
-
- #endif /* __VRFB_H */
-diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
-index 2ae0d68..649803e 100644
---- a/arch/arm/plat-omap/vrfb.c
-+++ b/arch/arm/plat-omap/vrfb.c
-@@ -39,6 +39,33 @@
- /* bitmap of reserved contexts */
- static unsigned ctx_map;
-
-+/*
-+ * Access to this happens from client drivers or the PM core after wake-up.
-+ * For the first case we require locking at the driver level, for the second
-+ * we don't need locking, since no drivers will run until after the wake-up
-+ * has finished.
-+ */
-+struct {
-+ u32 physical_ba;
-+ u32 control;
-+ u32 size;
-+} vrfb_hw_context[VRFB_NUM_CTXS];
-+
-+void omap_vrfb_restore_context(void)
-+{
-+ int i;
-+
-+ for (i = 0; i < VRFB_NUM_CTXS; i++) {
-+ /* Restore only the active contexts */
-+ if (!(ctx_map & (1 << i)))
-+ continue;
-+ omap_writel(vrfb_hw_context[i].control, SMS_ROT_CONTROL(i));
-+ omap_writel(vrfb_hw_context[i].size, SMS_ROT_SIZE(i));
-+ omap_writel(vrfb_hw_context[i].physical_ba,
-+ SMS_ROT_PHYSICAL_BA(i));
-+ }
-+}
-+
- void omap_vrfb_adjust_size(u16 *width, u16 *height,
- u8 bytespp)
- {
-@@ -56,6 +83,8 @@ void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
- u16 vrfb_height;
- u8 ctx = vrfb->context;
- u8 bytespp;
-+ u32 size;
-+ u32 control;
-
- DBG("omapfb_set_vrfb(%d, %lx, %dx%d, %d)\n", ctx, paddr,
- width, height, bytespp);
-@@ -100,15 +129,20 @@ void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
-
- DBG("vrfb w %u, h %u\n", vrfb_width, vrfb_height);
-
-+ size = vrfb_width << SMS_IMAGEWIDTH_OFFSET;
-+ size |= vrfb_height << SMS_IMAGEHEIGHT_OFFSET;
-+
-+ control = pixel_size_exp << SMS_PS_OFFSET;
-+ control |= VRFB_PAGE_WIDTH_EXP << SMS_PW_OFFSET;
-+ control |= VRFB_PAGE_HEIGHT_EXP << SMS_PH_OFFSET;
-+
-+ vrfb_hw_context[ctx].physical_ba = paddr;
-+ vrfb_hw_context[ctx].size = size;
-+ vrfb_hw_context[ctx].control = control;
-+
- omap_writel(paddr, SMS_ROT_PHYSICAL_BA(ctx));
-- omap_writel((vrfb_width << SMS_IMAGEWIDTH_OFFSET) |
-- (vrfb_height << SMS_IMAGEHEIGHT_OFFSET),
-- SMS_ROT_SIZE(ctx));
--
-- omap_writel(pixel_size_exp << SMS_PS_OFFSET |
-- VRFB_PAGE_WIDTH_EXP << SMS_PW_OFFSET |
-- VRFB_PAGE_HEIGHT_EXP << SMS_PH_OFFSET,
-- SMS_ROT_CONTROL(ctx));
-+ omap_writel(size, SMS_ROT_SIZE(ctx));
-+ omap_writel(control, SMS_ROT_CONTROL(ctx));
-
- DBG("vrfb offset pixels %d, %d\n",
- vrfb_width - width, vrfb_height - height);
---
-1.6.2.4
-
+++ /dev/null
-From 0fb6754f996b5022e1d856fda3d3258382383596 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Wed, 6 May 2009 09:03:43 +0300
-Subject: [PATCH 62/69] DSS2: VRAM: Fix indentation
-
----
- arch/arm/plat-omap/vram.c | 26 +++++++++++++-------------
- 1 files changed, 13 insertions(+), 13 deletions(-)
-
-diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
-index b126a64..f3ce849 100644
---- a/arch/arm/plat-omap/vram.c
-+++ b/arch/arm/plat-omap/vram.c
-@@ -287,35 +287,35 @@ static void _omap_vram_dma_cb(int lch, u16 ch_status, void *data)
- static int _omap_vram_clear(u32 paddr, unsigned pages)
- {
- struct completion compl;
-- unsigned elem_count;
-- unsigned frame_count;
-+ unsigned elem_count;
-+ unsigned frame_count;
- int r;
- int lch;
-
- init_completion(&compl);
-
-- r = omap_request_dma(OMAP_DMA_NO_DEVICE, "VRAM DMA",
-+ r = omap_request_dma(OMAP_DMA_NO_DEVICE, "VRAM DMA",
- _omap_vram_dma_cb,
-- &compl, &lch);
-- if (r) {
-+ &compl, &lch);
-+ if (r) {
- pr_err("VRAM: request_dma failed for memory clear\n");
- return -EBUSY;
- }
-
-- elem_count = pages * PAGE_SIZE / 4;
-- frame_count = 1;
-+ elem_count = pages * PAGE_SIZE / 4;
-+ frame_count = 1;
-
-- omap_set_dma_transfer_params(lch, OMAP_DMA_DATA_TYPE_S32,
-- elem_count, frame_count,
-- OMAP_DMA_SYNC_ELEMENT,
-- 0, 0);
-+ omap_set_dma_transfer_params(lch, OMAP_DMA_DATA_TYPE_S32,
-+ elem_count, frame_count,
-+ OMAP_DMA_SYNC_ELEMENT,
-+ 0, 0);
-
-- omap_set_dma_dest_params(lch, 0, OMAP_DMA_AMODE_POST_INC,
-+ omap_set_dma_dest_params(lch, 0, OMAP_DMA_AMODE_POST_INC,
- paddr, 0, 0);
-
- omap_set_dma_color_mode(lch, OMAP_DMA_CONSTANT_FILL, 0x000000);
-
-- omap_start_dma(lch);
-+ omap_start_dma(lch);
-
- if (wait_for_completion_timeout(&compl, msecs_to_jiffies(1000)) == 0) {
- omap_stop_dma(lch);
---
-1.6.2.4
-
+++ /dev/null
-From 5d3426ae63c27b9405be8179beabe1e095b44a35 Mon Sep 17 00:00:00 2001
-From: Imre Deak <imre.deak@nokia.com>
-Date: Tue, 5 May 2009 19:00:19 +0200
-Subject: [PATCH 63/69] DSS2: fix the usage of get_last_off_on_transaction_id
-
-The function returns int not unsigned since it can fail. Handle the
-failing case as if the context had been lost. So now:
-
-1. No get_last_off_on_transaction_id func in platform data->
- never restore the context
-2. Return val < 0 -> force the restore
-3. Return val >= 0 do the restore only if the counter has changed.
-
-Signed-off-by: Imre Deak <imre.deak@nokia.com>
----
- arch/arm/plat-omap/include/mach/display.h | 2 +-
- drivers/video/omap2/dss/core.c | 18 ++++++++++++------
- 2 files changed, 13 insertions(+), 7 deletions(-)
-
-diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
-index 45b16ca..31ebb96 100644
---- a/arch/arm/plat-omap/include/mach/display.h
-+++ b/arch/arm/plat-omap/include/mach/display.h
-@@ -234,7 +234,7 @@ struct device;
-
- /* Board specific data */
- struct omap_dss_board_info {
-- unsigned (*get_last_off_on_transaction_id)(struct device *dev);
-+ int (*get_last_off_on_transaction_id)(struct device *dev);
- int (*dsi_power_up)(void);
- void (*dsi_power_down)(void);
- int num_displays;
-diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c
-index ae7cd06..6d11b04 100644
---- a/drivers/video/omap2/dss/core.c
-+++ b/drivers/video/omap2/dss/core.c
-@@ -38,7 +38,7 @@
-
- static struct {
- struct platform_device *pdev;
-- unsigned ctx_id;
-+ int ctx_id;
-
- struct clk *dss_ick;
- struct clk *dss1_fck;
-@@ -63,22 +63,28 @@ module_param_named(debug, dss_debug, bool, 0644);
- #endif
-
- /* CONTEXT */
--static unsigned dss_get_ctx_id(void)
-+static int dss_get_ctx_id(void)
- {
- struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
-+ int r;
-
- if (!pdata->get_last_off_on_transaction_id)
- return 0;
--
-- return pdata->get_last_off_on_transaction_id(&core.pdev->dev);
-+ r = pdata->get_last_off_on_transaction_id(&core.pdev->dev);
-+ if (r < 0) {
-+ dev_err(&core.pdev->dev,
-+ "getting transaction ID failed, will force context restore\n");
-+ r = -1;
-+ }
-+ return r;
- }
-
- int dss_need_ctx_restore(void)
- {
- int id = dss_get_ctx_id();
-
-- if (id != core.ctx_id) {
-- DSSDBG("ctx id %u -> id %u\n",
-+ if (id < 0 || id != core.ctx_id) {
-+ DSSDBG("ctx id %d -> id %d\n",
- core.ctx_id, id);
- core.ctx_id = id;
- return 1;
---
-1.6.2.4
-
+++ /dev/null
-From 784271e9546844c5e69ec6d8f2fd3713847b6ab2 Mon Sep 17 00:00:00 2001
-From: Imre Deak <imre.deak@nokia.com>
-Date: Tue, 5 May 2009 11:16:14 +0200
-Subject: [PATCH 64/69] VRFB: fix debug messages
-
-Signed-off-by: Imre Deak <imre.deak@nokia.com>
----
- arch/arm/plat-omap/vrfb.c | 4 ++--
- 1 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
-index 649803e..289fc8a 100644
---- a/arch/arm/plat-omap/vrfb.c
-+++ b/arch/arm/plat-omap/vrfb.c
-@@ -87,7 +87,7 @@ void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
- u32 control;
-
- DBG("omapfb_set_vrfb(%d, %lx, %dx%d, %d)\n", ctx, paddr,
-- width, height, bytespp);
-+ width, height, color_mode);
-
- switch (color_mode) {
- case OMAP_DSS_COLOR_RGB16:
-@@ -127,7 +127,7 @@ void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
- vrfb_width = ALIGN(width * bytespp, VRFB_PAGE_WIDTH) / bytespp;
- vrfb_height = ALIGN(height, VRFB_PAGE_HEIGHT);
-
-- DBG("vrfb w %u, h %u\n", vrfb_width, vrfb_height);
-+ DBG("vrfb w %u, h %u bytespp %d\n", vrfb_width, vrfb_height, bytespp);
-
- size = vrfb_width << SMS_IMAGEWIDTH_OFFSET;
- size |= vrfb_height << SMS_IMAGEHEIGHT_OFFSET;
---
-1.6.2.4
-
+++ /dev/null
-From 1269429fe6ddd6e5f15e3b4edb4fc2bcd6fc0410 Mon Sep 17 00:00:00 2001
-From: Imre Deak <imre.deak@nokia.com>
-Date: Tue, 5 May 2009 11:16:13 +0200
-Subject: [PATCH 65/69] VRFB: add suspend/resume functionality
-
-At the moment the VRFB context is restored at each core power domain
-OFF->ON transition. This is not optimal since the VRFB might be unused
-temporarily for example when the screen is blanked. Add a suspend /
-resume function to mark these unused periods during which we'll avoid
-thea the context restore.
-
-Use atomic bitops for ctx_map for consistency.
-
-Signed-off-by: Imre Deak <imre.deak@nokia.com>
----
- arch/arm/plat-omap/include/mach/vrfb.h | 2 +
- arch/arm/plat-omap/vrfb.c | 75 ++++++++++++++++++++++++-----
- drivers/video/omap2/omapfb/omapfb-main.c | 28 +++++++++++
- 3 files changed, 92 insertions(+), 13 deletions(-)
-
-diff --git a/arch/arm/plat-omap/include/mach/vrfb.h b/arch/arm/plat-omap/include/mach/vrfb.h
-index ee6c062..9647d82 100644
---- a/arch/arm/plat-omap/include/mach/vrfb.h
-+++ b/arch/arm/plat-omap/include/mach/vrfb.h
-@@ -39,6 +39,8 @@ struct vrfb
-
- extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
- extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
-+extern void omap_vrfb_suspend_ctx(struct vrfb *vrfb);
-+extern void omap_vrfb_resume_ctx(struct vrfb *vrfb);
- extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
- u8 bytespp);
- extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
-diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
-index 289fc8a..29f04e2 100644
---- a/arch/arm/plat-omap/vrfb.c
-+++ b/arch/arm/plat-omap/vrfb.c
-@@ -1,7 +1,9 @@
- #include <linux/kernel.h>
- #include <linux/module.h>
- #include <linux/ioport.h>
-+
- #include <asm/io.h>
-+#include <asm/bitops.h>
-
- #include <mach/io.h>
- #include <mach/vrfb.h>
-@@ -37,7 +39,9 @@
-
- #define VRFB_NUM_CTXS 12
- /* bitmap of reserved contexts */
--static unsigned ctx_map;
-+static unsigned long ctx_map;
-+/* bitmap of contexts for which we have to keep the HW context valid */
-+static unsigned long ctx_map_active;
-
- /*
- * Access to this happens from client drivers or the PM core after wake-up.
-@@ -51,18 +55,23 @@ struct {
- u32 size;
- } vrfb_hw_context[VRFB_NUM_CTXS];
-
-+static void inline restore_hw_context(int ctx)
-+{
-+ omap_writel(vrfb_hw_context[ctx].control, SMS_ROT_CONTROL(ctx));
-+ omap_writel(vrfb_hw_context[ctx].size, SMS_ROT_SIZE(ctx));
-+ omap_writel(vrfb_hw_context[ctx].physical_ba, SMS_ROT_PHYSICAL_BA(ctx));
-+}
-+
- void omap_vrfb_restore_context(void)
- {
- int i;
-+ unsigned long map = ctx_map_active;
-
-- for (i = 0; i < VRFB_NUM_CTXS; i++) {
-- /* Restore only the active contexts */
-- if (!(ctx_map & (1 << i)))
-- continue;
-- omap_writel(vrfb_hw_context[i].control, SMS_ROT_CONTROL(i));
-- omap_writel(vrfb_hw_context[i].size, SMS_ROT_SIZE(i));
-- omap_writel(vrfb_hw_context[i].physical_ba,
-- SMS_ROT_PHYSICAL_BA(i));
-+ for (i = ffs(map); i; i = ffs(map)) {
-+ /* i=1..32 */
-+ i--;
-+ map &= ~(1 << i);
-+ restore_hw_context(i);
- }
- }
-
-@@ -156,13 +165,20 @@ EXPORT_SYMBOL(omap_vrfb_setup);
- void omap_vrfb_release_ctx(struct vrfb *vrfb)
- {
- int rot;
-+ int ctx = vrfb->context;
-
-- if (vrfb->context == 0xff)
-+ if (ctx == 0xff)
- return;
-
-- DBG("release ctx %d\n", vrfb->context);
-+ DBG("release ctx %d\n", ctx);
-
-- ctx_map &= ~(1 << vrfb->context);
-+ if (!(ctx_map & (1 << ctx))) {
-+ BUG();
-+ return;
-+ }
-+ WARN_ON(!(ctx_map_active & (1 << ctx)));
-+ clear_bit(ctx, &ctx_map_active);
-+ clear_bit(ctx, &ctx_map);
-
- for (rot = 0; rot < 4; ++rot) {
- if(vrfb->paddr[rot]) {
-@@ -194,7 +210,9 @@ int omap_vrfb_request_ctx(struct vrfb *vrfb)
-
- DBG("found free ctx %d\n", ctx);
-
-- ctx_map |= 1 << ctx;
-+ set_bit(ctx, &ctx_map);
-+ WARN_ON(ctx_map_active & (1 << ctx));
-+ set_bit(ctx, &ctx_map_active);
-
- memset(vrfb, 0, sizeof(*vrfb));
-
-@@ -219,3 +237,34 @@ int omap_vrfb_request_ctx(struct vrfb *vrfb)
- }
- EXPORT_SYMBOL(omap_vrfb_request_ctx);
-
-+void omap_vrfb_suspend_ctx(struct vrfb *vrfb)
-+{
-+ DBG("suspend ctx %d\n", vrfb->context);
-+ if (vrfb->context >= VRFB_NUM_CTXS ||
-+ (!(1 << vrfb->context) & ctx_map_active)) {
-+ BUG();
-+ return;
-+ }
-+ clear_bit(vrfb->context, &ctx_map_active);
-+}
-+EXPORT_SYMBOL(omap_vrfb_suspend_ctx);
-+
-+void omap_vrfb_resume_ctx(struct vrfb *vrfb)
-+{
-+ DBG("resume ctx %d\n", vrfb->context);
-+ if (vrfb->context >= VRFB_NUM_CTXS ||
-+ ((1 << vrfb->context) & ctx_map_active)) {
-+ BUG();
-+ return;
-+ }
-+ /*
-+ * omap_vrfb_restore_context is normally called by the core domain
-+ * save / restore logic, but since this VRFB context was suspended
-+ * those calls didn't actually restore the context and now we might
-+ * have an invalid context. Do an explicit restore here.
-+ */
-+ restore_hw_context(vrfb->context);
-+ set_bit(vrfb->context, &ctx_map_active);
-+}
-+EXPORT_SYMBOL(omap_vrfb_resume_ctx);
-+
-diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
-index 76e7c6c..4bb74b7 100644
---- a/drivers/video/omap2/omapfb/omapfb-main.c
-+++ b/drivers/video/omap2/omapfb/omapfb-main.c
-@@ -1036,6 +1036,30 @@ static int omapfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
- return 0;
- }
-
-+static void omapfb_vrfb_suspend_all(struct omapfb2_device *fbdev)
-+{
-+ int i;
-+
-+ for (i = 0; i < fbdev->num_fbs; i++) {
-+ struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
-+
-+ if (ofbi->region.vrfb.vaddr[0])
-+ omap_vrfb_suspend_ctx(&ofbi->region.vrfb);
-+ }
-+}
-+
-+static void omapfb_vrfb_resume_all(struct omapfb2_device *fbdev)
-+{
-+ int i;
-+
-+ for (i = 0; i < fbdev->num_fbs; i++) {
-+ struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
-+
-+ if (ofbi->region.vrfb.vaddr[0])
-+ omap_vrfb_resume_ctx(&ofbi->region.vrfb);
-+ }
-+}
-+
- static int omapfb_blank(int blank, struct fb_info *fbi)
- {
- struct omapfb_info *ofbi = FB2OFB(fbi);
-@@ -1051,6 +1075,8 @@ static int omapfb_blank(int blank, struct fb_info *fbi)
- if (display->state != OMAP_DSS_DISPLAY_SUSPENDED)
- goto exit;
-
-+ omapfb_vrfb_resume_all(fbdev);
-+
- if (display->resume)
- r = display->resume(display);
-
-@@ -1073,6 +1099,8 @@ static int omapfb_blank(int blank, struct fb_info *fbi)
- if (display->suspend)
- r = display->suspend(display);
-
-+ omapfb_vrfb_suspend_all(fbdev);
-+
- break;
-
- default:
---
-1.6.2.4
-
+++ /dev/null
-From 0201b40018d9e264f8c4ea7871223c94e0de61b1 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Thu, 7 May 2009 14:32:55 +0300
-Subject: [PATCH 66/69] DSS2: DSI: tune the timings to be more relaxed
-
-Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
----
- drivers/video/omap2/dss/dsi.c | 37 +++++++++++++++++++++----------------
- 1 files changed, 21 insertions(+), 16 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
-index 5225ed6..67ecfcf 100644
---- a/drivers/video/omap2/dss/dsi.c
-+++ b/drivers/video/omap2/dss/dsi.c
-@@ -1396,28 +1396,28 @@ static void dsi_complexio_timings(void)
- /* 1 * DDR_CLK = 2 * UI */
-
- /* min 40ns + 4*UI max 85ns + 6*UI */
-- ths_prepare = ns2ddr(59) + 2;
-+ ths_prepare = ns2ddr(70) + 2;
-
- /* min 145ns + 10*UI */
-- ths_prepare_ths_zero = ns2ddr(145) + 5;
-+ ths_prepare_ths_zero = ns2ddr(175) + 2;
-
- /* min max(8*UI, 60ns+4*UI) */
-- ths_trail = max((unsigned)4, ns2ddr(60) + 2);
-+ ths_trail = ns2ddr(60) + 5;
-
- /* min 100ns */
-- ths_exit = ns2ddr(100);
-+ ths_exit = ns2ddr(145);
-
- /* tlpx min 50n */
- tlpx_half = ns2ddr(25);
-
- /* min 60ns */
-- tclk_trail = ns2ddr(60);
-+ tclk_trail = ns2ddr(60) + 2;
-
- /* min 38ns, max 95ns */
-- tclk_prepare = ns2ddr(38);
-+ tclk_prepare = ns2ddr(65);
-
- /* min tclk-prepare + tclk-zero = 300ns */
-- tclk_zero = ns2ddr(300 - 38);
-+ tclk_zero = ns2ddr(260);
-
- DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
- ths_prepare, ddr2ns(ths_prepare),
-@@ -2340,9 +2340,19 @@ static void dsi_proto_timings(struct omap_display *display)
- /* min 60ns + 52*UI */
- tclk_post = ns2ddr(60) + 26;
-
-+ /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
-+ if (display->hw_config.u.dsi.data1_lane != 0 &&
-+ display->hw_config.u.dsi.data2_lane != 0)
-+ ths_eot = 2;
-+ else
-+ ths_eot = 4;
-+
- ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
- 4);
-- ddr_clk_post = DIV_ROUND_UP(tclk_post + tclk_trail, 4);
-+ ddr_clk_post = DIV_ROUND_UP(tclk_post + tclk_trail, 4) + ths_eot;
-+
-+ BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
-+ BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
-
- r = dsi_read_reg(DSI_CLK_TIMING);
- r = FLD_MOD(r, ddr_clk_pre, 15, 8);
-@@ -2353,14 +2363,9 @@ static void dsi_proto_timings(struct omap_display *display)
- ddr_clk_pre,
- ddr_clk_post);
-
-- /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
-- if (display->hw_config.u.dsi.data1_lane != 0 &&
-- display->hw_config.u.dsi.data2_lane != 0)
-- ths_eot = 2;
-- else
-- ths_eot = 4;
--
-- enter_hs_mode_lat = DIV_ROUND_UP(tlpx + ths_prepare + ths_zero, 4) + 4;
-+ enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
-+ DIV_ROUND_UP(ths_prepare, 4) +
-+ DIV_ROUND_UP(ths_zero + 3, 4);
- exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
-
- r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
---
-1.6.2.4
-
+++ /dev/null
-From c474849d7aff57d578c639f63a9c3cbdec0501dd Mon Sep 17 00:00:00 2001
-From: Imre Deak <imre.deak@nokia.com>
-Date: Mon, 11 May 2009 15:15:52 +0200
-Subject: [PATCH 67/69] DSS2: VRFB: don't WARN when releasing inactive ctx
-
-Releasing an inactive context is valid, it can happen when
-the application first blanks the screen then frees the
-framebuffer.
-
-Signed-off-by: Imre Deak <imre.deak@nokia.com>
----
- arch/arm/plat-omap/vrfb.c | 1 -
- 1 files changed, 0 insertions(+), 1 deletions(-)
-
-diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
-index 29f04e2..34395c2 100644
---- a/arch/arm/plat-omap/vrfb.c
-+++ b/arch/arm/plat-omap/vrfb.c
-@@ -176,7 +176,6 @@ void omap_vrfb_release_ctx(struct vrfb *vrfb)
- BUG();
- return;
- }
-- WARN_ON(!(ctx_map_active & (1 << ctx)));
- clear_bit(ctx, &ctx_map_active);
- clear_bit(ctx, &ctx_map);
-
---
-1.6.2.4
-
+++ /dev/null
-From 0db37fa025f0eac64f9fdad49e310d7660f48944 Mon Sep 17 00:00:00 2001
-From: =?utf-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@nokia.com>
-Date: Tue, 12 May 2009 14:38:05 +0200
-Subject: [PATCH 68/69] DSS2: Swap field offset values w/ VRFB rotation
-MIME-Version: 1.0
-Content-Type: text/plain; charset=utf-8
-Content-Transfer-Encoding: 8bit
-
-The field 0 and field 1 offset values were still incorrect when VRFB
-rotation is used. Swap them to put the fields into proper order.
-
-Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
----
- drivers/video/omap2/dss/dispc.c | 17 +++++++++++------
- 1 files changed, 11 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-index 5fc9457..b0e4960 100644
---- a/drivers/video/omap2/dss/dispc.c
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -1182,6 +1182,11 @@ static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
-
- DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
- width, height);
-+
-+ /*
-+ * field 0 = even field = bottom field
-+ * field 1 = odd field = top field
-+ */
- switch (rotation + mirror * 4) {
- case 0:
- case 2:
-@@ -1194,11 +1199,11 @@ static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
- width = width >> 1;
- case 1:
- case 3:
-- *offset0 = 0;
-+ *offset1 = 0;
- if (fieldmode)
-- *offset1 = screen_width * ps;
-+ *offset0 = screen_width * ps;
- else
-- *offset1 = 0;
-+ *offset0 = 0;
-
- *row_inc = pixinc(1 + (screen_width - width) +
- (fieldmode ? screen_width : 0),
-@@ -1216,11 +1221,11 @@ static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
- width = width >> 1;
- case 5:
- case 7:
-- *offset0 = 0;
-+ *offset1 = 0;
- if (fieldmode)
-- *offset1 = screen_width * ps;
-+ *offset0 = screen_width * ps;
- else
-- *offset1 = 0;
-+ *offset0 = 0;
- *row_inc = pixinc(1 - (screen_width + width) -
- (fieldmode ? screen_width : 0),
- ps);
---
-1.6.2.4
-
+++ /dev/null
-From b06406f3e5c3958f69185314c969f7c1a3265f71 Mon Sep 17 00:00:00 2001
-From: Hardik Shah <hardik.shah@ti.com>
-Date: Thu, 14 May 2009 15:04:17 +0530
-Subject: [PATCH 69/69] DSS2: OMAP3EVM: Added DSI powerup and powerdown functions
-
-Copied fom 3430sdp implementation.
-
-Signed-off-by: Hardik Shah <hardik.shah@ti.com>
----
- arch/arm/mach-omap2/board-omap3evm.c | 62 +++++++++++++++++++++-------------
- 1 files changed, 38 insertions(+), 24 deletions(-)
-
-diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
-index 6f5a866..57c4fc7 100644
---- a/arch/arm/mach-omap2/board-omap3evm.c
-+++ b/arch/arm/mach-omap2/board-omap3evm.c
-@@ -237,6 +237,38 @@ static int __init omap3_evm_i2c_init(void)
- static int lcd_enabled;
- static int dvi_enabled;
-
-+static void enable_vpll2(int enable)
-+{
-+ u8 ded_val, grp_val;
-+
-+ if (enable) {
-+ ded_val = ENABLE_VPLL2_DEDICATED;
-+ grp_val = ENABLE_VPLL2_DEV_GRP;
-+ } else {
-+ ded_val = 0;
-+ grp_val = 0;
-+ }
-+
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
-+ ded_val, TWL4030_VPLL2_DEDICATED);
-+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
-+ grp_val, TWL4030_VPLL2_DEV_GRP);
-+}
-+
-+static int omap3evm_dsi_power_up(void)
-+{
-+ if (omap_rev() > OMAP3430_REV_ES1_0)
-+ enable_vpll2(1);
-+ return 0;
-+}
-+
-+static void omap3evm_dsi_power_down(void)
-+{
-+ if (omap_rev() > OMAP3430_REV_ES1_0)
-+ enable_vpll2(0);
-+}
-+
-+
- static void __init omap3_evm_display_init(void)
- {
- int r;
-@@ -306,12 +338,7 @@ static int omap3_evm_panel_enable_lcd(struct omap_display *display)
- printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
- return -EINVAL;
- }
-- if (omap_rev() > OMAP3430_REV_ES1_0) {
-- twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
-- ENABLE_VPLL2_DEDICATED, TWL4030_VPLL2_DEDICATED);
-- twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
-- ENABLE_VPLL2_DEV_GRP, TWL4030_VPLL2_DEV_GRP);
-- }
-+ omap3evm_dsi_power_up();
- gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 0);
- lcd_enabled = 1;
- return 0;
-@@ -319,12 +346,7 @@ static int omap3_evm_panel_enable_lcd(struct omap_display *display)
-
- static void omap3_evm_panel_disable_lcd(struct omap_display *display)
- {
-- if (omap_rev() > OMAP3430_REV_ES1_0) {
-- twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
-- TWL4030_VPLL2_DEDICATED);
-- twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
-- TWL4030_VPLL2_DEV_GRP);
-- }
-+ omap3evm_dsi_power_down();
- gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 1);
- lcd_enabled = 0;
- }
-@@ -370,13 +392,8 @@ static int omap3_evm_panel_enable_dvi(struct omap_display *display)
- printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
- return -EINVAL;
- }
-- if (omap_rev() > OMAP3430_REV_ES1_0) {
-- twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
-- ENABLE_VPLL2_DEDICATED, TWL4030_VPLL2_DEDICATED);
-- twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
-- ENABLE_VPLL2_DEV_GRP, TWL4030_VPLL2_DEV_GRP);
-- }
-
-+ omap3evm_dsi_power_up();
- twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80,
- TWL4030_GPIODATA_IN3);
- twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80,
-@@ -388,13 +405,8 @@ static int omap3_evm_panel_enable_dvi(struct omap_display *display)
-
- static void omap3_evm_panel_disable_dvi(struct omap_display *display)
- {
-- if (omap_rev() > OMAP3430_REV_ES1_0) {
-- twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
-- TWL4030_VPLL2_DEDICATED);
-- twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x0,
-- TWL4030_VPLL2_DEV_GRP);
-- }
-
-+ omap3evm_dsi_power_down();
- twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x00,
- TWL4030_GPIODATA_IN3);
- twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0x00,
-@@ -413,6 +425,8 @@ static struct omap_dss_display_config omap3_evm_display_data_dvi = {
- };
-
- static struct omap_dss_board_info omap3_evm_dss_data = {
-+ .dsi_power_up = omap3evm_dsi_power_up,
-+ .dsi_power_down = omap3evm_dsi_power_down,
- .num_displays = 3,
- .displays = {
- &omap3_evm_display_data,
---
-1.6.2.4
-
+++ /dev/null
-From 093988f36ffcb0201927f8b452e546e1141aa0fa Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Sat, 23 May 2009 15:00:21 +0000
-Subject: DSS2: DISPC: fix irq handling locking
-
----
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-index b0e4960..b3685b2 100644
---- a/drivers/video/omap2/dss/dispc.c
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -154,23 +154,20 @@ static struct {
-
- struct clk *dpll4_m4_ck;
-
-- spinlock_t irq_lock;
--
- unsigned long cache_req_pck;
- unsigned long cache_prate;
- struct dispc_clock_info cache_cinfo;
-
-- u32 irq_error_mask;
-+ spinlock_t irq_lock;
-+ u32 irq_error_mask;
- struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
--
-- spinlock_t error_lock;
- u32 error_irqs;
- struct work_struct error_work;
-
- u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
- } dispc;
-
--static void omap_dispc_set_irqs(void);
-+static void _omap_dispc_set_irqs(void);
-
- static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
- {
-@@ -1691,10 +1688,13 @@ void dispc_enable_digit_out(bool enable)
- }
-
- if (enable) {
-+ unsigned long flags;
- /* When we enable digit output, we'll get an extra digit
- * sync lost interrupt, that we need to ignore */
-+ spin_lock_irqsave(&dispc.irq_lock, flags);
- dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
-- omap_dispc_set_irqs();
-+ _omap_dispc_set_irqs();
-+ spin_unlock_irqrestore(&dispc.irq_lock, flags);
- }
-
- /* When we disable digit output, we need to wait until fields are done.
-@@ -1728,9 +1728,12 @@ void dispc_enable_digit_out(bool enable)
- DSSERR("failed to unregister EVSYNC isr\n");
-
- if (enable) {
-+ unsigned long flags;
-+ spin_lock_irqsave(&dispc.irq_lock, flags);
- dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
- dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
-- omap_dispc_set_irqs();
-+ _omap_dispc_set_irqs();
-+ spin_unlock_irqrestore(&dispc.irq_lock, flags);
- }
-
- enable_clocks(0);
-@@ -2508,14 +2511,14 @@ int dispc_get_clock_div(struct dispc_clock_info *cinfo)
- return 0;
- }
-
--static void omap_dispc_set_irqs(void)
-+/* dispc.irq_lock has to be locked by the caller */
-+static void _omap_dispc_set_irqs(void)
- {
-- unsigned long flags;
-- u32 mask = dispc.irq_error_mask;
-+ u32 mask;
- int i;
- struct omap_dispc_isr_data *isr_data;
-
-- spin_lock_irqsave(&dispc.irq_lock, flags);
-+ mask = dispc.irq_error_mask;
-
- for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
- isr_data = &dispc.registered_isr[i];
-@@ -2528,9 +2531,8 @@ static void omap_dispc_set_irqs(void)
-
- enable_clocks(1);
- dispc_write_reg(DISPC_IRQENABLE, mask);
-- enable_clocks(0);
-
-- spin_unlock_irqrestore(&dispc.irq_lock, flags);
-+ enable_clocks(0);
- }
-
- int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
-@@ -2571,11 +2573,14 @@ int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
-
- break;
- }
--err:
-+
-+ _omap_dispc_set_irqs();
-+
- spin_unlock_irqrestore(&dispc.irq_lock, flags);
-
-- if (ret == 0)
-- omap_dispc_set_irqs();
-+ return 0;
-+err:
-+ spin_unlock_irqrestore(&dispc.irq_lock, flags);
-
- return ret;
- }
-@@ -2606,10 +2611,10 @@ int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
- break;
- }
-
-- spin_unlock_irqrestore(&dispc.irq_lock, flags);
--
- if (ret == 0)
-- omap_dispc_set_irqs();
-+ _omap_dispc_set_irqs();
-+
-+ spin_unlock_irqrestore(&dispc.irq_lock, flags);
-
- return ret;
- }
-@@ -2645,11 +2650,15 @@ static void print_irq_status(u32 status)
- void dispc_irq_handler(void)
- {
- int i;
-- u32 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
-+ u32 irqstatus;
- u32 handledirqs = 0;
- u32 unhandled_errors;
- struct omap_dispc_isr_data *isr_data;
-
-+ spin_lock(&dispc.irq_lock);
-+
-+ irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
-+
- #ifdef DEBUG
- if (dss_debug)
- print_irq_status(irqstatus);
-@@ -2673,15 +2682,15 @@ void dispc_irq_handler(void)
- unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
-
- if (unhandled_errors) {
-- spin_lock(&dispc.error_lock);
- dispc.error_irqs |= unhandled_errors;
-- spin_unlock(&dispc.error_lock);
-
- dispc.irq_error_mask &= ~unhandled_errors;
-- omap_dispc_set_irqs();
-+ _omap_dispc_set_irqs();
-
- schedule_work(&dispc.error_work);
- }
-+
-+ spin_unlock(&dispc.irq_lock);
- }
-
- static void dispc_error_worker(struct work_struct *work)
-@@ -2690,10 +2699,10 @@ static void dispc_error_worker(struct work_struct *work)
- u32 errors;
- unsigned long flags;
-
-- spin_lock_irqsave(&dispc.error_lock, flags);
-+ spin_lock_irqsave(&dispc.irq_lock, flags);
- errors = dispc.error_irqs;
- dispc.error_irqs = 0;
-- spin_unlock_irqrestore(&dispc.error_lock, flags);
-+ spin_unlock_irqrestore(&dispc.irq_lock, flags);
-
- if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
- DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
-@@ -2836,8 +2845,10 @@ static void dispc_error_worker(struct work_struct *work)
- }
- }
-
-+ spin_lock_irqsave(&dispc.irq_lock, flags);
- dispc.irq_error_mask |= errors;
-- omap_dispc_set_irqs();
-+ _omap_dispc_set_irqs();
-+ spin_unlock_irqrestore(&dispc.irq_lock, flags);
- }
-
- int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
-@@ -2921,6 +2932,10 @@ void dispc_fake_vsync_irq(void)
-
- static void _omap_dispc_initialize_irq(void)
- {
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&dispc.irq_lock, flags);
-+
- memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
-
- dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
-@@ -2929,7 +2944,9 @@ static void _omap_dispc_initialize_irq(void)
- * so clear it */
- dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
-
-- omap_dispc_set_irqs();
-+ _omap_dispc_set_irqs();
-+
-+ spin_unlock_irqrestore(&dispc.irq_lock, flags);
- }
-
- void dispc_enable_sidle(void)
-@@ -2970,7 +2987,6 @@ int dispc_init(void)
- u32 rev;
-
- spin_lock_init(&dispc.irq_lock);
-- spin_lock_init(&dispc.error_lock);
-
- INIT_WORK(&dispc.error_work, dispc_error_worker);
-
---
-cgit v0.8.2.1-10-g45e7
+++ /dev/null
-From 8af2f6550d6971875e4c5d3f93982f86f4bcf216 Mon Sep 17 00:00:00 2001
-From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
-Date: Sat, 23 May 2009 15:00:00 +0000
-Subject: DSS2: DISPC: clear irqstatus for newly enabled irqs
-
-This fixes the problem that when requesting a new irq
-we could get the isr called too early in case irqstatus
-already had that irq flag on.
----
-diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
-index b3685b2..2471cfe 100644
---- a/drivers/video/omap2/dss/dispc.c
-+++ b/drivers/video/omap2/dss/dispc.c
-@@ -2515,6 +2515,7 @@ int dispc_get_clock_div(struct dispc_clock_info *cinfo)
- static void _omap_dispc_set_irqs(void)
- {
- u32 mask;
-+ u32 old_mask;
- int i;
- struct omap_dispc_isr_data *isr_data;
-
-@@ -2530,6 +2531,11 @@ static void _omap_dispc_set_irqs(void)
- }
-
- enable_clocks(1);
-+
-+ old_mask = dispc_read_reg(DISPC_IRQENABLE);
-+ /* clear the irqstatus for newly enabled irqs */
-+ dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
-+
- dispc_write_reg(DISPC_IRQENABLE, mask);
-
- enable_clocks(0);
---
-cgit v0.8.2.1-10-g45e7
DEFAULT_PREFERENCE = "-1"
-SRCREV = "cbfc461bd5c4d0aff8501dd82db18146a22f49cf"
+SRCREV = "7e7377395d6b4576341a6939bf2179f3946f2ea0"
-PV = "2.6.29-pm1+gitr${SRCREV}"
+PV = "2.6.30+2.6.31rc1-pm0+gitr${SRCREV}"
-SRC_URI = "git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git;protocol=git;branch=pm-2.6.29 \
+SRC_URI = "git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git;protocol=git;branch=pm \
file://defconfig"
SRC_URI_append = " \
file://no-cortex-deadlock.patch;patch=1 \
file://read_die_ids.patch;patch=1 \
file://fix-install.patch;patch=1 \
- file://0124-leds-gpio-broken-with-current-git.patch;patch=1 \
- file://ehci.patch;patch=1 \
- file://dss2/0001-Revert-gro-Fix-legacy-path-napi_complete-crash.patch;patch=1 \
- file://dss2/0002-OMAPFB-move-omapfb.h-to-include-linux.patch;patch=1 \
- file://dss2/0003-DSS2-OMAP2-3-Display-Subsystem-driver.patch;patch=1 \
- file://dss2/0004-DSS2-OMAP-framebuffer-driver.patch;patch=1 \
- file://dss2/0005-DSS2-Add-panel-drivers.patch;patch=1 \
- file://dss2/0006-DSS2-HACK-Add-DSS2-support-for-N800.patch;patch=1 \
- file://dss2/0007-DSS2-Add-DSS2-support-for-SDP-Beagle-Overo-EVM.patch;patch=1 \
- file://dss2/0008-DSS2-Add-function-to-display-object-to-get-the-back.patch;patch=1 \
- file://dss2/0009-DSS2-Add-acx565akm-panel.patch;patch=1 \
- file://dss2/0010-DSS2-Small-VRFB-context-allocation-bug-fixed.patch;patch=1 \
- file://dss2/0011-DSS2-Allocated-memory-for-Color-Look-up-table.patch;patch=1 \
- file://dss2/0012-DSS2-Fix-DMA-rotation.patch;patch=1 \
- file://dss2/0013-DSS2-Verify-that-overlay-paddr-0.patch;patch=1 \
- file://dss2/0014-DSS2-Add-function-to-get-DSS-logic-clock-rate.patch;patch=1 \
- file://dss2/0015-DSS2-DSI-calculate-VP_CLK_RATIO-properly.patch;patch=1 \
- file://dss2/0016-DSS2-DSI-improve-packet-len-calculation.patch;patch=1 \
- file://dss2/0017-DSS2-Disable-video-planes-on-sync-lost-error.patch;patch=1 \
- file://dss2/0018-DSS2-check-for-ovl-paddr-only-when-enabling.patch;patch=1 \
- file://dss2/0019-DSS2-Check-fclk-limits-when-configuring-video-plane.patch;patch=1 \
- file://dss2/0020-DSS2-Check-scaling-limits-against-proper-values.patch;patch=1 \
- file://dss2/0021-DSS2-Add-venc-register-dump.patch;patch=1 \
- file://dss2/0022-DSS2-FB-remove-unused-var-warning.patch;patch=1 \
- file://dss2/0023-DSS2-pass-the-default-FB-color-format-through-board.patch;patch=1 \
- file://dss2/0024-DSS2-Beagle-Use-gpio_set_value.patch;patch=1 \
- file://dss2/0025-DSS2-VRFB-Macro-for-calculating-base-address-of-th.patch;patch=1 \
- file://dss2/0026-DSS2-DSI-sidlemode-to-noidle-while-sending-frame.patch;patch=1 \
- file://dss2/0027-DSS2-VRFB-rotation-and-mirroring-implemented.patch;patch=1 \
- file://dss2/0028-DSS2-OMAPFB-Added-support-for-the-YUV-VRFB-rotatio.patch;patch=1 \
- file://dss2/0029-DSS2-OMAPFB-Set-line_length-correctly-for-YUV-with.patch;patch=1 \
- file://dss2/0030-DSS2-dispc_get_trans_key-was-returning-wrong-key-ty.patch;patch=1 \
- file://dss2/0031-DSS2-do-bootmem-reserve-for-exclusive-access.patch;patch=1 \
- file://dss2/0032-DSS2-Fix-DISPC_VID_FIR-value-for-omap34xx.patch;patch=1 \
- file://dss2/0033-DSS2-Prefer-3-tap-filter.patch;patch=1 \
- file://dss2/0034-DSS2-VRAM-improve-omap_vram_add_region.patch;patch=1 \
- file://dss2/0035-DSS2-Added-the-function-pointer-for-getting-default.patch;patch=1 \
- file://dss2/0036-DSS2-Added-support-for-setting-and-querying-alpha-b.patch;patch=1 \
- file://dss2/0037-DSS2-Added-support-for-querying-color-keying.patch;patch=1 \
- file://dss2/0038-DSS2-OMAPFB-Some-color-keying-pointerd-renamed-in-D.patch;patch=1 \
- file://dss2/0039-DSS2-Add-sysfs-entry-to-for-the-alpha-blending-supp.patch;patch=1 \
- file://dss2/0040-DSS2-Provided-proper-exclusion-for-destination-colo.patch;patch=1 \
- file://dss2/0041-DSS2-Disable-vertical-offset-with-fieldmode.patch;patch=1 \
- file://dss2/0042-DSS2-Don-t-enable-fieldmode-automatically.patch;patch=1 \
- file://dss2/0043-DSS2-Swap-field-0-and-field-1-registers.patch;patch=1 \
- file://dss2/0044-DSS2-add-sysfs-entry-for-seting-the-rotate-type.patch;patch=1 \
- file://dss2/0045-DSS2-Fixed-line-endings-from-to.patch;patch=1 \
- file://dss2/0046-DSS2-DSI-decrease-sync-timeout-from-60s-to-2s.patch;patch=1 \
- file://dss2/0047-DSS2-fix-return-value-for-rotate_type-sysfs-functio.patch;patch=1 \
- file://dss2/0048-OMAP2-3-DMA-implement-trans-copy-and-const-fill.patch;patch=1 \
- file://dss2/0049-DSS2-VRAM-clear-allocated-area-with-DMA.patch;patch=1 \
- file://dss2/0050-DSS2-OMAPFB-remove-fb-clearing-code.patch;patch=1 \
- file://dss2/0051-DSS2-VRAM-use-debugfs-not-procfs.patch;patch=1 \
- file://dss2/0052-DSS2-VRAM-fix-section-mismatch-warning.patch;patch=1 \
- file://dss2/0053-DSS2-disable-LCD-DIGIT-before-resetting-DSS.patch;patch=1 \
- file://dss2/0054-DSS2-DSI-more-error-handling.patch;patch=1 \
- file://dss2/0055-DSS2-Added-global-alpha-support.patch;patch=1 \
- file://dss2/0056-DSS2-Rotation-attrs-for-YUV-need-not-to-be-reversed.patch;patch=1 \
- file://dss2/0057-DSS2-Documentation-update-for-new-sysfs-entries-in.patch;patch=1 \
- file://dss2/0058-DSS2-Don-t-touch-plane-coordinates-when-changing-fb.patch;patch=1 \
- file://dss2/0059-DSS2-DSI-configure-ENTER-EXIT_HS_MODE_LATENCY.patch;patch=1 \
- file://dss2/0060-DSS2-Avoid-div-by-zero-when-calculating-required-fc.patch;patch=1 \
- file://dss2/0061-DSS2-VRFB-save-restore-context.patch;patch=1 \
- file://dss2/0062-DSS2-VRAM-Fix-indentation.patch;patch=1 \
- file://dss2/0063-DSS2-fix-the-usage-of-get_last_off_on_transaction_i.patch;patch=1 \
- file://dss2/0064-VRFB-fix-debug-messages.patch;patch=1 \
- file://dss2/0065-VRFB-add-suspend-resume-functionality.patch;patch=1 \
- file://dss2/0066-DSS2-DSI-tune-the-timings-to-be-more-relaxed.patch;patch=1 \
- file://dss2/0067-DSS2-VRFB-don-t-WARN-when-releasing-inactive-ctx.patch;patch=1 \
- file://dss2/0068-DSS2-Swap-field-offset-values-w-VRFB-rotation.patch;patch=1 \
- file://dss2/0069-DSS2-OMAP3EVM-Added-DSI-powerup-and-powerdown-func.patch;patch=1 \
- file://dss2/0070-DSS2-fix-irq1.diff;patch=1 \
- file://dss2/0071-DSS2-fix-irq2.diff;patch=1 \
- file://dss2/merge-fixups.diff;patch=1 \
file://overo-cpufreq.diff;patch=1 \
file://register-all-OPPs.diff;patch=1 \
"
git.openpandora.org / openembedded.git / commitdiff