clk: qcom: apq8016: Fix SDCC clock warnings

As of commit dc8754e8e408 ("clk/qcom: apq8016: improve clk_enable logging")
there are now warnings in the U-Boot console on DragonBoard 410c:

  apq8016_clk_enable: unknown clk id 122
  apq8016_clk_enable: unknown clk id 123
  apq8016_clk_enable: unknown clk id 124
  apq8016_clk_enable: unknown clk id 125

This is because we don't implement enable() properly for the SDCC clocks.
Currently they are being enabled as part of set_rate().

Fix this by moving the enable calls out of the apq8016_clk_init_sdc()
function and convert them to the equivalent GATE_CLK_POLLED() definitions.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-6-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>

diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
index e3a9807..b7bd9c9 100644 (file)
--- a/drivers/clk/qcom/clock-apq8016.c
+++ b/drivers/clk/qcom/clock-apq8016.c
@@ -23,10 +23,7 @@
 #define APCS_GPLL_ENA_VOTE             (0x45000)
 #define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)
 
-#define SDCC_BCR(n)                    (((n) * 0x1000) + 0x42000)
 #define SDCC_CMD_RCGR(n)               (((n) * 0x1000) + 0x42004)
-#define SDCC_APPS_CBCR(n)              (((n) * 0x1000) + 0x42018)
-#define SDCC_AHB_CBCR(n)               (((n) * 0x1000) + 0x4201C)
 
 /* BLSP1 AHB clock (root clock for BLSP) */
 #define BLSP1_AHB_CBCR                 0x1008
@@ -55,6 +52,10 @@ static struct vote_clk gcc_blsp1_ahb_clk = {
 
 static const struct gate_clk apq8016_clks[] = {
        GATE_CLK_POLLED(GCC_PRNG_AHB_CLK,       0x45004, BIT(8), 0x13004),
+       GATE_CLK_POLLED(GCC_SDCC1_AHB_CLK,      0x4201c, BIT(0), 0x4201c),
+       GATE_CLK_POLLED(GCC_SDCC1_APPS_CLK,     0x42018, BIT(0), 0x42018),
+       GATE_CLK_POLLED(GCC_SDCC2_AHB_CLK,      0x4301c, BIT(0), 0x4301c),
+       GATE_CLK_POLLED(GCC_SDCC2_APPS_CLK,     0x43018, BIT(0), 0x43018),
        GATE_CLK_POLLED(GCC_USB_HS_AHB_CLK,     0x41008, BIT(0), 0x41008),
        GATE_CLK_POLLED(GCC_USB_HS_SYSTEM_CLK,  0x41004, BIT(0), 0x41004),
 };
@@ -67,12 +68,10 @@ static int apq8016_clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
        if (rate == 200000000)
                div = 4;
 
-       clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot));
        /* 800Mhz/div, gpll0 */
        clk_rcg_set_rate_mnd(priv->base, SDCC_CMD_RCGR(slot), div, 0, 0,
                             CFG_CLK_SRC_GPLL0, 8);
        clk_enable_gpll0(priv->base, &gpll0_vote_clk);
-       clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
 
        return rate;
 }