drm/i915/skl: Update watermarks for Y tiling

Display watermarks need different programming for different tiling
modes.

Set the relevant flag so this happens during the plane commit and
add relevant data into a structure made available to the watermark
computation code.

v2: Pass in tiling info to sprite plane updates as well.
v3: Rebased for plane handling changes.
v4: Handle fb == NULL when plane is disabled.
v5: Refactored for addfb2 interface.
v6: Refactored for fb modifier changes.
v7: Updated for atomic commit by only updating watermarks when tiling changes.
v8: BSpec watermark calculation updates.
v9: Restrict scope of y_tile_minimum variable. (Damien Lespiau)
v10: Get fb from plane state otherwise we are working on old state.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Acked-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> (v9)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e245bf6..a9e15cf 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12005,6 +12005,12 @@ intel_check_primary_plane(struct drm_plane *plane,
                        INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
 
                intel_crtc->atomic.update_fbc = true;
+
+               /* Update watermarks on tiling changes. */
+               if (!plane->state->fb || !state->base.fb ||
+                   plane->state->fb->modifier[0] !=
+                   state->base.fb->modifier[0])
+                       intel_crtc->atomic.update_wm = true;
        }
 
        return 0;

diff --cc drivers/gpu/drm/i915/intel_drv.h
Simple merge

diff --cc drivers/gpu/drm/i915/intel_pm.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_sprite.c
Simple merge