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clk: tegra: PLLD2 fixes for hdmi
authorDavid Ung <davidu@nvidia.com>
Fri, 27 Dec 2013 00:44:23 +0000 (16:44 -0800)
committerPeter De Schrijver <pdeschrijver@nvidia.com>
Mon, 17 Feb 2014 14:18:11 +0000 (16:18 +0200)
Set correct pll_d2_out0 divider and correct the p div values for pll_d2.

Signed-off-by: David Ung <davidu@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>

No differences found
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