clk: tegra: Add PLL post divider table

Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

diff --cc drivers/clk/tegra/clk-pll.c
Simple merge

diff --cc drivers/clk/tegra/clk-tegra20.c
Simple merge

diff --cc drivers/clk/tegra/clk-tegra30.c
Simple merge

diff --cc drivers/clk/tegra/clk.h
Simple merge