default y
select HAVE_AOUT
select HAVE_DMA_API_DEBUG
- ------ select HAVE_IDE
+ ++++++ select HAVE_IDE if PCI || ISA || PCMCIA
select HAVE_MEMBLOCK
select RTC_LIB
select SYS_SUPPORTS_APM_EMULATION
The base address of exception vectors.
config ARM_PATCH_PHYS_VIRT
--- - -- bool "Patch physical to virtual translations at runtime"
- bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
- depends on EXPERIMENTAL
+++++ ++ bool "Patch physical to virtual translations at runtime" if EMBEDDED
+++++ ++ default y
depends on !XIP_KERNEL && MMU
depends on !ARCH_REALVIEW || !SPARSEMEM
help
kernel in system memory.
This can only be used with non-XIP MMU kernels where the base
----- -- of physical memory is at a 16MB boundary, or theoretically 64K
----- -- for the MSM machine class.
+++++ ++ of physical memory is at a 16MB boundary.
+++++ ++
+++++ ++ Only disable this option if you know that you do not require
+++++ ++ this feature (eg, building a kernel for a single machine) and
+++++ ++ you need to shrink the kernel to the minimal size.
----- --config ARM_PATCH_PHYS_VIRT_16BIT
----- -- def_bool y
----- -- depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
----- -- help
----- -- This option extends the physical to virtual translation patching
----- -- to allow physical memory down to a theoretical minimum of 64K
----- -- boundaries.
source "init/Kconfig"
select ARCH_REQUIRE_GPIOLIB
select HAVE_CLK
select CLKDEV_LOOKUP
----- -- select ARM_PATCH_PHYS_VIRT if MMU
help
This enables support for systems based on the Atmel AT91RM9200,
AT91SAM9 and AT91CAP9 processors.
select CPU_SA110
select FOOTBRIDGE
select GENERIC_CLOCKEVENTS
+ ++++++ select HAVE_IDE
help
Support for systems based on the DC21285 companion chip
("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
select SPARSE_IRQ
select AUTO_ZRELADDR
select MULTI_IRQ_HANDLER
+ ++++++ select ARM_CPU_SUSPEND if PM
+ ++++++ select HAVE_IDE
help
Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
select NO_IOPORT
select ARCH_SPARSEMEM_ENABLE
select ARCH_USES_GETTIMEOFFSET
+ ++++++ select HAVE_IDE
help
On the Acorn Risc-PC, Linux can support the internal IDE disk and
CD-ROM interface, serial and parallel port, and the floppy drive.
select HAVE_SCHED_CLOCK
select TICK_ONESHOT
select ARCH_REQUIRE_GPIOLIB
+ ++++++ select HAVE_IDE
help
Support for StrongARM 11x0 based boards.
This workaround defines cpu_relax() as smp_mb(), preventing correctly
written polling loops from denying visibility of updates to memory.
+ + ++ config ARM_ERRATA_364296
+ + ++ bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
+ + ++ depends on CPU_V6 && !SMP
+ + ++ help
+ + ++ This options enables the workaround for the 364296 ARM1136
+ + ++ r0p2 erratum (possible cache data corruption with
+ + ++ hit-under-miss enabled). It sets the undocumented bit 31 in
+ + ++ the auxiliary control register and the FI bit in the control
+ + ++ register, thus disabling hit-under-miss without putting the
+ + ++ processor into full low interrupt latency mode. ARM11MPCore
+ + ++ is not affected.
+ + ++
+++++++config ARM_ERRATA_764369
+++++++ bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
+++++++ depends on CPU_V7 && SMP
+++++++ help
+++++++ This option enables the workaround for erratum 764369
+++++++ affecting Cortex-A9 MPCore with two or more processors (all
+++++++ current revisions). Under certain timing circumstances, a data
+++++++ cache line maintenance operation by MVA targeting an Inner
+++++++ Shareable memory region may fail to proceed up to either the
+++++++ Point of Coherency or to the Point of Unification of the
+++++++ system. This workaround adds a DSB instruction before the
+++++++ relevant cache maintenance functions and sets a specific bit
+++++++ in the diagnostic control register of the SCU.
+++++++
endmenu
source "arch/arm/common/Kconfig"
MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
+ ++++++ depends on MMU
select USE_GENERIC_SMP_HELPERS
select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
help
If you don't know what to do here, say Y.
+++++++ config ARM_CPU_TOPOLOGY
+++++++ bool "Support cpu topology definition"
+++++++ depends on SMP && CPU_V7
+++++++ default y
+++++++ help
+++++++ Support ARM cpu topology definition. The MPIDR register defines
+++++++ affinity between processors which is then used to describe the cpu
+++++++ topology of an ARM System.
+++++++
+++++++ config SCHED_MC
+++++++ bool "Multi-core scheduler support"
+++++++ depends on ARM_CPU_TOPOLOGY
+++++++ help
+++++++ Multi-core scheduler support improves the CPU scheduler's decision
+++++++ making when dealing with multi-core CPU chips at a cost of slightly
+++++++ increased overhead in some places. If unsure say N here.
+++++++
+++++++ config SCHED_SMT
+++++++ bool "SMT scheduler support"
+++++++ depends on ARM_CPU_TOPOLOGY
+++++++ help
+++++++ Improves the CPU scheduler's decision making when dealing with
+++++++ MultiThreading at a cost of slightly increased overhead in some
+++++++ places. If unsure say N here.
+++++++
config HAVE_ARM_SCU
bool
help
depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
select AEABI
select ARM_ASM_UNIFIED
+ ++++++ select ARM_UNWIND
help
By enabling this option, the kernel will be compiled in
Thumb-2 mode. A compiler/assembler that understand the unified
CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
def_bool y
+ ++++++config ARM_CPU_SUSPEND
+ ++++++ def_bool PM_SLEEP
+ ++++++
endmenu
source "net/Kconfig"
# These options are only for real kernel hackers who want to get their hands dirty.
config DEBUG_LL
-- ----- bool "Kernel low-level debugging functions"
++ +++++ bool "Kernel low-level debugging functions (read help!)"
depends on DEBUG_KERNEL
help
Say Y here to include definitions of printascii, printch, printhex
in the kernel. This is helpful if you are debugging code that
executes before the console is initialized.
++ +++++ Note that selecting this option will limit the kernel to a single
++ +++++ UART definition, as specified below. Attempting to boot the kernel
++ +++++ image on a different platform *will not work*, so this option should
++ +++++ not be enabled for kernels that are intended to be portable.
++ +++++
++ +++++choice
++ +++++ prompt "Kernel low-level debugging port"
++ +++++ depends on DEBUG_LL
++ +++++
++ +++++ config DEBUG_LL_UART_NONE
++ +++++ bool "No low-level debugging UART"
++ +++++ help
++ +++++ Say Y here if your platform doesn't provide a UART option
++ +++++ below. This relies on your platform choosing the right UART
++ +++++ definition internally in order for low-level debugging to
++ +++++ work.
++ +++++
++ +++++ config DEBUG_ICEDCC
++ +++++ bool "Kernel low-level debugging via EmbeddedICE DCC channel"
++ +++++ help
++ +++++ Say Y here if you want the debug print routines to direct
++ +++++ their output to the EmbeddedICE macrocell's DCC channel using
++ +++++ co-processor 14. This is known to work on the ARM9 style ICE
++ +++++ channel and on the XScale with the PEEDI.
++ +++++
++ +++++ Note that the system will appear to hang during boot if there
++ +++++ is nothing connected to read from the DCC.
++ +++++
++ +++++ config DEBUG_FOOTBRIDGE_COM1
++ +++++ bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1"
++ +++++ depends on FOOTBRIDGE
++ +++++ help
++ +++++ Say Y here if you want the debug print routines to direct
++ +++++ their output to the 8250 at PCI COM1.
++ +++++
++ +++++ config DEBUG_DC21285_PORT
++ +++++ bool "Kernel low-level debugging messages via footbridge serial port"
++ +++++ depends on FOOTBRIDGE
++ +++++ help
++ +++++ Say Y here if you want the debug print routines to direct
++ +++++ their output to the serial port in the DC21285 (Footbridge).
++ +++++
++ +++++ config DEBUG_CLPS711X_UART1
++ +++++ bool "Kernel low-level debugging messages via UART1"
++ +++++ depends on ARCH_CLPS711X
++ +++++ help
++ +++++ Say Y here if you want the debug print routines to direct
++ +++++ their output to the first serial port on these devices.
++ +++++
++ +++++ config DEBUG_CLPS711X_UART2
++ +++++ bool "Kernel low-level debugging messages via UART2"
++ +++++ depends on ARCH_CLPS711X
++ +++++ help
++ +++++ Say Y here if you want the debug print routines to direct
++ +++++ their output to the second serial port on these devices.
++ +++++
++ +++++endchoice
++ +++++
config EARLY_PRINTK
bool "Early printk"
depends on DEBUG_LL
kernel low-level debugging functions. Add earlyprintk to your
kernel parameters to enable this console.
-- -----config DEBUG_ICEDCC
-- ----- bool "Kernel low-level debugging via EmbeddedICE DCC channel"
-- ----- depends on DEBUG_LL
-- ----- help
-- ----- Say Y here if you want the debug print routines to direct their
-- ----- output to the EmbeddedICE macrocell's DCC channel using
-- ----- co-processor 14. This is known to work on the ARM9 style ICE
-- ----- channel and on the XScale with the PEEDI.
-- -----
-- ----- It does include a timeout to ensure that the system does not
-- ----- totally freeze when there is nothing connected to read.
-- -----
config OC_ETM
bool "On-chip ETM and ETB"
- ------ select ARM_AMBA
+ ++++++ depends on ARM_AMBA
help
Enables the on-chip embedded trace macrocell and embedded trace
buffer driver that will allow you to collect traces of the
kernel code.
-- -----config DEBUG_DC21285_PORT
-- ----- bool "Kernel low-level debugging messages via footbridge serial port"
-- ----- depends on DEBUG_LL && FOOTBRIDGE
-- ----- help
-- ----- Say Y here if you want the debug print routines to direct their
-- ----- output to the serial port in the DC21285 (Footbridge). Saying N
-- ----- will cause the debug messages to appear on the first 16550
-- ----- serial port.
-- -----
-- -----config DEBUG_CLPS711X_UART2
-- ----- bool "Kernel low-level debugging messages via UART2"
-- ----- depends on DEBUG_LL && ARCH_CLPS711X
-- ----- help
-- ----- Say Y here if you want the debug print routines to direct their
-- ----- output to the second serial port on these devices. Saying N will
-- ----- cause the debug messages to appear on the first serial port.
-- -----
config DEBUG_S3C_UART
depends on PLAT_SAMSUNG
int "S3C UART to use for low-level debug"
writel(0, base + VIC_INT_SELECT);
writel(0, base + VIC_INT_ENABLE);
writel(~0, base + VIC_INT_ENABLE_CLEAR);
------- writel(0, base + VIC_IRQ_STATUS);
writel(0, base + VIC_ITCR);
writel(~0, base + VIC_INT_SOFT_CLEAR);
}
/* Identify which VIC cell this one is, by reading the ID */
for (i = 0; i < 4; i++) {
- ------ u32 addr = ((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
+ ++++++ void __iomem *addr;
+ ++++++ addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
cellid |= (readl(addr) & 0xff) << (8 * i);
}
vendor = (cellid >> 12) & 0xff;
*/
#include <mach/io.h>
+++ ++++/*
+++ ++++ * This is the limit of PC card/PCI/ISA IO space, which is by default
+++ ++++ * 64K if we have PC card, PCI or ISA support. Otherwise, default to
+++ ++++ * zero to prevent ISA/PCI drivers claiming IO space (and potentially
+++ ++++ * oopsing.)
+++ ++++ *
+++ ++++ * Only set this larger if you really need inb() et.al. to operate over
+++ ++++ * a larger address space. Note that SOC_COMMON ioremaps each sockets
+++ ++++ * IO space area, and so inb() et.al. must be defined to operate as per
+++ ++++ * readb() et.al. on such platforms.
+++ ++++ */
+++ ++++#ifndef IO_SPACE_LIMIT
+++ ++++#if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE)
+++ ++++#define IO_SPACE_LIMIT ((resource_size_t)0xffffffff)
+++ ++++#elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD)
+++ ++++#define IO_SPACE_LIMIT ((resource_size_t)0xffff)
+++ ++++#else
+++ ++++#define IO_SPACE_LIMIT ((resource_size_t)0)
+++ ++++#endif
+++ ++++#endif
+++ ++++
/*
* IO port access primitives
* -------------------------
#define ioread16(p) ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; })
#define ioread32(p) ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; })
+ ++++++#define ioread16be(p) ({ unsigned int __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
+ ++++++#define ioread32be(p) ({ unsigned int __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
+ ++++++
#define iowrite8(v,p) ({ __iowmb(); (void)__raw_writeb(v, p); })
#define iowrite16(v,p) ({ __iowmb(); (void)__raw_writew((__force __u16)cpu_to_le16(v), p); })
#define iowrite32(v,p) ({ __iowmb(); (void)__raw_writel((__force __u32)cpu_to_le32(v), p); })
+ ++++++#define iowrite16be(v,p) ({ __iowmb(); (void)__raw_writew((__force __u16)cpu_to_be16(v), p); })
+ ++++++#define iowrite32be(v,p) ({ __iowmb(); (void)__raw_writel((__force __u32)cpu_to_be32(v), p); })
+ ++++++
#define ioread8_rep(p,d,c) __raw_readsb(p,d,c)
#define ioread16_rep(p,d,c) __raw_readsw(p,d,c)
#define ioread32_rep(p,d,c) __raw_readsl(p,d,c)
#ifndef __ASM_ARM_LOCALTIMER_H
#define __ASM_ARM_LOCALTIMER_H
+++++++#include <linux/errno.h>
+++++++
struct clock_event_device;
/*
*/
asmlinkage void do_local_timer(struct pt_regs *);
+++++++ /*
+++++++ * Called from C code
+++++++ */
+++++++ void handle_local_timer(struct pt_regs *);
#ifdef CONFIG_LOCAL_TIMERS
obj-$(CONFIG_ARTHUR) += arthur.o
obj-$(CONFIG_ISA_DMA) += dma-isa.o
obj-$(CONFIG_PCI) += bios32.o isa.o
- ------obj-$(CONFIG_PM_SLEEP) += sleep.o
+ ++++++obj-$(CONFIG_ARM_CPU_SUSPEND) += sleep.o
obj-$(CONFIG_HAVE_SCHED_CLOCK) += sched_clock.o
obj-$(CONFIG_SMP) += smp.o smp_tlb.o
obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o
obj-$(CONFIG_CPU_HAS_PMU) += pmu.o
obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt
+++++++ obj-$(CONFIG_ARM_CPU_TOPOLOGY) += topology.o
ifneq ($(CONFIG_ARCH_EBSA110),y)
obj-y += io.o
#include <asm/memory.h>
#include <asm/thread_info.h>
#include <asm/system.h>
++++++ +#include <asm/pgtable.h>
#ifdef CONFIG_DEBUG_LL
#include <mach/debug-macro.S>
#error KERNEL_RAM_VADDR must start at 0xXXXX8000
#endif
++++++ +#define PG_DIR_SIZE 0x4000
++++++ +#define PMD_ORDER 2
++++++ +
.globl swapper_pg_dir
------ - .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000
++++++ + .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
.macro pgtbl, rd, phys
------ - add \rd, \phys, #TEXT_OFFSET - 0x4000
++++++ + add \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE
.endm
#ifdef CONFIG_XIP_KERNEL
pgtbl r4, r8 @ page table address
/*
------ - * Clear the 16K level 1 swapper page table
++++++ + * Clear the swapper page table
*/
mov r0, r4
mov r3, #0
------ - add r6, r0, #0x4000
++++++ + add r6, r0, #PG_DIR_SIZE
1: str r3, [r0], #4
str r3, [r0], #4
str r3, [r0], #4
sub r0, r0, r3 @ virt->phys offset
add r5, r5, r0 @ phys __enable_mmu
add r6, r6, r0 @ phys __enable_mmu_end
------ - mov r5, r5, lsr #20
------ - mov r6, r6, lsr #20
++++++ + mov r5, r5, lsr #SECTION_SHIFT
++++++ + mov r6, r6, lsr #SECTION_SHIFT
------ -1: orr r3, r7, r5, lsl #20 @ flags + kernel base
------ - str r3, [r4, r5, lsl #2] @ identity mapping
------ - teq r5, r6
------ - addne r5, r5, #1 @ next section
------ - bne 1b
++++++ +1: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base
++++++ + str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping
++++++ + cmp r5, r6
++++++ + addlo r5, r5, #1 @ next section
++++++ + blo 1b
/*
* Now setup the pagetables for our kernel direct
* mapped region.
*/
mov r3, pc
------ - mov r3, r3, lsr #20
------ - orr r3, r7, r3, lsl #20
------ - add r0, r4, #(KERNEL_START & 0xff000000) >> 18
------ - str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]!
++++++ + mov r3, r3, lsr #SECTION_SHIFT
++++++ + orr r3, r7, r3, lsl #SECTION_SHIFT
++++++ + add r0, r4, #(KERNEL_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
++++++ + str r3, [r0, #((KERNEL_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
ldr r6, =(KERNEL_END - 1)
------ - add r0, r0, #4
------ - add r6, r4, r6, lsr #18
++++++ + add r0, r0, #1 << PMD_ORDER
++++++ + add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
1: cmp r0, r6
------ - add r3, r3, #1 << 20
------ - strls r3, [r0], #4
++++++ + add r3, r3, #1 << SECTION_SHIFT
++++++ + strls r3, [r0], #1 << PMD_ORDER
bls 1b
#ifdef CONFIG_XIP_KERNEL
*/
add r3, r8, #TEXT_OFFSET
orr r3, r3, r7
------ - add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> 18
------ - str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]!
++++++ + add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
++++++ + str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> (SECTION_SHIFT - PMD_ORDER)]!
ldr r6, =(_end - 1)
add r0, r0, #4
------ - add r6, r4, r6, lsr #18
++++++ + add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
1: cmp r0, r6
add r3, r3, #1 << 20
strls r3, [r0], #4
* Then map boot params address in r2 or
* the first 1MB of ram if boot params address is not specified.
*/
------ - mov r0, r2, lsr #20
------ - movs r0, r0, lsl #20
++++++ + mov r0, r2, lsr #SECTION_SHIFT
++++++ + movs r0, r0, lsl #SECTION_SHIFT
moveq r0, r8
sub r3, r0, r8
add r3, r3, #PAGE_OFFSET
------ - add r3, r4, r3, lsr #18
++++++ + add r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
orr r6, r7, r0
str r6, [r3]
*/
addruart r7, r3
------ - mov r3, r3, lsr #20
------ - mov r3, r3, lsl #2
++++++ + mov r3, r3, lsr #SECTION_SHIFT
++++++ + mov r3, r3, lsl #PMD_ORDER
add r0, r4, r3
rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
cmp r3, #0x0800 @ limit to 512MB
movhi r3, #0x0800
add r6, r0, r3
------ - mov r3, r7, lsr #20
++++++ + mov r3, r7, lsr #SECTION_SHIFT
ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
------ - orr r3, r7, r3, lsl #20
++++++ + orr r3, r7, r3, lsl #SECTION_SHIFT
1: str r3, [r0], #4
------ - add r3, r3, #1 << 20
------ - teq r0, r6
------ - bne 1b
++++++ + add r3, r3, #1 << SECTION_SHIFT
++++++ + cmp r0, r6
++++++ + blo 1b
#else /* CONFIG_DEBUG_ICEDCC */
/* we don't need any serial debugging mappings for ICEDCC */
* If we're using the NetWinder or CATS, we also need to map
* in the 16550-type serial port for the debug messages
*/
------ - add r0, r4, #0xff000000 >> 18
++++++ + add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER)
orr r3, r7, #0x7c000000
str r3, [r0]
#endif
* Similar reasons here - for debug. This is
* only for Acorn RiscPC architectures.
*/
------ - add r0, r4, #0x02000000 >> 18
++++++ + add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER)
orr r3, r7, #0x02000000
str r3, [r0]
------ - add r0, r4, #0xd8000000 >> 18
++++++ + add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
str r3, [r0]
#endif
#endif
add r5, r5, r3 @ adjust table end address
add r7, r7, r3 @ adjust __pv_phys_offset address
str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset
----- --#ifndef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
mov r6, r3, lsr #24 @ constant for add/sub instructions
teq r3, r6, lsl #24 @ must be 16MiB aligned
----- --#else
----- -- mov r6, r3, lsr #16 @ constant for add/sub instructions
----- -- teq r3, r6, lsl #16 @ must be 64kiB aligned
----- --#endif
THUMB( it ne @ cross section branch )
bne __error
str r6, [r7, #4] @ save to __pv_offset
.text
__fixup_a_pv_table:
#ifdef CONFIG_THUMB2_KERNEL
----- --#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
----- -- lsls r0, r6, #24
----- -- lsr r6, #8
----- -- beq 1f
----- -- clz r7, r0
----- -- lsr r0, #24
----- -- lsl r0, r7
----- -- bic r0, 0x0080
----- -- lsrs r7, #1
----- -- orrcs r0, #0x0080
----- -- orr r0, r0, r7, lsl #12
----- --#endif
----- --1: lsls r6, #24
----- -- beq 4f
+++++ ++ lsls r6, #24
+++++ ++ beq 2f
clz r7, r6
lsr r6, #24
lsl r6, r7
orrcs r6, #0x0080
orr r6, r6, r7, lsl #12
orr r6, #0x4000
----- -- b 4f
----- --2: @ at this point the C flag is always clear
----- -- add r7, r3
----- --#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
----- -- ldrh ip, [r7]
----- -- tst ip, 0x0400 @ the i bit tells us LS or MS byte
----- -- beq 3f
----- -- cmp r0, #0 @ set C flag, and ...
----- -- biceq ip, 0x0400 @ immediate zero value has a special encoding
----- -- streqh ip, [r7] @ that requires the i bit cleared
----- --#endif
----- --3: ldrh ip, [r7, #2]
+++++ ++ b 2f
+++++ ++1: add r7, r3
+++++ ++ ldrh ip, [r7, #2]
and ip, 0x8f00
----- -- orrcc ip, r6 @ mask in offset bits 31-24
----- -- orrcs ip, r0 @ mask in offset bits 23-16
+++++ ++ orr ip, r6 @ mask in offset bits 31-24
strh ip, [r7, #2]
----- --4: cmp r4, r5
+++++ ++2: cmp r4, r5
ldrcc r7, [r4], #4 @ use branch for delay slot
----- -- bcc 2b
+++++ ++ bcc 1b
bx lr
#else
----- --#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
----- -- and r0, r6, #255 @ offset bits 23-16
----- -- mov r6, r6, lsr #8 @ offset bits 31-24
----- --#else
----- -- mov r0, #0 @ just in case...
----- --#endif
----- -- b 3f
----- --2: ldr ip, [r7, r3]
+++++ ++ b 2f
+++++ ++1: ldr ip, [r7, r3]
bic ip, ip, #0x000000ff
----- -- tst ip, #0x400 @ rotate shift tells us LS or MS byte
----- -- orrne ip, ip, r6 @ mask in offset bits 31-24
----- -- orreq ip, ip, r0 @ mask in offset bits 23-16
+++++ ++ orr ip, ip, r6 @ mask in offset bits 31-24
str ip, [r7, r3]
----- --3: cmp r4, r5
+++++ ++2: cmp r4, r5
ldrcc r7, [r4], #4 @ use branch for delay slot
----- -- bcc 2b
+++++ ++ bcc 1b
mov pc, lr
#endif
ENDPROC(__fixup_a_pv_table)
#include <asm/smp_scu.h>
#include <asm/cacheflush.h>
+++++++#include <asm/cputype.h>
#define SCU_CTRL 0x00
#define SCU_CONFIG 0x04
/*
* Enable the SCU
*/
------- void __init scu_enable(void __iomem *scu_base)
+++++++ void scu_enable(void __iomem *scu_base)
{
u32 scu_ctrl;
+++++++#ifdef CONFIG_ARM_ERRATA_764369
+++++++ /* Cortex-A9 only */
+++++++ if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
+++++++ scu_ctrl = __raw_readl(scu_base + 0x30);
+++++++ if (!(scu_ctrl & 1))
+++++++ __raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
+++++++ }
+++++++#endif
+++++++
scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
/* already enabled? */
if (scu_ctrl & 1)
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
+++++++
+++++++ set_cpu_online(cpu, true);
}
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
ncores = scu_base ? scu_get_core_count(scu_base) : 1;
/* sanity check */
------- if (ncores > NR_CPUS) {
------- printk(KERN_WARNING
------- "EXYNOS4: no. of cores (%d) greater than configured "
------- "maximum of %d - clipping\n",
------- ncores, NR_CPUS);
------- ncores = NR_CPUS;
+++++++ if (ncores > nr_cpu_ids) {
+++++++ pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+++++++ ncores, nr_cpu_ids);
+++++++ ncores = nr_cpu_ids;
}
for (i = 0; i < ncores; i++)
#endif
#define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
------ -#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT)
------ -#define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)
++++++ +#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PMD_SHIFT)
++++++ +#define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PMD_SHIFT)
/*
* These are the page tables (2MB each) covering uncached, DMA consistent allocations
}
consistent_pte[i++] = pte;
------ - base += (1 << PGDIR_SHIFT);
++++++ + base += PMD_SIZE;
} while (base < CONSISTENT_END);
return ret;
if (addr)
*handle = pfn_to_dma(dev, page_to_pfn(page));
+++++++ else
+++++++ __dma_free_buffer(page, size);
return addr;
}
ENTRY(cpu_v7_reset)
mrc p15, 0, r1, c1, c0, 0 @ ctrl register
bic r1, r1, #0x1 @ ...............m
+ + ++ THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
mcr p15, 0, r1, c1, c0, 0 @ disable MMU
isb
mov pc, r0
/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
.globl cpu_v7_suspend_size
.equ cpu_v7_suspend_size, 4 * 9
- ------#ifdef CONFIG_PM_SLEEP
+ ++++++#ifdef CONFIG_ARM_CPU_SUSPEND
ENTRY(cpu_v7_do_suspend)
stmfd sp!, {r4 - r11, lr}
mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
mcr p15, 0, r7, c2, c0, 0 @ TTB 0
mcr p15, 0, r8, c2, c0, 1 @ TTB 1
mcr p15, 0, ip, c2, c0, 2 @ TTB control register
- - -- mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
+ + ++ mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
+ + ++ teq r4, r10 @ Is it already set?
+ + ++ mcrne p15, 0, r10, c1, c0, 1 @ No, so write it
mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control
ldr r4, =PRRR @ PRRR
ldr r5, =NMRR @ NMRR
mcr p15, 0, r4, c10, c2, 0 @ write PRRR
mcr p15, 0, r5, c10, c2, 1 @ write NMRR
isb
+ + ++ dsb
mov r0, r9 @ control register
mov r2, r7, lsr #14 @ get TTB0 base
mov r2, r2, lsl #14
git.openpandora.org / pandora-kernel.git / commitdiff