clk: rzg2l: Ignore disable for core clocks

Following on from commit 9a699a0a0d62 ("clk: rzg2l: Ignore enable for
core clocks"), we also need to ignore attempts to disable core clocks to
avoid the need for conditionals around clk_disable_bulk() calls in
drivers which support both RZ/G2L and other Renesas SoCs.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 3c5340d..7fce1f7 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -70,17 +70,12 @@ static int rzg2l_cpg_clk_set(struct clk *clk, bool enable)
        dev_dbg(clk->dev, "%s %s clock %u\n", enable ? "enable" : "disable",
                is_mod_clk(clk->id) ? "module" : "core", cpg_clk_id);
 
-       if (!is_mod_clk(clk->id)) {
-               /*
-                * Non-module clocks are always on. Ignore attempts to enable
-                * them and reject attempts to disable them.
-                */
-               if (enable)
-                       return 0;
-
-               dev_err(clk->dev, "ID %lu is not a module clock\n", clk->id);
-               return -EINVAL;
-       }
+       /*
+        * Non-module clocks are always on. Ignore attempts to enable or disable
+        * them.
+        */
+       if (!is_mod_clk(clk->id))
+               return 0;
 
        for (i = 0; i < data->info->num_mod_clks; i++) {
                if (data->info->mod_clks[i].id == cpg_clk_id) {