spl: starfive: visionfive2: Disable USB overcurrent pin by default.

For some JH7110 boards, USB host overcurent pin is not reserved,
To make USB host work, overcurrent pin must be disabled. So set the
pin default disabled in spl stage.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Tested-by: E Shattow <lucent@gmail.com>

diff --git a/arch/riscv/include/asm/arch-jh7110/gpio.h b/arch/riscv/include/asm/arch-jh7110/gpio.h
index 90aa2f8..be2a1e0 100644 (file)
--- a/arch/riscv/include/asm/arch-jh7110/gpio.h
+++ b/arch/riscv/include/asm/arch-jh7110/gpio.h
@@ -63,6 +63,11 @@ enum gpio_state {
                        GPIO_DIN_MASK << GPIO_SHIFT(gpi), \
                        ((gpio + 2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
 
+#define SYS_IOMUX_DIN_DISABLED(gpi)\
+       clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DIN + GPIO_OFFSET(gpi), \
+                       GPIO_DIN_MASK << GPIO_SHIFT(gpi), \
+                       ((0x1) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
+
 #define SYS_IOMUX_SET_DS(gpio, ds) \
        clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
                        GPIO_DS_MASK, (ds) << GPIO_DS_SHIFT)

diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index 22afd76..1538d6a 100644 (file)
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -103,6 +103,9 @@ void board_init_f(ulong dummy)
                        JH7110_CLK_CPU_ROOT_MASK,
                        BIT(JH7110_CLK_CPU_ROOT_SHIFT));
 
+       /* Set USB overcurrent overflow pin disable */
+       SYS_IOMUX_DIN_DISABLED(2);
+
        ret = spl_board_init_f();
        if (ret) {
                debug("spl_board_init_f init failed: %d\n", ret);