OMAP3 clock/SRAM: fix CORE DPLL M2 divider mask

3430ES2+ CORE DPLL M2 divider can divide by 1 to 31, unlike ES1, which
was more limited.  The SRAM code currently only supports dividing by 1
or 2, but we should mask off the full range of bits to guard against
the event that the previous contents of CM_CLKSEL_PLL1 included an M2
divider > 2.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>