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drm/i915: Use documented PLL timing limits for G4X platform
authorMa Ling <ling.ma@intel.com>
Wed, 18 Mar 2009 12:13:23 +0000 (20:13 +0800)
committerEric Anholt <eric@anholt.net>
Fri, 27 Mar 2009 21:45:11 +0000 (14:45 -0700)
The values come from the internal reference spreadsheet on PLL
timing limits for the G4X chipsets.

Part of fixing fd.o bug #17508

Signed-off-by: Ma Ling <ling.ma@intel.com>
[anholt: Cleaned up some whitespace]
Signed-off-by: Eric Anholt <eric@anholt.net>

No differences found
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