CLOCK_ID_COUNT, /* number of clocks */
CLOCK_ID_NONE = -1,
+ CLOCK_ID_DISPLAY2 = CLOCK_ID_NONE, /* for compatibility */
};
/* The clocks supported by the hardware */
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,
+ PERIPH_ID_DSIB = CLOCK_ID_NONE, /* for compatibility */
};
enum pll_out_id {
* We halve the rate if DISP1 parent is PLLD, since actual parent
* is plld_out0 which is PLLD divided by 2.
*/
- if (priv->clk_parent->id == CLOCK_ID_DISPLAY)
+ if (priv->clk_parent->id == CLOCK_ID_DISPLAY ||
+ priv->clk_parent->id == CLOCK_ID_DISPLAY2)
rate /= 2;
-#ifndef CONFIG_TEGRA20
- /* PLLD2 obeys same rules as PLLD but it is present only on T30+ */
- if (priv->clk_parent->id == CLOCK_ID_DISPLAY2)
- rate /= 2;
-#endif
-
/*
* The pixel clock divider is in 7.1 format (where the bottom bit
* represents 0.5). Here we calculate the divider needed to get from
int ret;
/* Initialize the Tegra display controller */
-#ifdef CONFIG_TEGRA20
- funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
-#endif
-
if (priv->soc->has_pgate) {
uint powergate;
return -1;
}
-#ifdef CONFIG_TEGRA20
- pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
- pinmux_tristate_disable(PMUX_PINGRP_GPU);
-#endif
-
ret = panel_enable_backlight(priv->panel);
if (ret) {
debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);