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ASoC: Fix WM8993 MCLK configuration for high frequency MCLKs
authorMark Brown <broonie@opensource.wolfsonmicro.com>
Mon, 17 Aug 2009 17:51:44 +0000 (18:51 +0100)
committerMark Brown <broonie@opensource.wolfsonmicro.com>
Mon, 17 Aug 2009 17:53:44 +0000 (18:53 +0100)
When used without the PLL we were accidentally clearing the MCLK/2
divider, resulting in a double rate SYSCLK when the divider should
have been used.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

No differences found
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