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linux-omap git: add dss2 and cache patches
authorKoen Kooi <koen@openembedded.org>
Fri, 4 Sep 2009 09:41:31 +0000 (11:41 +0200)
committerKoen Kooi <koen@openembedded.org>
Fri, 4 Sep 2009 09:41:31 +0000 (11:41 +0200)
23 files changed:
recipes/linux/linux-omap-2.6.31/beagleboard/defconfig patch | blob | history
recipes/linux/linux-omap-2.6.31/beagleboard/logo_linux_clut224.ppm [new file with mode: 0644] patch | blob
recipes/linux/linux-omap-2.6.31/cache/copy-page-tweak.patch [new file with mode: 0644] patch | blob
recipes/linux/linux-omap-2.6.31/cache/l1cache-shift.patch [new file with mode: 0644] patch | blob
recipes/linux/linux-omap-2.6.31/dss2/0001-OMAP2-Add-funcs-for-writing-SMS_ROT_-registers.patch [new file with mode: 0644] patch | blob
recipes/linux/linux-omap-2.6.31/dss2/0002-OMAP-OMAPFB-split-omapfb.h.patch [new file with mode: 0644] patch | blob
recipes/linux/linux-omap-2.6.31/dss2/0003-OMAP-OMAPFB-add-omapdss-device.patch [new file with mode: 0644] patch | blob
recipes/linux/linux-omap-2.6.31/dss2/0004-OMAP-Add-VRAM-manager.patch [new file with mode: 0644] patch | blob
recipes/linux/linux-omap-2.6.31/dss2/0005-OMAP-Add-support-for-VRFB-rotation-engine.patch [new file with mode: 0644] patch | blob
recipes/linux/linux-omap-2.6.31/dss2/0006-OMAP-DSS2-Documentation-for-DSS2.patch [new file with mode: 0644] patch | blob
recipes/linux/linux-omap-2.6.31/dss2/0007-OMAP-DSS2-Display-Subsystem-Driver-core.patch [new file with mode: 0644] patch | blob
recipes/linux/linux-omap-2.6.31/dss2/0008-OMAP-DSS2-Add-more-core-files.patch [new file with mode: 0644] patch | blob
recipes/linux/linux-omap-2.6.31/dss2/0009-OMAP-DSS2-DISPC.patch [new file with mode: 0644] patch | blob
recipes/linux/linux-omap-2.6.31/dss2/0010-OMAP-DSS2-DPI-driver.patch [new file with mode: 0644] patch | blob
recipes/linux/linux-omap-2.6.31/dss2/0011-OMAP-DSS2-Video-encoder-driver.patch [new file with mode: 0644] patch | blob
recipes/linux/linux-omap-2.6.31/dss2/0012-OMAP-DSS2-RFBI-driver.patch [new file with mode: 0644] patch | blob
recipes/linux/linux-omap-2.6.31/dss2/0013-OMAP-DSS2-SDI-driver.patch [new file with mode: 0644] patch | blob
recipes/linux/linux-omap-2.6.31/dss2/0014-OMAP-DSS2-DSI-driver.patch [new file with mode: 0644] patch | blob
recipes/linux/linux-omap-2.6.31/dss2/0015-OMAP-DSS2-omapfb-driver.patch [new file with mode: 0644] patch | blob
recipes/linux/linux-omap-2.6.31/dss2/0016-OMAP-DSS2-Add-DPI-panel-drivers.patch [new file with mode: 0644] patch | blob
recipes/linux/linux-omap-2.6.31/dss2/0017-OMAP-DSS2-Taal-DSI-command-mode-panel-driver.patch [new file with mode: 0644] patch | blob
recipes/linux/linux-omap-2.6.31/dss2/0018-OMAP-SDP-Enable-DSS2-for-OMAP3-SDP-board.patch [new file with mode: 0644] patch | blob
recipes/linux/linux-omap_git.bb patch | blob | history

diff --git a/recipes/linux/linux-omap-2.6.31/beagleboard/defconfig b/recipes/linux/linux-omap-2.6.31/beagleboard/defconfig
index f43c8f5..c9f8e99 100644 (file)
--- a/recipes/linux/linux-omap-2.6.31/beagleboard/defconfig
+++ b/recipes/linux/linux-omap-2.6.31/beagleboard/defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.31-rc1-omap1
-# Thu Jul 30 12:51:41 2009
+# Linux kernel version: 2.6.29-omap1
+# Thu Aug 13 12:58:49 2009
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -9,6 +9,7 @@ CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -17,19 +18,21 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_OPROFILE_ARMV7=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 # CONFIG_LOCALVERSION_AUTO is not set
@@ -67,9 +70,6 @@ CONFIG_USER_SCHED=y
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_LZMA=y
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
 CONFIG_ANON_INODES=y
@@ -91,31 +91,20 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
-
-#
-# Performance Counters
-#
 CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_STRIP_ASM_SYMS=y
 # CONFIG_COMPAT_BRK is not set
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 CONFIG_PROFILING=y
 CONFIG_TRACEPOINTS=y
-CONFIG_MARKERS=y
+# CONFIG_MARKERS is not set
 CONFIG_OPROFILE=y
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
 CONFIG_HAVE_CLK=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_GCOV_KERNEL is not set
-CONFIG_SLOW_WORK=y
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
@@ -127,9 +116,10 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 CONFIG_BLOCK=y
-CONFIG_LBDAF=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_BLK_DEV_INTEGRITY=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -154,14 +144,12 @@ CONFIG_FREEZER=y
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
 # CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
 # CONFIG_ARCH_EP93XX is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_STMP3XXX is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
 # CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
@@ -170,25 +158,24 @@ CONFIG_FREEZER=y
 # CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
 # CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_LOKI is not set
 # CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
 # CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_MMP is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_W90X900 is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_MSM is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_S3C64XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_U300 is not set
 # CONFIG_ARCH_DAVINCI is not set
 CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
 
 #
 # TI OMAP Implementations
@@ -197,26 +184,30 @@ CONFIG_ARCH_OMAP_OTG=y
 # CONFIG_ARCH_OMAP1 is not set
 # CONFIG_ARCH_OMAP2 is not set
 CONFIG_ARCH_OMAP3=y
-# CONFIG_ARCH_OMAP4 is not set
 
 #
 # OMAP Feature Selections
 #
 # CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
 # CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
+# CONFIG_OMAP_SMARTREFLEX is not set
 CONFIG_OMAP_RESET_CLOCKS=y
+CONFIG_OMAP_BOOT_TAG=y
+CONFIG_OMAP_BOOT_REASON=y
+# CONFIG_OMAP_COMPONENT_VERSION is not set
+# CONFIG_OMAP_GPIO_SWITCH is not set
 # CONFIG_OMAP_MUX is not set
 CONFIG_OMAP_MCBSP=y
 # CONFIG_OMAP_MBOX_FWK is not set
+CONFIG_OMAP_IOMMU=m
 # CONFIG_OMAP_MPU_TIMER is not set
 CONFIG_OMAP_32K_TIMER=y
 CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_TICK_GPTIMER=12
 CONFIG_OMAP_DM_TIMER=y
 # CONFIG_OMAP_LL_DEBUG_UART1 is not set
 # CONFIG_OMAP_LL_DEBUG_UART2 is not set
 CONFIG_OMAP_LL_DEBUG_UART3=y
-CONFIG_OMAP2_VRAM=y
-CONFIG_OMAP2_VRFB=y
 CONFIG_ARCH_OMAP34XX=y
 CONFIG_ARCH_OMAP3430=y
 
@@ -226,11 +217,10 @@ CONFIG_ARCH_OMAP3430=y
 # CONFIG_MACH_NOKIA_RX51 is not set
 # CONFIG_MACH_OMAP_LDP is not set
 # CONFIG_MACH_OMAP_3430SDP is not set
-# CONFIG_MACH_OMAP3EVM is not set
+CONFIG_MACH_OMAP3EVM=y
 CONFIG_MACH_OMAP3_BEAGLE=y
-# CONFIG_MACH_OVERO is not set
+CONFIG_MACH_OVERO=y
 # CONFIG_MACH_OMAP3_PANDORA is not set
-# CONFIG_MACH_OMAP_ZOOM2 is not set
 
 #
 # Processor Type
@@ -258,10 +248,7 @@ CONFIG_ARM_THUMBEE=y
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_BPREDICT_DISABLE is not set
 CONFIG_HAS_TLS_REG=y
-# CONFIG_ARM_ERRATA_430973 is not set
-# CONFIG_ARM_ERRATA_458693 is not set
-# CONFIG_ARM_ERRATA_460075 is not set
-CONFIG_COMMON_CLKDEV=y
+# CONFIG_OUTER_CACHE is not set
 
 #
 # Bus support
@@ -281,13 +268,13 @@ CONFIG_VMSPLIT_3G=y
 # CONFIG_VMSPLIT_2G is not set
 # CONFIG_VMSPLIT_1G is not set
 CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PREEMPT is not set
+CONFIG_PREEMPT=y
 CONFIG_HZ=128
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
 # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
 # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_HIGHMEM is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
@@ -299,12 +286,9 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_UNEVICTABLE_LRU=y
 CONFIG_LEDS=y
 CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
 
 #
 # Boot options
@@ -324,19 +308,17 @@ CONFIG_CPU_FREQ_TABLE=y
 CONFIG_CPU_FREQ_DEBUG=y
 CONFIG_CPU_FREQ_STAT=y
 CONFIG_CPU_FREQ_STAT_DETAILS=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
 # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
 # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
 CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
 CONFIG_CPU_FREQ_GOV_POWERSAVE=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
 CONFIG_CPU_FREQ_GOV_ONDEMAND=y
 CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
+# CONFIG_CPU_IDLE is not set
 
 #
 # Floating point emulation
@@ -376,6 +358,7 @@ CONFIG_NET=y
 #
 # Networking options
 #
+CONFIG_COMPAT_NET_DEV_OPS=y
 CONFIG_PACKET=y
 CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
@@ -407,7 +390,7 @@ CONFIG_INET_TUNNEL=m
 CONFIG_INET_XFRM_MODE_TRANSPORT=y
 CONFIG_INET_XFRM_MODE_TUNNEL=y
 CONFIG_INET_XFRM_MODE_BEET=y
-CONFIG_INET_LRO=y
+CONFIG_INET_LRO=m
 CONFIG_INET_DIAG=m
 CONFIG_INET_TCP_DIAG=m
 CONFIG_TCP_CONG_ADVANCED=y
@@ -487,8 +470,6 @@ CONFIG_NETFILTER_XTABLES=m
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 # CONFIG_NETFILTER_XT_TARGET_DSCP is not set
-CONFIG_NETFILTER_XT_TARGET_HL=m
-CONFIG_NETFILTER_XT_TARGET_LED=m
 CONFIG_NETFILTER_XT_TARGET_MARK=m
 CONFIG_NETFILTER_XT_TARGET_NFLOG=m
 CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
@@ -497,7 +478,6 @@ CONFIG_NETFILTER_XT_TARGET_RATEEST=m
 # CONFIG_NETFILTER_XT_TARGET_TRACE is not set
 CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
 # CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
-# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
 CONFIG_NETFILTER_XT_MATCH_COMMENT=m
 CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
 CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
@@ -508,7 +488,6 @@ CONFIG_NETFILTER_XT_MATCH_DSCP=m
 CONFIG_NETFILTER_XT_MATCH_ESP=m
 CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
 CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_HL=m
 CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
 CONFIG_NETFILTER_XT_MATCH_LENGTH=m
 CONFIG_NETFILTER_XT_MATCH_LIMIT=m
@@ -531,7 +510,6 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 CONFIG_NETFILTER_XT_MATCH_TIME=m
 CONFIG_NETFILTER_XT_MATCH_U32=m
-CONFIG_NETFILTER_XT_MATCH_OSF=m
 CONFIG_IP_VS=m
 CONFIG_IP_VS_IPV6=y
 CONFIG_IP_VS_DEBUG=y
@@ -586,6 +564,7 @@ CONFIG_NF_NAT_NEEDED=y
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_NETMAP=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_TARGET_IDLETIMER=m
 CONFIG_NF_NAT_SNMP_BASIC=m
 CONFIG_NF_NAT_PROTO_DCCP=m
 CONFIG_NF_NAT_PROTO_GRE=m
@@ -621,11 +600,11 @@ CONFIG_IP6_NF_MATCH_HL=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 CONFIG_IP6_NF_MATCH_MH=m
 CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_TARGET_HL=m
 CONFIG_IP6_NF_TARGET_LOG=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_TARGET_HL=m
 CONFIG_IP6_NF_RAW=m
 # CONFIG_BRIDGE_NF_EBTABLES is not set
 CONFIG_IP_DCCP=m
@@ -675,8 +654,6 @@ CONFIG_LLC=m
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 CONFIG_WAN_ROUTER=m
-# CONFIG_PHONET is not set
-CONFIG_IEEE802154=m
 CONFIG_NET_SCHED=y
 
 #
@@ -722,7 +699,6 @@ CONFIG_NET_SCH_FIFO=y
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
-# CONFIG_NET_DROP_MONITOR is not set
 # CONFIG_HAMRADIO is not set
 CONFIG_CAN=m
 CONFIG_CAN_RAW=m
@@ -732,10 +708,6 @@ CONFIG_CAN_BCM=m
 # CAN Device Drivers
 #
 CONFIG_CAN_VCAN=m
-CONFIG_CAN_DEV=m
-# CONFIG_CAN_CALC_BITTIMING is not set
-CONFIG_CAN_SJA1000=m
-CONFIG_CAN_SJA1000_PLATFORM=m
 # CONFIG_CAN_DEBUG_DEVICES is not set
 CONFIG_IRDA=m
 
@@ -787,6 +759,7 @@ CONFIG_KS959_DONGLE=m
 CONFIG_USB_IRDA=m
 CONFIG_SIGMATEL_FIR=m
 CONFIG_MCS_FIR=m
+# CONFIG_OMAP_IR is not set
 CONFIG_BT=y
 CONFIG_BT_L2CAP=y
 CONFIG_BT_SCO=y
@@ -809,15 +782,18 @@ CONFIG_BT_HCIUART_LL=y
 CONFIG_BT_HCIBCM203X=y
 CONFIG_BT_HCIBPA10X=y
 CONFIG_BT_HCIBFUSB=y
+# CONFIG_BT_HCIBRF6150 is not set
+# CONFIG_BT_HCIH4P is not set
 # CONFIG_BT_HCIVHCI is not set
 CONFIG_AF_RXRPC=m
 # CONFIG_AF_RXRPC_DEBUG is not set
 # CONFIG_RXKAD is not set
+# CONFIG_PHONET is not set
 CONFIG_FIB_RULES=y
 CONFIG_WIRELESS=y
 CONFIG_CFG80211=y
 # CONFIG_CFG80211_REG_DEBUG is not set
-# CONFIG_CFG80211_DEBUGFS is not set
+CONFIG_NL80211=y
 CONFIG_WIRELESS_OLD_REGULATORY=y
 CONFIG_WIRELESS_EXT=y
 CONFIG_WIRELESS_EXT_SYSFS=y
@@ -827,8 +803,6 @@ CONFIG_LIB80211_CRYPT_CCMP=y
 CONFIG_LIB80211_CRYPT_TKIP=y
 # CONFIG_LIB80211_DEBUG is not set
 CONFIG_MAC80211=y
-CONFIG_MAC80211_DEFAULT_PS=y
-CONFIG_MAC80211_DEFAULT_PS_VALUE=1
 
 #
 # Rate control algorithm selection
@@ -864,7 +838,7 @@ CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-CONFIG_CONNECTOR=m
+# CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 CONFIG_MTD_CONCAT=y
@@ -974,12 +948,10 @@ CONFIG_CDROM_PKTCDVD=m
 CONFIG_CDROM_PKTCDVD_BUFFERS=8
 # CONFIG_CDROM_PKTCDVD_WCACHE is not set
 # CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MG_DISK is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_ICS932S401 is not set
 # CONFIG_OMAP_STI is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_ISL29003 is not set
 # CONFIG_C2PORT is not set
 
 #
@@ -988,7 +960,6 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_AT24 is not set
 # CONFIG_EEPROM_AT25 is not set
 # CONFIG_EEPROM_LEGACY is not set
-# CONFIG_EEPROM_MAX6875 is not set
 CONFIG_EEPROM_93CX6=y
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
@@ -1000,7 +971,7 @@ CONFIG_RAID_ATTRS=m
 CONFIG_SCSI=y
 CONFIG_SCSI_DMA=y
 # CONFIG_SCSI_TGT is not set
-CONFIG_SCSI_NETLINK=y
+# CONFIG_SCSI_NETLINK is not set
 CONFIG_SCSI_PROC_FS=y
 
 #
@@ -1013,6 +984,10 @@ CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=y
 CONFIG_CHR_DEV_SCH=m
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
 CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
@@ -1023,20 +998,15 @@ CONFIG_SCSI_WAIT_SCAN=m
 # SCSI Transports
 #
 # CONFIG_SCSI_SPI_ATTRS is not set
-CONFIG_SCSI_FC_ATTRS=m
+# CONFIG_SCSI_FC_ATTRS is not set
 CONFIG_SCSI_ISCSI_ATTRS=m
 # CONFIG_SCSI_SAS_LIBSAS is not set
 # CONFIG_SCSI_SRP_ATTRS is not set
 CONFIG_SCSI_LOWLEVEL=y
 CONFIG_ISCSI_TCP=m
-CONFIG_LIBFC=m
-CONFIG_LIBFCOE=m
+# CONFIG_LIBFC is not set
 # CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_DH is not set
-CONFIG_SCSI_OSD_INITIATOR=m
-CONFIG_SCSI_OSD_ULD=m
-CONFIG_SCSI_OSD_DPRINT_SENSE=1
-# CONFIG_SCSI_OSD_DEBUG is not set
 # CONFIG_ATA is not set
 CONFIG_MD=y
 CONFIG_BLK_DEV_MD=m
@@ -1045,7 +1015,7 @@ CONFIG_MD_RAID0=m
 CONFIG_MD_RAID1=m
 CONFIG_MD_RAID10=m
 CONFIG_MD_RAID456=m
-CONFIG_MD_RAID6_PQ=m
+CONFIG_MD_RAID5_RESHAPE=y
 CONFIG_MD_MULTIPATH=m
 CONFIG_MD_FAULTY=m
 CONFIG_BLK_DEV_DM=m
@@ -1053,11 +1023,8 @@ CONFIG_BLK_DEV_DM=m
 CONFIG_DM_CRYPT=m
 CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
-CONFIG_DM_LOG_USERSPACE=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_QL=m
-CONFIG_DM_MULTIPATH_ST=m
 CONFIG_DM_DELAY=m
 # CONFIG_DM_UEVENT is not set
 CONFIG_NETDEVICES=y
@@ -1067,8 +1034,44 @@ CONFIG_MACVLAN=m
 CONFIG_EQUALIZER=m
 CONFIG_TUN=m
 CONFIG_VETH=m
-# CONFIG_NET_ETHERNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+CONFIG_ENC28J60=y
+# CONFIG_ENC28J60_WRITEVERIFY is not set
+CONFIG_SMC911X=y
+CONFIG_SMSC911X=y
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 
@@ -1080,28 +1083,20 @@ CONFIG_WLAN_80211=y
 CONFIG_LIBERTAS=y
 CONFIG_LIBERTAS_USB=y
 # CONFIG_LIBERTAS_SDIO is not set
-CONFIG_LIBERTAS_SPI=m
 # CONFIG_LIBERTAS_DEBUG is not set
 # CONFIG_LIBERTAS_THINFIRM is not set
-CONFIG_AT76C50X_USB=m
 CONFIG_USB_ZD1201=y
 CONFIG_USB_NET_RNDIS_WLAN=y
 CONFIG_RTL8187=y
-CONFIG_RTL8187_LEDS=y
 # CONFIG_MAC80211_HWSIM is not set
 CONFIG_P54_COMMON=y
 CONFIG_P54_USB=y
-# CONFIG_P54_SPI is not set
-CONFIG_P54_LEDS=y
-CONFIG_ATH_COMMON=m
-CONFIG_AR9170_USB=m
-CONFIG_AR9170_LEDS=y
+# CONFIG_IWLWIFI_LEDS is not set
 CONFIG_HOSTAP=y
 CONFIG_HOSTAP_FIRMWARE=y
 CONFIG_HOSTAP_FIRMWARE_NVRAM=y
 CONFIG_B43=y
 CONFIG_B43_LEDS=y
-CONFIG_B43_HWRNG=y
 # CONFIG_B43_DEBUG is not set
 # CONFIG_B43LEGACY is not set
 CONFIG_ZD1211RW=y
@@ -1109,18 +1104,12 @@ CONFIG_ZD1211RW=y
 CONFIG_RT2X00=y
 CONFIG_RT2500USB=y
 CONFIG_RT73USB=y
-CONFIG_RT2800USB=m
 CONFIG_RT2X00_LIB_USB=y
 CONFIG_RT2X00_LIB=y
-CONFIG_RT2X00_LIB_HT=y
 CONFIG_RT2X00_LIB_FIRMWARE=y
 CONFIG_RT2X00_LIB_CRYPTO=y
-CONFIG_RT2X00_LIB_RFKILL=y
 CONFIG_RT2X00_LIB_LEDS=y
 # CONFIG_RT2X00_DEBUG is not set
-CONFIG_WL12XX=m
-CONFIG_IWM=m
-# CONFIG_IWM_DEBUG is not set
 
 #
 # WiMAX Wireless Broadband devices
@@ -1138,7 +1127,6 @@ CONFIG_USB_RTL8150=y
 CONFIG_USB_USBNET=y
 CONFIG_USB_NET_AX8817X=y
 CONFIG_USB_NET_CDCETHER=y
-CONFIG_USB_NET_CDC_EEM=m
 CONFIG_USB_NET_DM9601=y
 CONFIG_USB_NET_SMSC95XX=y
 CONFIG_USB_NET_GL620A=y
@@ -1154,13 +1142,10 @@ CONFIG_USB_ARMLINUX=y
 CONFIG_USB_EPSON2888=y
 CONFIG_USB_KC2190=y
 CONFIG_USB_NET_ZAURUS=y
-CONFIG_USB_NET_INT51X1=m
 # CONFIG_WAN is not set
 CONFIG_ATM_DRIVERS=y
 # CONFIG_ATM_DUMMY is not set
 # CONFIG_ATM_TCP is not set
-CONFIG_IEEE802154_DRIVERS=m
-CONFIG_IEEE802154_FAKEHARD=m
 CONFIG_PPP=m
 CONFIG_PPP_MULTILINK=y
 CONFIG_PPP_FILTER=y
@@ -1186,7 +1171,7 @@ CONFIG_NET_POLL_CONTROLLER=y
 #
 CONFIG_INPUT=y
 CONFIG_INPUT_FF_MEMLESS=y
-CONFIG_INPUT_POLLDEV=y
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -1209,6 +1194,7 @@ CONFIG_INPUT_KEYBOARD=y
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_TWL4030 is not set
 # CONFIG_KEYBOARD_LM8323 is not set
 CONFIG_KEYBOARD_GPIO=y
 CONFIG_INPUT_MOUSE=y
@@ -1224,7 +1210,6 @@ CONFIG_MOUSE_PS2_TRACKPOINT=y
 # CONFIG_MOUSE_BCM5974 is not set
 # CONFIG_MOUSE_VSXXXAA is not set
 # CONFIG_MOUSE_GPIO is not set
-CONFIG_MOUSE_SYNAPTICS_I2C=m
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
@@ -1237,7 +1222,6 @@ CONFIG_INPUT_MISC=y
 # CONFIG_INPUT_CM109 is not set
 CONFIG_INPUT_TWL4030_PWRBUTTON=y
 CONFIG_INPUT_UINPUT=y
-CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
 
 #
 # Hardware I/O ports
@@ -1275,7 +1259,6 @@ CONFIG_SERIAL_8250_RSA=y
 #
 # Non-8250 serial port support
 #
-# CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
@@ -1283,7 +1266,6 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_IPMI_HANDLER is not set
 CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_TIMERIOMEM=m
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
@@ -1299,7 +1281,6 @@ CONFIG_I2C_HELPER_AUTO=y
 #
 # I2C system bus drivers (mostly embedded / system-on-chip)
 #
-# CONFIG_I2C_DESIGNWARE is not set
 # CONFIG_I2C_GPIO is not set
 # CONFIG_I2C_OCORES is not set
 CONFIG_I2C_OMAP=y
@@ -1325,7 +1306,12 @@ CONFIG_I2C_OMAP=y
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+CONFIG_TWL4030_MADC=m
+CONFIG_TWL4030_POWEROFF=y
+# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_TSL2563 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
@@ -1339,12 +1325,14 @@ CONFIG_SPI_MASTER=y
 #
 # CONFIG_SPI_BITBANG is not set
 # CONFIG_SPI_GPIO is not set
-# CONFIG_SPI_OMAP24XX is not set
+CONFIG_SPI_OMAP24XX=y
 
 #
 # SPI Protocol Masters
 #
-# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TSC210X is not set
+# CONFIG_SPI_TSC2301 is not set
+CONFIG_SPI_SPIDEV=y
 # CONFIG_SPI_TLE62X0 is not set
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
 CONFIG_GPIOLIB=y
@@ -1377,8 +1365,8 @@ CONFIG_POWER_SUPPLY=m
 # CONFIG_POWER_SUPPLY_DEBUG is not set
 # CONFIG_PDA_POWER is not set
 # CONFIG_BATTERY_DS2760 is not set
+# CONFIG_TWL4030_BCI_BATTERY is not set
 # CONFIG_BATTERY_BQ27x00 is not set
-# CONFIG_BATTERY_MAX17040 is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
 # CONFIG_SENSORS_AD7414 is not set
@@ -1399,7 +1387,6 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_F71805F is not set
 # CONFIG_SENSORS_F71882FG is not set
 # CONFIG_SENSORS_F75375S is not set
-# CONFIG_SENSORS_G760A is not set
 # CONFIG_SENSORS_GL518SM is not set
 # CONFIG_SENSORS_GL520SM is not set
 # CONFIG_SENSORS_IT87 is not set
@@ -1415,23 +1402,18 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_LM90 is not set
 # CONFIG_SENSORS_LM92 is not set
 # CONFIG_SENSORS_LM93 is not set
-# CONFIG_SENSORS_LTC4215 is not set
 # CONFIG_SENSORS_LTC4245 is not set
-# CONFIG_SENSORS_LM95241 is not set
 # CONFIG_SENSORS_MAX1111 is not set
 # CONFIG_SENSORS_MAX1619 is not set
 # CONFIG_SENSORS_MAX6650 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_SHT15 is not set
 # CONFIG_SENSORS_DME1737 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_SMSC47M192 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
 # CONFIG_SENSORS_ADS7828 is not set
 # CONFIG_SENSORS_THMC50 is not set
-# CONFIG_SENSORS_TMP401 is not set
 # CONFIG_SENSORS_VT1211 is not set
 # CONFIG_SENSORS_W83781D is not set
 # CONFIG_SENSORS_W83791D is not set
@@ -1441,7 +1423,6 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_W83L786NG is not set
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
-# CONFIG_SENSORS_LIS3_SPI is not set
 # CONFIG_SENSORS_TSC210X is not set
 CONFIG_SENSORS_OMAP34XX=y
 # CONFIG_HWMON_DEBUG_CHIP is not set
@@ -1455,7 +1436,6 @@ CONFIG_WATCHDOG_NOWAYOUT=y
 #
 # CONFIG_SOFT_WATCHDOG is not set
 CONFIG_OMAP_WATCHDOG=y
-CONFIG_TWL4030_WATCHDOG=m
 
 #
 # USB-based Watchdog Cards
@@ -1480,6 +1460,7 @@ CONFIG_SSB=y
 # CONFIG_HTC_PASIC3 is not set
 # CONFIG_TPS65010 is not set
 CONFIG_TWL4030_CORE=y
+# CONFIG_TWL4030_POWER is not set
 # CONFIG_MFD_TMIO is not set
 # CONFIG_MFD_T7L66XB is not set
 # CONFIG_MFD_TC6387XB is not set
@@ -1488,9 +1469,10 @@ CONFIG_TWL4030_CORE=y
 # CONFIG_MFD_WM8400 is not set
 # CONFIG_MFD_WM8350_I2C is not set
 # CONFIG_MFD_PCF50633 is not set
-# CONFIG_AB3100_CORE is not set
-# CONFIG_EZX_PCAP is not set
-CONFIG_MEDIA_SUPPORT=m
+
+#
+# Multimedia devices
+#
 
 #
 # Multimedia core support
@@ -1507,7 +1489,7 @@ CONFIG_VIDEO_MEDIA=m
 #
 CONFIG_MEDIA_ATTACH=y
 CONFIG_MEDIA_TUNER=m
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
 CONFIG_MEDIA_TUNER_SIMPLE=m
 CONFIG_MEDIA_TUNER_TDA8290=m
 CONFIG_MEDIA_TUNER_TDA827X=m
@@ -1522,11 +1504,10 @@ CONFIG_MEDIA_TUNER_QT1010=m
 CONFIG_MEDIA_TUNER_XC2028=m
 CONFIG_MEDIA_TUNER_XC5000=m
 CONFIG_MEDIA_TUNER_MXL5005S=m
-CONFIG_MEDIA_TUNER_MXL5007T=m
-CONFIG_MEDIA_TUNER_MC44S803=m
 CONFIG_VIDEO_V4L2=m
 CONFIG_VIDEO_V4L1=m
 CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEOBUF_DMA_SG=m
 CONFIG_VIDEOBUF_VMALLOC=m
 CONFIG_VIDEOBUF_DVB=m
 CONFIG_VIDEO_IR=m
@@ -1550,6 +1531,8 @@ CONFIG_VIDEO_VIVI=m
 # CONFIG_VIDEO_SAA5246A is not set
 # CONFIG_VIDEO_SAA5249 is not set
 # CONFIG_VIDEO_AU0828 is not set
+CONFIG_VIDEO_OMAP3=m
+CONFIG_VIDEO_OMAP34XX_ISP_RESIZER=m
 # CONFIG_SOC_CAMERA is not set
 CONFIG_V4L_USB_DRIVERS=y
 CONFIG_USB_VIDEO_CLASS=m
@@ -1561,7 +1544,6 @@ CONFIG_USB_GSPCA_CONEX=m
 CONFIG_USB_GSPCA_ETOMS=m
 CONFIG_USB_GSPCA_FINEPIX=m
 CONFIG_USB_GSPCA_MARS=m
-CONFIG_USB_GSPCA_MR97310A=m
 CONFIG_USB_GSPCA_OV519=m
 CONFIG_USB_GSPCA_OV534=m
 CONFIG_USB_GSPCA_PAC207=m
@@ -1574,8 +1556,6 @@ CONFIG_USB_GSPCA_SPCA505=m
 CONFIG_USB_GSPCA_SPCA506=m
 CONFIG_USB_GSPCA_SPCA508=m
 CONFIG_USB_GSPCA_SPCA561=m
-CONFIG_USB_GSPCA_SQ905=m
-CONFIG_USB_GSPCA_SQ905C=m
 CONFIG_USB_GSPCA_STK014=m
 CONFIG_USB_GSPCA_SUNPLUS=m
 CONFIG_USB_GSPCA_T613=m
@@ -1586,13 +1566,9 @@ CONFIG_VIDEO_PVRUSB2=m
 CONFIG_VIDEO_PVRUSB2_SYSFS=y
 CONFIG_VIDEO_PVRUSB2_DVB=y
 # CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
-CONFIG_VIDEO_HDPVR=m
 CONFIG_VIDEO_EM28XX=m
 CONFIG_VIDEO_EM28XX_ALSA=m
 CONFIG_VIDEO_EM28XX_DVB=m
-CONFIG_VIDEO_CX231XX=m
-CONFIG_VIDEO_CX231XX_ALSA=m
-CONFIG_VIDEO_CX231XX_DVB=m
 CONFIG_VIDEO_USBVISION=m
 CONFIG_VIDEO_USBVIDEO=m
 CONFIG_USB_VICAM=m
@@ -1609,7 +1585,6 @@ CONFIG_USB_STV680=m
 CONFIG_USB_ZC0301=m
 CONFIG_USB_PWC=m
 # CONFIG_USB_PWC_DEBUG is not set
-CONFIG_USB_PWC_INPUT_EVDEV=y
 CONFIG_USB_ZR364XX=m
 CONFIG_USB_STKWEBCAM=m
 CONFIG_USB_S2255=m
@@ -1652,7 +1627,6 @@ CONFIG_DVB_USB_CINERGY_T2=m
 CONFIG_DVB_USB_ANYSEE=m
 CONFIG_DVB_USB_DTV5100=m
 CONFIG_DVB_USB_AF9015=m
-CONFIG_DVB_USB_CE6230=m
 CONFIG_DVB_SIANO_SMS1XXX=m
 CONFIG_DVB_SIANO_SMS1XXX_SMS_IDS=y
 
@@ -1666,20 +1640,48 @@ CONFIG_DVB_B2C2_FLEXCOP_USB=m
 #
 # Supported DVB Frontends
 #
+
+#
+# Customise DVB Frontends
+#
 # CONFIG_DVB_FE_CUSTOMISE is not set
+
+#
+# Multistandard (satellite) frontends
+#
+CONFIG_DVB_STB0899=m
+CONFIG_DVB_STB6100=m
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24110=m
 CONFIG_DVB_CX24123=m
 CONFIG_DVB_MT312=m
 CONFIG_DVB_S5H1420=m
 CONFIG_DVB_STV0288=m
 CONFIG_DVB_STB6000=m
 CONFIG_DVB_STV0299=m
+CONFIG_DVB_TDA8083=m
 CONFIG_DVB_TDA10086=m
+CONFIG_DVB_TDA8261=m
+CONFIG_DVB_VES1X93=m
 CONFIG_DVB_TUNER_ITD1000=m
 CONFIG_DVB_TUNER_CX24113=m
 CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TUA6100=m
 CONFIG_DVB_CX24116=m
 CONFIG_DVB_SI21XX=m
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_CX22700=m
 CONFIG_DVB_CX22702=m
+CONFIG_DVB_DRX397XD=m
+CONFIG_DVB_L64781=m
 CONFIG_DVB_TDA1004X=m
 CONFIG_DVB_NXT6000=m
 CONFIG_DVB_MT352=m
@@ -1689,21 +1691,52 @@ CONFIG_DVB_DIB3000MC=m
 CONFIG_DVB_DIB7000M=m
 CONFIG_DVB_DIB7000P=m
 CONFIG_DVB_TDA10048=m
-CONFIG_DVB_AF9013=m
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_VES1820=m
 CONFIG_DVB_TDA10021=m
 CONFIG_DVB_TDA10023=m
 CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
 CONFIG_DVB_NXT200X=m
+CONFIG_DVB_OR51211=m
+CONFIG_DVB_OR51132=m
 CONFIG_DVB_BCM3510=m
 CONFIG_DVB_LGDT330X=m
-CONFIG_DVB_LGDT3305=m
+CONFIG_DVB_LGDT3304=m
 CONFIG_DVB_S5H1409=m
+CONFIG_DVB_AU8522=m
 CONFIG_DVB_S5H1411=m
+
+#
+# ISDB-T (terrestrial) frontends
+#
+CONFIG_DVB_S921=m
+
+#
+# Digital terrestrial only tuners/PLL
+#
 CONFIG_DVB_PLL=m
 CONFIG_DVB_TUNER_DIB0070=m
+
+#
+# SEC control devices for DVB-S
+#
 CONFIG_DVB_LNBP21=m
+# CONFIG_DVB_ISL6405 is not set
 CONFIG_DVB_ISL6421=m
 CONFIG_DVB_LGS8GL5=m
+
+#
+# Tools to develop new frontends
+#
+# CONFIG_DVB_DUMMY_FE is not set
+CONFIG_DVB_AF9013=m
 # CONFIG_DAB is not set
 
 #
@@ -1719,12 +1752,11 @@ CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
 # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-CONFIG_FB_SYS_FILLRECT=m
-CONFIG_FB_SYS_COPYAREA=m
-CONFIG_FB_SYS_IMAGEBLIT=m
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
 # CONFIG_FB_FOREIGN_ENDIAN is not set
-CONFIG_FB_SYS_FOPS=m
-CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SYS_FOPS is not set
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -1734,15 +1766,13 @@ CONFIG_FB_DEFERRED_IO=y
 #
 # Frame buffer hardware drivers
 #
-# CONFIG_FB_UVESA is not set
 # CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_VIRTUAL is not set
 # CONFIG_FB_METRONOME is not set
 # CONFIG_FB_MB862XX is not set
-CONFIG_FB_BROADSHEET=m
 # CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
 CONFIG_OMAP2_DSS=y
-CONFIG_OMAP2_VRAM_SIZE=14
+CONFIG_OMAP2_DSS_VRAM_SIZE=14
 CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
 # CONFIG_OMAP2_DSS_RFBI is not set
 CONFIG_OMAP2_DSS_VENC=y
@@ -1797,7 +1827,6 @@ CONFIG_SND_TIMER=y
 CONFIG_SND_PCM=y
 CONFIG_SND_HWDEP=y
 CONFIG_SND_RAWMIDI=y
-CONFIG_SND_JACK=y
 CONFIG_SND_SEQUENCER=m
 # CONFIG_SND_SEQ_DUMMY is not set
 CONFIG_SND_OSSEMUL=y
@@ -1812,11 +1841,6 @@ CONFIG_SND_SUPPORT_OLD_API=y
 CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
-CONFIG_SND_RAWMIDI_SEQ=m
-# CONFIG_SND_OPL3_LIB_SEQ is not set
-# CONFIG_SND_OPL4_LIB_SEQ is not set
-# CONFIG_SND_SBAWE_SEQ is not set
-# CONFIG_SND_EMU10K1_SEQ is not set
 CONFIG_SND_DRIVERS=y
 # CONFIG_SND_DUMMY is not set
 # CONFIG_SND_VIRMIDI is not set
@@ -1832,6 +1856,7 @@ CONFIG_SND_USB_CAIAQ_INPUT=y
 CONFIG_SND_SOC=y
 CONFIG_SND_OMAP_SOC=y
 CONFIG_SND_OMAP_SOC_MCBSP=y
+# CONFIG_SND_OMAP_SOC_OVERO is not set
 CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE=y
 CONFIG_SND_SOC_I2C_AND_SPI=y
 # CONFIG_SND_SOC_ALL_CODECS is not set
@@ -1852,17 +1877,15 @@ CONFIG_USB_HID=y
 #
 # Special HID drivers
 #
+CONFIG_HID_COMPAT=y
 CONFIG_HID_A4TECH=y
 CONFIG_HID_APPLE=y
 CONFIG_HID_BELKIN=y
 CONFIG_HID_CHERRY=y
 CONFIG_HID_CHICONY=y
 CONFIG_HID_CYPRESS=y
-# CONFIG_HID_DRAGONRISE is not set
 CONFIG_HID_EZKEY=y
-# CONFIG_HID_KYE is not set
 CONFIG_HID_GYRATION=y
-# CONFIG_HID_KENSINGTON is not set
 CONFIG_HID_LOGITECH=y
 # CONFIG_LOGITECH_FF is not set
 # CONFIG_LOGIRUMBLEPAD2_FF is not set
@@ -1875,13 +1898,10 @@ CONFIG_HID_PETALYNX=y
 CONFIG_HID_SAMSUNG=y
 CONFIG_HID_SONY=y
 CONFIG_HID_SUNPLUS=y
-# CONFIG_HID_GREENASIA is not set
-CONFIG_HID_SMARTJOYPLUS=m
-# CONFIG_SMARTJOYPLUS_FF is not set
+CONFIG_GREENASIA_FF=y
 CONFIG_HID_TOPSEED=y
-# CONFIG_HID_THRUSTMASTER is not set
-CONFIG_HID_WACOM=m
-# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
@@ -1909,11 +1929,12 @@ CONFIG_USB_MON=y
 #
 # CONFIG_USB_C67X00_HCD is not set
 CONFIG_USB_EHCI_HCD=y
+CONFIG_OMAP_EHCI_PHY_MODE=y
+# CONFIG_OMAP_EHCI_TLL_MODE is not set
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_USB_EHCI_TT_NEWSCHED=y
 CONFIG_USB_OXU210HP_HCD=y
 # CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
 # CONFIG_USB_OHCI_HCD is not set
 # CONFIG_USB_U132_HCD is not set
 # CONFIG_USB_SL811_HCD is not set
@@ -1944,11 +1965,11 @@ CONFIG_USB_WDM=m
 CONFIG_USB_TMC=m
 
 #
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
 #
 
 #
-# also be needed; see USB_STORAGE Help for more info
+# see USB_STORAGE Help for more information
 #
 CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_DEBUG is not set
@@ -1983,7 +2004,7 @@ CONFIG_USB_SERIAL_BELKIN=m
 CONFIG_USB_SERIAL_CH341=m
 CONFIG_USB_SERIAL_WHITEHEAT=m
 CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_CP2101=m
 CONFIG_USB_SERIAL_CYPRESS_M8=m
 CONFIG_USB_SERIAL_EMPEG=m
 CONFIG_USB_SERIAL_FTDI_SIO=m
@@ -2019,14 +2040,12 @@ CONFIG_USB_SERIAL_MOTOROLA=m
 CONFIG_USB_SERIAL_NAVMAN=m
 CONFIG_USB_SERIAL_PL2303=m
 CONFIG_USB_SERIAL_OTI6858=m
-CONFIG_USB_SERIAL_QUALCOMM=m
 CONFIG_USB_SERIAL_SPCP8X5=m
 CONFIG_USB_SERIAL_HP4X=m
 CONFIG_USB_SERIAL_SAFE=m
 # CONFIG_USB_SERIAL_SAFE_PADDED is not set
 CONFIG_USB_SERIAL_SIEMENS_MPI=m
 CONFIG_USB_SERIAL_SIERRAWIRELESS=m
-CONFIG_USB_SERIAL_SYMBOL=m
 CONFIG_USB_SERIAL_TI=m
 CONFIG_USB_SERIAL_CYBERJACK=m
 CONFIG_USB_SERIAL_XIRCOM=m
@@ -2049,6 +2068,10 @@ CONFIG_USB_BERRY_CHARGE=m
 CONFIG_USB_LED=m
 CONFIG_USB_CYPRESS_CY7C63=m
 CONFIG_USB_CYTHERM=m
+CONFIG_USB_PHIDGET=m
+CONFIG_USB_PHIDGETKIT=m
+CONFIG_USB_PHIDGETMOTORCONTROL=m
+CONFIG_USB_PHIDGETSERVO=m
 CONFIG_USB_IDMOUSE=m
 CONFIG_USB_FTDI_ELAN=m
 # CONFIG_USB_APPLEDISPLAY is not set
@@ -2078,7 +2101,6 @@ CONFIG_USB_GADGET_SELECTED=y
 # CONFIG_USB_GADGET_OMAP is not set
 # CONFIG_USB_GADGET_PXA25X is not set
 # CONFIG_USB_GADGET_PXA27X is not set
-# CONFIG_USB_GADGET_S3C_HSOTG is not set
 # CONFIG_USB_GADGET_S3C2410 is not set
 # CONFIG_USB_GADGET_IMX is not set
 # CONFIG_USB_GADGET_M66592 is not set
@@ -2087,12 +2109,10 @@ CONFIG_USB_GADGET_SELECTED=y
 # CONFIG_USB_GADGET_CI13XXX is not set
 # CONFIG_USB_GADGET_NET2280 is not set
 # CONFIG_USB_GADGET_GOKU is not set
-# CONFIG_USB_GADGET_LANGWELL is not set
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
 CONFIG_USB_GADGET_DUALSPEED=y
 CONFIG_USB_ZERO=m
 CONFIG_USB_ZERO_HNPTEST=y
-CONFIG_USB_AUDIO=m
 CONFIG_USB_ETH=m
 CONFIG_USB_ETH_RNDIS=y
 CONFIG_USB_GADGETFS=m
@@ -2110,7 +2130,7 @@ CONFIG_USB_OTG_UTILS=y
 CONFIG_USB_GPIO_VBUS=y
 # CONFIG_ISP1301_OMAP is not set
 CONFIG_TWL4030_USB=y
-CONFIG_NOP_USB_XCEIV=y
+# CONFIG_NOP_USB_XCEIV is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 CONFIG_MMC_UNSAFE_RESUME=y
@@ -2142,11 +2162,8 @@ CONFIG_LEDS_OMAP=y
 # CONFIG_LEDS_OMAP_PWM is not set
 # CONFIG_LEDS_PCA9532 is not set
 CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_GPIO_PLATFORM=y
 # CONFIG_LEDS_LP5521 is not set
 # CONFIG_LEDS_PCA955X is not set
-# CONFIG_LEDS_DAC124S085 is not set
-# CONFIG_LEDS_BD2802 is not set
 
 #
 # LED Triggers
@@ -2155,12 +2172,7 @@ CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=m
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_BACKLIGHT=m
-CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
-
-#
-# iptables trigger is under Netfilter config (LED target)
-#
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -2179,7 +2191,7 @@ CONFIG_RTC_INTF_DEV=y
 #
 # I2C RTC drivers
 #
-# CONFIG_RTC_DRV_DS1307 is not set
+CONFIG_RTC_DRV_DS1307=y
 # CONFIG_RTC_DRV_DS1374 is not set
 # CONFIG_RTC_DRV_DS1672 is not set
 # CONFIG_RTC_DRV_MAX6900 is not set
@@ -2189,11 +2201,10 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_PCF8563 is not set
 # CONFIG_RTC_DRV_PCF8583 is not set
 # CONFIG_RTC_DRV_M41T80 is not set
-CONFIG_RTC_DRV_TWL4030=y
+CONFIG_RTC_DRV_TWL4030=m
 # CONFIG_RTC_DRV_S35390A is not set
 # CONFIG_RTC_DRV_FM3130 is not set
 # CONFIG_RTC_DRV_RX8581 is not set
-# CONFIG_RTC_DRV_RX8025 is not set
 
 #
 # SPI RTC drivers
@@ -2225,16 +2236,12 @@ CONFIG_RTC_DRV_TWL4030=y
 # on-CPU RTC drivers
 #
 # CONFIG_DMADEVICES is not set
-# CONFIG_AUXDISPLAY is not set
 CONFIG_REGULATOR=y
 # CONFIG_REGULATOR_DEBUG is not set
 # CONFIG_REGULATOR_FIXED_VOLTAGE is not set
 # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-CONFIG_REGULATOR_USERSPACE_CONSUMER=m
 # CONFIG_REGULATOR_BQ24022 is not set
-# CONFIG_REGULATOR_MAX1586 is not set
 CONFIG_REGULATOR_TWL4030=y
-# CONFIG_REGULATOR_LP3971 is not set
 CONFIG_UIO=m
 CONFIG_UIO_PDRV=m
 CONFIG_UIO_PDRV_GENIRQ=m
@@ -2245,7 +2252,7 @@ CONFIG_STAGING=y
 # CONFIG_MEILHAUS is not set
 # CONFIG_USB_IP_COMMON is not set
 CONFIG_W35UND=m
-# CONFIG_PRISM2_USB is not set
+CONFIG_PRISM2_USB=m
 # CONFIG_ECHO is not set
 CONFIG_USB_ATMEL=m
 # CONFIG_AGNX is not set
@@ -2265,22 +2272,8 @@ CONFIG_ANDROID_RAM_CONSOLE=y
 CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y
 # CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION is not set
 # CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT is not set
-CONFIG_ANDROID_TIMED_OUTPUT=y
 CONFIG_ANDROID_TIMED_GPIO=m
-# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set
-# CONFIG_DST is not set
-CONFIG_POHMELFS=m
-# CONFIG_POHMELFS_DEBUG is not set
-CONFIG_POHMELFS_CRYPTO=y
-# CONFIG_STLC45XX is not set
-CONFIG_USB_SERIAL_ATEN2011=m
-# CONFIG_B3DFG is not set
-# CONFIG_PLAN9AUTH is not set
-# CONFIG_HECI is not set
-# CONFIG_LINE6_USB is not set
-CONFIG_USB_SERIAL_QUATECH2=m
-CONFIG_USB_CPC=m
-# CONFIG_FB_UDL is not set
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
 
 #
 # CBUS support
@@ -2294,7 +2287,6 @@ CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
 CONFIG_EXT4_FS=m
 # CONFIG_EXT4DEV_COMPAT is not set
@@ -2318,13 +2310,14 @@ CONFIG_JFS_FS=m
 # CONFIG_JFS_DEBUG is not set
 # CONFIG_JFS_STATISTICS is not set
 CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
 CONFIG_XFS_FS=m
 # CONFIG_XFS_QUOTA is not set
 # CONFIG_XFS_POSIX_ACL is not set
 # CONFIG_XFS_RT is not set
 # CONFIG_XFS_DEBUG is not set
 CONFIG_GFS2_FS=m
-# CONFIG_GFS2_FS_LOCKING_DLM is not set
+CONFIG_GFS2_FS_LOCKING_DLM=m
 CONFIG_OCFS2_FS=m
 CONFIG_OCFS2_FS_O2CB=m
 CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
@@ -2334,8 +2327,6 @@ CONFIG_OCFS2_DEBUG_MASKLOG=y
 # CONFIG_OCFS2_FS_POSIX_ACL is not set
 CONFIG_BTRFS_FS=m
 # CONFIG_BTRFS_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
-CONFIG_FSNOTIFY=y
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -2349,12 +2340,6 @@ CONFIG_QUOTACTL=y
 # CONFIG_AUTOFS_FS is not set
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
-CONFIG_CUSE=m
-
-#
-# Caches
-#
-# CONFIG_FSCACHE is not set
 
 #
 # CD-ROM/DVD Filesystems
@@ -2432,22 +2417,15 @@ CONFIG_OMFS_FS=m
 CONFIG_HPFS_FS=m
 CONFIG_QNX4FS_FS=m
 CONFIG_ROMFS_FS=m
-CONFIG_ROMFS_BACKED_BY_BLOCK=y
-# CONFIG_ROMFS_BACKED_BY_MTD is not set
-# CONFIG_ROMFS_BACKED_BY_BOTH is not set
-CONFIG_ROMFS_ON_BLOCK=y
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 # CONFIG_UFS_FS_WRITE is not set
 # CONFIG_UFS_DEBUG is not set
-# CONFIG_EXOFS_FS is not set
-CONFIG_NILFS2_FS=m
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
-CONFIG_NFS_V4_1=y
 CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V2_ACL=y
@@ -2461,6 +2439,7 @@ CONFIG_NFS_ACL_SUPPORT=m
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -2472,8 +2451,8 @@ CONFIG_CIFS_STATS2=y
 # CONFIG_CIFS_UPCALL is not set
 # CONFIG_CIFS_XATTR is not set
 # CONFIG_CIFS_DEBUG2 is not set
-# CONFIG_CIFS_DFS_UPCALL is not set
 CONFIG_CIFS_EXPERIMENTAL=y
+# CONFIG_CIFS_DFS_UPCALL is not set
 CONFIG_NCP_FS=m
 # CONFIG_NCPFS_PACKET_SIGNING is not set
 # CONFIG_NCPFS_IOCTL_LOCKING is not set
@@ -2569,15 +2548,12 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_SOFTLOCKUP=y
 # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 CONFIG_SCHEDSTATS=y
 CONFIG_TIMER_STATS=y
 # CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
+CONFIG_DEBUG_PREEMPT=y
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
@@ -2597,6 +2573,7 @@ CONFIG_STACKTRACE=y
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
 # CONFIG_DEBUG_NOTIFIERS is not set
+CONFIG_FRAME_POINTER=y
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
@@ -2604,20 +2581,27 @@ CONFIG_STACKTRACE=y
 # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_LATENCYTOP is not set
-# CONFIG_PAGE_POISONING is not set
 CONFIG_NOP_TRACER=y
 CONFIG_HAVE_FUNCTION_TRACER=y
 CONFIG_RING_BUFFER=y
-CONFIG_EVENT_TRACING=y
-CONFIG_CONTEXT_SWITCH_TRACER=y
 CONFIG_TRACING=y
-CONFIG_TRACING_SUPPORT=y
-# CONFIG_FTRACE is not set
-# CONFIG_DYNAMIC_DEBUG is not set
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
-CONFIG_ARM_UNWIND=y
 # CONFIG_DEBUG_USER is not set
 # CONFIG_DEBUG_ERRORS is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
@@ -2651,12 +2635,10 @@ CONFIG_CRYPTO_HASH=y
 CONFIG_CRYPTO_HASH2=y
 CONFIG_CRYPTO_RNG=m
 CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_PCOMP=y
 CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_MANAGER2=y
 CONFIG_CRYPTO_GF128MUL=m
 CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_WORKQUEUE=y
 CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_AUTHENC=m
 CONFIG_CRYPTO_TEST=m
@@ -2726,7 +2708,6 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m
 # Compression
 #
 CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_ZLIB=m
 CONFIG_CRYPTO_LZO=y
 
 #
@@ -2734,7 +2715,6 @@ CONFIG_CRYPTO_LZO=y
 #
 CONFIG_CRYPTO_ANSI_CPRNG=m
 CONFIG_CRYPTO_HW=y
-CONFIG_BINARY_PRINTF=y
 
 #
 # Library routines
@@ -2752,14 +2732,11 @@ CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
 CONFIG_LZO_COMPRESS=y
 CONFIG_LZO_DECOMPRESS=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_LZMA=y
 CONFIG_TEXTSEARCH=y
 CONFIG_TEXTSEARCH_KMP=m
 CONFIG_TEXTSEARCH_BM=m
 CONFIG_TEXTSEARCH_FSM=m
+CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
-CONFIG_NLATTR=y
diff --git a/recipes/linux/linux-omap-2.6.31/beagleboard/logo_linux_clut224.ppm b/recipes/linux/linux-omap-2.6.31/beagleboard/logo_linux_clut224.ppm
new file mode 100644 (file)
index 0000000..d29fc1c
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.31/beagleboard/logo_linux_clut224.ppm
@@ -0,0 +1,73147 @@
+P3
+# CREATOR: GIMP PNM Filter Version 1.1
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diff --git a/recipes/linux/linux-omap-2.6.31/cache/copy-page-tweak.patch b/recipes/linux/linux-omap-2.6.31/cache/copy-page-tweak.patch
new file mode 100644 (file)
index 0000000..9da3740
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.31/cache/copy-page-tweak.patch
@@ -0,0 +1,169 @@
+Path: news.gmane.org!not-for-mail
+From: "Kirill A. Shutemov" <kirill@shutemov.name>
+Newsgroups: gmane.linux.ports.arm.kernel
+Subject: [PATCH] ARM: copy_page.S: take into account the size of the cache line
+Date: Wed,  2 Sep 2009 20:19:58 +0300
+Lines: 92
+Approved: news@gmane.org
+Message-ID: <1251911998-3112-1-git-send-email-kirill__11898.5180197798$1251901300$gmane$org@shutemov.name>
+References: <20090902132423.GA12595@n2100.arm.linux.org.uk>
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+Content-Transfer-Encoding: 7bit
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+X-Complaints-To: usenet@ger.gmane.org
+NNTP-Posting-Date: Wed, 2 Sep 2009 14:21:40 +0000 (UTC)
+Cc: Bityutskiy Artem <Artem.Bityutskiy@nokia.com>,
+       "Kirill A. Shutemov" <kirill@shutemov.name>,
+       Siarhei Siamashka <siarhei.siamashka@nokia.com>,
+       Moiseichuk Leonid <leonid.moiseichuk@nokia.com>,
+       Koskinen Aaro <aaro.koskinen@nokia.com>
+To: linux-arm-kernel@lists.infradead.org,
+       linux-kernel@vger.kernel.org
+Original-X-From: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org Wed Sep 02 16:21:32 2009
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+Xref: news.gmane.org gmane.linux.ports.arm.kernel:65025
+Archived-At: <http://permalink.gmane.org/gmane.linux.ports.arm.kernel/65025>
+
+Optimized version of copy_page() was written with assumption that cache
+line size is 32 bytes. On Cortex-A8 cache line size is 64 bytes.
+
+This patch tries to generalize copy_page() to work with any cache line
+size if cache line size is multiple of 16 and page size is multiple of
+two cache line size.
+
+After this optimization we've got ~25% speedup on OMAP3(tested in
+userspace).
+
+There is test for kernelspace which trigger copy-on-write after fork():
+
+ #include <stdlib.h>
+ #include <string.h>
+ #include <unistd.h>
+
+ #define BUF_SIZE (10000*4096)
+ #define NFORK 200
+
+ int main(int argc, char **argv)
+ {
+         char *buf = malloc(BUF_SIZE);
+         int i;
+
+         memset(buf, 0, BUF_SIZE);
+
+         for(i = 0; i < NFORK; i++) {
+                 if (fork()) {
+                         wait(NULL);
+                 } else {
+                         int j;
+
+                         for(j = 0; j < BUF_SIZE; j+= 4096)
+                                 buf[j] = (j & 0xFF) + 1;
+                         break;
+                 }
+         }
+
+         free(buf);
+         return 0;
+ }
+
+Before optimization this test takes ~66 seconds, after optimization
+takes ~56 seconds.
+
+Signed-off-by: Siarhei Siamashka <siarhei.siamashka@nokia.com>
+Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
+---
+ arch/arm/lib/copy_page.S |   16 ++++++++--------
+ 1 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/lib/copy_page.S b/arch/arm/lib/copy_page.S
+index 6ae04db..6ee2f67 100644
+--- a/arch/arm/lib/copy_page.S
++++ b/arch/arm/lib/copy_page.S
+@@ -12,8 +12,9 @@
+ #include <linux/linkage.h>
+ #include <asm/assembler.h>
+ #include <asm/asm-offsets.h>
++#include <asm/cache.h>
+ 
+-#define COPY_COUNT (PAGE_SZ/64 PLD( -1 ))
++#define COPY_COUNT (PAGE_SZ / (2 * L1_CACHE_BYTES) PLD( -1 ))
+ 
+               .text
+               .align  5
+@@ -26,17 +27,16 @@
+ ENTRY(copy_page)
+               stmfd   sp!, {r4, lr}                   @       2
+       PLD(    pld     [r1, #0]                )
+-      PLD(    pld     [r1, #32]               )
++      PLD(    pld     [r1, #L1_CACHE_BYTES]           )
+               mov     r2, #COPY_COUNT                 @       1
+               ldmia   r1!, {r3, r4, ip, lr}           @       4+1
+-1:    PLD(    pld     [r1, #64]               )
+-      PLD(    pld     [r1, #96]               )
+-2:            stmia   r0!, {r3, r4, ip, lr}           @       4
+-              ldmia   r1!, {r3, r4, ip, lr}           @       4+1
+-              stmia   r0!, {r3, r4, ip, lr}           @       4
+-              ldmia   r1!, {r3, r4, ip, lr}           @       4+1
++1:    PLD(    pld     [r1, #2 * L1_CACHE_BYTES])
++      PLD(    pld     [r1, #3 * L1_CACHE_BYTES])
++2:
++      .rept   (2 * L1_CACHE_BYTES / 16 - 1)
+               stmia   r0!, {r3, r4, ip, lr}           @       4
+               ldmia   r1!, {r3, r4, ip, lr}           @       4
++      .endr
+               subs    r2, r2, #1                      @       1
+               stmia   r0!, {r3, r4, ip, lr}           @       4
+               ldmgtia r1!, {r3, r4, ip, lr}           @       4
+-- 
+1.6.4.2
diff --git a/recipes/linux/linux-omap-2.6.31/cache/l1cache-shift.patch b/recipes/linux/linux-omap-2.6.31/cache/l1cache-shift.patch
new file mode 100644 (file)
index 0000000..e58d49c
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.31/cache/l1cache-shift.patch
@@ -0,0 +1,115 @@
+Path: news.gmane.org!not-for-mail
+From: "Kirill A. Shutemov" <kirill@shutemov.name>
+Newsgroups: gmane.linux.ports.arm.kernel
+Subject: [PATCH 1/2] ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line
+       size
+Date: Wed,  2 Sep 2009 19:11:52 +0300
+Lines: 39
+Approved: news@gmane.org
+Message-ID: <1251907913-16261-1-git-send-email-kirill__21953.4654439942$1251897245$gmane$org@shutemov.name>
+NNTP-Posting-Host: lo.gmane.org
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+NNTP-Posting-Date: Wed, 2 Sep 2009 13:14:05 +0000 (UTC)
+Cc: Bityutskiy Artem <Artem.Bityutskiy@nokia.com>,
+       "Kirill A. Shutemov" <kirill@shutemov.name>,
+       Siarhei Siamashka <siarhei.siamashka@nokia.com>,
+       Moiseichuk Leonid <leonid.moiseichuk@nokia.com>,
+       Koskinen Aaro <aaro.koskinen@nokia.com>
+To: linux-arm-kernel@lists.infradead.org,
+       linux-kernel@vger.kernel.org
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+Xref: news.gmane.org gmane.linux.ports.arm.kernel:65017
+Archived-At: <http://permalink.gmane.org/gmane.linux.ports.arm.kernel/65017>
+
+Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5.
+It's not true at least for CPUs based on Cortex-A8.
+
+List of CPUs with cache line size != 32 should be expanded later.
+
+Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
+---
+ arch/arm/include/asm/cache.h |    2 +-
+ arch/arm/mm/Kconfig          |    5 +++++
+ 2 files changed, 6 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
+index feaa75f..2ee7743 100644
+--- a/arch/arm/include/asm/cache.h
++++ b/arch/arm/include/asm/cache.h
+@@ -4,7 +4,7 @@
+ #ifndef __ASMARM_CACHE_H
+ #define __ASMARM_CACHE_H
+ 
+-#define L1_CACHE_SHIFT                5
++#define L1_CACHE_SHIFT                (CONFIG_ARM_L1_CACHE_SHIFT)
+ #define L1_CACHE_BYTES                (1 << L1_CACHE_SHIFT)
+ 
+ /*
+diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
+index 83c025e..3c37d4c 100644
+--- a/arch/arm/mm/Kconfig
++++ b/arch/arm/mm/Kconfig
+@@ -771,3 +771,8 @@ config CACHE_XSC3L2
+       select OUTER_CACHE
+       help
+         This option enables the L2 cache on XScale3.
++
++config ARM_L1_CACHE_SHIFT
++      int
++      default 6 if ARCH_OMAP3
++      default 5
+-- 
+1.6.3.4
diff --git a/recipes/linux/linux-omap-2.6.31/dss2/0001-OMAP2-Add-funcs-for-writing-SMS_ROT_-registers.patch b/recipes/linux/linux-omap-2.6.31/dss2/0001-OMAP2-Add-funcs-for-writing-SMS_ROT_-registers.patch
new file mode 100644 (file)
index 0000000..8880c8b
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.31/dss2/0001-OMAP2-Add-funcs-for-writing-SMS_ROT_-registers.patch
@@ -0,0 +1,69 @@
+From 17091382ab8f92a366e7e1267c30f83711ccd9f8 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Fri, 7 Aug 2009 11:26:12 +0300
+Subject: [PATCH 01/18] OMAP2: Add funcs for writing SMS_ROT_* registers
+
+SMS_ROT_* registers are used by VRFB rotation engine.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Acked-by: Tony Lindgren <tony@atomide.com>
+Acked-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/sdrc.c             |   16 ++++++++++++++++
+ arch/arm/plat-omap/include/mach/sdrc.h |    9 ++++++++-
+ 2 files changed, 24 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
+index 9e3bd4f..6a5a2c5 100644
+--- a/arch/arm/mach-omap2/sdrc.c
++++ b/arch/arm/mach-omap2/sdrc.c
+@@ -133,3 +133,19 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+               (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
+       sdrc_write_reg(l, SDRC_POWER);
+ }
++
++void omap2_sms_write_rot_control(u32 val, unsigned ctx)
++{
++      sms_write_reg(val, SMS_ROT_CONTROL(ctx));
++}
++
++void omap2_sms_write_rot_size(u32 val, unsigned ctx)
++{
++      sms_write_reg(val, SMS_ROT_SIZE(ctx));
++}
++
++void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx)
++{
++      sms_write_reg(val, SMS_ROT_PHYSICAL_BA(ctx));
++}
++
+diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h
+index 0be18e4..6438f0f 100644
+--- a/arch/arm/plat-omap/include/mach/sdrc.h
++++ b/arch/arm/plat-omap/include/mach/sdrc.h
+@@ -79,7 +79,10 @@
+ 
+ /* SMS register offsets - read/write with sms_{read,write}_reg() */
+ 
+-#define SMS_SYSCONFIG         0x010
++#define SMS_SYSCONFIG                 0x010
++#define SMS_ROT_CONTROL(context)      (0x180 + 0x10 * context)
++#define SMS_ROT_SIZE(context)         (0x184 + 0x10 * context)
++#define SMS_ROT_PHYSICAL_BA(context)  (0x188 + 0x10 * context)
+ /* REVISIT: fill in other SMS registers here */
+ 
+ 
+@@ -112,6 +115,10 @@ int omap2_sdrc_get_params(unsigned long r,
+                         struct omap_sdrc_params **sdrc_cs0,
+                         struct omap_sdrc_params **sdrc_cs1);
+ 
++void omap2_sms_write_rot_control(u32 val, unsigned ctx);
++void omap2_sms_write_rot_size(u32 val, unsigned ctx);
++void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx);
++
+ #ifdef CONFIG_ARCH_OMAP2
+ 
+ struct memory_timings {
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-2.6.31/dss2/0002-OMAP-OMAPFB-split-omapfb.h.patch b/recipes/linux/linux-omap-2.6.31/dss2/0002-OMAP-OMAPFB-split-omapfb.h.patch
new file mode 100644 (file)
index 0000000..405ea72
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.31/dss2/0002-OMAP-OMAPFB-split-omapfb.h.patch
@@ -0,0 +1,1151 @@
+From c87b390673167a65a52c0e8da22e2842862227f1 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Mon, 3 Aug 2009 15:06:36 +0300
+Subject: [PATCH 02/18] OMAP: OMAPFB: split omapfb.h
+
+Split arch/arm/plat-omap/include/mach/omapfb.h into two files:
+
+include/linux/omapfb.h - ioctls etc for userspace and some kernel
+                         stuff for board files
+drivers/video/omap/omapfb.h - for omapfb internal use
+
+This cleans up omapfb.h and also makes it easier for the upcoming new
+DSS driver to co-exist with the old driver.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Acked-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap1/board-nokia770.c     |    2 +-
+ arch/arm/mach-omap2/io.c                 |    2 +-
+ arch/arm/plat-omap/fb.c                  |    2 +-
+ arch/arm/plat-omap/include/mach/omapfb.h |  398 ------------------------------
+ drivers/video/omap/blizzard.c            |    2 +-
+ drivers/video/omap/dispc.c               |    2 +-
+ drivers/video/omap/hwa742.c              |    2 +-
+ drivers/video/omap/lcd_h3.c              |    2 +-
+ drivers/video/omap/lcd_h4.c              |    2 +-
+ drivers/video/omap/lcd_inn1510.c         |    2 +-
+ drivers/video/omap/lcd_inn1610.c         |    2 +-
+ drivers/video/omap/lcd_osk.c             |    2 +-
+ drivers/video/omap/lcd_palmte.c          |    2 +-
+ drivers/video/omap/lcd_palmtt.c          |    2 +-
+ drivers/video/omap/lcd_palmz71.c         |    2 +-
+ drivers/video/omap/lcdc.c                |    3 +-
+ drivers/video/omap/omapfb.h              |  227 +++++++++++++++++
+ drivers/video/omap/omapfb_main.c         |    2 +-
+ drivers/video/omap/rfbi.c                |    3 +-
+ drivers/video/omap/sossi.c               |    2 +-
+ include/linux/omapfb.h                   |  197 +++++++++++++++
+ 21 files changed, 443 insertions(+), 417 deletions(-)
+ delete mode 100644 arch/arm/plat-omap/include/mach/omapfb.h
+ create mode 100644 drivers/video/omap/omapfb.h
+ create mode 100644 include/linux/omapfb.h
+
+diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
+index ed2a48a..6fbde33 100644
+--- a/arch/arm/mach-omap1/board-nokia770.c
++++ b/arch/arm/mach-omap1/board-nokia770.c
+@@ -14,6 +14,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/input.h>
+ #include <linux/clk.h>
++#include <linux/omapfb.h>
+ 
+ #include <linux/spi/spi.h>
+ #include <linux/spi/ads7846.h>
+@@ -32,7 +33,6 @@
+ #include <mach/keypad.h>
+ #include <mach/common.h>
+ #include <mach/dsp_common.h>
+-#include <mach/omapfb.h>
+ #include <mach/hwa742.h>
+ #include <mach/lcd_mipid.h>
+ #include <mach/mmc.h>
+diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
+index e9b9bcb..49199a3 100644
+--- a/arch/arm/mach-omap2/io.c
++++ b/arch/arm/mach-omap2/io.c
+@@ -22,13 +22,13 @@
+ #include <linux/init.h>
+ #include <linux/io.h>
+ #include <linux/clk.h>
++#include <linux/omapfb.h>
+ 
+ #include <asm/tlb.h>
+ 
+ #include <asm/mach/map.h>
+ 
+ #include <mach/mux.h>
+-#include <mach/omapfb.h>
+ #include <mach/sram.h>
+ #include <mach/sdrc.h>
+ #include <mach/gpmc.h>
+diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
+index 3746222..40615a6 100644
+--- a/arch/arm/plat-omap/fb.c
++++ b/arch/arm/plat-omap/fb.c
+@@ -28,13 +28,13 @@
+ #include <linux/platform_device.h>
+ #include <linux/bootmem.h>
+ #include <linux/io.h>
++#include <linux/omapfb.h>
+ 
+ #include <mach/hardware.h>
+ #include <asm/mach/map.h>
+ 
+ #include <mach/board.h>
+ #include <mach/sram.h>
+-#include <mach/omapfb.h>
+ 
+ #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
+ 
+diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/mach/omapfb.h
+deleted file mode 100644
+index 7b74d12..0000000
+--- a/arch/arm/plat-omap/include/mach/omapfb.h
++++ /dev/null
+@@ -1,398 +0,0 @@
+-/*
+- * File: arch/arm/plat-omap/include/mach/omapfb.h
+- *
+- * Framebuffer driver for TI OMAP boards
+- *
+- * Copyright (C) 2004 Nokia Corporation
+- * Author: Imre Deak <imre.deak@nokia.com>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful, but
+- * WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+- * General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License along
+- * with this program; if not, write to the Free Software Foundation, Inc.,
+- * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+- */
+-
+-#ifndef __OMAPFB_H
+-#define __OMAPFB_H
+-
+-#include <asm/ioctl.h>
+-#include <asm/types.h>
+-
+-/* IOCTL commands. */
+-
+-#define OMAP_IOW(num, dtype)  _IOW('O', num, dtype)
+-#define OMAP_IOR(num, dtype)  _IOR('O', num, dtype)
+-#define OMAP_IOWR(num, dtype) _IOWR('O', num, dtype)
+-#define OMAP_IO(num)          _IO('O', num)
+-
+-#define OMAPFB_MIRROR         OMAP_IOW(31, int)
+-#define OMAPFB_SYNC_GFX               OMAP_IO(37)
+-#define OMAPFB_VSYNC          OMAP_IO(38)
+-#define OMAPFB_SET_UPDATE_MODE        OMAP_IOW(40, int)
+-#define OMAPFB_GET_CAPS               OMAP_IOR(42, struct omapfb_caps)
+-#define OMAPFB_GET_UPDATE_MODE        OMAP_IOW(43, int)
+-#define OMAPFB_LCD_TEST               OMAP_IOW(45, int)
+-#define OMAPFB_CTRL_TEST      OMAP_IOW(46, int)
+-#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old)
+-#define OMAPFB_SET_COLOR_KEY  OMAP_IOW(50, struct omapfb_color_key)
+-#define OMAPFB_GET_COLOR_KEY  OMAP_IOW(51, struct omapfb_color_key)
+-#define OMAPFB_SETUP_PLANE    OMAP_IOW(52, struct omapfb_plane_info)
+-#define OMAPFB_QUERY_PLANE    OMAP_IOW(53, struct omapfb_plane_info)
+-#define OMAPFB_UPDATE_WINDOW  OMAP_IOW(54, struct omapfb_update_window)
+-#define OMAPFB_SETUP_MEM      OMAP_IOW(55, struct omapfb_mem_info)
+-#define OMAPFB_QUERY_MEM      OMAP_IOW(56, struct omapfb_mem_info)
+-
+-#define OMAPFB_CAPS_GENERIC_MASK      0x00000fff
+-#define OMAPFB_CAPS_LCDC_MASK         0x00fff000
+-#define OMAPFB_CAPS_PANEL_MASK                0xff000000
+-
+-#define OMAPFB_CAPS_MANUAL_UPDATE     0x00001000
+-#define OMAPFB_CAPS_TEARSYNC          0x00002000
+-#define OMAPFB_CAPS_PLANE_RELOCATE_MEM        0x00004000
+-#define OMAPFB_CAPS_PLANE_SCALE               0x00008000
+-#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE       0x00010000
+-#define OMAPFB_CAPS_WINDOW_SCALE      0x00020000
+-#define OMAPFB_CAPS_WINDOW_OVERLAY    0x00040000
+-#define OMAPFB_CAPS_WINDOW_ROTATE     0x00080000
+-#define OMAPFB_CAPS_SET_BACKLIGHT     0x01000000
+-
+-/* Values from DSP must map to lower 16-bits */
+-#define OMAPFB_FORMAT_MASK            0x00ff
+-#define OMAPFB_FORMAT_FLAG_DOUBLE     0x0100
+-#define OMAPFB_FORMAT_FLAG_TEARSYNC   0x0200
+-#define OMAPFB_FORMAT_FLAG_FORCE_VSYNC        0x0400
+-#define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY     0x0800
+-#define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY    0x1000
+-
+-#define OMAPFB_EVENT_READY    1
+-#define OMAPFB_EVENT_DISABLED 2
+-
+-#define OMAPFB_MEMTYPE_SDRAM          0
+-#define OMAPFB_MEMTYPE_SRAM           1
+-#define OMAPFB_MEMTYPE_MAX            1
+-
+-enum omapfb_color_format {
+-      OMAPFB_COLOR_RGB565 = 0,
+-      OMAPFB_COLOR_YUV422,
+-      OMAPFB_COLOR_YUV420,
+-      OMAPFB_COLOR_CLUT_8BPP,
+-      OMAPFB_COLOR_CLUT_4BPP,
+-      OMAPFB_COLOR_CLUT_2BPP,
+-      OMAPFB_COLOR_CLUT_1BPP,
+-      OMAPFB_COLOR_RGB444,
+-      OMAPFB_COLOR_YUY422,
+-};
+-
+-struct omapfb_update_window {
+-      __u32 x, y;
+-      __u32 width, height;
+-      __u32 format;
+-      __u32 out_x, out_y;
+-      __u32 out_width, out_height;
+-      __u32 reserved[8];
+-};
+-
+-struct omapfb_update_window_old {
+-      __u32 x, y;
+-      __u32 width, height;
+-      __u32 format;
+-};
+-
+-enum omapfb_plane {
+-      OMAPFB_PLANE_GFX = 0,
+-      OMAPFB_PLANE_VID1,
+-      OMAPFB_PLANE_VID2,
+-};
+-
+-enum omapfb_channel_out {
+-      OMAPFB_CHANNEL_OUT_LCD = 0,
+-      OMAPFB_CHANNEL_OUT_DIGIT,
+-};
+-
+-struct omapfb_plane_info {
+-      __u32 pos_x;
+-      __u32 pos_y;
+-      __u8  enabled;
+-      __u8  channel_out;
+-      __u8  mirror;
+-      __u8  reserved1;
+-      __u32 out_width;
+-      __u32 out_height;
+-      __u32 reserved2[12];
+-};
+-
+-struct omapfb_mem_info {
+-      __u32 size;
+-      __u8  type;
+-      __u8  reserved[3];
+-};
+-
+-struct omapfb_caps {
+-      __u32 ctrl;
+-      __u32 plane_color;
+-      __u32 wnd_color;
+-};
+-
+-enum omapfb_color_key_type {
+-      OMAPFB_COLOR_KEY_DISABLED = 0,
+-      OMAPFB_COLOR_KEY_GFX_DST,
+-      OMAPFB_COLOR_KEY_VID_SRC,
+-};
+-
+-struct omapfb_color_key {
+-      __u8  channel_out;
+-      __u32 background;
+-      __u32 trans_key;
+-      __u8  key_type;
+-};
+-
+-enum omapfb_update_mode {
+-      OMAPFB_UPDATE_DISABLED = 0,
+-      OMAPFB_AUTO_UPDATE,
+-      OMAPFB_MANUAL_UPDATE
+-};
+-
+-#ifdef __KERNEL__
+-
+-#include <linux/completion.h>
+-#include <linux/interrupt.h>
+-#include <linux/fb.h>
+-#include <linux/mutex.h>
+-
+-#include <mach/board.h>
+-
+-#define OMAP_LCDC_INV_VSYNC             0x0001
+-#define OMAP_LCDC_INV_HSYNC             0x0002
+-#define OMAP_LCDC_INV_PIX_CLOCK         0x0004
+-#define OMAP_LCDC_INV_OUTPUT_EN         0x0008
+-#define OMAP_LCDC_HSVS_RISING_EDGE      0x0010
+-#define OMAP_LCDC_HSVS_OPPOSITE         0x0020
+-
+-#define OMAP_LCDC_SIGNAL_MASK         0x003f
+-
+-#define OMAP_LCDC_PANEL_TFT           0x0100
+-
+-#define OMAPFB_PLANE_XRES_MIN         8
+-#define OMAPFB_PLANE_YRES_MIN         8
+-
+-#ifdef CONFIG_ARCH_OMAP1
+-#define OMAPFB_PLANE_NUM              1
+-#else
+-#define OMAPFB_PLANE_NUM              3
+-#endif
+-
+-struct omapfb_device;
+-
+-struct lcd_panel {
+-      const char      *name;
+-      int             config;         /* TFT/STN, signal inversion */
+-      int             bpp;            /* Pixel format in fb mem */
+-      int             data_lines;     /* Lines on LCD HW interface */
+-
+-      int             x_res, y_res;
+-      int             pixel_clock;    /* In kHz */
+-      int             hsw;            /* Horizontal synchronization
+-                                         pulse width */
+-      int             hfp;            /* Horizontal front porch */
+-      int             hbp;            /* Horizontal back porch */
+-      int             vsw;            /* Vertical synchronization
+-                                         pulse width */
+-      int             vfp;            /* Vertical front porch */
+-      int             vbp;            /* Vertical back porch */
+-      int             acb;            /* ac-bias pin frequency */
+-      int             pcd;            /* pixel clock divider.
+-                                         Obsolete use pixel_clock instead */
+-
+-      int             (*init)         (struct lcd_panel *panel,
+-                                       struct omapfb_device *fbdev);
+-      void            (*cleanup)      (struct lcd_panel *panel);
+-      int             (*enable)       (struct lcd_panel *panel);
+-      void            (*disable)      (struct lcd_panel *panel);
+-      unsigned long   (*get_caps)     (struct lcd_panel *panel);
+-      int             (*set_bklight_level)(struct lcd_panel *panel,
+-                                           unsigned int level);
+-      unsigned int    (*get_bklight_level)(struct lcd_panel *panel);
+-      unsigned int    (*get_bklight_max)  (struct lcd_panel *panel);
+-      int             (*run_test)     (struct lcd_panel *panel, int test_num);
+-};
+-
+-struct extif_timings {
+-      int cs_on_time;
+-      int cs_off_time;
+-      int we_on_time;
+-      int we_off_time;
+-      int re_on_time;
+-      int re_off_time;
+-      int we_cycle_time;
+-      int re_cycle_time;
+-      int cs_pulse_width;
+-      int access_time;
+-
+-      int clk_div;
+-
+-      u32 tim[5];             /* set by extif->convert_timings */
+-
+-      int converted;
+-};
+-
+-struct lcd_ctrl_extif {
+-      int  (*init)            (struct omapfb_device *fbdev);
+-      void (*cleanup)         (void);
+-      void (*get_clk_info)    (u32 *clk_period, u32 *max_clk_div);
+-      unsigned long (*get_max_tx_rate)(void);
+-      int  (*convert_timings) (struct extif_timings *timings);
+-      void (*set_timings)     (const struct extif_timings *timings);
+-      void (*set_bits_per_cycle)(int bpc);
+-      void (*write_command)   (const void *buf, unsigned int len);
+-      void (*read_data)       (void *buf, unsigned int len);
+-      void (*write_data)      (const void *buf, unsigned int len);
+-      void (*transfer_area)   (int width, int height,
+-                               void (callback)(void * data), void *data);
+-      int  (*setup_tearsync)  (unsigned pin_cnt,
+-                               unsigned hs_pulse_time, unsigned vs_pulse_time,
+-                               int hs_pol_inv, int vs_pol_inv, int div);
+-      int  (*enable_tearsync) (int enable, unsigned line);
+-
+-      unsigned long           max_transmit_size;
+-};
+-
+-struct omapfb_notifier_block {
+-      struct notifier_block   nb;
+-      void                    *data;
+-      int                     plane_idx;
+-};
+-
+-typedef int (*omapfb_notifier_callback_t)(struct notifier_block *,
+-                                        unsigned long event,
+-                                        void *fbi);
+-
+-struct omapfb_mem_region {
+-      dma_addr_t      paddr;
+-      void            *vaddr;
+-      unsigned long   size;
+-      u8              type;           /* OMAPFB_PLANE_MEM_* */
+-      unsigned        alloc:1;        /* allocated by the driver */
+-      unsigned        map:1;          /* kernel mapped by the driver */
+-};
+-
+-struct omapfb_mem_desc {
+-      int                             region_cnt;
+-      struct omapfb_mem_region        region[OMAPFB_PLANE_NUM];
+-};
+-
+-struct lcd_ctrl {
+-      const char      *name;
+-      void            *data;
+-
+-      int             (*init)           (struct omapfb_device *fbdev,
+-                                         int ext_mode,
+-                                         struct omapfb_mem_desc *req_md);
+-      void            (*cleanup)        (void);
+-      void            (*bind_client)    (struct omapfb_notifier_block *nb);
+-      void            (*get_caps)       (int plane, struct omapfb_caps *caps);
+-      int             (*set_update_mode)(enum omapfb_update_mode mode);
+-      enum omapfb_update_mode (*get_update_mode)(void);
+-      int             (*setup_plane)    (int plane, int channel_out,
+-                                         unsigned long offset,
+-                                         int screen_width,
+-                                         int pos_x, int pos_y, int width,
+-                                         int height, int color_mode);
+-      int             (*set_rotate)     (int angle);
+-      int             (*setup_mem)      (int plane, size_t size,
+-                                         int mem_type, unsigned long *paddr);
+-      int             (*mmap)           (struct fb_info *info,
+-                                         struct vm_area_struct *vma);
+-      int             (*set_scale)      (int plane,
+-                                         int orig_width, int orig_height,
+-                                         int out_width, int out_height);
+-      int             (*enable_plane)   (int plane, int enable);
+-      int             (*update_window)  (struct fb_info *fbi,
+-                                         struct omapfb_update_window *win,
+-                                         void (*callback)(void *),
+-                                         void *callback_data);
+-      void            (*sync)           (void);
+-      void            (*suspend)        (void);
+-      void            (*resume)         (void);
+-      int             (*run_test)       (int test_num);
+-      int             (*setcolreg)      (u_int regno, u16 red, u16 green,
+-                                         u16 blue, u16 transp,
+-                                         int update_hw_mem);
+-      int             (*set_color_key)  (struct omapfb_color_key *ck);
+-      int             (*get_color_key)  (struct omapfb_color_key *ck);
+-};
+-
+-enum omapfb_state {
+-      OMAPFB_DISABLED = 0,
+-      OMAPFB_SUSPENDED= 99,
+-      OMAPFB_ACTIVE   = 100
+-};
+-
+-struct omapfb_plane_struct {
+-      int                             idx;
+-      struct omapfb_plane_info        info;
+-      enum omapfb_color_format        color_mode;
+-      struct omapfb_device            *fbdev;
+-};
+-
+-struct omapfb_device {
+-      int                     state;
+-      int                     ext_lcdc;               /* Using external
+-                                                           LCD controller */
+-      struct mutex            rqueue_mutex;
+-
+-      int                     palette_size;
+-      u32                     pseudo_palette[17];
+-
+-      struct lcd_panel        *panel;                 /* LCD panel */
+-      const struct lcd_ctrl   *ctrl;                  /* LCD controller */
+-      const struct lcd_ctrl   *int_ctrl;              /* internal LCD ctrl */
+-      struct lcd_ctrl_extif   *ext_if;                /* LCD ctrl external
+-                                                         interface */
+-      struct device           *dev;
+-      struct fb_var_screeninfo        new_var;        /* for mode changes */
+-
+-      struct omapfb_mem_desc          mem_desc;
+-      struct fb_info                  *fb_info[OMAPFB_PLANE_NUM];
+-};
+-
+-struct omapfb_platform_data {
+-      struct omap_lcd_config          lcd;
+-      struct omapfb_mem_desc          mem_desc;
+-      void                            *ctrl_platform_data;
+-};
+-
+-#ifdef CONFIG_ARCH_OMAP1
+-extern struct lcd_ctrl omap1_lcd_ctrl;
+-#else
+-extern struct lcd_ctrl omap2_disp_ctrl;
+-#endif
+-
+-extern void omapfb_reserve_sdram(void);
+-extern void omapfb_register_panel(struct lcd_panel *panel);
+-extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
+-extern void omapfb_notify_clients(struct omapfb_device *fbdev,
+-                                unsigned long event);
+-extern int  omapfb_register_client(struct omapfb_notifier_block *nb,
+-                                 omapfb_notifier_callback_t callback,
+-                                 void *callback_data);
+-extern int  omapfb_unregister_client(struct omapfb_notifier_block *nb);
+-extern int  omapfb_update_window_async(struct fb_info *fbi,
+-                                     struct omapfb_update_window *win,
+-                                     void (*callback)(void *),
+-                                     void *callback_data);
+-
+-/* in arch/arm/plat-omap/fb.c */
+-extern void omapfb_set_ctrl_platform_data(void *pdata);
+-
+-#endif /* __KERNEL__ */
+-
+-#endif /* __OMAPFB_H */
+diff --git a/drivers/video/omap/blizzard.c b/drivers/video/omap/blizzard.c
+index 9dfcf39..38de019 100644
+--- a/drivers/video/omap/blizzard.c
++++ b/drivers/video/omap/blizzard.c
+@@ -27,9 +27,9 @@
+ #include <linux/clk.h>
+ 
+ #include <mach/dma.h>
+-#include <mach/omapfb.h>
+ #include <mach/blizzard.h>
+ 
++#include "omapfb.h"
+ #include "dispc.h"
+ 
+ #define MODULE_NAME                           "blizzard"
+diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
+index 148cbcc..f021770 100644
+--- a/drivers/video/omap/dispc.c
++++ b/drivers/video/omap/dispc.c
+@@ -26,9 +26,9 @@
+ #include <linux/io.h>
+ 
+ #include <mach/sram.h>
+-#include <mach/omapfb.h>
+ #include <mach/board.h>
+ 
++#include "omapfb.h"
+ #include "dispc.h"
+ 
+ #define MODULE_NAME                   "dispc"
+diff --git a/drivers/video/omap/hwa742.c b/drivers/video/omap/hwa742.c
+index 5d4f348..f5c5bfb 100644
+--- a/drivers/video/omap/hwa742.c
++++ b/drivers/video/omap/hwa742.c
+@@ -27,8 +27,8 @@
+ #include <linux/clk.h>
+ 
+ #include <mach/dma.h>
+-#include <mach/omapfb.h>
+ #include <mach/hwa742.h>
++#include "omapfb.h"
+ 
+ #define HWA742_REV_CODE_REG       0x0
+ #define HWA742_CONFIG_REG         0x2
+diff --git a/drivers/video/omap/lcd_h3.c b/drivers/video/omap/lcd_h3.c
+index 2486237..fb4cc4b 100644
+--- a/drivers/video/omap/lcd_h3.c
++++ b/drivers/video/omap/lcd_h3.c
+@@ -24,7 +24,7 @@
+ #include <linux/i2c/tps65010.h>
+ 
+ #include <mach/gpio.h>
+-#include <mach/omapfb.h>
++#include "omapfb.h"
+ 
+ #define MODULE_NAME   "omapfb-lcd_h3"
+ 
+diff --git a/drivers/video/omap/lcd_h4.c b/drivers/video/omap/lcd_h4.c
+index 6ff5643..d7e9b36 100644
+--- a/drivers/video/omap/lcd_h4.c
++++ b/drivers/video/omap/lcd_h4.c
+@@ -22,7 +22,7 @@
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+ 
+-#include <mach/omapfb.h>
++#include "omapfb.h"
+ 
+ static int h4_panel_init(struct lcd_panel *panel, struct omapfb_device *fbdev)
+ {
+diff --git a/drivers/video/omap/lcd_inn1510.c b/drivers/video/omap/lcd_inn1510.c
+index 6953ed4..bc34607 100644
+--- a/drivers/video/omap/lcd_inn1510.c
++++ b/drivers/video/omap/lcd_inn1510.c
+@@ -24,7 +24,7 @@
+ #include <linux/io.h>
+ 
+ #include <mach/fpga.h>
+-#include <mach/omapfb.h>
++#include "omapfb.h"
+ 
+ static int innovator1510_panel_init(struct lcd_panel *panel,
+                                   struct omapfb_device *fbdev)
+diff --git a/drivers/video/omap/lcd_inn1610.c b/drivers/video/omap/lcd_inn1610.c
+index 4c4f7ee..3e0abda 100644
+--- a/drivers/video/omap/lcd_inn1610.c
++++ b/drivers/video/omap/lcd_inn1610.c
+@@ -23,7 +23,7 @@
+ #include <linux/platform_device.h>
+ 
+ #include <mach/gpio.h>
+-#include <mach/omapfb.h>
++#include "omapfb.h"
+ 
+ #define MODULE_NAME   "omapfb-lcd_h3"
+ 
+diff --git a/drivers/video/omap/lcd_osk.c b/drivers/video/omap/lcd_osk.c
+index 379c96d..68b8668 100644
+--- a/drivers/video/omap/lcd_osk.c
++++ b/drivers/video/omap/lcd_osk.c
+@@ -25,7 +25,7 @@
+ 
+ #include <mach/gpio.h>
+ #include <mach/mux.h>
+-#include <mach/omapfb.h>
++#include "omapfb.h"
+ 
+ static int osk_panel_init(struct lcd_panel *panel, struct omapfb_device *fbdev)
+ {
+diff --git a/drivers/video/omap/lcd_palmte.c b/drivers/video/omap/lcd_palmte.c
+index 2183173..f993457 100644
+--- a/drivers/video/omap/lcd_palmte.c
++++ b/drivers/video/omap/lcd_palmte.c
+@@ -24,7 +24,7 @@
+ #include <linux/io.h>
+ 
+ #include <mach/fpga.h>
+-#include <mach/omapfb.h>
++#include "omapfb.h"
+ 
+ static int palmte_panel_init(struct lcd_panel *panel,
+                               struct omapfb_device *fbdev)
+diff --git a/drivers/video/omap/lcd_palmtt.c b/drivers/video/omap/lcd_palmtt.c
+index 57b0f6c..d4cf822 100644
+--- a/drivers/video/omap/lcd_palmtt.c
++++ b/drivers/video/omap/lcd_palmtt.c
+@@ -30,7 +30,7 @@ GPIO13 - screen blanking
+ #include <linux/io.h>
+ 
+ #include <mach/gpio.h>
+-#include <mach/omapfb.h>
++#include "omapfb.h"
+ 
+ static int palmtt_panel_init(struct lcd_panel *panel,
+       struct omapfb_device *fbdev)
+diff --git a/drivers/video/omap/lcd_palmz71.c b/drivers/video/omap/lcd_palmz71.c
+index d33d78b..1382891 100644
+--- a/drivers/video/omap/lcd_palmz71.c
++++ b/drivers/video/omap/lcd_palmz71.c
+@@ -24,7 +24,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/io.h>
+ 
+-#include <mach/omapfb.h>
++#include "omapfb.h"
+ 
+ static int palmz71_panel_init(struct lcd_panel *panel,
+                             struct omapfb_device *fbdev)
+diff --git a/drivers/video/omap/lcdc.c b/drivers/video/omap/lcdc.c
+index ab39492..520ed97 100644
+--- a/drivers/video/omap/lcdc.c
++++ b/drivers/video/omap/lcdc.c
+@@ -30,10 +30,11 @@
+ #include <linux/clk.h>
+ 
+ #include <mach/dma.h>
+-#include <mach/omapfb.h>
+ 
+ #include <asm/mach-types.h>
+ 
++#include "omapfb.h"
++
+ #include "lcdc.h"
+ 
+ #define MODULE_NAME                   "lcdc"
+diff --git a/drivers/video/omap/omapfb.h b/drivers/video/omap/omapfb.h
+new file mode 100644
+index 0000000..46e4714
+--- /dev/null
++++ b/drivers/video/omap/omapfb.h
+@@ -0,0 +1,227 @@
++/*
++ * File: drivers/video/omap/omapfb.h
++ *
++ * Framebuffer driver for TI OMAP boards
++ *
++ * Copyright (C) 2004 Nokia Corporation
++ * Author: Imre Deak <imre.deak@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
++ */
++
++#ifndef __OMAPFB_H
++#define __OMAPFB_H
++
++#include <linux/fb.h>
++#include <linux/mutex.h>
++#include <linux/omapfb.h>
++
++#define OMAPFB_EVENT_READY    1
++#define OMAPFB_EVENT_DISABLED 2
++
++#define OMAP_LCDC_INV_VSYNC             0x0001
++#define OMAP_LCDC_INV_HSYNC             0x0002
++#define OMAP_LCDC_INV_PIX_CLOCK         0x0004
++#define OMAP_LCDC_INV_OUTPUT_EN         0x0008
++#define OMAP_LCDC_HSVS_RISING_EDGE      0x0010
++#define OMAP_LCDC_HSVS_OPPOSITE         0x0020
++
++#define OMAP_LCDC_SIGNAL_MASK         0x003f
++
++#define OMAP_LCDC_PANEL_TFT           0x0100
++
++#define OMAPFB_PLANE_XRES_MIN         8
++#define OMAPFB_PLANE_YRES_MIN         8
++
++struct omapfb_device;
++
++struct lcd_panel {
++      const char      *name;
++      int             config;         /* TFT/STN, signal inversion */
++      int             bpp;            /* Pixel format in fb mem */
++      int             data_lines;     /* Lines on LCD HW interface */
++
++      int             x_res, y_res;
++      int             pixel_clock;    /* In kHz */
++      int             hsw;            /* Horizontal synchronization
++                                         pulse width */
++      int             hfp;            /* Horizontal front porch */
++      int             hbp;            /* Horizontal back porch */
++      int             vsw;            /* Vertical synchronization
++                                         pulse width */
++      int             vfp;            /* Vertical front porch */
++      int             vbp;            /* Vertical back porch */
++      int             acb;            /* ac-bias pin frequency */
++      int             pcd;            /* pixel clock divider.
++                                         Obsolete use pixel_clock instead */
++
++      int             (*init)         (struct lcd_panel *panel,
++                                       struct omapfb_device *fbdev);
++      void            (*cleanup)      (struct lcd_panel *panel);
++      int             (*enable)       (struct lcd_panel *panel);
++      void            (*disable)      (struct lcd_panel *panel);
++      unsigned long   (*get_caps)     (struct lcd_panel *panel);
++      int             (*set_bklight_level)(struct lcd_panel *panel,
++                                           unsigned int level);
++      unsigned int    (*get_bklight_level)(struct lcd_panel *panel);
++      unsigned int    (*get_bklight_max)  (struct lcd_panel *panel);
++      int             (*run_test)     (struct lcd_panel *panel, int test_num);
++};
++
++struct extif_timings {
++      int cs_on_time;
++      int cs_off_time;
++      int we_on_time;
++      int we_off_time;
++      int re_on_time;
++      int re_off_time;
++      int we_cycle_time;
++      int re_cycle_time;
++      int cs_pulse_width;
++      int access_time;
++
++      int clk_div;
++
++      u32 tim[5];             /* set by extif->convert_timings */
++
++      int converted;
++};
++
++struct lcd_ctrl_extif {
++      int  (*init)            (struct omapfb_device *fbdev);
++      void (*cleanup)         (void);
++      void (*get_clk_info)    (u32 *clk_period, u32 *max_clk_div);
++      unsigned long (*get_max_tx_rate)(void);
++      int  (*convert_timings) (struct extif_timings *timings);
++      void (*set_timings)     (const struct extif_timings *timings);
++      void (*set_bits_per_cycle)(int bpc);
++      void (*write_command)   (const void *buf, unsigned int len);
++      void (*read_data)       (void *buf, unsigned int len);
++      void (*write_data)      (const void *buf, unsigned int len);
++      void (*transfer_area)   (int width, int height,
++                               void (callback)(void *data), void *data);
++      int  (*setup_tearsync)  (unsigned pin_cnt,
++                               unsigned hs_pulse_time, unsigned vs_pulse_time,
++                               int hs_pol_inv, int vs_pol_inv, int div);
++      int  (*enable_tearsync) (int enable, unsigned line);
++
++      unsigned long           max_transmit_size;
++};
++
++struct omapfb_notifier_block {
++      struct notifier_block   nb;
++      void                    *data;
++      int                     plane_idx;
++};
++
++typedef int (*omapfb_notifier_callback_t)(struct notifier_block *,
++                                        unsigned long event,
++                                        void *fbi);
++
++struct lcd_ctrl {
++      const char      *name;
++      void            *data;
++
++      int             (*init)           (struct omapfb_device *fbdev,
++                                         int ext_mode,
++                                         struct omapfb_mem_desc *req_md);
++      void            (*cleanup)        (void);
++      void            (*bind_client)    (struct omapfb_notifier_block *nb);
++      void            (*get_caps)       (int plane, struct omapfb_caps *caps);
++      int             (*set_update_mode)(enum omapfb_update_mode mode);
++      enum omapfb_update_mode (*get_update_mode)(void);
++      int             (*setup_plane)    (int plane, int channel_out,
++                                         unsigned long offset,
++                                         int screen_width,
++                                         int pos_x, int pos_y, int width,
++                                         int height, int color_mode);
++      int             (*set_rotate)     (int angle);
++      int             (*setup_mem)      (int plane, size_t size,
++                                         int mem_type, unsigned long *paddr);
++      int             (*mmap)           (struct fb_info *info,
++                                         struct vm_area_struct *vma);
++      int             (*set_scale)      (int plane,
++                                         int orig_width, int orig_height,
++                                         int out_width, int out_height);
++      int             (*enable_plane)   (int plane, int enable);
++      int             (*update_window)  (struct fb_info *fbi,
++                                         struct omapfb_update_window *win,
++                                         void (*callback)(void *),
++                                         void *callback_data);
++      void            (*sync)           (void);
++      void            (*suspend)        (void);
++      void            (*resume)         (void);
++      int             (*run_test)       (int test_num);
++      int             (*setcolreg)      (u_int regno, u16 red, u16 green,
++                                         u16 blue, u16 transp,
++                                         int update_hw_mem);
++      int             (*set_color_key)  (struct omapfb_color_key *ck);
++      int             (*get_color_key)  (struct omapfb_color_key *ck);
++};
++
++enum omapfb_state {
++      OMAPFB_DISABLED         = 0,
++      OMAPFB_SUSPENDED        = 99,
++      OMAPFB_ACTIVE           = 100
++};
++
++struct omapfb_plane_struct {
++      int                             idx;
++      struct omapfb_plane_info        info;
++      enum omapfb_color_format        color_mode;
++      struct omapfb_device            *fbdev;
++};
++
++struct omapfb_device {
++      int                     state;
++      int                     ext_lcdc;               /* Using external
++                                                         LCD controller */
++      struct mutex            rqueue_mutex;
++
++      int                     palette_size;
++      u32                     pseudo_palette[17];
++
++      struct lcd_panel        *panel;                 /* LCD panel */
++      const struct lcd_ctrl   *ctrl;                  /* LCD controller */
++      const struct lcd_ctrl   *int_ctrl;              /* internal LCD ctrl */
++      struct lcd_ctrl_extif   *ext_if;                /* LCD ctrl external
++                                                         interface */
++      struct device           *dev;
++      struct fb_var_screeninfo        new_var;        /* for mode changes */
++
++      struct omapfb_mem_desc          mem_desc;
++      struct fb_info                  *fb_info[OMAPFB_PLANE_NUM];
++};
++
++#ifdef CONFIG_ARCH_OMAP1
++extern struct lcd_ctrl omap1_lcd_ctrl;
++#else
++extern struct lcd_ctrl omap2_disp_ctrl;
++#endif
++
++extern void omapfb_register_panel(struct lcd_panel *panel);
++extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
++extern void omapfb_notify_clients(struct omapfb_device *fbdev,
++                                unsigned long event);
++extern int  omapfb_register_client(struct omapfb_notifier_block *nb,
++                                 omapfb_notifier_callback_t callback,
++                                 void *callback_data);
++extern int  omapfb_unregister_client(struct omapfb_notifier_block *nb);
++extern int  omapfb_update_window_async(struct fb_info *fbi,
++                                     struct omapfb_update_window *win,
++                                     void (*callback)(void *),
++                                     void *callback_data);
++
++#endif /* __OMAPFB_H */
+diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c
+index 8862233..a6c4abe 100644
+--- a/drivers/video/omap/omapfb_main.c
++++ b/drivers/video/omap/omapfb_main.c
+@@ -29,8 +29,8 @@
+ #include <linux/uaccess.h>
+ 
+ #include <mach/dma.h>
+-#include <mach/omapfb.h>
+ 
++#include "omapfb.h"
+ #include "lcdc.h"
+ #include "dispc.h"
+ 
+diff --git a/drivers/video/omap/rfbi.c b/drivers/video/omap/rfbi.c
+index 9332d6c..2e71446 100644
+--- a/drivers/video/omap/rfbi.c
++++ b/drivers/video/omap/rfbi.c
+@@ -27,8 +27,7 @@
+ #include <linux/clk.h>
+ #include <linux/io.h>
+ 
+-#include <mach/omapfb.h>
+-
++#include "omapfb.h"
+ #include "dispc.h"
+ 
+ /* To work around an RFBI transfer rate limitation */
+diff --git a/drivers/video/omap/sossi.c b/drivers/video/omap/sossi.c
+index a769462..6853627 100644
+--- a/drivers/video/omap/sossi.c
++++ b/drivers/video/omap/sossi.c
+@@ -25,8 +25,8 @@
+ #include <linux/io.h>
+ 
+ #include <mach/dma.h>
+-#include <mach/omapfb.h>
+ 
++#include "omapfb.h"
+ #include "lcdc.h"
+ 
+ #define MODULE_NAME           "omapfb-sossi"
+diff --git a/include/linux/omapfb.h b/include/linux/omapfb.h
+new file mode 100644
+index 0000000..a3611d3
+--- /dev/null
++++ b/include/linux/omapfb.h
+@@ -0,0 +1,197 @@
++/*
++ * File: include/linux/omapfb.h
++ *
++ * Framebuffer driver for TI OMAP boards
++ *
++ * Copyright (C) 2004 Nokia Corporation
++ * Author: Imre Deak <imre.deak@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
++ */
++
++#ifndef __LINUX_OMAPFB_H__
++#define __LINUX_OMAPFB_H__
++
++#include <linux/ioctl.h>
++#include <linux/types.h>
++
++/* IOCTL commands. */
++
++#define OMAP_IOW(num, dtype)  _IOW('O', num, dtype)
++#define OMAP_IOR(num, dtype)  _IOR('O', num, dtype)
++#define OMAP_IOWR(num, dtype) _IOWR('O', num, dtype)
++#define OMAP_IO(num)          _IO('O', num)
++
++#define OMAPFB_MIRROR         OMAP_IOW(31, int)
++#define OMAPFB_SYNC_GFX               OMAP_IO(37)
++#define OMAPFB_VSYNC          OMAP_IO(38)
++#define OMAPFB_SET_UPDATE_MODE        OMAP_IOW(40, int)
++#define OMAPFB_GET_CAPS               OMAP_IOR(42, struct omapfb_caps)
++#define OMAPFB_GET_UPDATE_MODE        OMAP_IOW(43, int)
++#define OMAPFB_LCD_TEST               OMAP_IOW(45, int)
++#define OMAPFB_CTRL_TEST      OMAP_IOW(46, int)
++#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old)
++#define OMAPFB_SET_COLOR_KEY  OMAP_IOW(50, struct omapfb_color_key)
++#define OMAPFB_GET_COLOR_KEY  OMAP_IOW(51, struct omapfb_color_key)
++#define OMAPFB_SETUP_PLANE    OMAP_IOW(52, struct omapfb_plane_info)
++#define OMAPFB_QUERY_PLANE    OMAP_IOW(53, struct omapfb_plane_info)
++#define OMAPFB_UPDATE_WINDOW  OMAP_IOW(54, struct omapfb_update_window)
++#define OMAPFB_SETUP_MEM      OMAP_IOW(55, struct omapfb_mem_info)
++#define OMAPFB_QUERY_MEM      OMAP_IOW(56, struct omapfb_mem_info)
++
++#define OMAPFB_CAPS_GENERIC_MASK      0x00000fff
++#define OMAPFB_CAPS_LCDC_MASK         0x00fff000
++#define OMAPFB_CAPS_PANEL_MASK                0xff000000
++
++#define OMAPFB_CAPS_MANUAL_UPDATE     0x00001000
++#define OMAPFB_CAPS_TEARSYNC          0x00002000
++#define OMAPFB_CAPS_PLANE_RELOCATE_MEM        0x00004000
++#define OMAPFB_CAPS_PLANE_SCALE               0x00008000
++#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE       0x00010000
++#define OMAPFB_CAPS_WINDOW_SCALE      0x00020000
++#define OMAPFB_CAPS_WINDOW_OVERLAY    0x00040000
++#define OMAPFB_CAPS_WINDOW_ROTATE     0x00080000
++#define OMAPFB_CAPS_SET_BACKLIGHT     0x01000000
++
++/* Values from DSP must map to lower 16-bits */
++#define OMAPFB_FORMAT_MASK            0x00ff
++#define OMAPFB_FORMAT_FLAG_DOUBLE     0x0100
++#define OMAPFB_FORMAT_FLAG_TEARSYNC   0x0200
++#define OMAPFB_FORMAT_FLAG_FORCE_VSYNC        0x0400
++#define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY     0x0800
++#define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY    0x1000
++
++#define OMAPFB_MEMTYPE_SDRAM          0
++#define OMAPFB_MEMTYPE_SRAM           1
++#define OMAPFB_MEMTYPE_MAX            1
++
++enum omapfb_color_format {
++      OMAPFB_COLOR_RGB565 = 0,
++      OMAPFB_COLOR_YUV422,
++      OMAPFB_COLOR_YUV420,
++      OMAPFB_COLOR_CLUT_8BPP,
++      OMAPFB_COLOR_CLUT_4BPP,
++      OMAPFB_COLOR_CLUT_2BPP,
++      OMAPFB_COLOR_CLUT_1BPP,
++      OMAPFB_COLOR_RGB444,
++      OMAPFB_COLOR_YUY422,
++};
++
++struct omapfb_update_window {
++      __u32 x, y;
++      __u32 width, height;
++      __u32 format;
++      __u32 out_x, out_y;
++      __u32 out_width, out_height;
++      __u32 reserved[8];
++};
++
++struct omapfb_update_window_old {
++      __u32 x, y;
++      __u32 width, height;
++      __u32 format;
++};
++
++enum omapfb_plane {
++      OMAPFB_PLANE_GFX = 0,
++      OMAPFB_PLANE_VID1,
++      OMAPFB_PLANE_VID2,
++};
++
++enum omapfb_channel_out {
++      OMAPFB_CHANNEL_OUT_LCD = 0,
++      OMAPFB_CHANNEL_OUT_DIGIT,
++};
++
++struct omapfb_plane_info {
++      __u32 pos_x;
++      __u32 pos_y;
++      __u8  enabled;
++      __u8  channel_out;
++      __u8  mirror;
++      __u8  reserved1;
++      __u32 out_width;
++      __u32 out_height;
++      __u32 reserved2[12];
++};
++
++struct omapfb_mem_info {
++      __u32 size;
++      __u8  type;
++      __u8  reserved[3];
++};
++
++struct omapfb_caps {
++      __u32 ctrl;
++      __u32 plane_color;
++      __u32 wnd_color;
++};
++
++enum omapfb_color_key_type {
++      OMAPFB_COLOR_KEY_DISABLED = 0,
++      OMAPFB_COLOR_KEY_GFX_DST,
++      OMAPFB_COLOR_KEY_VID_SRC,
++};
++
++struct omapfb_color_key {
++      __u8  channel_out;
++      __u32 background;
++      __u32 trans_key;
++      __u8  key_type;
++};
++
++enum omapfb_update_mode {
++      OMAPFB_UPDATE_DISABLED = 0,
++      OMAPFB_AUTO_UPDATE,
++      OMAPFB_MANUAL_UPDATE
++};
++
++#ifdef __KERNEL__
++
++#include <mach/board.h>
++
++#ifdef CONFIG_ARCH_OMAP1
++#define OMAPFB_PLANE_NUM              1
++#else
++#define OMAPFB_PLANE_NUM              3
++#endif
++
++struct omapfb_mem_region {
++      u32             paddr;
++      void __iomem    *vaddr;
++      unsigned long   size;
++      u8              type;           /* OMAPFB_PLANE_MEM_* */
++      unsigned        alloc:1;        /* allocated by the driver */
++      unsigned        map:1;          /* kernel mapped by the driver */
++};
++
++struct omapfb_mem_desc {
++      int                             region_cnt;
++      struct omapfb_mem_region        region[OMAPFB_PLANE_NUM];
++};
++
++struct omapfb_platform_data {
++      struct omap_lcd_config          lcd;
++      struct omapfb_mem_desc          mem_desc;
++      void                            *ctrl_platform_data;
++};
++
++/* in arch/arm/plat-omap/fb.c */
++extern void omapfb_set_ctrl_platform_data(void *pdata);
++extern void omapfb_reserve_sdram(void);
++
++#endif
++
++#endif /* __OMAPFB_H */
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-2.6.31/dss2/0003-OMAP-OMAPFB-add-omapdss-device.patch b/recipes/linux/linux-omap-2.6.31/dss2/0003-OMAP-OMAPFB-add-omapdss-device.patch
new file mode 100644 (file)
index 0000000..fb9928c
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.31/dss2/0003-OMAP-OMAPFB-add-omapdss-device.patch
@@ -0,0 +1,136 @@
+From 40b33143283fda49f0be9113b952c1d77e1c709a Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Thu, 18 Jun 2009 13:02:39 +0300
+Subject: [PATCH 03/18] OMAP: OMAPFB: add omapdss device
+
+The upcoming new display subsystem driver is divided to two devices,
+omapdss and omapfb, of which omapdss handles the actual hardware.
+
+This patch adds a dummy omapdss platform device for the current omapfb
+driver, which is then used to get the clocks. This will make it possible
+for the current and the new display drivers to co-exist.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Acked-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/clock24xx.c |    8 ++++----
+ arch/arm/mach-omap2/clock34xx.c |   14 +++++++-------
+ drivers/video/omap/dispc.c      |   19 ++++++++++++++++---
+ 3 files changed, 27 insertions(+), 14 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
+index bc5d3ac..8cb8368 100644
+--- a/arch/arm/mach-omap2/clock24xx.c
++++ b/arch/arm/mach-omap2/clock24xx.c
+@@ -116,10 +116,10 @@ static struct omap_clk omap24xx_clks[] = {
+       CLK(NULL,       "mdm_ick",      &mdm_ick,       CK_243X),
+       CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
+       /* DSS domain clocks */
+-      CLK("omapfb",   "ick",          &dss_ick,       CK_243X | CK_242X),
+-      CLK("omapfb",   "dss1_fck",     &dss1_fck,      CK_243X | CK_242X),
+-      CLK("omapfb",   "dss2_fck",     &dss2_fck,      CK_243X | CK_242X),
+-      CLK("omapfb",   "tv_fck",       &dss_54m_fck,   CK_243X | CK_242X),
++      CLK("omapdss",  "ick",          &dss_ick,       CK_243X | CK_242X),
++      CLK("omapdss",  "dss1_fck",     &dss1_fck,      CK_243X | CK_242X),
++      CLK("omapdss",  "dss2_fck",     &dss2_fck,      CK_243X | CK_242X),
++      CLK("omapdss",  "tv_fck",       &dss_54m_fck,   CK_243X | CK_242X),
+       /* L3 domain clocks */
+       CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_243X | CK_242X),
+       CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_243X | CK_242X),
+diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
+index cd7819c..aff72ea 100644
+--- a/arch/arm/mach-omap2/clock34xx.c
++++ b/arch/arm/mach-omap2/clock34xx.c
+@@ -235,13 +235,13 @@ static struct omap_clk omap34xx_clks[] = {
+       CLK("omap_rng", "ick",          &rng_ick,       CK_343X),
+       CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_343X),
+       CLK(NULL,       "des1_ick",     &des1_ick,      CK_343X),
+-      CLK("omapfb",   "dss1_fck",     &dss1_alwon_fck_3430es1, CK_3430ES1),
+-      CLK("omapfb",   "dss1_fck",     &dss1_alwon_fck_3430es2, CK_3430ES2),
+-      CLK("omapfb",   "tv_fck",       &dss_tv_fck,    CK_343X),
+-      CLK("omapfb",   "video_fck",    &dss_96m_fck,   CK_343X),
+-      CLK("omapfb",   "dss2_fck",     &dss2_alwon_fck, CK_343X),
+-      CLK("omapfb",   "ick",          &dss_ick_3430es1,       CK_3430ES1),
+-      CLK("omapfb",   "ick",          &dss_ick_3430es2,       CK_3430ES2),
++      CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es1, CK_3430ES1),
++      CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es2, CK_3430ES2),
++      CLK("omapdss",  "tv_fck",       &dss_tv_fck,    CK_343X),
++      CLK("omapdss",  "video_fck",    &dss_96m_fck,   CK_343X),
++      CLK("omapdss",  "dss2_fck",     &dss2_alwon_fck, CK_343X),
++      CLK("omapdss",  "ick",          &dss_ick_3430es1,       CK_3430ES1),
++      CLK("omapdss",  "ick",          &dss_ick_3430es2,       CK_3430ES2),
+       CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_343X),
+       CLK(NULL,       "cam_ick",      &cam_ick,       CK_343X),
+       CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_343X),
+diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
+index f021770..d383888 100644
+--- a/drivers/video/omap/dispc.c
++++ b/drivers/video/omap/dispc.c
+@@ -24,6 +24,7 @@
+ #include <linux/vmalloc.h>
+ #include <linux/clk.h>
+ #include <linux/io.h>
++#include <linux/platform_device.h>
+ 
+ #include <mach/sram.h>
+ #include <mach/board.h>
+@@ -184,6 +185,11 @@ static struct {
+       struct omapfb_color_key color_key;
+ } dispc;
+ 
++static struct platform_device omapdss_device = {
++      .name           = "omapdss",
++      .id             = -1,
++};
++
+ static void enable_lcd_clocks(int enable);
+ 
+ static void inline dispc_write_reg(int idx, u32 val)
+@@ -880,20 +886,20 @@ static irqreturn_t omap_dispc_irq_handler(int irq, void *dev)
+ 
+ static int get_dss_clocks(void)
+ {
+-      dispc.dss_ick = clk_get(dispc.fbdev->dev, "ick");
++      dispc.dss_ick = clk_get(&omapdss_device.dev, "ick");
+       if (IS_ERR(dispc.dss_ick)) {
+               dev_err(dispc.fbdev->dev, "can't get ick\n");
+               return PTR_ERR(dispc.dss_ick);
+       }
+ 
+-      dispc.dss1_fck = clk_get(dispc.fbdev->dev, "dss1_fck");
++      dispc.dss1_fck = clk_get(&omapdss_device.dev, "dss1_fck");
+       if (IS_ERR(dispc.dss1_fck)) {
+               dev_err(dispc.fbdev->dev, "can't get dss1_fck\n");
+               clk_put(dispc.dss_ick);
+               return PTR_ERR(dispc.dss1_fck);
+       }
+ 
+-      dispc.dss_54m_fck = clk_get(dispc.fbdev->dev, "tv_fck");
++      dispc.dss_54m_fck = clk_get(&omapdss_device.dev, "tv_fck");
+       if (IS_ERR(dispc.dss_54m_fck)) {
+               dev_err(dispc.fbdev->dev, "can't get tv_fck\n");
+               clk_put(dispc.dss_ick);
+@@ -1349,6 +1355,12 @@ static int omap_dispc_init(struct omapfb_device *fbdev, int ext_mode,
+       int skip_init = 0;
+       int i;
+ 
++      r = platform_device_register(&omapdss_device);
++      if (r) {
++              dev_err(fbdev->dev, "can't register omapdss device\n");
++              return r;
++      }
++
+       memset(&dispc, 0, sizeof(dispc));
+ 
+       dispc.base = ioremap(DISPC_BASE, SZ_1K);
+@@ -1490,6 +1502,7 @@ static void omap_dispc_cleanup(void)
+       enable_interface_clocks(0);
+       put_dss_clocks();
+       iounmap(dispc.base);
++      platform_device_unregister(&omapdss_device);
+ }
+ 
+ const struct lcd_ctrl omap2_int_ctrl = {
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-2.6.31/dss2/0004-OMAP-Add-VRAM-manager.patch b/recipes/linux/linux-omap-2.6.31/dss2/0004-OMAP-Add-VRAM-manager.patch
new file mode 100644 (file)
index 0000000..13fe0b0
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.31/dss2/0004-OMAP-Add-VRAM-manager.patch
@@ -0,0 +1,854 @@
+From cb8ce54283e64bd30636b7bcd2d7bb4e200825d2 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Fri, 7 Aug 2009 12:01:55 +0300
+Subject: [PATCH 04/18] OMAP: Add VRAM manager
+
+Add a Video RAM manager for OMAP 2 and 3 platforms. VRAM manager is used
+to allocate large continuous blocks of SDRAM or SRAM. The features VRAM
+manager has that are missing from dma_alloc_* functions are:
+
+- Support for OMAP2's SRAM
+- Allocate without ioremapping
+- Allocate at defined physical addresses
+- Allows larger VRAM area and larger allocations
+
+The upcoming DSS2 uses VRAM manager.
+
+VRAM area size can be defined in kernel config, board file or with
+kernel boot parameters. Board file definition overrides kernel config,
+and boot parameter overrides kernel config and board file.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ arch/arm/mach-omap2/io.c               |    2 +
+ arch/arm/plat-omap/include/mach/vram.h |   63 +++
+ arch/arm/plat-omap/sram.c              |    8 +
+ drivers/video/Kconfig                  |    1 +
+ drivers/video/Makefile                 |    1 +
+ drivers/video/omap2/Kconfig            |    2 +
+ drivers/video/omap2/Makefile           |    1 +
+ drivers/video/omap2/vram.c             |  655 ++++++++++++++++++++++++++++++++
+ 8 files changed, 733 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/plat-omap/include/mach/vram.h
+ create mode 100644 drivers/video/omap2/Kconfig
+ create mode 100644 drivers/video/omap2/Makefile
+ create mode 100644 drivers/video/omap2/vram.c
+
+diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
+index 49199a3..f837063 100644
+--- a/arch/arm/mach-omap2/io.c
++++ b/arch/arm/mach-omap2/io.c
+@@ -32,6 +32,7 @@
+ #include <mach/sram.h>
+ #include <mach/sdrc.h>
+ #include <mach/gpmc.h>
++#include <mach/vram.h>
+ 
+ #ifndef CONFIG_ARCH_OMAP4     /* FIXME: Remove this once clkdev is ready */
+ #include "clock.h"
+@@ -240,6 +241,7 @@ void __init omap2_map_common_io(void)
+       omap2_check_revision();
+       omap_sram_init();
+       omapfb_reserve_sdram();
++      omap_vram_reserve_sdram();
+ }
+ 
+ /*
+diff --git a/arch/arm/plat-omap/include/mach/vram.h b/arch/arm/plat-omap/include/mach/vram.h
+new file mode 100644
+index 0000000..fe72f81
+--- /dev/null
++++ b/arch/arm/plat-omap/include/mach/vram.h
+@@ -0,0 +1,63 @@
++/*
++ * VRAM manager for OMAP
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
++ */
++
++#ifndef __OMAP_VRAM_H__
++#define __OMAP_VRAM_H__
++
++#include <linux/autoconf.h>
++#include <linux/types.h>
++
++#define OMAP_VRAM_MEMTYPE_SDRAM               0
++#define OMAP_VRAM_MEMTYPE_SRAM                1
++#define OMAP_VRAM_MEMTYPE_MAX         1
++
++extern int omap_vram_add_region(unsigned long paddr, size_t size);
++extern int omap_vram_free(unsigned long paddr, size_t size);
++extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr);
++extern int omap_vram_reserve(unsigned long paddr, size_t size);
++extern void omap_vram_get_info(unsigned long *vram, unsigned long *free_vram,
++              unsigned long *largest_free_block);
++
++#ifdef CONFIG_OMAP2_VRAM
++extern void omap_vram_set_sdram_vram(u32 size, u32 start);
++extern void omap_vram_set_sram_vram(u32 size, u32 start);
++
++extern void omap_vram_reserve_sdram(void);
++extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
++                                          unsigned long sram_vstart,
++                                          unsigned long sram_size,
++                                          unsigned long pstart_avail,
++                                          unsigned long size_avail);
++#else
++static inline void omap_vram_set_sdram_vram(u32 size, u32 start) { }
++static inline void omap_vram_set_sram_vram(u32 size, u32 start) { }
++
++static inline void omap_vram_reserve_sdram(void) { }
++static inline unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
++                                          unsigned long sram_vstart,
++                                          unsigned long sram_size,
++                                          unsigned long pstart_avail,
++                                          unsigned long size_avail)
++{
++      return 0;
++}
++#endif
++
++#endif
+diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
+index 5eae787..c9b89cd 100644
+--- a/arch/arm/plat-omap/sram.c
++++ b/arch/arm/plat-omap/sram.c
+@@ -28,6 +28,7 @@
+ #include <mach/sram.h>
+ #include <mach/board.h>
+ #include <mach/cpu.h>
++#include <mach/vram.h>
+ 
+ #include <mach/control.h>
+ 
+@@ -185,6 +186,13 @@ void __init omap_detect_sram(void)
+                                      omap_sram_start + SRAM_BOOTLOADER_SZ,
+                                      omap_sram_size - SRAM_BOOTLOADER_SZ);
+       omap_sram_size -= reserved;
++
++      reserved = omap_vram_reserve_sram(omap_sram_start, omap_sram_base,
++                      omap_sram_size,
++                      omap_sram_start + SRAM_BOOTLOADER_SZ,
++                      omap_sram_size - SRAM_BOOTLOADER_SZ);
++      omap_sram_size -= reserved;
++
+       omap_sram_ceil = omap_sram_base + omap_sram_size;
+ }
+ 
+diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
+index 3b54b39..e09367a 100644
+--- a/drivers/video/Kconfig
++++ b/drivers/video/Kconfig
+@@ -2149,6 +2149,7 @@ config FB_BROADSHEET
+         a bridge adapter.
+ 
+ source "drivers/video/omap/Kconfig"
++source "drivers/video/omap2/Kconfig"
+ 
+ source "drivers/video/backlight/Kconfig"
+ source "drivers/video/display/Kconfig"
+diff --git a/drivers/video/Makefile b/drivers/video/Makefile
+index 01a819f..cc7f5c8 100644
+--- a/drivers/video/Makefile
++++ b/drivers/video/Makefile
+@@ -123,6 +123,7 @@ obj-$(CONFIG_FB_SM501)            += sm501fb.o
+ obj-$(CONFIG_FB_XILINX)           += xilinxfb.o
+ obj-$(CONFIG_FB_SH_MOBILE_LCDC)         += sh_mobile_lcdcfb.o
+ obj-$(CONFIG_FB_OMAP)             += omap/
++obj-y                             += omap2/
+ obj-$(CONFIG_XEN_FBDEV_FRONTEND)  += xen-fbfront.o
+ obj-$(CONFIG_FB_CARMINE)          += carminefb.o
+ obj-$(CONFIG_FB_MB862XX)        += mb862xx/
+diff --git a/drivers/video/omap2/Kconfig b/drivers/video/omap2/Kconfig
+new file mode 100644
+index 0000000..7a6c4c9
+--- /dev/null
++++ b/drivers/video/omap2/Kconfig
+@@ -0,0 +1,2 @@
++config OMAP2_VRAM
++      bool
+diff --git a/drivers/video/omap2/Makefile b/drivers/video/omap2/Makefile
+new file mode 100644
+index 0000000..7fdf7bd
+--- /dev/null
++++ b/drivers/video/omap2/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_OMAP2_VRAM) += vram.o
+diff --git a/drivers/video/omap2/vram.c b/drivers/video/omap2/vram.c
+new file mode 100644
+index 0000000..634ce23
+--- /dev/null
++++ b/drivers/video/omap2/vram.c
+@@ -0,0 +1,655 @@
++/*
++ * VRAM manager for OMAP
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
++ */
++
++/*#define DEBUG*/
++
++#include <linux/kernel.h>
++#include <linux/mm.h>
++#include <linux/list.h>
++#include <linux/seq_file.h>
++#include <linux/bootmem.h>
++#include <linux/completion.h>
++#include <linux/debugfs.h>
++#include <linux/jiffies.h>
++#include <linux/module.h>
++
++#include <asm/setup.h>
++
++#include <mach/sram.h>
++#include <mach/vram.h>
++#include <mach/dma.h>
++
++#ifdef DEBUG
++#define DBG(format, ...) pr_debug("VRAM: " format, ## __VA_ARGS__)
++#else
++#define DBG(format, ...)
++#endif
++
++#define OMAP2_SRAM_START              0x40200000
++/* Maximum size, in reality this is smaller if SRAM is partially locked. */
++#define OMAP2_SRAM_SIZE                       0xa0000         /* 640k */
++
++/* postponed regions are used to temporarily store region information at boot
++ * time when we cannot yet allocate the region list */
++#define MAX_POSTPONED_REGIONS 10
++
++static bool vram_initialized;
++static int postponed_cnt;
++static struct {
++      unsigned long paddr;
++      size_t size;
++} postponed_regions[MAX_POSTPONED_REGIONS];
++
++struct vram_alloc {
++      struct list_head list;
++      unsigned long paddr;
++      unsigned pages;
++};
++
++struct vram_region {
++      struct list_head list;
++      struct list_head alloc_list;
++      unsigned long paddr;
++      unsigned pages;
++};
++
++static DEFINE_MUTEX(region_mutex);
++static LIST_HEAD(region_list);
++
++static inline int region_mem_type(unsigned long paddr)
++{
++      if (paddr >= OMAP2_SRAM_START &&
++          paddr < OMAP2_SRAM_START + OMAP2_SRAM_SIZE)
++              return OMAP_VRAM_MEMTYPE_SRAM;
++      else
++              return OMAP_VRAM_MEMTYPE_SDRAM;
++}
++
++static struct vram_region *omap_vram_create_region(unsigned long paddr,
++              unsigned pages)
++{
++      struct vram_region *rm;
++
++      rm = kzalloc(sizeof(*rm), GFP_KERNEL);
++
++      if (rm) {
++              INIT_LIST_HEAD(&rm->alloc_list);
++              rm->paddr = paddr;
++              rm->pages = pages;
++      }
++
++      return rm;
++}
++
++#if 0
++static void omap_vram_free_region(struct vram_region *vr)
++{
++      list_del(&vr->list);
++      kfree(vr);
++}
++#endif
++
++static struct vram_alloc *omap_vram_create_allocation(struct vram_region *vr,
++              unsigned long paddr, unsigned pages)
++{
++      struct vram_alloc *va;
++      struct vram_alloc *new;
++
++      new = kzalloc(sizeof(*va), GFP_KERNEL);
++
++      if (!new)
++              return NULL;
++
++      new->paddr = paddr;
++      new->pages = pages;
++
++      list_for_each_entry(va, &vr->alloc_list, list) {
++              if (va->paddr > new->paddr)
++                      break;
++      }
++
++      list_add_tail(&new->list, &va->list);
++
++      return new;
++}
++
++static void omap_vram_free_allocation(struct vram_alloc *va)
++{
++      list_del(&va->list);
++      kfree(va);
++}
++
++int omap_vram_add_region(unsigned long paddr, size_t size)
++{
++      struct vram_region *rm;
++      unsigned pages;
++
++      if (vram_initialized) {
++              DBG("adding region paddr %08lx size %d\n",
++                              paddr, size);
++
++              size &= PAGE_MASK;
++              pages = size >> PAGE_SHIFT;
++
++              rm = omap_vram_create_region(paddr, pages);
++              if (rm == NULL)
++                      return -ENOMEM;
++
++              list_add(&rm->list, &region_list);
++      } else {
++              if (postponed_cnt == MAX_POSTPONED_REGIONS)
++                      return -ENOMEM;
++
++              postponed_regions[postponed_cnt].paddr = paddr;
++              postponed_regions[postponed_cnt].size = size;
++
++              ++postponed_cnt;
++      }
++      return 0;
++}
++
++int omap_vram_free(unsigned long paddr, size_t size)
++{
++      struct vram_region *rm;
++      struct vram_alloc *alloc;
++      unsigned start, end;
++
++      DBG("free mem paddr %08lx size %d\n", paddr, size);
++
++      size = PAGE_ALIGN(size);
++
++      mutex_lock(&region_mutex);
++
++      list_for_each_entry(rm, &region_list, list) {
++              list_for_each_entry(alloc, &rm->alloc_list, list) {
++                      start = alloc->paddr;
++                      end = alloc->paddr + (alloc->pages >> PAGE_SHIFT);
++
++                      if (start >= paddr && end < paddr + size)
++                              goto found;
++              }
++      }
++
++      mutex_unlock(&region_mutex);
++      return -EINVAL;
++
++found:
++      omap_vram_free_allocation(alloc);
++
++      mutex_unlock(&region_mutex);
++      return 0;
++}
++EXPORT_SYMBOL(omap_vram_free);
++
++static int _omap_vram_reserve(unsigned long paddr, unsigned pages)
++{
++      struct vram_region *rm;
++      struct vram_alloc *alloc;
++      size_t size;
++
++      size = pages << PAGE_SHIFT;
++
++      list_for_each_entry(rm, &region_list, list) {
++              unsigned long start, end;
++
++              DBG("checking region %lx %d\n", rm->paddr, rm->pages);
++
++              if (region_mem_type(rm->paddr) != region_mem_type(paddr))
++                      continue;
++
++              start = rm->paddr;
++              end = start + (rm->pages << PAGE_SHIFT) - 1;
++              if (start > paddr || end < paddr + size - 1)
++                      continue;
++
++              DBG("block ok, checking allocs\n");
++
++              list_for_each_entry(alloc, &rm->alloc_list, list) {
++                      end = alloc->paddr - 1;
++
++                      if (start <= paddr && end >= paddr + size - 1)
++                              goto found;
++
++                      start = alloc->paddr + (alloc->pages << PAGE_SHIFT);
++              }
++
++              end = rm->paddr + (rm->pages << PAGE_SHIFT) - 1;
++
++              if (!(start <= paddr && end >= paddr + size - 1))
++                      continue;
++found:
++              DBG("found area start %lx, end %lx\n", start, end);
++
++              if (omap_vram_create_allocation(rm, paddr, pages) == NULL)
++                      return -ENOMEM;
++
++              return 0;
++      }
++
++      return -ENOMEM;
++}
++
++int omap_vram_reserve(unsigned long paddr, size_t size)
++{
++      unsigned pages;
++      int r;
++
++      DBG("reserve mem paddr %08lx size %d\n", paddr, size);
++
++      size = PAGE_ALIGN(size);
++      pages = size >> PAGE_SHIFT;
++
++      mutex_lock(&region_mutex);
++
++      r = _omap_vram_reserve(paddr, pages);
++
++      mutex_unlock(&region_mutex);
++
++      return r;
++}
++EXPORT_SYMBOL(omap_vram_reserve);
++
++static void _omap_vram_dma_cb(int lch, u16 ch_status, void *data)
++{
++      struct completion *compl = data;
++      complete(compl);
++}
++
++static int _omap_vram_clear(u32 paddr, unsigned pages)
++{
++      struct completion compl;
++      unsigned elem_count;
++      unsigned frame_count;
++      int r;
++      int lch;
++
++      init_completion(&compl);
++
++      r = omap_request_dma(OMAP_DMA_NO_DEVICE, "VRAM DMA",
++                      _omap_vram_dma_cb,
++                      &compl, &lch);
++      if (r) {
++              pr_err("VRAM: request_dma failed for memory clear\n");
++              return -EBUSY;
++      }
++
++      elem_count = pages * PAGE_SIZE / 4;
++      frame_count = 1;
++
++      omap_set_dma_transfer_params(lch, OMAP_DMA_DATA_TYPE_S32,
++                      elem_count, frame_count,
++                      OMAP_DMA_SYNC_ELEMENT,
++                      0, 0);
++
++      omap_set_dma_dest_params(lch, 0, OMAP_DMA_AMODE_POST_INC,
++                      paddr, 0, 0);
++
++      omap_set_dma_color_mode(lch, OMAP_DMA_CONSTANT_FILL, 0x000000);
++
++      omap_start_dma(lch);
++
++      if (wait_for_completion_timeout(&compl, msecs_to_jiffies(1000)) == 0) {
++              omap_stop_dma(lch);
++              pr_err("VRAM: dma timeout while clearing memory\n");
++              r = -EIO;
++              goto err;
++      }
++
++      r = 0;
++err:
++      omap_free_dma(lch);
++
++      return r;
++}
++
++static int _omap_vram_alloc(int mtype, unsigned pages, unsigned long *paddr)
++{
++      struct vram_region *rm;
++      struct vram_alloc *alloc;
++
++      list_for_each_entry(rm, &region_list, list) {
++              unsigned long start, end;
++
++              DBG("checking region %lx %d\n", rm->paddr, rm->pages);
++
++              if (region_mem_type(rm->paddr) != mtype)
++                      continue;
++
++              start = rm->paddr;
++
++              list_for_each_entry(alloc, &rm->alloc_list, list) {
++                      end = alloc->paddr;
++
++                      if (end - start >= pages << PAGE_SHIFT)
++                              goto found;
++
++                      start = alloc->paddr + (alloc->pages << PAGE_SHIFT);
++              }
++
++              end = rm->paddr + (rm->pages << PAGE_SHIFT);
++found:
++              if (end - start < pages << PAGE_SHIFT)
++                      continue;
++
++              DBG("found %lx, end %lx\n", start, end);
++
++              alloc = omap_vram_create_allocation(rm, start, pages);
++              if (alloc == NULL)
++                      return -ENOMEM;
++
++              *paddr = start;
++
++              _omap_vram_clear(start, pages);
++
++              return 0;
++      }
++
++      return -ENOMEM;
++}
++
++int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr)
++{
++      unsigned pages;
++      int r;
++
++      BUG_ON(mtype > OMAP_VRAM_MEMTYPE_MAX || !size);
++
++      DBG("alloc mem type %d size %d\n", mtype, size);
++
++      size = PAGE_ALIGN(size);
++      pages = size >> PAGE_SHIFT;
++
++      mutex_lock(&region_mutex);
++
++      r = _omap_vram_alloc(mtype, pages, paddr);
++
++      mutex_unlock(&region_mutex);
++
++      return r;
++}
++EXPORT_SYMBOL(omap_vram_alloc);
++
++void omap_vram_get_info(unsigned long *vram,
++              unsigned long *free_vram,
++              unsigned long *largest_free_block)
++{
++      struct vram_region *vr;
++      struct vram_alloc *va;
++
++      *vram = 0;
++      *free_vram = 0;
++      *largest_free_block = 0;
++
++      mutex_lock(&region_mutex);
++
++      list_for_each_entry(vr, &region_list, list) {
++              unsigned free;
++              unsigned long pa;
++
++              pa = vr->paddr;
++              *vram += vr->pages << PAGE_SHIFT;
++
++              list_for_each_entry(va, &vr->alloc_list, list) {
++                      free = va->paddr - pa;
++                      *free_vram += free;
++                      if (free > *largest_free_block)
++                              *largest_free_block = free;
++                      pa = va->paddr + (va->pages << PAGE_SHIFT);
++              }
++
++              free = vr->paddr + (vr->pages << PAGE_SHIFT) - pa;
++              *free_vram += free;
++              if (free > *largest_free_block)
++                      *largest_free_block = free;
++      }
++
++      mutex_unlock(&region_mutex);
++}
++EXPORT_SYMBOL(omap_vram_get_info);
++
++#if defined(CONFIG_DEBUG_FS)
++static int vram_debug_show(struct seq_file *s, void *unused)
++{
++      struct vram_region *vr;
++      struct vram_alloc *va;
++      unsigned size;
++
++      mutex_lock(&region_mutex);
++
++      list_for_each_entry(vr, &region_list, list) {
++              size = vr->pages << PAGE_SHIFT;
++              seq_printf(s, "%08lx-%08lx (%d bytes)\n",
++                              vr->paddr, vr->paddr + size - 1,
++                              size);
++
++              list_for_each_entry(va, &vr->alloc_list, list) {
++                      size = va->pages << PAGE_SHIFT;
++                      seq_printf(s, "    %08lx-%08lx (%d bytes)\n",
++                                      va->paddr, va->paddr + size - 1,
++                                      size);
++              }
++      }
++
++      mutex_unlock(&region_mutex);
++
++      return 0;
++}
++
++static int vram_debug_open(struct inode *inode, struct file *file)
++{
++      return single_open(file, vram_debug_show, inode->i_private);
++}
++
++static const struct file_operations vram_debug_fops = {
++      .open           = vram_debug_open,
++      .read           = seq_read,
++      .llseek         = seq_lseek,
++      .release        = single_release,
++};
++
++static int __init omap_vram_create_debugfs(void)
++{
++      struct dentry *d;
++
++      d = debugfs_create_file("vram", S_IRUGO, NULL,
++                      NULL, &vram_debug_fops);
++      if (IS_ERR(d))
++              return PTR_ERR(d);
++
++      return 0;
++}
++#endif
++
++static __init int omap_vram_init(void)
++{
++      int i;
++
++      vram_initialized = 1;
++
++      for (i = 0; i < postponed_cnt; i++)
++              omap_vram_add_region(postponed_regions[i].paddr,
++                              postponed_regions[i].size);
++
++#ifdef CONFIG_DEBUG_FS
++      if (omap_vram_create_debugfs())
++              pr_err("VRAM: Failed to create debugfs file\n");
++#endif
++
++      return 0;
++}
++
++arch_initcall(omap_vram_init);
++
++/* boottime vram alloc stuff */
++
++/* set from board file */
++static u32 omap_vram_sram_start __initdata;
++static u32 omap_vram_sram_size __initdata;
++
++/* set from board file */
++static u32 omap_vram_sdram_start __initdata;
++static u32 omap_vram_sdram_size __initdata;
++
++/* set from kernel cmdline */
++static u32 omap_vram_def_sdram_size __initdata;
++static u32 omap_vram_def_sdram_start __initdata;
++
++static void __init omap_vram_early_vram(char **p)
++{
++      omap_vram_def_sdram_size = memparse(*p, p);
++      if (**p == ',')
++              omap_vram_def_sdram_start = simple_strtoul((*p) + 1, p, 16);
++}
++__early_param("vram=", omap_vram_early_vram);
++
++/*
++ * Called from map_io. We need to call to this early enough so that we
++ * can reserve the fixed SDRAM regions before VM could get hold of them.
++ */
++void __init omap_vram_reserve_sdram(void)
++{
++      struct bootmem_data     *bdata;
++      unsigned long           sdram_start, sdram_size;
++      u32 paddr;
++      u32 size = 0;
++
++      /* cmdline arg overrides the board file definition */
++      if (omap_vram_def_sdram_size) {
++              size = omap_vram_def_sdram_size;
++              paddr = omap_vram_def_sdram_start;
++      }
++
++      if (!size) {
++              size = omap_vram_sdram_size;
++              paddr = omap_vram_sdram_start;
++      }
++
++#ifdef CONFIG_OMAP2_VRAM_SIZE
++      if (!size) {
++              size = CONFIG_OMAP2_VRAM_SIZE * 1024 * 1024;
++              paddr = 0;
++      }
++#endif
++
++      if (!size)
++              return;
++
++      size = PAGE_ALIGN(size);
++
++      bdata = NODE_DATA(0)->bdata;
++      sdram_start = bdata->node_min_pfn << PAGE_SHIFT;
++      sdram_size = (bdata->node_low_pfn << PAGE_SHIFT) - sdram_start;
++
++      if (paddr) {
++              if ((paddr & ~PAGE_MASK) || paddr < sdram_start ||
++                              paddr + size > sdram_start + sdram_size) {
++                      pr_err("Illegal SDRAM region for VRAM\n");
++                      return;
++              }
++
++              if (reserve_bootmem(paddr, size, BOOTMEM_EXCLUSIVE) < 0) {
++                      pr_err("FB: failed to reserve VRAM\n");
++                      return;
++              }
++      } else {
++              if (size > sdram_size) {
++                      pr_err("Illegal SDRAM size for VRAM\n");
++                      return;
++              }
++
++              paddr = virt_to_phys(alloc_bootmem_pages(size));
++              BUG_ON(paddr & ~PAGE_MASK);
++      }
++
++      omap_vram_add_region(paddr, size);
++
++      pr_info("Reserving %u bytes SDRAM for VRAM\n", size);
++}
++
++/*
++ * Called at sram init time, before anything is pushed to the SRAM stack.
++ * Because of the stack scheme, we will allocate everything from the
++ * start of the lowest address region to the end of SRAM. This will also
++ * include padding for page alignment and possible holes between regions.
++ *
++ * As opposed to the SDRAM case, we'll also do any dynamic allocations at
++ * this point, since the driver built as a module would have problem with
++ * freeing / reallocating the regions.
++ */
++unsigned long __init omap_vram_reserve_sram(unsigned long sram_pstart,
++                                unsigned long sram_vstart,
++                                unsigned long sram_size,
++                                unsigned long pstart_avail,
++                                unsigned long size_avail)
++{
++      unsigned long                   pend_avail;
++      unsigned long                   reserved;
++      u32 paddr;
++      u32 size;
++
++      paddr = omap_vram_sram_start;
++      size = omap_vram_sram_size;
++
++      if (!size)
++              return 0;
++
++      reserved = 0;
++      pend_avail = pstart_avail + size_avail;
++
++      if (!paddr) {
++              /* Dynamic allocation */
++              if ((size_avail & PAGE_MASK) < size) {
++                      pr_err("Not enough SRAM for VRAM\n");
++                      return 0;
++              }
++              size_avail = (size_avail - size) & PAGE_MASK;
++              paddr = pstart_avail + size_avail;
++      }
++
++      if (paddr < sram_pstart ||
++                      paddr + size > sram_pstart + sram_size) {
++              pr_err("Illegal SRAM region for VRAM\n");
++              return 0;
++      }
++
++      /* Reserve everything above the start of the region. */
++      if (pend_avail - paddr > reserved)
++              reserved = pend_avail - paddr;
++      size_avail = pend_avail - reserved - pstart_avail;
++
++      omap_vram_add_region(paddr, size);
++
++      if (reserved)
++              pr_info("Reserving %lu bytes SRAM for VRAM\n", reserved);
++
++      return reserved;
++}
++
++void __init omap_vram_set_sdram_vram(u32 size, u32 start)
++{
++      omap_vram_sdram_start = start;
++      omap_vram_sdram_size = size;
++}
++
++void __init omap_vram_set_sram_vram(u32 size, u32 start)
++{
++      omap_vram_sram_start = start;
++      omap_vram_sram_size = size;
++}
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-2.6.31/dss2/0005-OMAP-Add-support-for-VRFB-rotation-engine.patch b/recipes/linux/linux-omap-2.6.31/dss2/0005-OMAP-Add-support-for-VRFB-rotation-engine.patch
new file mode 100644 (file)
index 0000000..0a38a31
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.31/dss2/0005-OMAP-Add-support-for-VRFB-rotation-engine.patch
@@ -0,0 +1,378 @@
+From 4df5684fb6c8cab641a843d890bd010cb32ccc97 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Fri, 7 Aug 2009 12:04:26 +0300
+Subject: [PATCH 05/18] OMAP: Add support for VRFB rotation engine
+
+VRFB rotation engine is a block in OMAP2/3 that offers 12 independent
+contexts that can be used for framebuffer rotation.
+
+Each context has a backend area of real memory, where it stores the
+pixels in undisclosed format. This memory is offered to users via 4
+virtual memory areas, which see the same memory area in different
+rotation angles (0, 90, 180 and 270 degrees).
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ arch/arm/plat-omap/include/mach/vrfb.h |   46 ++++++
+ drivers/video/omap2/Kconfig            |    3 +
+ drivers/video/omap2/Makefile           |    1 +
+ drivers/video/omap2/vrfb.c             |  277 ++++++++++++++++++++++++++++++++
+ 4 files changed, 327 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/plat-omap/include/mach/vrfb.h
+ create mode 100644 drivers/video/omap2/vrfb.c
+
+diff --git a/arch/arm/plat-omap/include/mach/vrfb.h b/arch/arm/plat-omap/include/mach/vrfb.h
+new file mode 100644
+index 0000000..8790612
+--- /dev/null
++++ b/arch/arm/plat-omap/include/mach/vrfb.h
+@@ -0,0 +1,46 @@
++/*
++ * VRFB Rotation Engine
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
++ */
++
++#ifndef __OMAP_VRFB_H__
++#define __OMAP_VRFB_H__
++
++#define OMAP_VRFB_LINE_LEN 2048
++
++struct vrfb {
++      u8 context;
++      void __iomem *vaddr[4];
++      unsigned long paddr[4];
++      u16 xoffset;
++      u16 yoffset;
++      u8 bytespp;
++};
++
++extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
++extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
++extern void omap_vrfb_suspend_ctx(struct vrfb *vrfb);
++extern void omap_vrfb_resume_ctx(struct vrfb *vrfb);
++extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
++              u8 bytespp);
++extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
++              u16 width, u16 height,
++              unsigned bytespp, bool yuv_mode);
++extern void omap_vrfb_restore_context(void);
++
++#endif /* __VRFB_H */
+diff --git a/drivers/video/omap2/Kconfig b/drivers/video/omap2/Kconfig
+index 7a6c4c9..ac8b650 100644
+--- a/drivers/video/omap2/Kconfig
++++ b/drivers/video/omap2/Kconfig
+@@ -1,2 +1,5 @@
+ config OMAP2_VRAM
+       bool
++
++config OMAP2_VRFB
++      bool
+diff --git a/drivers/video/omap2/Makefile b/drivers/video/omap2/Makefile
+index 7fdf7bd..aa3751b 100644
+--- a/drivers/video/omap2/Makefile
++++ b/drivers/video/omap2/Makefile
+@@ -1 +1,2 @@
+ obj-$(CONFIG_OMAP2_VRAM) += vram.o
++obj-$(CONFIG_OMAP2_VRFB) += vrfb.o
+diff --git a/drivers/video/omap2/vrfb.c b/drivers/video/omap2/vrfb.c
+new file mode 100644
+index 0000000..8726689
+--- /dev/null
++++ b/drivers/video/omap2/vrfb.c
+@@ -0,0 +1,277 @@
++/*
++ * VRFB Rotation Engine
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/ioport.h>
++#include <linux/io.h>
++#include <linux/bitops.h>
++#include <linux/mutex.h>
++
++#include <mach/io.h>
++#include <mach/vrfb.h>
++#include <mach/sdrc.h>
++/*#define DEBUG*/
++
++#ifdef DEBUG
++#define DBG(format, ...) pr_debug("VRFB: " format, ## __VA_ARGS__)
++#else
++#define DBG(format, ...)
++#endif
++
++#define SMS_ROT_VIRT_BASE(context, rot) \
++      (((context >= 4) ? 0xD0000000 : 0x70000000) \
++       + (0x4000000 * (context)) \
++       + (0x1000000 * (rot)))
++
++#define OMAP_VRFB_SIZE                        (2048 * 2048 * 4)
++
++#define VRFB_PAGE_WIDTH_EXP   5 /* Assuming SDRAM pagesize= 1024 */
++#define VRFB_PAGE_HEIGHT_EXP  5 /* 1024 = 2^5 * 2^5 */
++#define VRFB_PAGE_WIDTH               (1 << VRFB_PAGE_WIDTH_EXP)
++#define VRFB_PAGE_HEIGHT      (1 << VRFB_PAGE_HEIGHT_EXP)
++#define SMS_IMAGEHEIGHT_OFFSET        16
++#define SMS_IMAGEWIDTH_OFFSET 0
++#define SMS_PH_OFFSET         8
++#define SMS_PW_OFFSET         4
++#define SMS_PS_OFFSET         0
++
++#define VRFB_NUM_CTXS 12
++/* bitmap of reserved contexts */
++static unsigned long ctx_map;
++/* bitmap of contexts for which we have to keep the HW context valid */
++static unsigned long ctx_map_active;
++
++static DEFINE_MUTEX(ctx_lock);
++
++/*
++ * Access to this happens from client drivers or the PM core after wake-up.
++ * For the first case we require locking at the driver level, for the second
++ * we don't need locking, since no drivers will run until after the wake-up
++ * has finished.
++ */
++static struct {
++      u32 physical_ba;
++      u32 control;
++      u32 size;
++} vrfb_hw_context[VRFB_NUM_CTXS];
++
++static inline void restore_hw_context(int ctx)
++{
++      omap2_sms_write_rot_control(vrfb_hw_context[ctx].control, ctx);
++      omap2_sms_write_rot_size(vrfb_hw_context[ctx].size, ctx);
++      omap2_sms_write_rot_physical_ba(vrfb_hw_context[ctx].physical_ba, ctx);
++}
++
++void omap_vrfb_restore_context(void)
++{
++      int i;
++      unsigned long map = ctx_map_active;
++
++      for (i = ffs(map); i; i = ffs(map)) {
++              /* i=1..32 */
++              i--;
++              map &= ~(1 << i);
++              restore_hw_context(i);
++      }
++}
++
++void omap_vrfb_adjust_size(u16 *width, u16 *height,
++              u8 bytespp)
++{
++      *width = ALIGN(*width * bytespp, VRFB_PAGE_WIDTH) / bytespp;
++      *height = ALIGN(*height, VRFB_PAGE_HEIGHT);
++}
++EXPORT_SYMBOL(omap_vrfb_adjust_size);
++
++void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
++              u16 width, u16 height,
++              unsigned bytespp, bool yuv_mode)
++{
++      unsigned pixel_size_exp;
++      u16 vrfb_width;
++      u16 vrfb_height;
++      u8 ctx = vrfb->context;
++      u32 size;
++      u32 control;
++
++      DBG("omapfb_set_vrfb(%d, %lx, %dx%d, %d)\n", ctx, paddr,
++                      width, height, color_mode);
++
++      /* For YUV2 and UYVY modes VRFB needs to handle pixels a bit
++       * differently. See TRM. */
++      if (yuv_mode) {
++              bytespp *= 2;
++              width /= 2;
++      }
++
++      if (bytespp == 4)
++              pixel_size_exp = 2;
++      else if (bytespp == 2)
++              pixel_size_exp = 1;
++      else
++              BUG();
++
++      vrfb_width = ALIGN(width * bytespp, VRFB_PAGE_WIDTH) / bytespp;
++      vrfb_height = ALIGN(height, VRFB_PAGE_HEIGHT);
++
++      DBG("vrfb w %u, h %u bytespp %d\n", vrfb_width, vrfb_height, bytespp);
++
++      size  = vrfb_width << SMS_IMAGEWIDTH_OFFSET;
++      size |= vrfb_height << SMS_IMAGEHEIGHT_OFFSET;
++
++      control  = pixel_size_exp << SMS_PS_OFFSET;
++      control |= VRFB_PAGE_WIDTH_EXP  << SMS_PW_OFFSET;
++      control |= VRFB_PAGE_HEIGHT_EXP << SMS_PH_OFFSET;
++
++      vrfb_hw_context[ctx].physical_ba = paddr;
++      vrfb_hw_context[ctx].size = size;
++      vrfb_hw_context[ctx].control = control;
++
++      omap2_sms_write_rot_physical_ba(paddr, ctx);
++      omap2_sms_write_rot_size(size, ctx);
++      omap2_sms_write_rot_control(control, ctx);
++
++      DBG("vrfb offset pixels %d, %d\n",
++                      vrfb_width - width, vrfb_height - height);
++
++      vrfb->xoffset = vrfb_width - width;
++      vrfb->yoffset = vrfb_height - height;
++      vrfb->bytespp = bytespp;
++}
++EXPORT_SYMBOL(omap_vrfb_setup);
++
++void omap_vrfb_release_ctx(struct vrfb *vrfb)
++{
++      int rot;
++      int ctx = vrfb->context;
++
++      if (ctx == 0xff)
++              return;
++
++      DBG("release ctx %d\n", ctx);
++
++      mutex_lock(&ctx_lock);
++
++      BUG_ON(!(ctx_map & (1 << ctx)));
++
++      clear_bit(ctx, &ctx_map_active);
++      clear_bit(ctx, &ctx_map);
++
++      for (rot = 0; rot < 4; ++rot) {
++              if (vrfb->paddr[rot]) {
++                      release_mem_region(vrfb->paddr[rot], OMAP_VRFB_SIZE);
++                      vrfb->paddr[rot] = 0;
++              }
++      }
++
++      vrfb->context = 0xff;
++
++      mutex_unlock(&ctx_lock);
++}
++EXPORT_SYMBOL(omap_vrfb_release_ctx);
++
++int omap_vrfb_request_ctx(struct vrfb *vrfb)
++{
++      int rot;
++      u32 paddr;
++      u8 ctx;
++      int r;
++
++      DBG("request ctx\n");
++
++      mutex_lock(&ctx_lock);
++
++      for (ctx = 0; ctx < VRFB_NUM_CTXS; ++ctx)
++              if ((ctx_map & (1 << ctx)) == 0)
++                      break;
++
++      if (ctx == VRFB_NUM_CTXS) {
++              pr_err("vrfb: no free contexts\n");
++              r = -EBUSY;
++              goto out;
++      }
++
++      DBG("found free ctx %d\n", ctx);
++
++      set_bit(ctx, &ctx_map);
++      WARN_ON(ctx_map_active & (1 << ctx));
++      set_bit(ctx, &ctx_map_active);
++
++      memset(vrfb, 0, sizeof(*vrfb));
++
++      vrfb->context = ctx;
++
++      for (rot = 0; rot < 4; ++rot) {
++              paddr = SMS_ROT_VIRT_BASE(ctx, rot);
++              if (!request_mem_region(paddr, OMAP_VRFB_SIZE, "vrfb")) {
++                      pr_err("vrfb: failed to reserve VRFB "
++                                      "area for ctx %d, rotation %d\n",
++                                      ctx, rot * 90);
++                      omap_vrfb_release_ctx(vrfb);
++                      r = -ENOMEM;
++                      goto out;
++              }
++
++              vrfb->paddr[rot] = paddr;
++
++              DBG("VRFB %d/%d: %lx\n", ctx, rot*90, vrfb->paddr[rot]);
++      }
++
++      r = 0;
++out:
++      mutex_unlock(&ctx_lock);
++      return r;
++}
++EXPORT_SYMBOL(omap_vrfb_request_ctx);
++
++void omap_vrfb_suspend_ctx(struct vrfb *vrfb)
++{
++      DBG("suspend ctx %d\n", vrfb->context);
++      mutex_lock(&ctx_lock);
++
++      BUG_ON(vrfb->context >= VRFB_NUM_CTXS);
++      BUG_ON(!((1 << vrfb->context) & ctx_map_active));
++
++      clear_bit(vrfb->context, &ctx_map_active);
++      mutex_unlock(&ctx_lock);
++}
++EXPORT_SYMBOL(omap_vrfb_suspend_ctx);
++
++void omap_vrfb_resume_ctx(struct vrfb *vrfb)
++{
++      DBG("resume ctx %d\n", vrfb->context);
++      mutex_lock(&ctx_lock);
++
++      BUG_ON(vrfb->context >= VRFB_NUM_CTXS);
++      BUG_ON((1 << vrfb->context) & ctx_map_active);
++
++      /*
++       * omap_vrfb_restore_context is normally called by the core domain
++       * save / restore logic, but since this VRFB context was suspended
++       * those calls didn't actually restore the context and now we might
++       * have an invalid context. Do an explicit restore here.
++       */
++      restore_hw_context(vrfb->context);
++      set_bit(vrfb->context, &ctx_map_active);
++      mutex_unlock(&ctx_lock);
++}
++EXPORT_SYMBOL(omap_vrfb_resume_ctx);
++
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-2.6.31/dss2/0006-OMAP-DSS2-Documentation-for-DSS2.patch b/recipes/linux/linux-omap-2.6.31/dss2/0006-OMAP-DSS2-Documentation-for-DSS2.patch
new file mode 100644 (file)
index 0000000..ab159d5
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.31/dss2/0006-OMAP-DSS2-Documentation-for-DSS2.patch
@@ -0,0 +1,337 @@
+From f7ffb36c21956befc2b8b51cf4db0e99f954ae06 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Tue, 4 Aug 2009 15:47:11 +0300
+Subject: [PATCH 06/18] OMAP: DSS2: Documentation for DSS2
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ Documentation/arm/OMAP/DSS |  317 ++++++++++++++++++++++++++++++++++++++++++++
+ 1 files changed, 317 insertions(+), 0 deletions(-)
+ create mode 100644 Documentation/arm/OMAP/DSS
+
+diff --git a/Documentation/arm/OMAP/DSS b/Documentation/arm/OMAP/DSS
+new file mode 100644
+index 0000000..0af0e9e
+--- /dev/null
++++ b/Documentation/arm/OMAP/DSS
+@@ -0,0 +1,317 @@
++OMAP2/3 Display Subsystem
++-------------------------
++
++This is an almost total rewrite of the OMAP FB driver in drivers/video/omap
++(let's call it DSS1). The main differences between DSS1 and DSS2 are DSI,
++TV-out and multiple display support, but there are lots of small improvements
++also.
++
++The DSS2 driver (omapdss module) is in arch/arm/plat-omap/dss/, and the FB,
++panel and controller drivers are in drivers/video/omap2/. DSS1 and DSS2 live
++currently side by side, you can choose which one to use.
++
++Features
++--------
++
++Working and tested features include:
++
++- MIPI DPI (parallel) output
++- MIPI DSI output in command mode
++- MIPI DBI (RFBI) output
++- SDI output
++- TV output
++- All pieces can be compiled as a module or inside kernel
++- Use DISPC to update any of the outputs
++- Use CPU to update RFBI or DSI output
++- OMAP DISPC planes
++- RGB16, RGB24 packed, RGB24 unpacked
++- YUV2, UYVY
++- Scaling
++- Adjusting DSS FCK to find a good pixel clock
++- Use DSI DPLL to create DSS FCK
++
++Tested boards include:
++- OMAP3 SDP board
++- Beagle board
++- N810
++
++omapdss driver
++--------------
++
++The DSS driver does not itself have any support for Linux framebuffer, V4L or
++such like the current ones, but it has an internal kernel API that upper level
++drivers can use.
++
++The DSS driver models OMAP's overlays, overlay managers and displays in a
++flexible way to enable non-common multi-display configuration. In addition to
++modelling the hardware overlays, omapdss supports virtual overlays and overlay
++managers. These can be used when updating a display with CPU or system DMA.
++
++Panel and controller drivers
++----------------------------
++
++The drivers implement panel or controller specific functionality and are not
++usually visible to users except through omapfb driver.  They register
++themselves to the DSS driver.
++
++omapfb driver
++-------------
++
++The omapfb driver implements arbitrary number of standard linux framebuffers.
++These framebuffers can be routed flexibly to any overlays, thus allowing very
++dynamic display architecture.
++
++The driver exports some omapfb specific ioctls, which are compatible with the
++ioctls in the old driver.
++
++The rest of the non standard features are exported via sysfs. Whether the final
++implementation will use sysfs, or ioctls, is still open.
++
++V4L2 drivers
++------------
++
++V4L2 is being implemented in TI.
++
++From omapdss point of view the V4L2 drivers should be similar to framebuffer
++driver.
++
++Architecture
++--------------------
++
++Some clarification what the different components do:
++
++    - Framebuffer is a memory area inside OMAP's SRAM/SDRAM that contains the
++      pixel data for the image. Framebuffer has width and height and color
++      depth.
++    - Overlay defines where the pixels are read from and where they go on the
++      screen. The overlay may be smaller than framebuffer, thus displaying only
++      part of the framebuffer. The position of the overlay may be changed if
++      the overlay is smaller than the display.
++    - Overlay manager combines the overlays in to one image and feeds them to
++      display.
++    - Display is the actual physical display device.
++
++A framebuffer can be connected to multiple overlays to show the same pixel data
++on all of the overlays. Note that in this case the overlay input sizes must be
++the same, but, in case of video overlays, the output size can be different. Any
++framebuffer can be connected to any overlay.
++
++An overlay can be connected to one overlay manager. Also DISPC overlays can be
++connected only to DISPC overlay managers, and virtual overlays can be only
++connected to virtual overlays.
++
++An overlay manager can be connected to one display. There are certain
++restrictions which kinds of displays an overlay manager can be connected:
++
++    - DISPC TV overlay manager can be only connected to TV display.
++    - Virtual overlay managers can only be connected to DBI or DSI displays.
++    - DISPC LCD overlay manager can be connected to all displays, except TV
++      display.
++
++Sysfs
++-----
++The sysfs interface is mainly used for testing. I don't think sysfs
++interface is the best for this in the final version, but I don't quite know
++what would be the best interfaces for these things.
++
++The sysfs interface is divided to two parts: DSS and FB.
++
++/sys/class/graphics/fb? directory:
++mirror                0=off, 1=on
++rotate                Rotation 0-3 for 0, 90, 180, 270 degrees
++rotate_type   0 = DMA rotation, 1 = VRFB rotation
++overlays      List of overlay numbers to which framebuffer pixels go
++phys_addr     Physical address of the framebuffer
++virt_addr     Virtual address of the framebuffer
++size          Size of the framebuffer
++
++/sys/devices/platform/omapdss/overlay? directory:
++enabled               0=off, 1=on
++input_size    width,height (ie. the framebuffer size)
++manager               Destination overlay manager name
++name
++output_size   width,height
++position      x,y
++screen_width  width
++global_alpha          global alpha 0-255 0=transparent 255=opaque
++
++/sys/devices/platform/omapdss/manager? directory:
++display                               Destination display
++name
++alpha_blending_enabled                0=off, 1=on
++trans_key_enabled             0=off, 1=on
++trans_key_type                        gfx-destination, video-source
++trans_key_value                       transparency color key (RGB24)
++default_color                 default background color (RGB24)
++
++/sys/devices/platform/omapdss/display? directory:
++ctrl_name     Controller name
++mirror                0=off, 1=on
++update_mode   0=off, 1=auto, 2=manual
++enabled               0=off, 1=on
++name
++rotate                Rotation 0-3 for 0, 90, 180, 270 degrees
++timings               Display timings (pixclock,xres/hfp/hbp/hsw,yres/vfp/vbp/vsw)
++              When writing, two special timings are accepted for tv-out:
++              "pal" and "ntsc"
++panel_name
++tear_elim     Tearing elimination 0=off, 1=on
++
++There are also some debugfs files at <debugfs>/omapdss/ which show information
++about clocks and registers.
++
++Examples
++--------
++
++The following definitions have been made for the examples below:
++
++ovl0=/sys/devices/platform/omapdss/overlay0
++ovl1=/sys/devices/platform/omapdss/overlay1
++ovl2=/sys/devices/platform/omapdss/overlay2
++
++mgr0=/sys/devices/platform/omapdss/manager0
++mgr1=/sys/devices/platform/omapdss/manager1
++
++lcd=/sys/devices/platform/omapdss/display0
++dvi=/sys/devices/platform/omapdss/display1
++tv=/sys/devices/platform/omapdss/display2
++
++fb0=/sys/class/graphics/fb0
++fb1=/sys/class/graphics/fb1
++fb2=/sys/class/graphics/fb2
++
++Default setup on OMAP3 SDP
++--------------------------
++
++Here's the default setup on OMAP3 SDP board. All planes go to LCD. DVI
++and TV-out are not in use. The columns from left to right are:
++framebuffers, overlays, overlay managers, displays. Framebuffers are
++handled by omapfb, and the rest by the DSS.
++
++FB0 --- GFX  -\            DVI
++FB1 --- VID1 --+- LCD ---- LCD
++FB2 --- VID2 -/   TV ----- TV
++
++Example: Switch from LCD to DVI
++----------------------
++
++w=`cat $dvi/timings | cut -d "," -f 2 | cut -d "/" -f 1`
++h=`cat $dvi/timings | cut -d "," -f 3 | cut -d "/" -f 1`
++
++echo "0" > $lcd/enabled
++echo "" > $mgr0/display
++fbset -fb /dev/fb0 -xres $w -yres $h -vxres $w -vyres $h
++# at this point you have to switch the dvi/lcd dip-switch from the omap board
++echo "dvi" > $mgr0/display
++echo "1" > $dvi/enabled
++
++After this the configuration looks like:
++
++FB0 --- GFX  -\         -- DVI
++FB1 --- VID1 --+- LCD -/   LCD
++FB2 --- VID2 -/   TV ----- TV
++
++Example: Clone GFX overlay to LCD and TV
++-------------------------------
++
++w=`cat $tv/timings | cut -d "," -f 2 | cut -d "/" -f 1`
++h=`cat $tv/timings | cut -d "," -f 3 | cut -d "/" -f 1`
++
++echo "0" > $ovl0/enabled
++echo "0" > $ovl1/enabled
++
++echo "" > $fb1/overlays
++echo "0,1" > $fb0/overlays
++
++echo "$w,$h" > $ovl1/output_size
++echo "tv" > $ovl1/manager
++
++echo "1" > $ovl0/enabled
++echo "1" > $ovl1/enabled
++
++echo "1" > $tv/enabled
++
++After this the configuration looks like (only relevant parts shown):
++
++FB0 +-- GFX  ---- LCD ---- LCD
++     \- VID1 ---- TV  ---- TV
++
++Misc notes
++----------
++
++OMAP FB allocates the framebuffer memory using the OMAP VRAM allocator.
++
++Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
++of 86.5MHz (max possible), and with that you get 1280x1024@57 output from DVI.
++
++Rotation and mirroring currently only supports RGB565 and RGB8888 modes. VRFB
++does not support mirroring.
++
++VRFB rotation requires much more memory than non-rotated framebuffer, so you
++probably need to increase your vram setting before using VRFB rotation. Also,
++many applications may not work with VRFB if they do not pay attention to all
++framebuffer parameters.
++
++Kernel boot arguments
++---------------------
++
++vram=<size>
++      - Amount of total VRAM to preallocate. For example, "10M". omapfb
++        allocates memory for framebuffers from VRAM.
++
++omapfb.mode=<display>:<mode>[,...]
++      - Default video mode for specified displays. For example,
++        "dvi:800x400MR-24@60".  See drivers/video/modedb.c.
++        There are also two special modes: "pal" and "ntsc" that
++        can be used to tv out.
++
++omapfb.vram=<fbnum>:<size>[@<physaddr>][,...]
++      - VRAM allocated for a framebuffer. Normally omapfb allocates vram
++        depending on the display size. With this you can manually allocate
++        more or define the physical address of each framebuffer. For example,
++        "1:4M" to allocate 4M for fb1.
++
++omapfb.debug=<y|n>
++      - Enable debug printing. You have to have OMAPFB debug support enabled
++        in kernel config.
++
++omapfb.test=<y|n>
++      - Draw test pattern to framebuffer whenever framebuffer settings change.
++        You need to have OMAPFB debug support enabled in kernel config.
++
++omapfb.vrfb=<y|n>
++      - Use VRFB rotation for all framebuffers.
++
++omapfb.rotate=<angle>
++      - Default rotation applied to all framebuffers.
++        0 - 0 degree rotation
++        1 - 90 degree rotation
++        2 - 180 degree rotation
++        3 - 270 degree rotation
++
++omapfb.mirror=<y|n>
++      - Default mirror for all framebuffers. Only works with DMA rotation.
++
++omapdss.def_disp=<display>
++      - Name of default display, to which all overlays will be connected.
++        Common examples are "lcd" or "tv".
++
++omapdss.debug=<y|n>
++      - Enable debug printing. You have to have DSS debug support enabled in
++        kernel config.
++
++TODO
++----
++
++DSS locking
++
++Error checking
++- Lots of checks are missing or implemented just as BUG()
++
++System DMA update for DSI
++- Can be used for RGB16 and RGB24P modes. Probably not for RGB24U (how
++  to skip the empty byte?)
++
++OMAP1 support
++- Not sure if needed
++
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-2.6.31/dss2/0007-OMAP-DSS2-Display-Subsystem-Driver-core.patch b/recipes/linux/linux-omap-2.6.31/dss2/0007-OMAP-DSS2-Display-Subsystem-Driver-core.patch
new file mode 100644 (file)
index 0000000..8692200
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.31/dss2/0007-OMAP-DSS2-Display-Subsystem-Driver-core.patch
@@ -0,0 +1,2341 @@
+From 17254fca49c4f3a8897a6afb10af3416a691cb8a Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Fri, 7 Aug 2009 13:42:34 +0300
+Subject: [PATCH 07/18] OMAP: DSS2: Display Subsystem Driver core
+
+The core files of DSS2. DSS2 commits are split a bit artificially to
+make the individual commits smaller, and DSS2 doesn't compile properly
+without the rest of the core commits. This shouldn't be a problem, as no
+configuration uses DSS2 yet.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ arch/arm/plat-omap/include/mach/display.h |  540 +++++++++++++++++
+ drivers/video/omap2/Kconfig               |    2 +
+ drivers/video/omap2/Makefile              |    2 +
+ drivers/video/omap2/dss/Kconfig           |   89 +++
+ drivers/video/omap2/dss/Makefile          |    6 +
+ drivers/video/omap2/dss/core.c            |  917 +++++++++++++++++++++++++++++
+ drivers/video/omap2/dss/dss.c             |  347 +++++++++++
+ drivers/video/omap2/dss/dss.h             |  356 +++++++++++
+ 8 files changed, 2259 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/plat-omap/include/mach/display.h
+ create mode 100644 drivers/video/omap2/dss/Kconfig
+ create mode 100644 drivers/video/omap2/dss/Makefile
+ create mode 100644 drivers/video/omap2/dss/core.c
+ create mode 100644 drivers/video/omap2/dss/dss.c
+ create mode 100644 drivers/video/omap2/dss/dss.h
+
+diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
+new file mode 100644
+index 0000000..4c7422e
+--- /dev/null
++++ b/arch/arm/plat-omap/include/mach/display.h
+@@ -0,0 +1,540 @@
++/*
++ * linux/include/asm-arm/arch-omap/display.h
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef __ASM_ARCH_OMAP_DISPLAY_H
++#define __ASM_ARCH_OMAP_DISPLAY_H
++
++#include <linux/list.h>
++#include <linux/kobject.h>
++#include <linux/device.h>
++#include <asm/atomic.h>
++
++#define DISPC_IRQ_FRAMEDONE           (1 << 0)
++#define DISPC_IRQ_VSYNC                       (1 << 1)
++#define DISPC_IRQ_EVSYNC_EVEN         (1 << 2)
++#define DISPC_IRQ_EVSYNC_ODD          (1 << 3)
++#define DISPC_IRQ_ACBIAS_COUNT_STAT   (1 << 4)
++#define DISPC_IRQ_PROG_LINE_NUM               (1 << 5)
++#define DISPC_IRQ_GFX_FIFO_UNDERFLOW  (1 << 6)
++#define DISPC_IRQ_GFX_END_WIN         (1 << 7)
++#define DISPC_IRQ_PAL_GAMMA_MASK      (1 << 8)
++#define DISPC_IRQ_OCP_ERR             (1 << 9)
++#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
++#define DISPC_IRQ_VID1_END_WIN                (1 << 11)
++#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
++#define DISPC_IRQ_VID2_END_WIN                (1 << 13)
++#define DISPC_IRQ_SYNC_LOST           (1 << 14)
++#define DISPC_IRQ_SYNC_LOST_DIGIT     (1 << 15)
++#define DISPC_IRQ_WAKEUP              (1 << 16)
++
++struct omap_dss_device;
++struct omap_overlay_manager;
++
++enum omap_display_type {
++      OMAP_DISPLAY_TYPE_NONE          = 0,
++      OMAP_DISPLAY_TYPE_DPI           = 1 << 0,
++      OMAP_DISPLAY_TYPE_DBI           = 1 << 1,
++      OMAP_DISPLAY_TYPE_SDI           = 1 << 2,
++      OMAP_DISPLAY_TYPE_DSI           = 1 << 3,
++      OMAP_DISPLAY_TYPE_VENC          = 1 << 4,
++};
++
++enum omap_plane {
++      OMAP_DSS_GFX    = 0,
++      OMAP_DSS_VIDEO1 = 1,
++      OMAP_DSS_VIDEO2 = 2
++};
++
++enum omap_channel {
++      OMAP_DSS_CHANNEL_LCD    = 0,
++      OMAP_DSS_CHANNEL_DIGIT  = 1,
++};
++
++enum omap_color_mode {
++      OMAP_DSS_COLOR_CLUT1    = 1 << 0,  /* BITMAP 1 */
++      OMAP_DSS_COLOR_CLUT2    = 1 << 1,  /* BITMAP 2 */
++      OMAP_DSS_COLOR_CLUT4    = 1 << 2,  /* BITMAP 4 */
++      OMAP_DSS_COLOR_CLUT8    = 1 << 3,  /* BITMAP 8 */
++      OMAP_DSS_COLOR_RGB12U   = 1 << 4,  /* RGB12, 16-bit container */
++      OMAP_DSS_COLOR_ARGB16   = 1 << 5,  /* ARGB16 */
++      OMAP_DSS_COLOR_RGB16    = 1 << 6,  /* RGB16 */
++      OMAP_DSS_COLOR_RGB24U   = 1 << 7,  /* RGB24, 32-bit container */
++      OMAP_DSS_COLOR_RGB24P   = 1 << 8,  /* RGB24, 24-bit container */
++      OMAP_DSS_COLOR_YUV2     = 1 << 9,  /* YUV2 4:2:2 co-sited */
++      OMAP_DSS_COLOR_UYVY     = 1 << 10, /* UYVY 4:2:2 co-sited */
++      OMAP_DSS_COLOR_ARGB32   = 1 << 11, /* ARGB32 */
++      OMAP_DSS_COLOR_RGBA32   = 1 << 12, /* RGBA32 */
++      OMAP_DSS_COLOR_RGBX32   = 1 << 13, /* RGBx32 */
++
++      OMAP_DSS_COLOR_GFX_OMAP3 =
++              OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
++              OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
++              OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
++              OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
++              OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
++              OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
++
++      OMAP_DSS_COLOR_VID_OMAP3 =
++              OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
++              OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
++              OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
++              OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
++              OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
++};
++
++enum omap_lcd_display_type {
++      OMAP_DSS_LCD_DISPLAY_STN,
++      OMAP_DSS_LCD_DISPLAY_TFT,
++};
++
++enum omap_dss_load_mode {
++      OMAP_DSS_LOAD_CLUT_AND_FRAME    = 0,
++      OMAP_DSS_LOAD_CLUT_ONLY         = 1,
++      OMAP_DSS_LOAD_FRAME_ONLY        = 2,
++      OMAP_DSS_LOAD_CLUT_ONCE_FRAME   = 3,
++};
++
++enum omap_dss_trans_key_type {
++      OMAP_DSS_COLOR_KEY_GFX_DST = 0,
++      OMAP_DSS_COLOR_KEY_VID_SRC = 1,
++};
++
++enum omap_rfbi_te_mode {
++      OMAP_DSS_RFBI_TE_MODE_1 = 1,
++      OMAP_DSS_RFBI_TE_MODE_2 = 2,
++};
++
++enum omap_panel_config {
++      OMAP_DSS_LCD_IVS                = 1<<0,
++      OMAP_DSS_LCD_IHS                = 1<<1,
++      OMAP_DSS_LCD_IPC                = 1<<2,
++      OMAP_DSS_LCD_IEO                = 1<<3,
++      OMAP_DSS_LCD_RF                 = 1<<4,
++      OMAP_DSS_LCD_ONOFF              = 1<<5,
++
++      OMAP_DSS_LCD_TFT                = 1<<20,
++};
++
++enum omap_dss_venc_type {
++      OMAP_DSS_VENC_TYPE_COMPOSITE,
++      OMAP_DSS_VENC_TYPE_SVIDEO,
++};
++
++enum omap_display_caps {
++      OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
++};
++
++enum omap_dss_update_mode {
++      OMAP_DSS_UPDATE_DISABLED = 0,
++      OMAP_DSS_UPDATE_AUTO,
++      OMAP_DSS_UPDATE_MANUAL,
++};
++
++enum omap_dss_display_state {
++      OMAP_DSS_DISPLAY_DISABLED = 0,
++      OMAP_DSS_DISPLAY_ACTIVE,
++      OMAP_DSS_DISPLAY_SUSPENDED,
++};
++
++/* XXX perhaps this should be removed */
++enum omap_dss_overlay_managers {
++      OMAP_DSS_OVL_MGR_LCD,
++      OMAP_DSS_OVL_MGR_TV,
++};
++
++enum omap_dss_rotation_type {
++      OMAP_DSS_ROT_DMA = 0,
++      OMAP_DSS_ROT_VRFB = 1,
++};
++
++enum omap_overlay_caps {
++      OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
++      OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
++};
++
++enum omap_overlay_manager_caps {
++      OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
++};
++
++/* RFBI */
++
++struct rfbi_timings {
++      int cs_on_time;
++      int cs_off_time;
++      int we_on_time;
++      int we_off_time;
++      int re_on_time;
++      int re_off_time;
++      int we_cycle_time;
++      int re_cycle_time;
++      int cs_pulse_width;
++      int access_time;
++
++      int clk_div;
++
++      u32 tim[5];             /* set by rfbi_convert_timings() */
++
++      int converted;
++};
++
++void omap_rfbi_write_command(const void *buf, u32 len);
++void omap_rfbi_read_data(void *buf, u32 len);
++void omap_rfbi_write_data(const void *buf, u32 len);
++void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
++              u16 x, u16 y,
++              u16 w, u16 h);
++int omap_rfbi_enable_te(bool enable, unsigned line);
++int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
++                           unsigned hs_pulse_time, unsigned vs_pulse_time,
++                           int hs_pol_inv, int vs_pol_inv, int extif_div);
++
++/* DSI */
++void dsi_bus_lock(void);
++void dsi_bus_unlock(void);
++int dsi_vc_dcs_write(int channel, u8 *data, int len);
++int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
++int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
++int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
++int dsi_vc_send_null(int channel);
++int dsi_vc_send_bta_sync(int channel);
++
++/* Board specific data */
++struct omap_dss_board_info {
++      int (*get_last_off_on_transaction_id)(struct device *dev);
++      int num_devices;
++      struct omap_dss_device **devices;
++      struct omap_dss_device *default_device;
++};
++
++struct omap_video_timings {
++      /* Unit: pixels */
++      u16 x_res;
++      /* Unit: pixels */
++      u16 y_res;
++      /* Unit: KHz */
++      u32 pixel_clock;
++      /* Unit: pixel clocks */
++      u16 hsw;        /* Horizontal synchronization pulse width */
++      /* Unit: pixel clocks */
++      u16 hfp;        /* Horizontal front porch */
++      /* Unit: pixel clocks */
++      u16 hbp;        /* Horizontal back porch */
++      /* Unit: line clocks */
++      u16 vsw;        /* Vertical synchronization pulse width */
++      /* Unit: line clocks */
++      u16 vfp;        /* Vertical front porch */
++      /* Unit: line clocks */
++      u16 vbp;        /* Vertical back porch */
++};
++
++#ifdef CONFIG_OMAP2_DSS_VENC
++/* Hardcoded timings for tv modes. Venc only uses these to
++ * identify the mode, and does not actually use the configs
++ * itself. However, the configs should be something that
++ * a normal monitor can also show */
++const extern struct omap_video_timings omap_dss_pal_timings;
++const extern struct omap_video_timings omap_dss_ntsc_timings;
++#endif
++
++struct omap_overlay_info {
++      bool enabled;
++
++      u32 paddr;
++      void __iomem *vaddr;
++      u16 screen_width;
++      u16 width;
++      u16 height;
++      enum omap_color_mode color_mode;
++      u8 rotation;
++      enum omap_dss_rotation_type rotation_type;
++      bool mirror;
++
++      u16 pos_x;
++      u16 pos_y;
++      u16 out_width;  /* if 0, out_width == width */
++      u16 out_height; /* if 0, out_height == height */
++      u8 global_alpha;
++};
++
++struct omap_overlay {
++      struct kobject kobj;
++      struct list_head list;
++
++      /* static fields */
++      const char *name;
++      int id;
++      enum omap_color_mode supported_modes;
++      enum omap_overlay_caps caps;
++
++      /* dynamic fields */
++      struct omap_overlay_manager *manager;
++      struct omap_overlay_info info;
++
++      /* if true, info has been changed, but not applied() yet */
++      bool info_dirty;
++
++      int (*set_manager)(struct omap_overlay *ovl,
++              struct omap_overlay_manager *mgr);
++      int (*unset_manager)(struct omap_overlay *ovl);
++
++      int (*set_overlay_info)(struct omap_overlay *ovl,
++                      struct omap_overlay_info *info);
++      void (*get_overlay_info)(struct omap_overlay *ovl,
++                      struct omap_overlay_info *info);
++
++      int (*wait_for_go)(struct omap_overlay *ovl);
++};
++
++struct omap_overlay_manager_info {
++      u32 default_color;
++
++      enum omap_dss_trans_key_type trans_key_type;
++      u32 trans_key;
++      bool trans_enabled;
++
++      bool alpha_enabled;
++};
++
++struct omap_overlay_manager {
++      struct kobject kobj;
++      struct list_head list;
++
++      /* static fields */
++      const char *name;
++      int id;
++      enum omap_overlay_manager_caps caps;
++      int num_overlays;
++      struct omap_overlay **overlays;
++      enum omap_display_type supported_displays;
++
++      /* dynamic fields */
++      struct omap_dss_device *device;
++      struct omap_overlay_manager_info info;
++
++      bool device_changed;
++      /* if true, info has been changed but not applied() yet */
++      bool info_dirty;
++
++      int (*set_device)(struct omap_overlay_manager *mgr,
++              struct omap_dss_device *dssdev);
++      int (*unset_device)(struct omap_overlay_manager *mgr);
++
++      int (*set_manager_info)(struct omap_overlay_manager *mgr,
++                      struct omap_overlay_manager_info *info);
++      void (*get_manager_info)(struct omap_overlay_manager *mgr,
++                      struct omap_overlay_manager_info *info);
++
++      int (*apply)(struct omap_overlay_manager *mgr);
++      int (*wait_for_go)(struct omap_overlay_manager *mgr);
++};
++
++struct omap_dss_device {
++      struct device dev;
++
++      enum omap_display_type type;
++
++      union {
++              struct {
++                      u8 data_lines;
++              } dpi;
++
++              struct {
++                      u8 channel;
++                      u8 data_lines;
++              } rfbi;
++
++              struct {
++                      u8 datapairs;
++              } sdi;
++
++              struct {
++                      u8 clk_lane;
++                      u8 clk_pol;
++                      u8 data1_lane;
++                      u8 data1_pol;
++                      u8 data2_lane;
++                      u8 data2_pol;
++                      unsigned long lp_clk_hz;
++                      unsigned long ddr_clk_hz;
++
++                      bool ext_te;
++                      u8 ext_te_gpio;
++              } dsi;
++
++              struct {
++                      enum omap_dss_venc_type type;
++                      bool invert_polarity;
++              } venc;
++      } phy;
++
++      struct {
++              struct omap_video_timings timings;
++
++              int acbi;       /* ac-bias pin transitions per interrupt */
++              /* Unit: line clocks */
++              int acb;        /* ac-bias pin frequency */
++
++              enum omap_panel_config config;
++
++              u8 recommended_bpp;
++
++              struct omap_dss_device *ctrl;
++      } panel;
++
++      struct {
++              u8 pixel_size;
++              struct rfbi_timings rfbi_timings;
++              struct omap_dss_device *panel;
++      } ctrl;
++
++      int reset_gpio;
++
++      int max_backlight_level;
++
++      const char *name;
++
++      /* used to match device to driver */
++      const char *driver_name;
++
++      void *data;
++
++      struct omap_dss_driver *driver;
++
++      /* helper variable for driver suspend/resume */
++      bool activate_after_resume;
++
++      enum omap_display_caps caps;
++
++      struct omap_overlay_manager *manager;
++
++      enum omap_dss_display_state state;
++
++      int (*enable)(struct omap_dss_device *dssdev);
++      void (*disable)(struct omap_dss_device *dssdev);
++
++      int (*suspend)(struct omap_dss_device *dssdev);
++      int (*resume)(struct omap_dss_device *dssdev);
++
++      void (*get_resolution)(struct omap_dss_device *dssdev,
++                      u16 *xres, u16 *yres);
++      int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
++
++      int (*check_timings)(struct omap_dss_device *dssdev,
++                      struct omap_video_timings *timings);
++      void (*set_timings)(struct omap_dss_device *dssdev,
++                      struct omap_video_timings *timings);
++      void (*get_timings)(struct omap_dss_device *dssdev,
++                      struct omap_video_timings *timings);
++      int (*update)(struct omap_dss_device *dssdev,
++                             u16 x, u16 y, u16 w, u16 h);
++      int (*sync)(struct omap_dss_device *dssdev);
++      int (*wait_vsync)(struct omap_dss_device *dssdev);
++
++      int (*set_update_mode)(struct omap_dss_device *dssdev,
++                      enum omap_dss_update_mode);
++      enum omap_dss_update_mode (*get_update_mode)
++              (struct omap_dss_device *dssdev);
++
++      int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
++      int (*get_te)(struct omap_dss_device *dssdev);
++
++      u8 (*get_rotate)(struct omap_dss_device *dssdev);
++      int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
++
++      bool (*get_mirror)(struct omap_dss_device *dssdev);
++      int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
++
++      int (*run_test)(struct omap_dss_device *dssdev, int test);
++      int (*memory_read)(struct omap_dss_device *dssdev,
++                      void *buf, size_t size,
++                      u16 x, u16 y, u16 w, u16 h);
++
++      int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
++      u32 (*get_wss)(struct omap_dss_device *dssdev);
++
++      /* platform specific  */
++      int (*platform_enable)(struct omap_dss_device *dssdev);
++      void (*platform_disable)(struct omap_dss_device *dssdev);
++      int (*set_backlight)(struct omap_dss_device *dssdev, int level);
++      int (*get_backlight)(struct omap_dss_device *dssdev);
++};
++
++struct omap_dss_driver {
++      struct device_driver driver;
++
++      int (*probe)(struct omap_dss_device *);
++      void (*remove)(struct omap_dss_device *);
++
++      int (*enable)(struct omap_dss_device *display);
++      void (*disable)(struct omap_dss_device *display);
++      int (*suspend)(struct omap_dss_device *display);
++      int (*resume)(struct omap_dss_device *display);
++      int (*run_test)(struct omap_dss_device *display, int test);
++
++      void (*setup_update)(struct omap_dss_device *dssdev,
++                      u16 x, u16 y, u16 w, u16 h);
++
++      int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
++      int (*wait_for_te)(struct omap_dss_device *dssdev);
++
++      u8 (*get_rotate)(struct omap_dss_device *dssdev);
++      int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
++
++      bool (*get_mirror)(struct omap_dss_device *dssdev);
++      int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
++
++      int (*memory_read)(struct omap_dss_device *dssdev,
++                      void *buf, size_t size,
++                      u16 x, u16 y, u16 w, u16 h);
++};
++
++int omap_dss_register_driver(struct omap_dss_driver *);
++void omap_dss_unregister_driver(struct omap_dss_driver *);
++
++int omap_dss_register_device(struct omap_dss_device *);
++void omap_dss_unregister_device(struct omap_dss_device *);
++
++void omap_dss_get_device(struct omap_dss_device *dssdev);
++void omap_dss_put_device(struct omap_dss_device *dssdev);
++#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
++struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
++struct omap_dss_device *omap_dss_find_device(void *data,
++              int (*match)(struct omap_dss_device *dssdev, void *data));
++
++int omap_dss_start_device(struct omap_dss_device *dssdev);
++void omap_dss_stop_device(struct omap_dss_device *dssdev);
++
++int omap_dss_get_num_overlay_managers(void);
++struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
++
++int omap_dss_get_num_overlays(void);
++struct omap_overlay *omap_dss_get_overlay(int num);
++
++typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
++int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
++int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
++
++int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
++int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
++              unsigned long timeout);
++
++#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
++#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
++
++#endif
+diff --git a/drivers/video/omap2/Kconfig b/drivers/video/omap2/Kconfig
+index ac8b650..55b4c42 100644
+--- a/drivers/video/omap2/Kconfig
++++ b/drivers/video/omap2/Kconfig
+@@ -3,3 +3,5 @@ config OMAP2_VRAM
+ 
+ config OMAP2_VRFB
+       bool
++
++source "drivers/video/omap2/dss/Kconfig"
+diff --git a/drivers/video/omap2/Makefile b/drivers/video/omap2/Makefile
+index aa3751b..ee0644f 100644
+--- a/drivers/video/omap2/Makefile
++++ b/drivers/video/omap2/Makefile
+@@ -1,2 +1,4 @@
+ obj-$(CONFIG_OMAP2_VRAM) += vram.o
+ obj-$(CONFIG_OMAP2_VRFB) += vrfb.o
++
++obj-y += dss/
+diff --git a/drivers/video/omap2/dss/Kconfig b/drivers/video/omap2/dss/Kconfig
+new file mode 100644
+index 0000000..71d8dec
+--- /dev/null
++++ b/drivers/video/omap2/dss/Kconfig
+@@ -0,0 +1,89 @@
++menuconfig OMAP2_DSS
++        tristate "OMAP2/3 Display Subsystem support (EXPERIMENTAL)"
++        depends on ARCH_OMAP2 || ARCH_OMAP3
++        help
++          OMAP2/3 Display Subsystem support.
++
++if OMAP2_DSS
++
++config OMAP2_VRAM_SIZE
++      int "VRAM size (MB)"
++      range 0 32
++      default 0
++      help
++        The amount of SDRAM to reserve at boot time for video RAM use.
++        This VRAM will be used by omapfb and other drivers that need
++        large continuous RAM area for video use.
++
++        You can also set this with "vram=<bytes>" kernel argument, or
++        in the board file.
++
++config OMAP2_DSS_DEBUG_SUPPORT
++        bool "Debug support"
++      default y
++      help
++        This enables debug messages. You need to enable printing
++        with 'debug' module parameter.
++
++config OMAP2_DSS_RFBI
++      bool "RFBI support"
++        default n
++      help
++        MIPI DBI, or RFBI (Remote Framebuffer Interface), support.
++
++config OMAP2_DSS_VENC
++      bool "VENC support"
++        default y
++      help
++        OMAP Video Encoder support.
++
++config OMAP2_DSS_SDI
++      bool "SDI support"
++      depends on ARCH_OMAP3
++        default n
++      help
++        SDI (Serial Display Interface) support.
++
++config OMAP2_DSS_DSI
++      bool "DSI support"
++      depends on ARCH_OMAP3
++        default n
++      help
++        MIPI DSI support.
++
++config OMAP2_DSS_USE_DSI_PLL
++      bool "Use DSI PLL for PCLK (EXPERIMENTAL)"
++      default n
++      depends on OMAP2_DSS_DSI
++      help
++        Use DSI PLL to generate pixel clock.  Currently only for DPI output.
++        DSI PLL can be used to generate higher and more precise pixel clocks.
++
++config OMAP2_DSS_FAKE_VSYNC
++      bool "Fake VSYNC irq from manual update displays"
++      default n
++      help
++        If this is selected, DSI will generate a fake DISPC VSYNC interrupt
++        when DSI has sent a frame. This is only needed with DSI or RFBI
++        displays using manual mode, and you want VSYNC to, for example,
++        time animation.
++
++config OMAP2_DSS_MIN_FCK_PER_PCK
++      int "Minimum FCK/PCK ratio (for scaling)"
++      range 0 32
++      default 0
++      help
++        This can be used to adjust the minimum FCK/PCK ratio.
++
++        With this you can make sure that DISPC FCK is at least
++        n x PCK. Video plane scaling requires higher FCK than
++        normally.
++
++        If this is set to 0, there's no extra constraint on the
++        DISPC FCK. However, the FCK will at minimum be
++        2xPCK (if active matrix) or 3xPCK (if passive matrix).
++
++        Max FCK is 173MHz, so this doesn't work if your PCK
++        is very high.
++
++endif
+diff --git a/drivers/video/omap2/dss/Makefile b/drivers/video/omap2/dss/Makefile
+new file mode 100644
+index 0000000..980c72c
+--- /dev/null
++++ b/drivers/video/omap2/dss/Makefile
+@@ -0,0 +1,6 @@
++obj-$(CONFIG_OMAP2_DSS) += omapdss.o
++omapdss-y := core.o dss.o dispc.o dpi.o display.o manager.o overlay.o
++omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o
++omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o
++omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o
++omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o
+diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c
+new file mode 100644
+index 0000000..e8d430c
+--- /dev/null
++++ b/drivers/video/omap2/dss/core.c
+@@ -0,0 +1,917 @@
++/*
++ * linux/drivers/video/omap2/dss/core.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "CORE"
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/platform_device.h>
++#include <linux/seq_file.h>
++#include <linux/debugfs.h>
++#include <linux/io.h>
++#include <linux/device.h>
++
++#include <mach/display.h>
++#include <mach/clock.h>
++
++#include "dss.h"
++
++static struct {
++      struct platform_device *pdev;
++      int             ctx_id;
++
++      struct clk      *dss_ick;
++      struct clk      *dss1_fck;
++      struct clk      *dss2_fck;
++      struct clk      *dss_54m_fck;
++      struct clk      *dss_96m_fck;
++      unsigned        num_clks_enabled;
++} core;
++
++static void dss_clk_enable_all_no_ctx(void);
++static void dss_clk_disable_all_no_ctx(void);
++static void dss_clk_enable_no_ctx(enum dss_clock clks);
++static void dss_clk_disable_no_ctx(enum dss_clock clks);
++
++static char *def_disp_name;
++module_param_named(def_disp, def_disp_name, charp, 0);
++MODULE_PARM_DESC(def_disp_name, "default display name");
++
++#ifdef DEBUG
++unsigned int dss_debug;
++module_param_named(debug, dss_debug, bool, 0644);
++#endif
++
++/* CONTEXT */
++static int dss_get_ctx_id(void)
++{
++      struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
++      int r;
++
++      if (!pdata->get_last_off_on_transaction_id)
++              return 0;
++      r = pdata->get_last_off_on_transaction_id(&core.pdev->dev);
++      if (r < 0) {
++              dev_err(&core.pdev->dev, "getting transaction ID failed, "
++                              "will force context restore\n");
++              r = -1;
++      }
++      return r;
++}
++
++int dss_need_ctx_restore(void)
++{
++      int id = dss_get_ctx_id();
++
++      if (id < 0 || id != core.ctx_id) {
++              DSSDBG("ctx id %d -> id %d\n",
++                              core.ctx_id, id);
++              core.ctx_id = id;
++              return 1;
++      } else {
++              return 0;
++      }
++}
++
++static void save_all_ctx(void)
++{
++      DSSDBG("save context\n");
++
++      dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++      dss_save_context();
++      dispc_save_context();
++#ifdef CONFIG_OMAP2_DSS_DSI
++      dsi_save_context();
++#endif
++
++      dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
++}
++
++static void restore_all_ctx(void)
++{
++      DSSDBG("restore context\n");
++
++      dss_clk_enable_all_no_ctx();
++
++      dss_restore_context();
++      dispc_restore_context();
++#ifdef CONFIG_OMAP2_DSS_DSI
++      dsi_restore_context();
++#endif
++
++      dss_clk_disable_all_no_ctx();
++}
++
++/* CLOCKS */
++void dss_dump_clocks(struct seq_file *s)
++{
++      int i;
++      struct clk *clocks[5] = {
++              core.dss_ick,
++              core.dss1_fck,
++              core.dss2_fck,
++              core.dss_54m_fck,
++              core.dss_96m_fck
++      };
++
++      seq_printf(s, "- dss -\n");
++
++      seq_printf(s, "internal clk count\t%u\n", core.num_clks_enabled);
++
++      for (i = 0; i < 5; i++) {
++              if (!clocks[i])
++                      continue;
++              seq_printf(s, "%-15s\t%lu\t%d\n",
++                              clocks[i]->name,
++                              clk_get_rate(clocks[i]),
++                              clocks[i]->usecount);
++      }
++}
++
++static int dss_get_clock(struct clk **clock, const char *clk_name)
++{
++      struct clk *clk;
++
++      clk = clk_get(&core.pdev->dev, clk_name);
++
++      if (IS_ERR(clk)) {
++              DSSERR("can't get clock %s", clk_name);
++              return PTR_ERR(clk);
++      }
++
++      *clock = clk;
++
++      DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk));
++
++      return 0;
++}
++
++static int dss_get_clocks(void)
++{
++      int r;
++
++      core.dss_ick = NULL;
++      core.dss1_fck = NULL;
++      core.dss2_fck = NULL;
++      core.dss_54m_fck = NULL;
++      core.dss_96m_fck = NULL;
++
++      r = dss_get_clock(&core.dss_ick, "ick");
++      if (r)
++              goto err;
++
++      r = dss_get_clock(&core.dss1_fck, "dss1_fck");
++      if (r)
++              goto err;
++
++      r = dss_get_clock(&core.dss2_fck, "dss2_fck");
++      if (r)
++              goto err;
++
++      r = dss_get_clock(&core.dss_54m_fck, "tv_fck");
++      if (r)
++              goto err;
++
++      r = dss_get_clock(&core.dss_96m_fck, "video_fck");
++      if (r)
++              goto err;
++
++      return 0;
++
++err:
++      if (core.dss_ick)
++              clk_put(core.dss_ick);
++      if (core.dss1_fck)
++              clk_put(core.dss1_fck);
++      if (core.dss2_fck)
++              clk_put(core.dss2_fck);
++      if (core.dss_54m_fck)
++              clk_put(core.dss_54m_fck);
++      if (core.dss_96m_fck)
++              clk_put(core.dss_96m_fck);
++
++      return r;
++}
++
++static void dss_put_clocks(void)
++{
++      if (core.dss_96m_fck)
++              clk_put(core.dss_96m_fck);
++      clk_put(core.dss_54m_fck);
++      clk_put(core.dss1_fck);
++      clk_put(core.dss2_fck);
++      clk_put(core.dss_ick);
++}
++
++unsigned long dss_clk_get_rate(enum dss_clock clk)
++{
++      switch (clk) {
++      case DSS_CLK_ICK:
++              return clk_get_rate(core.dss_ick);
++      case DSS_CLK_FCK1:
++              return clk_get_rate(core.dss1_fck);
++      case DSS_CLK_FCK2:
++              return clk_get_rate(core.dss2_fck);
++      case DSS_CLK_54M:
++              return clk_get_rate(core.dss_54m_fck);
++      case DSS_CLK_96M:
++              return clk_get_rate(core.dss_96m_fck);
++      }
++
++      BUG();
++      return 0;
++}
++
++static unsigned count_clk_bits(enum dss_clock clks)
++{
++      unsigned num_clks = 0;
++
++      if (clks & DSS_CLK_ICK)
++              ++num_clks;
++      if (clks & DSS_CLK_FCK1)
++              ++num_clks;
++      if (clks & DSS_CLK_FCK2)
++              ++num_clks;
++      if (clks & DSS_CLK_54M)
++              ++num_clks;
++      if (clks & DSS_CLK_96M)
++              ++num_clks;
++
++      return num_clks;
++}
++
++static void dss_clk_enable_no_ctx(enum dss_clock clks)
++{
++      unsigned num_clks = count_clk_bits(clks);
++
++      if (clks & DSS_CLK_ICK)
++              clk_enable(core.dss_ick);
++      if (clks & DSS_CLK_FCK1)
++              clk_enable(core.dss1_fck);
++      if (clks & DSS_CLK_FCK2)
++              clk_enable(core.dss2_fck);
++      if (clks & DSS_CLK_54M)
++              clk_enable(core.dss_54m_fck);
++      if (clks & DSS_CLK_96M)
++              clk_enable(core.dss_96m_fck);
++
++      core.num_clks_enabled += num_clks;
++}
++
++void dss_clk_enable(enum dss_clock clks)
++{
++      dss_clk_enable_no_ctx(clks);
++
++      if (cpu_is_omap34xx() && dss_need_ctx_restore())
++              restore_all_ctx();
++}
++
++static void dss_clk_disable_no_ctx(enum dss_clock clks)
++{
++      unsigned num_clks = count_clk_bits(clks);
++
++      if (clks & DSS_CLK_ICK)
++              clk_disable(core.dss_ick);
++      if (clks & DSS_CLK_FCK1)
++              clk_disable(core.dss1_fck);
++      if (clks & DSS_CLK_FCK2)
++              clk_disable(core.dss2_fck);
++      if (clks & DSS_CLK_54M)
++              clk_disable(core.dss_54m_fck);
++      if (clks & DSS_CLK_96M)
++              clk_disable(core.dss_96m_fck);
++
++      core.num_clks_enabled -= num_clks;
++}
++
++void dss_clk_disable(enum dss_clock clks)
++{
++      if (cpu_is_omap34xx()) {
++              unsigned num_clks = count_clk_bits(clks);
++
++              BUG_ON(core.num_clks_enabled < num_clks);
++
++              if (core.num_clks_enabled == num_clks)
++                      save_all_ctx();
++      }
++
++      dss_clk_disable_no_ctx(clks);
++}
++
++static void dss_clk_enable_all_no_ctx(void)
++{
++      enum dss_clock clks;
++
++      clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
++      if (cpu_is_omap34xx())
++              clks |= DSS_CLK_96M;
++      dss_clk_enable_no_ctx(clks);
++}
++
++static void dss_clk_disable_all_no_ctx(void)
++{
++      enum dss_clock clks;
++
++      clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
++      if (cpu_is_omap34xx())
++              clks |= DSS_CLK_96M;
++      dss_clk_disable_no_ctx(clks);
++}
++
++static void dss_clk_disable_all(void)
++{
++      enum dss_clock clks;
++
++      clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
++      if (cpu_is_omap34xx())
++              clks |= DSS_CLK_96M;
++      dss_clk_disable(clks);
++}
++
++/* DEBUGFS */
++#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
++static void dss_debug_dump_clocks(struct seq_file *s)
++{
++      dss_dump_clocks(s);
++      dispc_dump_clocks(s);
++#ifdef CONFIG_OMAP2_DSS_DSI
++      dsi_dump_clocks(s);
++#endif
++}
++
++static int dss_debug_show(struct seq_file *s, void *unused)
++{
++      void (*func)(struct seq_file *) = s->private;
++      func(s);
++      return 0;
++}
++
++static int dss_debug_open(struct inode *inode, struct file *file)
++{
++      return single_open(file, dss_debug_show, inode->i_private);
++}
++
++static const struct file_operations dss_debug_fops = {
++      .open           = dss_debug_open,
++      .read           = seq_read,
++      .llseek         = seq_lseek,
++      .release        = single_release,
++};
++
++static struct dentry *dss_debugfs_dir;
++
++static int dss_initialize_debugfs(void)
++{
++      dss_debugfs_dir = debugfs_create_dir("omapdss", NULL);
++      if (IS_ERR(dss_debugfs_dir)) {
++              int err = PTR_ERR(dss_debugfs_dir);
++              dss_debugfs_dir = NULL;
++              return err;
++      }
++
++      debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir,
++                      &dss_debug_dump_clocks, &dss_debug_fops);
++
++      debugfs_create_file("dss", S_IRUGO, dss_debugfs_dir,
++                      &dss_dump_regs, &dss_debug_fops);
++      debugfs_create_file("dispc", S_IRUGO, dss_debugfs_dir,
++                      &dispc_dump_regs, &dss_debug_fops);
++#ifdef CONFIG_OMAP2_DSS_RFBI
++      debugfs_create_file("rfbi", S_IRUGO, dss_debugfs_dir,
++                      &rfbi_dump_regs, &dss_debug_fops);
++#endif
++#ifdef CONFIG_OMAP2_DSS_DSI
++      debugfs_create_file("dsi", S_IRUGO, dss_debugfs_dir,
++                      &dsi_dump_regs, &dss_debug_fops);
++#endif
++#ifdef CONFIG_OMAP2_DSS_VENC
++      debugfs_create_file("venc", S_IRUGO, dss_debugfs_dir,
++                      &venc_dump_regs, &dss_debug_fops);
++#endif
++      return 0;
++}
++
++static void dss_uninitialize_debugfs(void)
++{
++      if (dss_debugfs_dir)
++              debugfs_remove_recursive(dss_debugfs_dir);
++}
++#endif /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */
++
++/* PLATFORM DEVICE */
++static int omap_dss_probe(struct platform_device *pdev)
++{
++      struct omap_dss_board_info *pdata = pdev->dev.platform_data;
++      int skip_init = 0;
++      int r;
++      int i;
++
++      core.pdev = pdev;
++
++      dss_init_overlay_managers(pdev);
++      dss_init_overlays(pdev);
++
++      r = dss_get_clocks();
++      if (r)
++              goto fail0;
++
++      dss_clk_enable_all_no_ctx();
++
++      core.ctx_id = dss_get_ctx_id();
++      DSSDBG("initial ctx id %u\n", core.ctx_id);
++
++#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
++      /* DISPC_CONTROL */
++      if (omap_readl(0x48050440) & 1) /* LCD enabled? */
++              skip_init = 1;
++#endif
++
++      r = dss_init(skip_init);
++      if (r) {
++              DSSERR("Failed to initialize DSS\n");
++              goto fail0;
++      }
++
++#ifdef CONFIG_OMAP2_DSS_RFBI
++      r = rfbi_init();
++      if (r) {
++              DSSERR("Failed to initialize rfbi\n");
++              goto fail0;
++      }
++#endif
++
++      r = dpi_init();
++      if (r) {
++              DSSERR("Failed to initialize dpi\n");
++              goto fail0;
++      }
++
++      r = dispc_init();
++      if (r) {
++              DSSERR("Failed to initialize dispc\n");
++              goto fail0;
++      }
++#ifdef CONFIG_OMAP2_DSS_VENC
++      r = venc_init(pdev);
++      if (r) {
++              DSSERR("Failed to initialize venc\n");
++              goto fail0;
++      }
++#endif
++      if (cpu_is_omap34xx()) {
++#ifdef CONFIG_OMAP2_DSS_SDI
++              r = sdi_init(skip_init);
++              if (r) {
++                      DSSERR("Failed to initialize SDI\n");
++                      goto fail0;
++              }
++#endif
++#ifdef CONFIG_OMAP2_DSS_DSI
++              r = dsi_init(pdev);
++              if (r) {
++                      DSSERR("Failed to initialize DSI\n");
++                      goto fail0;
++              }
++#endif
++      }
++
++#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
++      r = dss_initialize_debugfs();
++      if (r)
++              goto fail0;
++#endif
++
++      for (i = 0; i < pdata->num_devices; ++i) {
++              struct omap_dss_device *dssdev = pdata->devices[i];
++
++              r = omap_dss_register_device(dssdev);
++              if (r)
++                      DSSERR("device reg failed %d\n", i);
++
++              if (def_disp_name && strcmp(def_disp_name, dssdev->name) == 0)
++                      pdata->default_device = dssdev;
++      }
++
++      dss_clk_disable_all();
++
++      return 0;
++
++      /* XXX fail correctly */
++fail0:
++      return r;
++}
++
++static int omap_dss_remove(struct platform_device *pdev)
++{
++      struct omap_dss_board_info *pdata = pdev->dev.platform_data;
++      int i;
++      int c;
++
++#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
++      dss_uninitialize_debugfs();
++#endif
++
++#ifdef CONFIG_OMAP2_DSS_VENC
++      venc_exit();
++#endif
++      dispc_exit();
++      dpi_exit();
++#ifdef CONFIG_OMAP2_DSS_RFBI
++      rfbi_exit();
++#endif
++      if (cpu_is_omap34xx()) {
++#ifdef CONFIG_OMAP2_DSS_DSI
++              dsi_exit();
++#endif
++#ifdef CONFIG_OMAP2_DSS_SDI
++              sdi_exit();
++#endif
++      }
++
++      dss_exit();
++
++      /* these should be removed at some point */
++      c = core.dss_ick->usecount;
++      if (c > 0) {
++              DSSERR("warning: dss_ick usecount %d, disabling\n", c);
++              while (c-- > 0)
++                      clk_disable(core.dss_ick);
++      }
++
++      c = core.dss1_fck->usecount;
++      if (c > 0) {
++              DSSERR("warning: dss1_fck usecount %d, disabling\n", c);
++              while (c-- > 0)
++                      clk_disable(core.dss1_fck);
++      }
++
++      c = core.dss2_fck->usecount;
++      if (c > 0) {
++              DSSERR("warning: dss2_fck usecount %d, disabling\n", c);
++              while (c-- > 0)
++                      clk_disable(core.dss2_fck);
++      }
++
++      c = core.dss_54m_fck->usecount;
++      if (c > 0) {
++              DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c);
++              while (c-- > 0)
++                      clk_disable(core.dss_54m_fck);
++      }
++
++      if (core.dss_96m_fck) {
++              c = core.dss_96m_fck->usecount;
++              if (c > 0) {
++                      DSSERR("warning: dss_96m_fck usecount %d, disabling\n",
++                                      c);
++                      while (c-- > 0)
++                              clk_disable(core.dss_96m_fck);
++              }
++      }
++
++      dss_put_clocks();
++
++      dss_uninit_overlays(pdev);
++      dss_uninit_overlay_managers(pdev);
++
++      for (i = 0; i < pdata->num_devices; ++i)
++              omap_dss_unregister_device(pdata->devices[i]);
++
++      return 0;
++}
++
++static void omap_dss_shutdown(struct platform_device *pdev)
++{
++      DSSDBG("shutdown\n");
++}
++
++static int omap_dss_suspend(struct platform_device *pdev, pm_message_t state)
++{
++      DSSDBG("suspend %d\n", state.event);
++
++      return dss_suspend_all_devices();
++}
++
++static int omap_dss_resume(struct platform_device *pdev)
++{
++      DSSDBG("resume\n");
++
++      return dss_resume_all_devices();
++}
++
++static struct platform_driver omap_dss_driver = {
++      .probe          = omap_dss_probe,
++      .remove         = omap_dss_remove,
++      .shutdown       = omap_dss_shutdown,
++      .suspend        = omap_dss_suspend,
++      .resume         = omap_dss_resume,
++      .driver         = {
++              .name   = "omapdss",
++              .owner  = THIS_MODULE,
++      },
++};
++
++/* BUS */
++static int dss_bus_match(struct device *dev, struct device_driver *driver)
++{
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++
++      DSSDBG("bus_match. dev %s/%s, drv %s\n",
++                      dev_name(dev), dssdev->driver_name, driver->name);
++
++      return strcmp(dssdev->driver_name, driver->name) == 0;
++}
++
++static ssize_t device_name_show(struct device *dev,
++              struct device_attribute *attr, char *buf)
++{
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++      return snprintf(buf, PAGE_SIZE, "%s\n",
++                      dssdev->name ?
++                      dssdev->name : "");
++}
++
++static struct device_attribute default_dev_attrs[] = {
++      __ATTR(name, S_IRUGO, device_name_show, NULL),
++      __ATTR_NULL,
++};
++
++static ssize_t driver_name_show(struct device_driver *drv, char *buf)
++{
++      struct omap_dss_driver *dssdrv = to_dss_driver(drv);
++      return snprintf(buf, PAGE_SIZE, "%s\n",
++                      dssdrv->driver.name ?
++                      dssdrv->driver.name : "");
++}
++static struct driver_attribute default_drv_attrs[] = {
++      __ATTR(name, S_IRUGO, driver_name_show, NULL),
++      __ATTR_NULL,
++};
++
++static struct bus_type dss_bus_type = {
++      .name = "omapdss",
++      .match = dss_bus_match,
++      .dev_attrs = default_dev_attrs,
++      .drv_attrs = default_drv_attrs,
++};
++
++static void dss_bus_release(struct device *dev)
++{
++      DSSDBG("bus_release\n");
++}
++
++static struct device dss_bus = {
++      .release = dss_bus_release,
++};
++
++struct bus_type *dss_get_bus(void)
++{
++      return &dss_bus_type;
++}
++
++/* DRIVER */
++static int dss_driver_probe(struct device *dev)
++{
++      int r;
++      struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver);
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++      struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
++      bool force;
++
++      DSSDBG("driver_probe: dev %s/%s, drv %s\n",
++                              dev_name(dev), dssdev->driver_name,
++                              dssdrv->driver.name);
++
++      dss_init_device(core.pdev, dssdev);
++
++      /* skip this if the device is behind a ctrl */
++      if (!dssdev->panel.ctrl) {
++              force = pdata->default_device == dssdev;
++              dss_recheck_connections(dssdev, force);
++      }
++
++      r = dssdrv->probe(dssdev);
++
++      if (r) {
++              DSSERR("driver probe failed: %d\n", r);
++              return r;
++      }
++
++      DSSDBG("probe done for device %s\n", dev_name(dev));
++
++      dssdev->driver = dssdrv;
++
++      return 0;
++}
++
++static int dss_driver_remove(struct device *dev)
++{
++      struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver);
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++
++      DSSDBG("driver_remove: dev %s/%s\n", dev_name(dev),
++                      dssdev->driver_name);
++
++      dssdrv->remove(dssdev);
++
++      dss_uninit_device(core.pdev, dssdev);
++
++      dssdev->driver = NULL;
++
++      return 0;
++}
++
++int omap_dss_register_driver(struct omap_dss_driver *dssdriver)
++{
++      dssdriver->driver.bus = &dss_bus_type;
++      dssdriver->driver.probe = dss_driver_probe;
++      dssdriver->driver.remove = dss_driver_remove;
++      return driver_register(&dssdriver->driver);
++}
++EXPORT_SYMBOL(omap_dss_register_driver);
++
++void omap_dss_unregister_driver(struct omap_dss_driver *dssdriver)
++{
++      driver_unregister(&dssdriver->driver);
++}
++EXPORT_SYMBOL(omap_dss_unregister_driver);
++
++/* DEVICE */
++static void reset_device(struct device *dev, int check)
++{
++      u8 *dev_p = (u8 *)dev;
++      u8 *dev_end = dev_p + sizeof(*dev);
++      void *saved_pdata;
++
++      saved_pdata = dev->platform_data;
++      if (check) {
++              /*
++               * Check if there is any other setting than platform_data
++               * in struct device; warn that these will be reset by our
++               * init.
++               */
++              dev->platform_data = NULL;
++              while (dev_p < dev_end) {
++                      if (*dev_p) {
++                              WARN("%s: struct device fields will be "
++                                              "discarded\n",
++                                   __func__);
++                              break;
++                      }
++                      dev_p++;
++              }
++      }
++      memset(dev, 0, sizeof(*dev));
++      dev->platform_data = saved_pdata;
++}
++
++
++static void omap_dss_dev_release(struct device *dev)
++{
++      reset_device(dev, 0);
++}
++
++int omap_dss_register_device(struct omap_dss_device *dssdev)
++{
++      static int dev_num;
++      static int panel_num;
++      int r;
++
++      WARN_ON(!dssdev->driver_name);
++
++      reset_device(&dssdev->dev, 1);
++      dssdev->dev.bus = &dss_bus_type;
++      dssdev->dev.parent = &dss_bus;
++      dssdev->dev.release = omap_dss_dev_release;
++      dev_set_name(&dssdev->dev, "display%d", dev_num++);
++      r = device_register(&dssdev->dev);
++      if (r)
++              return r;
++
++      if (dssdev->ctrl.panel) {
++              struct omap_dss_device *panel = dssdev->ctrl.panel;
++
++              panel->panel.ctrl = dssdev;
++
++              reset_device(&panel->dev, 1);
++              panel->dev.bus = &dss_bus_type;
++              panel->dev.parent = &dssdev->dev;
++              panel->dev.release = omap_dss_dev_release;
++              dev_set_name(&panel->dev, "panel%d", panel_num++);
++              r = device_register(&panel->dev);
++              if (r)
++                      return r;
++      }
++
++      return 0;
++}
++
++void omap_dss_unregister_device(struct omap_dss_device *dssdev)
++{
++      device_unregister(&dssdev->dev);
++
++      if (dssdev->ctrl.panel) {
++              struct omap_dss_device *panel = dssdev->ctrl.panel;
++              device_unregister(&panel->dev);
++      }
++}
++
++/* BUS */
++static int omap_dss_bus_register(void)
++{
++      int r;
++
++      r = bus_register(&dss_bus_type);
++      if (r) {
++              DSSERR("bus register failed\n");
++              return r;
++      }
++
++      dev_set_name(&dss_bus, "omapdss");
++      r = device_register(&dss_bus);
++      if (r) {
++              DSSERR("bus driver register failed\n");
++              bus_unregister(&dss_bus_type);
++              return r;
++      }
++
++      return 0;
++}
++
++/* INIT */
++
++#ifdef CONFIG_OMAP2_DSS_MODULE
++static void omap_dss_bus_unregister(void)
++{
++      device_unregister(&dss_bus);
++
++      bus_unregister(&dss_bus_type);
++}
++
++static int __init omap_dss_init(void)
++{
++      int r;
++
++      r = omap_dss_bus_register();
++      if (r)
++              return r;
++
++      r = platform_driver_register(&omap_dss_driver);
++      if (r) {
++              omap_dss_bus_unregister();
++              return r;
++      }
++
++      return 0;
++}
++
++static void __exit omap_dss_exit(void)
++{
++      platform_driver_unregister(&omap_dss_driver);
++
++      omap_dss_bus_unregister();
++}
++
++module_init(omap_dss_init);
++module_exit(omap_dss_exit);
++#else
++static int __init omap_dss_init(void)
++{
++      return omap_dss_bus_register();
++}
++
++static int __init omap_dss_init2(void)
++{
++      return platform_driver_register(&omap_dss_driver);
++}
++
++core_initcall(omap_dss_init);
++device_initcall(omap_dss_init2);
++#endif
++
++MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
++MODULE_DESCRIPTION("OMAP2/3 Display Subsystem");
++MODULE_LICENSE("GPL v2");
++
+diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
+new file mode 100644
+index 0000000..aab9758
+--- /dev/null
++++ b/drivers/video/omap2/dss/dss.c
+@@ -0,0 +1,347 @@
++/*
++ * linux/drivers/video/omap2/dss/dss.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "DSS"
++
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/err.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/seq_file.h>
++
++#include <mach/display.h>
++#include "dss.h"
++
++#define DSS_BASE                      0x48050000
++
++#define DSS_SZ_REGS                   SZ_512
++
++struct dss_reg {
++      u16 idx;
++};
++
++#define DSS_REG(idx)                  ((const struct dss_reg) { idx })
++
++#define DSS_REVISION                  DSS_REG(0x0000)
++#define DSS_SYSCONFIG                 DSS_REG(0x0010)
++#define DSS_SYSSTATUS                 DSS_REG(0x0014)
++#define DSS_IRQSTATUS                 DSS_REG(0x0018)
++#define DSS_CONTROL                   DSS_REG(0x0040)
++#define DSS_SDI_CONTROL                       DSS_REG(0x0044)
++#define DSS_PLL_CONTROL                       DSS_REG(0x0048)
++#define DSS_SDI_STATUS                        DSS_REG(0x005C)
++
++#define REG_GET(idx, start, end) \
++      FLD_GET(dss_read_reg(idx), start, end)
++
++#define REG_FLD_MOD(idx, val, start, end) \
++      dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
++
++static struct {
++      void __iomem    *base;
++
++      u32             ctx[DSS_SZ_REGS / sizeof(u32)];
++} dss;
++
++static int _omap_dss_wait_reset(void);
++
++static inline void dss_write_reg(const struct dss_reg idx, u32 val)
++{
++      __raw_writel(val, dss.base + idx.idx);
++}
++
++static inline u32 dss_read_reg(const struct dss_reg idx)
++{
++      return __raw_readl(dss.base + idx.idx);
++}
++
++#define SR(reg) \
++      dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
++#define RR(reg) \
++      dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
++
++void dss_save_context(void)
++{
++      if (cpu_is_omap24xx())
++              return;
++
++      SR(SYSCONFIG);
++      SR(CONTROL);
++
++#ifdef CONFIG_OMAP2_DSS_SDI
++      SR(SDI_CONTROL);
++      SR(PLL_CONTROL);
++#endif
++}
++
++void dss_restore_context(void)
++{
++      if (_omap_dss_wait_reset())
++              DSSERR("DSS not coming out of reset after sleep\n");
++
++      RR(SYSCONFIG);
++      RR(CONTROL);
++
++#ifdef CONFIG_OMAP2_DSS_SDI
++      RR(SDI_CONTROL);
++      RR(PLL_CONTROL);
++#endif
++}
++
++#undef SR
++#undef RR
++
++void dss_sdi_init(u8 datapairs)
++{
++      u32 l;
++
++      BUG_ON(datapairs > 3 || datapairs < 1);
++
++      l = dss_read_reg(DSS_SDI_CONTROL);
++      l = FLD_MOD(l, 0xf, 19, 15);            /* SDI_PDIV */
++      l = FLD_MOD(l, datapairs-1, 3, 2);      /* SDI_PRSEL */
++      l = FLD_MOD(l, 2, 1, 0);                /* SDI_BWSEL */
++      dss_write_reg(DSS_SDI_CONTROL, l);
++
++      l = dss_read_reg(DSS_PLL_CONTROL);
++      l = FLD_MOD(l, 0x7, 25, 22);    /* SDI_PLL_FREQSEL */
++      l = FLD_MOD(l, 0xb, 16, 11);    /* SDI_PLL_REGN */
++      l = FLD_MOD(l, 0xb4, 10, 1);    /* SDI_PLL_REGM */
++      dss_write_reg(DSS_PLL_CONTROL, l);
++}
++
++void dss_sdi_enable(void)
++{
++      dispc_pck_free_enable(1);
++
++      /* Reset SDI PLL */
++      REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
++      udelay(1);      /* wait 2x PCLK */
++
++      /* Lock SDI PLL */
++      REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
++
++      /* Waiting for PLL lock request to complete */
++      while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6))
++              ;
++
++      /* Clearing PLL_GO bit */
++      REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
++
++      /* Waiting for PLL to lock */
++      while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5)))
++              ;
++
++      dispc_lcd_enable_signal(1);
++
++      /* Waiting for SDI reset to complete */
++      while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2)))
++              ;
++}
++
++void dss_sdi_disable(void)
++{
++      dispc_lcd_enable_signal(0);
++
++      dispc_pck_free_enable(0);
++
++      /* Reset SDI PLL */
++      REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
++}
++
++void dss_dump_regs(struct seq_file *s)
++{
++#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
++
++      dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++      DUMPREG(DSS_REVISION);
++      DUMPREG(DSS_SYSCONFIG);
++      DUMPREG(DSS_SYSSTATUS);
++      DUMPREG(DSS_IRQSTATUS);
++      DUMPREG(DSS_CONTROL);
++      DUMPREG(DSS_SDI_CONTROL);
++      DUMPREG(DSS_PLL_CONTROL);
++      DUMPREG(DSS_SDI_STATUS);
++
++      dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++#undef DUMPREG
++}
++
++void dss_select_clk_source(bool dsi, bool dispc)
++{
++      u32 r;
++      r = dss_read_reg(DSS_CONTROL);
++      r = FLD_MOD(r, dsi, 1, 1);      /* DSI_CLK_SWITCH */
++      r = FLD_MOD(r, dispc, 0, 0);    /* DISPC_CLK_SWITCH */
++      dss_write_reg(DSS_CONTROL, r);
++}
++
++int dss_get_dsi_clk_source(void)
++{
++      return FLD_GET(dss_read_reg(DSS_CONTROL), 1, 1);
++}
++
++int dss_get_dispc_clk_source(void)
++{
++      return FLD_GET(dss_read_reg(DSS_CONTROL), 0, 0);
++}
++
++static irqreturn_t dss_irq_handler_omap2(int irq, void *arg)
++{
++      dispc_irq_handler();
++
++      return IRQ_HANDLED;
++}
++
++static irqreturn_t dss_irq_handler_omap3(int irq, void *arg)
++{
++      u32 irqstatus;
++
++      irqstatus = dss_read_reg(DSS_IRQSTATUS);
++
++      if (irqstatus & (1<<0)) /* DISPC_IRQ */
++              dispc_irq_handler();
++#ifdef CONFIG_OMAP2_DSS_DSI
++      if (irqstatus & (1<<1)) /* DSI_IRQ */
++              dsi_irq_handler();
++#endif
++
++      return IRQ_HANDLED;
++}
++
++static int _omap_dss_wait_reset(void)
++{
++      unsigned timeout = 1000;
++
++      while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) {
++              udelay(1);
++              if (!--timeout) {
++                      DSSERR("soft reset failed\n");
++                      return -ENODEV;
++              }
++      }
++
++      return 0;
++}
++
++static int _omap_dss_reset(void)
++{
++      /* Soft reset */
++      REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1);
++      return _omap_dss_wait_reset();
++}
++
++void dss_set_venc_output(enum omap_dss_venc_type type)
++{
++      int l = 0;
++
++      if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
++              l = 0;
++      else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
++              l = 1;
++      else
++              BUG();
++
++      /* venc out selection. 0 = comp, 1 = svideo */
++      REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
++}
++
++void dss_set_dac_pwrdn_bgz(bool enable)
++{
++      REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
++}
++
++int dss_init(bool skip_init)
++{
++      int r;
++      u32 rev;
++
++      dss.base = ioremap(DSS_BASE, DSS_SZ_REGS);
++      if (!dss.base) {
++              DSSERR("can't ioremap DSS\n");
++              r = -ENOMEM;
++              goto fail0;
++      }
++
++      if (!skip_init) {
++              /* disable LCD and DIGIT output. This seems to fix the synclost
++               * problem that we get, if the bootloader starts the DSS and
++               * the kernel resets it */
++              omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440);
++
++              /* We need to wait here a bit, otherwise we sometimes start to
++               * get synclost errors, and after that only power cycle will
++               * restore DSS functionality. I have no idea why this happens.
++               * And we have to wait _before_ resetting the DSS, but after
++               * enabling clocks.
++               */
++              msleep(50);
++
++              _omap_dss_reset();
++      }
++
++      /* autoidle */
++      REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
++
++      /* Select DPLL */
++      REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
++
++#ifdef CONFIG_OMAP2_DSS_VENC
++      REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);      /* venc dac demen */
++      REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);      /* venc clock 4x enable */
++      REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);      /* venc clock mode = normal */
++#endif
++
++      r = request_irq(INT_24XX_DSS_IRQ,
++                      cpu_is_omap24xx()
++                      ? dss_irq_handler_omap2
++                      : dss_irq_handler_omap3,
++                      0, "OMAP DSS", NULL);
++
++      if (r < 0) {
++              DSSERR("omap2 dss: request_irq failed\n");
++              goto fail1;
++      }
++
++      dss_save_context();
++
++      rev = dss_read_reg(DSS_REVISION);
++      printk(KERN_INFO "OMAP DSS rev %d.%d\n",
++                      FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
++
++      return 0;
++
++fail1:
++      iounmap(dss.base);
++fail0:
++      return r;
++}
++
++void dss_exit(void)
++{
++      free_irq(INT_24XX_DSS_IRQ, NULL);
++
++      iounmap(dss.base);
++}
++
+diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
+new file mode 100644
+index 0000000..50f7f5f
+--- /dev/null
++++ b/drivers/video/omap2/dss/dss.h
+@@ -0,0 +1,356 @@
++/*
++ * linux/drivers/video/omap2/dss/dss.h
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef __OMAP2_DSS_H
++#define __OMAP2_DSS_H
++
++#ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
++#define DEBUG
++#endif
++
++#ifdef DEBUG
++extern unsigned int dss_debug;
++#ifdef DSS_SUBSYS_NAME
++#define DSSDBG(format, ...) \
++      if (dss_debug) \
++              printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \
++              ## __VA_ARGS__)
++#else
++#define DSSDBG(format, ...) \
++      if (dss_debug) \
++              printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__)
++#endif
++
++#ifdef DSS_SUBSYS_NAME
++#define DSSDBGF(format, ...) \
++      if (dss_debug) \
++              printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \
++                              ": %s(" format ")\n", \
++                              __func__, \
++                              ## __VA_ARGS__)
++#else
++#define DSSDBGF(format, ...) \
++      if (dss_debug) \
++              printk(KERN_DEBUG "omapdss: " \
++                              ": %s(" format ")\n", \
++                              __func__, \
++                              ## __VA_ARGS__)
++#endif
++
++#else /* DEBUG */
++#define DSSDBG(format, ...)
++#define DSSDBGF(format, ...)
++#endif
++
++
++#ifdef DSS_SUBSYS_NAME
++#define DSSERR(format, ...) \
++      printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
++      ## __VA_ARGS__)
++#else
++#define DSSERR(format, ...) \
++      printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
++#endif
++
++#ifdef DSS_SUBSYS_NAME
++#define DSSINFO(format, ...) \
++      printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
++      ## __VA_ARGS__)
++#else
++#define DSSINFO(format, ...) \
++      printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
++#endif
++
++#ifdef DSS_SUBSYS_NAME
++#define DSSWARN(format, ...) \
++      printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
++      ## __VA_ARGS__)
++#else
++#define DSSWARN(format, ...) \
++      printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
++#endif
++
++/* OMAP TRM gives bitfields as start:end, where start is the higher bit
++   number. For example 7:0 */
++#define FLD_MASK(start, end)  (((1 << (start - end + 1)) - 1) << (end))
++#define FLD_VAL(val, start, end) (((val) << end) & FLD_MASK(start, end))
++#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
++#define FLD_MOD(orig, val, start, end) \
++      (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
++
++#define DISPC_MAX_FCK 173000000
++
++enum omap_burst_size {
++      OMAP_DSS_BURST_4x32 = 0,
++      OMAP_DSS_BURST_8x32 = 1,
++      OMAP_DSS_BURST_16x32 = 2,
++};
++
++enum omap_parallel_interface_mode {
++      OMAP_DSS_PARALLELMODE_BYPASS,           /* MIPI DPI */
++      OMAP_DSS_PARALLELMODE_RFBI,             /* MIPI DBI */
++      OMAP_DSS_PARALLELMODE_DSI,
++};
++
++enum dss_clock {
++      DSS_CLK_ICK     = 1 << 0,
++      DSS_CLK_FCK1    = 1 << 1,
++      DSS_CLK_FCK2    = 1 << 2,
++      DSS_CLK_54M     = 1 << 3,
++      DSS_CLK_96M     = 1 << 4,
++};
++
++struct dispc_clock_info {
++      /* rates that we get with dividers below */
++      unsigned long fck;
++      unsigned long lck;
++      unsigned long pck;
++
++      /* dividers */
++      u16 fck_div;
++      u16 lck_div;
++      u16 pck_div;
++};
++
++struct dsi_clock_info {
++      /* rates that we get with dividers below */
++      unsigned long fint;
++      unsigned long dsiphy;
++      unsigned long clkin;
++      unsigned long dsi1_pll_fclk;
++      unsigned long dsi2_pll_fclk;
++      unsigned long lck;
++      unsigned long pck;
++
++      /* dividers */
++      u16 regn;
++      u16 regm;
++      u16 regm3;
++      u16 regm4;
++
++      u16 lck_div;
++      u16 pck_div;
++
++      u8 highfreq;
++      bool use_dss2_fck;
++};
++
++struct seq_file;
++struct platform_device;
++
++/* core */
++void dss_clk_enable(enum dss_clock clks);
++void dss_clk_disable(enum dss_clock clks);
++unsigned long dss_clk_get_rate(enum dss_clock clk);
++int dss_need_ctx_restore(void);
++void dss_dump_clocks(struct seq_file *s);
++struct bus_type *dss_get_bus(void);
++
++/* display */
++int dss_suspend_all_devices(void);
++int dss_resume_all_devices(void);
++
++void dss_init_device(struct platform_device *pdev,
++              struct omap_dss_device *dssdev);
++void dss_uninit_device(struct platform_device *pdev,
++              struct omap_dss_device *dssdev);
++bool dss_use_replication(struct omap_dss_device *dssdev,
++              enum omap_color_mode mode);
++void default_get_overlay_fifo_thresholds(enum omap_plane plane,
++              u32 fifo_size, enum omap_burst_size *burst_size,
++              u32 *fifo_low, u32 *fifo_high);
++
++/* manager */
++int dss_init_overlay_managers(struct platform_device *pdev);
++void dss_uninit_overlay_managers(struct platform_device *pdev);
++int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl);
++void dss_setup_partial_planes(struct omap_dss_device *dssdev,
++                              u16 *x, u16 *y, u16 *w, u16 *h);
++void dss_start_update(struct omap_dss_device *dssdev);
++
++/* overlay */
++void dss_init_overlays(struct platform_device *pdev);
++void dss_uninit_overlays(struct platform_device *pdev);
++int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev);
++void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
++#ifdef L4_EXAMPLE
++void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr);
++#endif
++void dss_recheck_connections(struct omap_dss_device *dssdev, bool force);
++
++/* DSS */
++int dss_init(bool skip_init);
++void dss_exit(void);
++
++void dss_save_context(void);
++void dss_restore_context(void);
++
++void dss_dump_regs(struct seq_file *s);
++
++void dss_sdi_init(u8 datapairs);
++void dss_sdi_enable(void);
++void dss_sdi_disable(void);
++
++void dss_select_clk_source(bool dsi, bool dispc);
++int dss_get_dsi_clk_source(void);
++int dss_get_dispc_clk_source(void);
++void dss_set_venc_output(enum omap_dss_venc_type type);
++void dss_set_dac_pwrdn_bgz(bool enable);
++
++/* SDI */
++int sdi_init(bool skip_init);
++void sdi_exit(void);
++int sdi_init_display(struct omap_dss_device *display);
++
++/* DSI */
++int dsi_init(struct platform_device *pdev);
++void dsi_exit(void);
++
++void dsi_dump_clocks(struct seq_file *s);
++void dsi_dump_regs(struct seq_file *s);
++
++void dsi_save_context(void);
++void dsi_restore_context(void);
++
++int dsi_init_display(struct omap_dss_device *display);
++void dsi_irq_handler(void);
++unsigned long dsi_get_dsi1_pll_rate(void);
++unsigned long dsi_get_dsi2_pll_rate(void);
++int dsi_pll_calc_pck(bool is_tft, unsigned long req_pck,
++              struct dsi_clock_info *cinfo);
++int dsi_pll_program(struct dsi_clock_info *cinfo);
++int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv);
++void dsi_pll_uninit(void);
++void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
++              u32 fifo_size, enum omap_burst_size *burst_size,
++              u32 *fifo_low, u32 *fifo_high);
++
++/* DPI */
++int dpi_init(void);
++void dpi_exit(void);
++int dpi_init_display(struct omap_dss_device *dssdev);
++
++/* DISPC */
++int dispc_init(void);
++void dispc_exit(void);
++void dispc_dump_clocks(struct seq_file *s);
++void dispc_dump_regs(struct seq_file *s);
++void dispc_irq_handler(void);
++void dispc_fake_vsync_irq(void);
++
++void dispc_save_context(void);
++void dispc_restore_context(void);
++
++void dispc_enable_sidle(void);
++void dispc_disable_sidle(void);
++
++void dispc_lcd_enable_signal_polarity(bool act_high);
++void dispc_lcd_enable_signal(bool enable);
++void dispc_pck_free_enable(bool enable);
++void dispc_enable_fifohandcheck(bool enable);
++
++void dispc_set_lcd_size(u16 width, u16 height);
++void dispc_set_digit_size(u16 width, u16 height);
++u32 dispc_get_plane_fifo_size(enum omap_plane plane);
++void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high);
++void dispc_enable_fifomerge(bool enable);
++void dispc_set_burst_size(enum omap_plane plane,
++              enum omap_burst_size burst_size);
++
++void dispc_set_plane_ba0(enum omap_plane plane, u32 paddr);
++void dispc_set_plane_ba1(enum omap_plane plane, u32 paddr);
++void dispc_set_plane_pos(enum omap_plane plane, u16 x, u16 y);
++void dispc_set_plane_size(enum omap_plane plane, u16 width, u16 height);
++void dispc_set_channel_out(enum omap_plane plane,
++              enum omap_channel channel_out);
++
++int dispc_setup_plane(enum omap_plane plane,
++                    u32 paddr, u16 screen_width,
++                    u16 pos_x, u16 pos_y,
++                    u16 width, u16 height,
++                    u16 out_width, u16 out_height,
++                    enum omap_color_mode color_mode,
++                    bool ilace,
++                    enum omap_dss_rotation_type rotation_type,
++                    u8 rotation, bool mirror,
++                    u8 global_alpha);
++
++bool dispc_go_busy(enum omap_channel channel);
++void dispc_go(enum omap_channel channel);
++void dispc_enable_lcd_out(bool enable);
++void dispc_enable_digit_out(bool enable);
++int dispc_enable_plane(enum omap_plane plane, bool enable);
++void dispc_enable_replication(enum omap_plane plane, bool enable);
++
++void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode);
++void dispc_set_tft_data_lines(u8 data_lines);
++void dispc_set_lcd_display_type(enum omap_lcd_display_type type);
++void dispc_set_loadmode(enum omap_dss_load_mode mode);
++
++void dispc_set_default_color(enum omap_channel channel, u32 color);
++u32 dispc_get_default_color(enum omap_channel channel);
++void dispc_set_trans_key(enum omap_channel ch,
++              enum omap_dss_trans_key_type type,
++              u32 trans_key);
++void dispc_get_trans_key(enum omap_channel ch,
++              enum omap_dss_trans_key_type *type,
++              u32 *trans_key);
++void dispc_enable_trans_key(enum omap_channel ch, bool enable);
++void dispc_enable_alpha_blending(enum omap_channel ch, bool enable);
++bool dispc_trans_key_enabled(enum omap_channel ch);
++bool dispc_alpha_blending_enabled(enum omap_channel ch);
++
++bool dispc_lcd_timings_ok(struct omap_video_timings *timings);
++void dispc_set_lcd_timings(struct omap_video_timings *timings);
++unsigned long dispc_fclk_rate(void);
++unsigned long dispc_lclk_rate(void);
++unsigned long dispc_pclk_rate(void);
++void dispc_set_pol_freq(enum omap_panel_config config, u8 acbi, u8 acb);
++void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
++              u16 *lck_div, u16 *pck_div);
++int dispc_calc_clock_div(bool is_tft, unsigned long req_pck,
++              struct dispc_clock_info *cinfo);
++int dispc_set_clock_div(struct dispc_clock_info *cinfo);
++int dispc_get_clock_div(struct dispc_clock_info *cinfo);
++void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div);
++
++
++/* VENC */
++int venc_init(struct platform_device *pdev);
++void venc_exit(void);
++void venc_dump_regs(struct seq_file *s);
++int venc_init_display(struct omap_dss_device *display);
++
++/* RFBI */
++int rfbi_init(void);
++void rfbi_exit(void);
++void rfbi_dump_regs(struct seq_file *s);
++
++int rfbi_configure(int rfbi_module, int bpp, int lines);
++void rfbi_enable_rfbi(bool enable);
++void rfbi_transfer_area(u16 width, u16 height,
++                           void (callback)(void *data), void *data);
++void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t);
++unsigned long rfbi_get_max_tx_rate(void);
++int rfbi_init_display(struct omap_dss_device *display);
++
++#endif
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-2.6.31/dss2/0008-OMAP-DSS2-Add-more-core-files.patch b/recipes/linux/linux-omap-2.6.31/dss2/0008-OMAP-DSS2-Add-more-core-files.patch
new file mode 100644 (file)
index 0000000..3237d49
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.31/dss2/0008-OMAP-DSS2-Add-more-core-files.patch
@@ -0,0 +1,2856 @@
+From 9e37324c13a58b705b85e63b0779f7efbd94342a Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Fri, 7 Aug 2009 13:43:20 +0300
+Subject: [PATCH 08/18] OMAP: DSS2: Add more core files
+
+Add more core files to DSS2.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ drivers/video/omap2/dss/display.c |  658 ++++++++++++++++
+ drivers/video/omap2/dss/manager.c | 1487 +++++++++++++++++++++++++++++++++++++
+ drivers/video/omap2/dss/overlay.c |  673 +++++++++++++++++
+ 3 files changed, 2818 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/video/omap2/dss/display.c
+ create mode 100644 drivers/video/omap2/dss/manager.c
+ create mode 100644 drivers/video/omap2/dss/overlay.c
+
+diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c
+new file mode 100644
+index 0000000..6b5d0cf
+--- /dev/null
++++ b/drivers/video/omap2/dss/display.c
+@@ -0,0 +1,658 @@
++/*
++ * linux/drivers/video/omap2/dss/display.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "DISPLAY"
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/jiffies.h>
++#include <linux/list.h>
++#include <linux/platform_device.h>
++
++#include <mach/display.h>
++#include "dss.h"
++
++static LIST_HEAD(display_list);
++
++static ssize_t display_enabled_show(struct device *dev,
++              struct device_attribute *attr, char *buf)
++{
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++      bool enabled = dssdev->state != OMAP_DSS_DISPLAY_DISABLED;
++
++      return snprintf(buf, PAGE_SIZE, "%d\n", enabled);
++}
++
++static ssize_t display_enabled_store(struct device *dev,
++              struct device_attribute *attr,
++              const char *buf, size_t size)
++{
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++      bool enabled, r;
++
++      enabled = simple_strtoul(buf, NULL, 10);
++
++      if (enabled != (dssdev->state != OMAP_DSS_DISPLAY_DISABLED)) {
++              if (enabled) {
++                      r = dssdev->enable(dssdev);
++                      if (r)
++                              return r;
++              } else {
++                      dssdev->disable(dssdev);
++              }
++      }
++
++      return size;
++}
++
++static ssize_t display_upd_mode_show(struct device *dev,
++              struct device_attribute *attr, char *buf)
++{
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++      enum omap_dss_update_mode mode = OMAP_DSS_UPDATE_AUTO;
++      if (dssdev->get_update_mode)
++              mode = dssdev->get_update_mode(dssdev);
++      return snprintf(buf, PAGE_SIZE, "%d\n", mode);
++}
++
++static ssize_t display_upd_mode_store(struct device *dev,
++              struct device_attribute *attr,
++              const char *buf, size_t size)
++{
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++      int val, r;
++      enum omap_dss_update_mode mode;
++
++      val = simple_strtoul(buf, NULL, 10);
++
++      switch (val) {
++      case OMAP_DSS_UPDATE_DISABLED:
++      case OMAP_DSS_UPDATE_AUTO:
++      case OMAP_DSS_UPDATE_MANUAL:
++              mode = (enum omap_dss_update_mode)val;
++              break;
++      default:
++              return -EINVAL;
++      }
++
++      r = dssdev->set_update_mode(dssdev, mode);
++      if (r)
++              return r;
++
++      return size;
++}
++
++static ssize_t display_tear_show(struct device *dev,
++              struct device_attribute *attr, char *buf)
++{
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++      return snprintf(buf, PAGE_SIZE, "%d\n",
++                      dssdev->get_te ? dssdev->get_te(dssdev) : 0);
++}
++
++static ssize_t display_tear_store(struct device *dev,
++              struct device_attribute *attr, const char *buf, size_t size)
++{
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++      unsigned long te;
++      int r;
++
++      if (!dssdev->enable_te || !dssdev->get_te)
++              return -ENOENT;
++
++      te = simple_strtoul(buf, NULL, 0);
++
++      r = dssdev->enable_te(dssdev, te);
++      if (r)
++              return r;
++
++      return size;
++}
++
++static ssize_t display_timings_show(struct device *dev,
++              struct device_attribute *attr, char *buf)
++{
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++      struct omap_video_timings t;
++
++      if (!dssdev->get_timings)
++              return -ENOENT;
++
++      dssdev->get_timings(dssdev, &t);
++
++      return snprintf(buf, PAGE_SIZE, "%u,%u/%u/%u/%u,%u/%u/%u/%u\n",
++                      t.pixel_clock,
++                      t.x_res, t.hfp, t.hbp, t.hsw,
++                      t.y_res, t.vfp, t.vbp, t.vsw);
++}
++
++static ssize_t display_timings_store(struct device *dev,
++              struct device_attribute *attr, const char *buf, size_t size)
++{
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++      struct omap_video_timings t;
++      int r, found;
++
++      if (!dssdev->set_timings || !dssdev->check_timings)
++              return -ENOENT;
++
++      found = 0;
++#ifdef CONFIG_OMAP2_DSS_VENC
++      if (strncmp("pal", buf, 3) == 0) {
++              t = omap_dss_pal_timings;
++              found = 1;
++      } else if (strncmp("ntsc", buf, 4) == 0) {
++              t = omap_dss_ntsc_timings;
++              found = 1;
++      }
++#endif
++      if (!found && sscanf(buf, "%u,%hu/%hu/%hu/%hu,%hu/%hu/%hu/%hu",
++                              &t.pixel_clock,
++                              &t.x_res, &t.hfp, &t.hbp, &t.hsw,
++                              &t.y_res, &t.vfp, &t.vbp, &t.vsw) != 9)
++              return -EINVAL;
++
++      r = dssdev->check_timings(dssdev, &t);
++      if (r)
++              return r;
++
++      dssdev->set_timings(dssdev, &t);
++
++      return size;
++}
++
++static ssize_t display_rotate_show(struct device *dev,
++              struct device_attribute *attr, char *buf)
++{
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++      int rotate;
++      if (!dssdev->get_rotate)
++              return -ENOENT;
++      rotate = dssdev->get_rotate(dssdev);
++      return snprintf(buf, PAGE_SIZE, "%u\n", rotate);
++}
++
++static ssize_t display_rotate_store(struct device *dev,
++              struct device_attribute *attr, const char *buf, size_t size)
++{
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++      unsigned long rot;
++      int r;
++
++      if (!dssdev->set_rotate || !dssdev->get_rotate)
++              return -ENOENT;
++
++      rot = simple_strtoul(buf, NULL, 0);
++
++      r = dssdev->set_rotate(dssdev, rot);
++      if (r)
++              return r;
++
++      return size;
++}
++
++static ssize_t display_mirror_show(struct device *dev,
++              struct device_attribute *attr, char *buf)
++{
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++      int mirror;
++      if (!dssdev->get_mirror)
++              return -ENOENT;
++      mirror = dssdev->get_mirror(dssdev);
++      return snprintf(buf, PAGE_SIZE, "%u\n", mirror);
++}
++
++static ssize_t display_mirror_store(struct device *dev,
++              struct device_attribute *attr, const char *buf, size_t size)
++{
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++      unsigned long mirror;
++      int r;
++
++      if (!dssdev->set_mirror || !dssdev->get_mirror)
++              return -ENOENT;
++
++      mirror = simple_strtoul(buf, NULL, 0);
++
++      r = dssdev->set_mirror(dssdev, mirror);
++      if (r)
++              return r;
++
++      return size;
++}
++
++static ssize_t display_wss_show(struct device *dev,
++              struct device_attribute *attr, char *buf)
++{
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++      unsigned int wss;
++
++      if (!dssdev->get_wss)
++              return -ENOENT;
++
++      wss = dssdev->get_wss(dssdev);
++
++      return snprintf(buf, PAGE_SIZE, "0x%05x\n", wss);
++}
++
++static ssize_t display_wss_store(struct device *dev,
++              struct device_attribute *attr, const char *buf, size_t size)
++{
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++      unsigned long wss;
++      int r;
++
++      if (!dssdev->get_wss || !dssdev->set_wss)
++              return -ENOENT;
++
++      if (strict_strtoul(buf, 0, &wss))
++              return -EINVAL;
++
++      if (wss > 0xfffff)
++              return -EINVAL;
++
++      r = dssdev->set_wss(dssdev, wss);
++      if (r)
++              return r;
++
++      return size;
++}
++
++static DEVICE_ATTR(enabled, S_IRUGO|S_IWUSR,
++              display_enabled_show, display_enabled_store);
++static DEVICE_ATTR(update_mode, S_IRUGO|S_IWUSR,
++              display_upd_mode_show, display_upd_mode_store);
++static DEVICE_ATTR(tear_elim, S_IRUGO|S_IWUSR,
++              display_tear_show, display_tear_store);
++static DEVICE_ATTR(timings, S_IRUGO|S_IWUSR,
++              display_timings_show, display_timings_store);
++static DEVICE_ATTR(rotate, S_IRUGO|S_IWUSR,
++              display_rotate_show, display_rotate_store);
++static DEVICE_ATTR(mirror, S_IRUGO|S_IWUSR,
++              display_mirror_show, display_mirror_store);
++static DEVICE_ATTR(wss, S_IRUGO|S_IWUSR,
++              display_wss_show, display_wss_store);
++
++static struct device_attribute *display_sysfs_attrs[] = {
++      &dev_attr_enabled,
++      &dev_attr_update_mode,
++      &dev_attr_tear_elim,
++      &dev_attr_timings,
++      &dev_attr_rotate,
++      &dev_attr_mirror,
++      &dev_attr_wss,
++      NULL
++};
++
++static void default_get_resolution(struct omap_dss_device *dssdev,
++                      u16 *xres, u16 *yres)
++{
++      *xres = dssdev->panel.timings.x_res;
++      *yres = dssdev->panel.timings.y_res;
++}
++
++void default_get_overlay_fifo_thresholds(enum omap_plane plane,
++              u32 fifo_size, enum omap_burst_size *burst_size,
++              u32 *fifo_low, u32 *fifo_high)
++{
++      unsigned burst_size_bytes;
++
++      *burst_size = OMAP_DSS_BURST_16x32;
++      burst_size_bytes = 16 * 32 / 8;
++
++      *fifo_high = fifo_size - 1;
++      *fifo_low = fifo_size - burst_size_bytes;
++}
++
++static int default_wait_vsync(struct omap_dss_device *dssdev)
++{
++      unsigned long timeout = msecs_to_jiffies(500);
++      u32 irq;
++
++      if (dssdev->type == OMAP_DISPLAY_TYPE_VENC)
++              irq = DISPC_IRQ_EVSYNC_ODD;
++      else
++              irq = DISPC_IRQ_VSYNC;
++
++      return omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
++}
++
++static int default_get_recommended_bpp(struct omap_dss_device *dssdev)
++{
++      if (dssdev->panel.recommended_bpp)
++              return dssdev->panel.recommended_bpp;
++
++      switch (dssdev->type) {
++      case OMAP_DISPLAY_TYPE_DPI:
++              if (dssdev->phy.dpi.data_lines == 24)
++                      return 24;
++              else
++                      return 16;
++
++      case OMAP_DISPLAY_TYPE_DBI:
++      case OMAP_DISPLAY_TYPE_DSI:
++              if (dssdev->ctrl.pixel_size == 24)
++                      return 24;
++              else
++                      return 16;
++      case OMAP_DISPLAY_TYPE_VENC:
++      case OMAP_DISPLAY_TYPE_SDI:
++              return 24;
++              return 24;
++      default:
++              BUG();
++      }
++}
++
++/* Checks if replication logic should be used. Only use for active matrix,
++ * when overlay is in RGB12U or RGB16 mode, and LCD interface is
++ * 18bpp or 24bpp */
++bool dss_use_replication(struct omap_dss_device *dssdev,
++              enum omap_color_mode mode)
++{
++      int bpp;
++
++      if (mode != OMAP_DSS_COLOR_RGB12U && mode != OMAP_DSS_COLOR_RGB16)
++              return false;
++
++      if (dssdev->type == OMAP_DISPLAY_TYPE_DPI &&
++                      (dssdev->panel.config & OMAP_DSS_LCD_TFT) == 0)
++              return false;
++
++      switch (dssdev->type) {
++      case OMAP_DISPLAY_TYPE_DPI:
++              bpp = dssdev->phy.dpi.data_lines;
++              break;
++      case OMAP_DISPLAY_TYPE_VENC:
++      case OMAP_DISPLAY_TYPE_SDI:
++              bpp = 24;
++              break;
++      case OMAP_DISPLAY_TYPE_DBI:
++      case OMAP_DISPLAY_TYPE_DSI:
++              bpp = dssdev->ctrl.pixel_size;
++              break;
++      default:
++              BUG();
++      }
++
++      return bpp > 16;
++}
++
++void dss_init_device(struct platform_device *pdev,
++              struct omap_dss_device *dssdev)
++{
++      struct device_attribute *attr;
++      int i;
++      int r;
++
++      switch (dssdev->type) {
++      case OMAP_DISPLAY_TYPE_DPI:
++#ifdef CONFIG_OMAP2_DSS_RFBI
++      case OMAP_DISPLAY_TYPE_DBI:
++#endif
++#ifdef CONFIG_OMAP2_DSS_SDI
++      case OMAP_DISPLAY_TYPE_SDI:
++#endif
++#ifdef CONFIG_OMAP2_DSS_DSI
++      case OMAP_DISPLAY_TYPE_DSI:
++#endif
++#ifdef CONFIG_OMAP2_DSS_VENC
++      case OMAP_DISPLAY_TYPE_VENC:
++#endif
++              break;
++      default:
++              DSSERR("Support for display '%s' not compiled in.\n",
++                              dssdev->name);
++              return;
++      }
++
++      dssdev->get_resolution = default_get_resolution;
++      dssdev->get_recommended_bpp = default_get_recommended_bpp;
++      dssdev->wait_vsync = default_wait_vsync;
++
++      switch (dssdev->type) {
++      case OMAP_DISPLAY_TYPE_DPI:
++              r = dpi_init_display(dssdev);
++              break;
++#ifdef CONFIG_OMAP2_DSS_RFBI
++      case OMAP_DISPLAY_TYPE_DBI:
++              r = rfbi_init_display(dssdev);
++              break;
++#endif
++#ifdef CONFIG_OMAP2_DSS_VENC
++      case OMAP_DISPLAY_TYPE_VENC:
++              r = venc_init_display(dssdev);
++              break;
++#endif
++#ifdef CONFIG_OMAP2_DSS_SDI
++      case OMAP_DISPLAY_TYPE_SDI:
++              r = sdi_init_display(dssdev);
++              break;
++#endif
++#ifdef CONFIG_OMAP2_DSS_DSI
++      case OMAP_DISPLAY_TYPE_DSI:
++              r = dsi_init_display(dssdev);
++              break;
++#endif
++      default:
++              BUG();
++      }
++
++      if (r) {
++              DSSERR("failed to init display %s\n", dssdev->name);
++              return;
++      }
++
++      /* create device sysfs files */
++      i = 0;
++      while ((attr = display_sysfs_attrs[i++]) != NULL) {
++              r = device_create_file(&dssdev->dev, attr);
++              if (r)
++                      DSSERR("failed to create sysfs file\n");
++      }
++
++      /* create display? sysfs links */
++      r = sysfs_create_link(&pdev->dev.kobj, &dssdev->dev.kobj,
++                      dev_name(&dssdev->dev));
++      if (r)
++              DSSERR("failed to create sysfs display link\n");
++}
++
++void dss_uninit_device(struct platform_device *pdev,
++              struct omap_dss_device *dssdev)
++{
++      struct device_attribute *attr;
++      int i = 0;
++
++      sysfs_remove_link(&pdev->dev.kobj, dev_name(&dssdev->dev));
++
++      while ((attr = display_sysfs_attrs[i++]) != NULL)
++              device_remove_file(&dssdev->dev, attr);
++
++      if (dssdev->manager)
++              dssdev->manager->unset_device(dssdev->manager);
++}
++
++static int dss_suspend_device(struct device *dev, void *data)
++{
++      int r;
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++
++      if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) {
++              dssdev->activate_after_resume = false;
++              return 0;
++      }
++
++      if (!dssdev->suspend) {
++              DSSERR("display '%s' doesn't implement suspend\n",
++                              dssdev->name);
++              return -ENOSYS;
++      }
++
++      r = dssdev->suspend(dssdev);
++      if (r)
++              return r;
++
++      dssdev->activate_after_resume = true;
++
++      return 0;
++}
++
++int dss_suspend_all_devices(void)
++{
++      int r;
++      struct bus_type *bus = dss_get_bus();
++
++      r = bus_for_each_dev(bus, NULL, NULL, dss_suspend_device);
++      if (r) {
++              /* resume all displays that were suspended */
++              dss_resume_all_devices();
++              return r;
++      }
++
++      return 0;
++}
++
++static int dss_resume_device(struct device *dev, void *data)
++{
++      int r;
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++
++      if (dssdev->activate_after_resume && dssdev->resume) {
++              r = dssdev->resume(dssdev);
++              if (r)
++                      return r;
++      }
++
++      dssdev->activate_after_resume = false;
++
++      return 0;
++}
++
++int dss_resume_all_devices(void)
++{
++      struct bus_type *bus = dss_get_bus();
++
++      return bus_for_each_dev(bus, NULL, NULL, dss_resume_device);
++}
++
++
++void omap_dss_get_device(struct omap_dss_device *dssdev)
++{
++      get_device(&dssdev->dev);
++}
++EXPORT_SYMBOL(omap_dss_get_device);
++
++void omap_dss_put_device(struct omap_dss_device *dssdev)
++{
++      put_device(&dssdev->dev);
++}
++EXPORT_SYMBOL(omap_dss_put_device);
++
++/* ref count of the found device is incremented. ref count
++ * of from-device is decremented. */
++struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from)
++{
++      struct device *dev;
++      struct device *dev_start = NULL;
++      struct omap_dss_device *dssdev = NULL;
++
++      int match(struct device *dev, void *data)
++      {
++              /* skip panels connected to controllers */
++              if (to_dss_device(dev)->panel.ctrl)
++                      return 0;
++
++              return 1;
++      }
++
++      if (from)
++              dev_start = &from->dev;
++      dev = bus_find_device(dss_get_bus(), dev_start, NULL, match);
++      if (dev)
++              dssdev = to_dss_device(dev);
++      if (from)
++              put_device(&from->dev);
++
++      return dssdev;
++}
++EXPORT_SYMBOL(omap_dss_get_next_device);
++
++struct omap_dss_device *omap_dss_find_device(void *data,
++              int (*match)(struct omap_dss_device *dssdev, void *data))
++{
++      struct omap_dss_device *dssdev = NULL;
++
++      while ((dssdev = omap_dss_get_next_device(dssdev)) != NULL) {
++              if (match(dssdev, data))
++                      return dssdev;
++      }
++
++      return NULL;
++}
++EXPORT_SYMBOL(omap_dss_find_device);
++
++int omap_dss_start_device(struct omap_dss_device *dssdev)
++{
++      int r;
++
++      if (!dssdev->driver) {
++              DSSDBG("no driver\n");
++              r = -ENODEV;
++              goto err0;
++      }
++
++      if (dssdev->ctrl.panel && !dssdev->ctrl.panel->driver) {
++              DSSDBG("no panel driver\n");
++              r = -ENODEV;
++              goto err0;
++      }
++
++      if (!try_module_get(dssdev->dev.driver->owner)) {
++              r = -ENODEV;
++              goto err0;
++      }
++
++      if (dssdev->ctrl.panel) {
++              if (!try_module_get(dssdev->ctrl.panel->dev.driver->owner)) {
++                      r = -ENODEV;
++                      goto err1;
++              }
++      }
++
++      return 0;
++err1:
++      module_put(dssdev->dev.driver->owner);
++err0:
++      return r;
++}
++EXPORT_SYMBOL(omap_dss_start_device);
++
++void omap_dss_stop_device(struct omap_dss_device *dssdev)
++{
++      if (dssdev->ctrl.panel)
++              module_put(dssdev->ctrl.panel->dev.driver->owner);
++
++      module_put(dssdev->dev.driver->owner);
++}
++EXPORT_SYMBOL(omap_dss_stop_device);
++
+diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
+new file mode 100644
+index 0000000..7ee0b2b
+--- /dev/null
++++ b/drivers/video/omap2/dss/manager.c
+@@ -0,0 +1,1487 @@
++/*
++ * linux/drivers/video/omap2/dss/manager.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "MANAGER"
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/spinlock.h>
++#include <linux/jiffies.h>
++
++#include <mach/display.h>
++#include <mach/cpu.h>
++
++#include "dss.h"
++
++static int num_managers;
++static struct list_head manager_list;
++
++static ssize_t manager_name_show(struct omap_overlay_manager *mgr, char *buf)
++{
++      return snprintf(buf, PAGE_SIZE, "%s\n", mgr->name);
++}
++
++static ssize_t manager_display_show(struct omap_overlay_manager *mgr, char *buf)
++{
++      return snprintf(buf, PAGE_SIZE, "%s\n",
++                      mgr->device ? mgr->device->name : "<none>");
++}
++
++static ssize_t manager_display_store(struct omap_overlay_manager *mgr,
++              const char *buf, size_t size)
++{
++      int r = 0;
++      size_t len = size;
++      struct omap_dss_device *dssdev = NULL;
++
++      int match(struct omap_dss_device *dssdev, void *data)
++      {
++              const char *str = data;
++              return sysfs_streq(dssdev->name, str);
++      }
++
++      if (buf[size-1] == '\n')
++              --len;
++
++      if (len > 0)
++              dssdev = omap_dss_find_device((void *)buf, match);
++
++      if (len > 0 && dssdev == NULL)
++              return -EINVAL;
++
++      if (dssdev)
++              DSSDBG("display %s found\n", dssdev->name);
++
++      if (mgr->device) {
++              r = mgr->unset_device(mgr);
++              if (r) {
++                      DSSERR("failed to unset display\n");
++                      goto put_device;
++              }
++      }
++
++      if (dssdev) {
++              r = mgr->set_device(mgr, dssdev);
++              if (r) {
++                      DSSERR("failed to set manager\n");
++                      goto put_device;
++              }
++
++              r = mgr->apply(mgr);
++              if (r) {
++                      DSSERR("failed to apply dispc config\n");
++                      goto put_device;
++              }
++      }
++
++put_device:
++      if (dssdev)
++              omap_dss_put_device(dssdev);
++
++      return r ? r : size;
++}
++
++static ssize_t manager_default_color_show(struct omap_overlay_manager *mgr,
++                                        char *buf)
++{
++      return snprintf(buf, PAGE_SIZE, "%d\n", mgr->info.default_color);
++}
++
++static ssize_t manager_default_color_store(struct omap_overlay_manager *mgr,
++                                         const char *buf, size_t size)
++{
++      struct omap_overlay_manager_info info;
++      u32 color;
++      int r;
++
++      if (sscanf(buf, "%d", &color) != 1)
++              return -EINVAL;
++
++      mgr->get_manager_info(mgr, &info);
++
++      info.default_color = color;
++
++      r = mgr->set_manager_info(mgr, &info);
++      if (r)
++              return r;
++
++      r = mgr->apply(mgr);
++      if (r)
++              return r;
++
++      return size;
++}
++
++static const char *trans_key_type_str[] = {
++      "gfx-destination",
++      "video-source",
++};
++
++static ssize_t manager_trans_key_type_show(struct omap_overlay_manager *mgr,
++                                         char *buf)
++{
++      enum omap_dss_trans_key_type key_type;
++
++      key_type = mgr->info.trans_key_type;
++      BUG_ON(key_type >= ARRAY_SIZE(trans_key_type_str));
++
++      return snprintf(buf, PAGE_SIZE, "%s\n", trans_key_type_str[key_type]);
++}
++
++static ssize_t manager_trans_key_type_store(struct omap_overlay_manager *mgr,
++                                          const char *buf, size_t size)
++{
++      enum omap_dss_trans_key_type key_type;
++      struct omap_overlay_manager_info info;
++      int r;
++
++      for (key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
++                      key_type < ARRAY_SIZE(trans_key_type_str); key_type++) {
++              if (sysfs_streq(buf, trans_key_type_str[key_type]))
++                      break;
++      }
++
++      if (key_type == ARRAY_SIZE(trans_key_type_str))
++              return -EINVAL;
++
++      mgr->get_manager_info(mgr, &info);
++
++      info.trans_key_type = key_type;
++
++      r = mgr->set_manager_info(mgr, &info);
++      if (r)
++              return r;
++
++      r = mgr->apply(mgr);
++      if (r)
++              return r;
++
++      return size;
++}
++
++static ssize_t manager_trans_key_value_show(struct omap_overlay_manager *mgr,
++                                          char *buf)
++{
++      return snprintf(buf, PAGE_SIZE, "%d\n", mgr->info.trans_key);
++}
++
++static ssize_t manager_trans_key_value_store(struct omap_overlay_manager *mgr,
++                                           const char *buf, size_t size)
++{
++      struct omap_overlay_manager_info info;
++      u32 key_value;
++      int r;
++
++      if (sscanf(buf, "%d", &key_value) != 1)
++              return -EINVAL;
++
++      mgr->get_manager_info(mgr, &info);
++
++      info.trans_key = key_value;
++
++      r = mgr->set_manager_info(mgr, &info);
++      if (r)
++              return r;
++
++      r = mgr->apply(mgr);
++      if (r)
++              return r;
++
++      return size;
++}
++
++static ssize_t manager_trans_key_enabled_show(struct omap_overlay_manager *mgr,
++                                            char *buf)
++{
++      return snprintf(buf, PAGE_SIZE, "%d\n", mgr->info.trans_enabled);
++}
++
++static ssize_t manager_trans_key_enabled_store(struct omap_overlay_manager *mgr,
++                                             const char *buf, size_t size)
++{
++      struct omap_overlay_manager_info info;
++      int enable;
++      int r;
++
++      if (sscanf(buf, "%d", &enable) != 1)
++              return -EINVAL;
++
++      mgr->get_manager_info(mgr, &info);
++
++      info.trans_enabled = enable ? true : false;
++
++      r = mgr->set_manager_info(mgr, &info);
++      if (r)
++              return r;
++
++      r = mgr->apply(mgr);
++      if (r)
++              return r;
++
++      return size;
++}
++
++static ssize_t manager_alpha_blending_enabled_show(
++              struct omap_overlay_manager *mgr, char *buf)
++{
++      return snprintf(buf, PAGE_SIZE, "%d\n", mgr->info.alpha_enabled);
++}
++
++static ssize_t manager_alpha_blending_enabled_store(
++              struct omap_overlay_manager *mgr,
++              const char *buf, size_t size)
++{
++      struct omap_overlay_manager_info info;
++      int enable;
++      int r;
++
++      if (sscanf(buf, "%d", &enable) != 1)
++              return -EINVAL;
++
++      mgr->get_manager_info(mgr, &info);
++
++      info.alpha_enabled = enable ? true : false;
++
++      r = mgr->set_manager_info(mgr, &info);
++      if (r)
++              return r;
++
++      r = mgr->apply(mgr);
++      if (r)
++              return r;
++
++      return size;
++}
++
++struct manager_attribute {
++      struct attribute attr;
++      ssize_t (*show)(struct omap_overlay_manager *, char *);
++      ssize_t (*store)(struct omap_overlay_manager *, const char *, size_t);
++};
++
++#define MANAGER_ATTR(_name, _mode, _show, _store) \
++      struct manager_attribute manager_attr_##_name = \
++      __ATTR(_name, _mode, _show, _store)
++
++static MANAGER_ATTR(name, S_IRUGO, manager_name_show, NULL);
++static MANAGER_ATTR(display, S_IRUGO|S_IWUSR,
++              manager_display_show, manager_display_store);
++static MANAGER_ATTR(default_color, S_IRUGO|S_IWUSR,
++              manager_default_color_show, manager_default_color_store);
++static MANAGER_ATTR(trans_key_type, S_IRUGO|S_IWUSR,
++              manager_trans_key_type_show, manager_trans_key_type_store);
++static MANAGER_ATTR(trans_key_value, S_IRUGO|S_IWUSR,
++              manager_trans_key_value_show, manager_trans_key_value_store);
++static MANAGER_ATTR(trans_key_enabled, S_IRUGO|S_IWUSR,
++              manager_trans_key_enabled_show,
++              manager_trans_key_enabled_store);
++static MANAGER_ATTR(alpha_blending_enabled, S_IRUGO|S_IWUSR,
++              manager_alpha_blending_enabled_show,
++              manager_alpha_blending_enabled_store);
++
++
++static struct attribute *manager_sysfs_attrs[] = {
++      &manager_attr_name.attr,
++      &manager_attr_display.attr,
++      &manager_attr_default_color.attr,
++      &manager_attr_trans_key_type.attr,
++      &manager_attr_trans_key_value.attr,
++      &manager_attr_trans_key_enabled.attr,
++      &manager_attr_alpha_blending_enabled.attr,
++      NULL
++};
++
++static ssize_t manager_attr_show(struct kobject *kobj, struct attribute *attr,
++              char *buf)
++{
++      struct omap_overlay_manager *manager;
++      struct manager_attribute *manager_attr;
++
++      manager = container_of(kobj, struct omap_overlay_manager, kobj);
++      manager_attr = container_of(attr, struct manager_attribute, attr);
++
++      if (!manager_attr->show)
++              return -ENOENT;
++
++      return manager_attr->show(manager, buf);
++}
++
++static ssize_t manager_attr_store(struct kobject *kobj, struct attribute *attr,
++              const char *buf, size_t size)
++{
++      struct omap_overlay_manager *manager;
++      struct manager_attribute *manager_attr;
++
++      manager = container_of(kobj, struct omap_overlay_manager, kobj);
++      manager_attr = container_of(attr, struct manager_attribute, attr);
++
++      if (!manager_attr->store)
++              return -ENOENT;
++
++      return manager_attr->store(manager, buf, size);
++}
++
++static struct sysfs_ops manager_sysfs_ops = {
++      .show = manager_attr_show,
++      .store = manager_attr_store,
++};
++
++static struct kobj_type manager_ktype = {
++      .sysfs_ops = &manager_sysfs_ops,
++      .default_attrs = manager_sysfs_attrs,
++};
++
++/*
++ * We have 4 levels of cache for the dispc settings. First two are in SW and
++ * the latter two in HW.
++ *
++ * +--------------------+
++ * |overlay/manager_info|
++ * +--------------------+
++ *          v
++ *        apply()
++ *          v
++ * +--------------------+
++ * |     dss_cache      |
++ * +--------------------+
++ *          v
++ *      configure()
++ *          v
++ * +--------------------+
++ * |  shadow registers  |
++ * +--------------------+
++ *          v
++ * VFP or lcd/digit_enable
++ *          v
++ * +--------------------+
++ * |      registers     |
++ * +--------------------+
++ */
++
++struct overlay_cache_data {
++      /* If true, cache changed, but not written to shadow registers. Set
++       * in apply(), cleared when registers written. */
++      bool dirty;
++      /* If true, shadow registers contain changed values not yet in real
++       * registers. Set when writing to shadow registers, cleared at
++       * VSYNC/EVSYNC */
++      bool shadow_dirty;
++
++      bool enabled;
++
++      u32 paddr;
++      void __iomem *vaddr;
++      u16 screen_width;
++      u16 width;
++      u16 height;
++      enum omap_color_mode color_mode;
++      u8 rotation;
++      enum omap_dss_rotation_type rotation_type;
++      bool mirror;
++
++      u16 pos_x;
++      u16 pos_y;
++      u16 out_width;  /* if 0, out_width == width */
++      u16 out_height; /* if 0, out_height == height */
++      u8 global_alpha;
++
++      enum omap_channel channel;
++      bool replication;
++      bool ilace;
++
++      enum omap_burst_size burst_size;
++      u32 fifo_low;
++      u32 fifo_high;
++
++      bool manual_update;
++};
++
++struct manager_cache_data {
++      /* If true, cache changed, but not written to shadow registers. Set
++       * in apply(), cleared when registers written. */
++      bool dirty;
++      /* If true, shadow registers contain changed values not yet in real
++       * registers. Set when writing to shadow registers, cleared at
++       * VSYNC/EVSYNC */
++      bool shadow_dirty;
++
++      u32 default_color;
++
++      enum omap_dss_trans_key_type trans_key_type;
++      u32 trans_key;
++      bool trans_enabled;
++
++      bool alpha_enabled;
++
++      bool manual_upd_display;
++      bool manual_update;
++      bool do_manual_update;
++
++      /* manual update region */
++      u16 x, y, w, h;
++};
++
++static struct {
++      spinlock_t lock;
++      struct overlay_cache_data overlay_cache[3];
++      struct manager_cache_data manager_cache[2];
++
++      bool irq_enabled;
++} dss_cache;
++
++
++
++static int omap_dss_set_device(struct omap_overlay_manager *mgr,
++              struct omap_dss_device *dssdev)
++{
++      int i;
++      int r;
++
++      if (dssdev->manager) {
++              DSSERR("display '%s' already has a manager '%s'\n",
++                             dssdev->name, dssdev->manager->name);
++              return -EINVAL;
++      }
++
++      if ((mgr->supported_displays & dssdev->type) == 0) {
++              DSSERR("display '%s' does not support manager '%s'\n",
++                             dssdev->name, mgr->name);
++              return -EINVAL;
++      }
++
++      for (i = 0; i < mgr->num_overlays; i++) {
++              struct omap_overlay *ovl = mgr->overlays[i];
++
++              if (ovl->manager != mgr || !ovl->info.enabled)
++                      continue;
++
++              r = dss_check_overlay(ovl, dssdev);
++              if (r)
++                      return r;
++      }
++
++      dssdev->manager = mgr;
++      mgr->device = dssdev;
++      mgr->device_changed = true;
++
++      return 0;
++}
++
++static int omap_dss_unset_device(struct omap_overlay_manager *mgr)
++{
++      if (!mgr->device) {
++              DSSERR("failed to unset display, display not set.\n");
++              return -EINVAL;
++      }
++
++      mgr->device->manager = NULL;
++      mgr->device = NULL;
++      mgr->device_changed = true;
++
++      return 0;
++}
++
++static int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr)
++{
++      unsigned long timeout = msecs_to_jiffies(500);
++      struct manager_cache_data *mc;
++      enum omap_channel channel;
++      u32 irq;
++      int r;
++      int i;
++
++      if (!mgr->device)
++              return 0;
++
++      if (mgr->device->type == OMAP_DISPLAY_TYPE_VENC) {
++              irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
++              channel = OMAP_DSS_CHANNEL_DIGIT;
++      } else {
++              if (mgr->device->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
++                      enum omap_dss_update_mode mode;
++                      mode = mgr->device->get_update_mode(mgr->device);
++                      if (mode != OMAP_DSS_UPDATE_AUTO)
++                              return 0;
++
++                      irq = DISPC_IRQ_FRAMEDONE;
++              } else {
++                      irq = DISPC_IRQ_VSYNC;
++              }
++              channel = OMAP_DSS_CHANNEL_LCD;
++      }
++
++      mc = &dss_cache.manager_cache[mgr->id];
++      i = 0;
++      while (1) {
++              unsigned long flags;
++              bool shadow_dirty, dirty;
++
++              spin_lock_irqsave(&dss_cache.lock, flags);
++              dirty = mc->dirty;
++              shadow_dirty = mc->shadow_dirty;
++              spin_unlock_irqrestore(&dss_cache.lock, flags);
++
++              if (!dirty && !shadow_dirty) {
++                      r = 0;
++                      break;
++              }
++
++              /* 4 iterations is the worst case:
++               * 1 - initial iteration, dirty = true (between VFP and VSYNC)
++               * 2 - first VSYNC, dirty = true
++               * 3 - dirty = false, shadow_dirty = true
++               * 4 - shadow_dirty = false */
++              if (i++ == 3) {
++                      DSSERR("mgr(%d)->wait_for_go() not finishing\n",
++                                      mgr->id);
++                      r = 0;
++                      break;
++              }
++
++              r = omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
++              if (r == -ERESTARTSYS)
++                      break;
++
++              if (r) {
++                      DSSERR("mgr(%d)->wait_for_go() timeout\n", mgr->id);
++                      break;
++              }
++      }
++
++      return r;
++}
++
++int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl)
++{
++      unsigned long timeout = msecs_to_jiffies(500);
++      enum omap_channel channel;
++      struct overlay_cache_data *oc;
++      struct omap_dss_device *dssdev;
++      u32 irq;
++      int r;
++      int i;
++
++      if (!ovl->manager || !ovl->manager->device)
++              return 0;
++
++      dssdev = ovl->manager->device;
++
++      if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) {
++              irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
++              channel = OMAP_DSS_CHANNEL_DIGIT;
++      } else {
++              if (dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
++                      enum omap_dss_update_mode mode;
++                      mode = dssdev->get_update_mode(dssdev);
++                      if (mode != OMAP_DSS_UPDATE_AUTO)
++                              return 0;
++
++                      irq = DISPC_IRQ_FRAMEDONE;
++              } else {
++                      irq = DISPC_IRQ_VSYNC;
++              }
++              channel = OMAP_DSS_CHANNEL_LCD;
++      }
++
++      oc = &dss_cache.overlay_cache[ovl->id];
++      i = 0;
++      while (1) {
++              unsigned long flags;
++              bool shadow_dirty, dirty;
++
++              spin_lock_irqsave(&dss_cache.lock, flags);
++              dirty = oc->dirty;
++              shadow_dirty = oc->shadow_dirty;
++              spin_unlock_irqrestore(&dss_cache.lock, flags);
++
++              if (!dirty && !shadow_dirty) {
++                      r = 0;
++                      break;
++              }
++
++              /* 4 iterations is the worst case:
++               * 1 - initial iteration, dirty = true (between VFP and VSYNC)
++               * 2 - first VSYNC, dirty = true
++               * 3 - dirty = false, shadow_dirty = true
++               * 4 - shadow_dirty = false */
++              if (i++ == 3) {
++                      DSSERR("ovl(%d)->wait_for_go() not finishing\n",
++                                      ovl->id);
++                      r = 0;
++                      break;
++              }
++
++              r = omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
++              if (r == -ERESTARTSYS)
++                      break;
++
++              if (r) {
++                      DSSERR("ovl(%d)->wait_for_go() timeout\n", ovl->id);
++                      break;
++              }
++      }
++
++      return r;
++}
++
++static int overlay_enabled(struct omap_overlay *ovl)
++{
++      return ovl->info.enabled && ovl->manager && ovl->manager->device;
++}
++
++/* Is rect1 a subset of rect2? */
++static bool rectangle_subset(int x1, int y1, int w1, int h1,
++              int x2, int y2, int w2, int h2)
++{
++      if (x1 < x2 || y1 < y2)
++              return false;
++
++      if (x1 + w1 > x2 + w2)
++              return false;
++
++      if (y1 + h1 > y2 + h2)
++              return false;
++
++      return true;
++}
++
++/* Do rect1 and rect2 overlap? */
++static bool rectangle_intersects(int x1, int y1, int w1, int h1,
++              int x2, int y2, int w2, int h2)
++{
++      if (x1 >= x2 + w2)
++              return false;
++
++      if (x2 >= x1 + w1)
++              return false;
++
++      if (y1 >= y2 + h2)
++              return false;
++
++      if (y2 >= y1 + h1)
++              return false;
++
++      return true;
++}
++
++static bool dispc_is_overlay_scaled(struct overlay_cache_data *oc)
++{
++      if (oc->out_width != 0 && oc->width != oc->out_width)
++              return true;
++
++      if (oc->out_height != 0 && oc->height != oc->out_height)
++              return true;
++
++      return false;
++}
++
++static int configure_overlay(enum omap_plane plane)
++{
++      struct overlay_cache_data *c;
++      struct manager_cache_data *mc;
++      u16 outw, outh;
++      u16 x, y, w, h;
++      u32 paddr;
++      int r;
++
++      DSSDBGF("%d", plane);
++
++      c = &dss_cache.overlay_cache[plane];
++
++      if (!c->enabled) {
++              dispc_enable_plane(plane, 0);
++              return 0;
++      }
++
++      mc = &dss_cache.manager_cache[c->channel];
++
++      x = c->pos_x;
++      y = c->pos_y;
++      w = c->width;
++      h = c->height;
++      outw = c->out_width == 0 ? c->width : c->out_width;
++      outh = c->out_height == 0 ? c->height : c->out_height;
++      paddr = c->paddr;
++
++      if (c->manual_update && mc->do_manual_update) {
++              unsigned bpp;
++              /* If the overlay is outside the update region, disable it */
++              if (!rectangle_intersects(mc->x, mc->y, mc->w, mc->h,
++                                      x, y, outw, outh)) {
++                      dispc_enable_plane(plane, 0);
++                      return 0;
++              }
++
++              switch (c->color_mode) {
++              case OMAP_DSS_COLOR_RGB16:
++              case OMAP_DSS_COLOR_ARGB16:
++              case OMAP_DSS_COLOR_YUV2:
++              case OMAP_DSS_COLOR_UYVY:
++                      bpp = 16;
++                      break;
++
++              case OMAP_DSS_COLOR_RGB24P:
++                      bpp = 24;
++                      break;
++
++              case OMAP_DSS_COLOR_RGB24U:
++              case OMAP_DSS_COLOR_ARGB32:
++              case OMAP_DSS_COLOR_RGBA32:
++              case OMAP_DSS_COLOR_RGBX32:
++                      bpp = 32;
++                      break;
++
++              default:
++                      BUG();
++              }
++
++              if (dispc_is_overlay_scaled(c)) {
++                      /* If the overlay is scaled, the update area has
++                       * already been enlarged to cover the whole overlay. We
++                       * only need to adjust x/y here */
++                      x = c->pos_x - mc->x;
++                      y = c->pos_y - mc->y;
++              } else {
++                      if (mc->x > c->pos_x) {
++                              x = 0;
++                              w -= (mc->x - c->pos_x);
++                              paddr += (mc->x - c->pos_x) * bpp / 8;
++                      } else {
++                              x = c->pos_x - mc->x;
++                      }
++
++                      if (mc->y > c->pos_y) {
++                              y = 0;
++                              h -= (mc->y - c->pos_y);
++                              paddr += (mc->y - c->pos_y) * c->screen_width *
++                                      bpp / 8;
++                      } else {
++                              y = c->pos_y - mc->y;
++                      }
++
++                      if (mc->w < (x+w))
++                              w -= (x+w) - (mc->w);
++
++                      if (mc->h < (y+h))
++                              h -= (y+h) - (mc->h);
++
++                      outw = w;
++                      outh = h;
++              }
++      }
++
++      r = dispc_setup_plane(plane,
++                      paddr,
++                      c->screen_width,
++                      x, y,
++                      w, h,
++                      outw, outh,
++                      c->color_mode,
++                      c->ilace,
++                      c->rotation_type,
++                      c->rotation,
++                      c->mirror,
++                      c->global_alpha);
++
++      if (r) {
++              /* this shouldn't happen */
++              DSSERR("dispc_setup_plane failed for ovl %d\n", plane);
++              dispc_enable_plane(plane, 0);
++              return r;
++      }
++
++      dispc_enable_replication(plane, c->replication);
++
++      dispc_set_burst_size(plane, c->burst_size);
++      dispc_setup_plane_fifo(plane, c->fifo_low, c->fifo_high);
++
++      dispc_enable_plane(plane, 1);
++
++      return 0;
++}
++
++static void configure_manager(enum omap_channel channel)
++{
++      struct manager_cache_data *c;
++
++      DSSDBGF("%d", channel);
++
++      c = &dss_cache.manager_cache[channel];
++
++      dispc_set_trans_key(channel, c->trans_key_type, c->trans_key);
++      dispc_enable_trans_key(channel, c->trans_enabled);
++      dispc_enable_alpha_blending(channel, c->alpha_enabled);
++}
++
++/* configure_dispc() tries to write values from cache to shadow registers.
++ * It writes only to those managers/overlays that are not busy.
++ * returns 0 if everything could be written to shadow registers.
++ * returns 1 if not everything could be written to shadow registers. */
++static int configure_dispc(void)
++{
++      struct overlay_cache_data *oc;
++      struct manager_cache_data *mc;
++      const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache);
++      const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache);
++      int i;
++      int r;
++      bool mgr_busy[2];
++      bool mgr_go[2];
++      bool busy;
++
++      r = 0;
++      busy = false;
++
++      mgr_busy[0] = dispc_go_busy(0);
++      mgr_busy[1] = dispc_go_busy(1);
++      mgr_go[0] = false;
++      mgr_go[1] = false;
++
++      /* Commit overlay settings */
++      for (i = 0; i < num_ovls; ++i) {
++              oc = &dss_cache.overlay_cache[i];
++              mc = &dss_cache.manager_cache[oc->channel];
++
++              if (!oc->dirty)
++                      continue;
++
++              if (oc->manual_update && !mc->do_manual_update)
++                      continue;
++
++              if (mgr_busy[oc->channel]) {
++                      busy = true;
++                      continue;
++              }
++
++              r = configure_overlay(i);
++              if (r)
++                      DSSERR("configure_overlay %d failed\n", i);
++
++              oc->dirty = false;
++              oc->shadow_dirty = true;
++              mgr_go[oc->channel] = true;
++      }
++
++      /* Commit manager settings */
++      for (i = 0; i < num_mgrs; ++i) {
++              mc = &dss_cache.manager_cache[i];
++
++              if (!mc->dirty)
++                      continue;
++
++              if (mc->manual_update && !mc->do_manual_update)
++                      continue;
++
++              if (mgr_busy[i]) {
++                      busy = true;
++                      continue;
++              }
++
++              configure_manager(i);
++              mc->dirty = false;
++              mc->shadow_dirty = true;
++              mgr_go[i] = true;
++      }
++
++      /* set GO */
++      for (i = 0; i < num_mgrs; ++i) {
++              mc = &dss_cache.manager_cache[i];
++
++              if (!mgr_go[i])
++                      continue;
++
++              /* We don't need GO with manual update display. LCD iface will
++               * always be turned off after frame, and new settings will be
++               * taken in to use at next update */
++              if (!mc->manual_upd_display)
++                      dispc_go(i);
++      }
++
++      if (busy)
++              r = 1;
++      else
++              r = 0;
++
++      return r;
++}
++
++/* Configure dispc for partial update. Return possibly modified update
++ * area */
++void dss_setup_partial_planes(struct omap_dss_device *dssdev,
++              u16 *xi, u16 *yi, u16 *wi, u16 *hi)
++{
++      struct overlay_cache_data *oc;
++      struct manager_cache_data *mc;
++      const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache);
++      struct omap_overlay_manager *mgr;
++      int i;
++      u16 x, y, w, h;
++      unsigned long flags;
++
++      x = *xi;
++      y = *yi;
++      w = *wi;
++      h = *hi;
++
++      DSSDBG("dispc_setup_partial_planes %d,%d %dx%d\n",
++              *xi, *yi, *wi, *hi);
++
++      mgr = dssdev->manager;
++
++      if (!mgr) {
++              DSSDBG("no manager\n");
++              return;
++      }
++
++      spin_lock_irqsave(&dss_cache.lock, flags);
++
++      /* We need to show the whole overlay if it is scaled. So look for
++       * those, and make the update area larger if found.
++       * Also mark the overlay cache dirty */
++      for (i = 0; i < num_ovls; ++i) {
++              unsigned x1, y1, x2, y2;
++              unsigned outw, outh;
++
++              oc = &dss_cache.overlay_cache[i];
++
++              if (oc->channel != mgr->id)
++                      continue;
++
++              oc->dirty = true;
++
++              if (!oc->enabled)
++                      continue;
++
++              if (!dispc_is_overlay_scaled(oc))
++                      continue;
++
++              outw = oc->out_width == 0 ? oc->width : oc->out_width;
++              outh = oc->out_height == 0 ? oc->height : oc->out_height;
++
++              /* is the overlay outside the update region? */
++              if (!rectangle_intersects(x, y, w, h,
++                                      oc->pos_x, oc->pos_y,
++                                      outw, outh))
++                      continue;
++
++              /* if the overlay totally inside the update region? */
++              if (rectangle_subset(oc->pos_x, oc->pos_y, outw, outh,
++                                      x, y, w, h))
++                      continue;
++
++              if (x > oc->pos_x)
++                      x1 = oc->pos_x;
++              else
++                      x1 = x;
++
++              if (y > oc->pos_y)
++                      y1 = oc->pos_y;
++              else
++                      y1 = y;
++
++              if ((x + w) < (oc->pos_x + outw))
++                      x2 = oc->pos_x + outw;
++              else
++                      x2 = x + w;
++
++              if ((y + h) < (oc->pos_y + outh))
++                      y2 = oc->pos_y + outh;
++              else
++                      y2 = y + h;
++
++              x = x1;
++              y = y1;
++              w = x2 - x1;
++              h = y2 - y1;
++
++              DSSDBG("changing upd area due to ovl(%d) scaling %d,%d %dx%d\n",
++                              i, x, y, w, h);
++      }
++
++      mc = &dss_cache.manager_cache[mgr->id];
++      mc->do_manual_update = true;
++      mc->x = x;
++      mc->y = y;
++      mc->w = w;
++      mc->h = h;
++
++      configure_dispc();
++
++      mc->do_manual_update = false;
++
++      spin_unlock_irqrestore(&dss_cache.lock, flags);
++
++      *xi = x;
++      *yi = y;
++      *wi = w;
++      *hi = h;
++}
++
++void dss_start_update(struct omap_dss_device *dssdev)
++{
++      struct manager_cache_data *mc;
++      struct overlay_cache_data *oc;
++      const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache);
++      const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache);
++      struct omap_overlay_manager *mgr;
++      int i;
++
++      mgr = dssdev->manager;
++
++      for (i = 0; i < num_ovls; ++i) {
++              oc = &dss_cache.overlay_cache[i];
++              if (oc->channel != mgr->id)
++                      continue;
++
++              oc->shadow_dirty = false;
++      }
++
++      for (i = 0; i < num_mgrs; ++i) {
++              mc = &dss_cache.manager_cache[i];
++              if (mgr->id != i)
++                      continue;
++
++              mc->shadow_dirty = false;
++      }
++
++      dispc_enable_lcd_out(1);
++}
++
++static void dss_apply_irq_handler(void *data, u32 mask)
++{
++      struct manager_cache_data *mc;
++      struct overlay_cache_data *oc;
++      const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache);
++      const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache);
++      int i, r;
++      bool mgr_busy[2];
++
++      mgr_busy[0] = dispc_go_busy(0);
++      mgr_busy[1] = dispc_go_busy(1);
++
++      spin_lock(&dss_cache.lock);
++
++      for (i = 0; i < num_ovls; ++i) {
++              oc = &dss_cache.overlay_cache[i];
++              if (!mgr_busy[oc->channel])
++                      oc->shadow_dirty = false;
++      }
++
++      for (i = 0; i < num_mgrs; ++i) {
++              mc = &dss_cache.manager_cache[i];
++              if (!mgr_busy[i])
++                      mc->shadow_dirty = false;
++      }
++
++      r = configure_dispc();
++      if (r == 1)
++              goto end;
++
++      /* re-read busy flags */
++      mgr_busy[0] = dispc_go_busy(0);
++      mgr_busy[1] = dispc_go_busy(1);
++
++      /* keep running as long as there are busy managers, so that
++       * we can collect overlay-applied information */
++      for (i = 0; i < num_mgrs; ++i) {
++              if (mgr_busy[i])
++                      goto end;
++      }
++
++      omap_dispc_unregister_isr(dss_apply_irq_handler, NULL,
++                      DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_ODD |
++                      DISPC_IRQ_EVSYNC_EVEN);
++      dss_cache.irq_enabled = false;
++
++end:
++      spin_unlock(&dss_cache.lock);
++}
++
++static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
++{
++      struct overlay_cache_data *oc;
++      struct manager_cache_data *mc;
++      int i;
++      struct omap_overlay *ovl;
++      int num_planes_enabled = 0;
++      bool use_fifomerge;
++      unsigned long flags;
++      int r;
++
++      DSSDBG("omap_dss_mgr_apply(%s)\n", mgr->name);
++
++      spin_lock_irqsave(&dss_cache.lock, flags);
++
++      /* Configure overlays */
++      for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
++              struct omap_dss_device *dssdev;
++
++              ovl = omap_dss_get_overlay(i);
++
++              if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
++                      continue;
++
++              oc = &dss_cache.overlay_cache[ovl->id];
++
++              if (!overlay_enabled(ovl)) {
++                      if (oc->enabled) {
++                              oc->enabled = false;
++                              oc->dirty = true;
++                      }
++                      continue;
++              }
++
++              if (!ovl->info_dirty) {
++                      if (oc->enabled)
++                              ++num_planes_enabled;
++                      continue;
++              }
++
++              dssdev = ovl->manager->device;
++
++              if (dss_check_overlay(ovl, dssdev)) {
++                      if (oc->enabled) {
++                              oc->enabled = false;
++                              oc->dirty = true;
++                      }
++                      continue;
++              }
++
++              ovl->info_dirty = false;
++              oc->dirty = true;
++
++              oc->paddr = ovl->info.paddr;
++              oc->vaddr = ovl->info.vaddr;
++              oc->screen_width = ovl->info.screen_width;
++              oc->width = ovl->info.width;
++              oc->height = ovl->info.height;
++              oc->color_mode = ovl->info.color_mode;
++              oc->rotation = ovl->info.rotation;
++              oc->rotation_type = ovl->info.rotation_type;
++              oc->mirror = ovl->info.mirror;
++              oc->pos_x = ovl->info.pos_x;
++              oc->pos_y = ovl->info.pos_y;
++              oc->out_width = ovl->info.out_width;
++              oc->out_height = ovl->info.out_height;
++              oc->global_alpha = ovl->info.global_alpha;
++
++              oc->replication =
++                      dss_use_replication(dssdev, ovl->info.color_mode);
++
++              oc->ilace = dssdev->type == OMAP_DISPLAY_TYPE_VENC;
++
++              oc->channel = ovl->manager->id;
++
++              oc->enabled = true;
++
++              oc->manual_update =
++                      dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE &&
++                      dssdev->get_update_mode(dssdev) != OMAP_DSS_UPDATE_AUTO;
++
++              ++num_planes_enabled;
++      }
++
++      /* Configure managers */
++      list_for_each_entry(mgr, &manager_list, list) {
++              struct omap_dss_device *dssdev;
++
++              if (!(mgr->caps & OMAP_DSS_OVL_MGR_CAP_DISPC))
++                      continue;
++
++              mc = &dss_cache.manager_cache[mgr->id];
++
++              if (mgr->device_changed) {
++                      mgr->device_changed = false;
++                      mgr->info_dirty  = true;
++              }
++
++              if (!mgr->info_dirty)
++                      continue;
++
++              if (!mgr->device)
++                      continue;
++
++              dssdev = mgr->device;
++
++              mgr->info_dirty = false;
++              mc->dirty = true;
++
++              mc->default_color = mgr->info.default_color;
++              mc->trans_key_type = mgr->info.trans_key_type;
++              mc->trans_key = mgr->info.trans_key;
++              mc->trans_enabled = mgr->info.trans_enabled;
++              mc->alpha_enabled = mgr->info.alpha_enabled;
++
++              mc->manual_upd_display =
++                      dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
++
++              mc->manual_update =
++                      dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE &&
++                      dssdev->get_update_mode(dssdev) != OMAP_DSS_UPDATE_AUTO;
++      }
++
++      /* XXX TODO: Try to get fifomerge working. The problem is that it
++       * affects both managers, not individually but at the same time. This
++       * means the change has to be well synchronized. I guess the proper way
++       * is to have a two step process for fifo merge:
++       *        fifomerge enable:
++       *             1. disable other planes, leaving one plane enabled
++       *             2. wait until the planes are disabled on HW
++       *             3. config merged fifo thresholds, enable fifomerge
++       *        fifomerge disable:
++       *             1. config unmerged fifo thresholds, disable fifomerge
++       *             2. wait until fifo changes are in HW
++       *             3. enable planes
++       */
++      use_fifomerge = false;
++
++      /* Configure overlay fifos */
++      for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
++              struct omap_dss_device *dssdev;
++              u32 size;
++
++              ovl = omap_dss_get_overlay(i);
++
++              if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
++                      continue;
++
++              oc = &dss_cache.overlay_cache[ovl->id];
++
++              if (!oc->enabled)
++                      continue;
++
++              dssdev = ovl->manager->device;
++
++              size = dispc_get_plane_fifo_size(ovl->id);
++              if (use_fifomerge)
++                      size *= 3;
++
++              switch (dssdev->type) {
++              case OMAP_DISPLAY_TYPE_DPI:
++              case OMAP_DISPLAY_TYPE_DBI:
++              case OMAP_DISPLAY_TYPE_SDI:
++              case OMAP_DISPLAY_TYPE_VENC:
++                      default_get_overlay_fifo_thresholds(ovl->id, size,
++                                      &oc->burst_size, &oc->fifo_low,
++                                      &oc->fifo_high);
++                      break;
++#ifdef CONFIG_OMAP2_DSS_DSI
++              case OMAP_DISPLAY_TYPE_DSI:
++                      dsi_get_overlay_fifo_thresholds(ovl->id, size,
++                                      &oc->burst_size, &oc->fifo_low,
++                                      &oc->fifo_high);
++                      break;
++#endif
++              default:
++                      BUG();
++              }
++      }
++
++      r = 0;
++      dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++      if (!dss_cache.irq_enabled) {
++              r = omap_dispc_register_isr(dss_apply_irq_handler, NULL,
++                              DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_ODD |
++                              DISPC_IRQ_EVSYNC_EVEN);
++              dss_cache.irq_enabled = true;
++      }
++      configure_dispc();
++      dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++      spin_unlock_irqrestore(&dss_cache.lock, flags);
++
++      return r;
++}
++
++static int dss_check_manager(struct omap_overlay_manager *mgr)
++{
++      /* OMAP supports only graphics source transparency color key and alpha
++       * blending simultaneously. See TRM 15.4.2.4.2.2 Alpha Mode */
++
++      if (mgr->info.alpha_enabled && mgr->info.trans_enabled &&
++                      mgr->info.trans_key_type != OMAP_DSS_COLOR_KEY_GFX_DST)
++              return -EINVAL;
++
++      return 0;
++}
++
++static int omap_dss_mgr_set_info(struct omap_overlay_manager *mgr,
++              struct omap_overlay_manager_info *info)
++{
++      int r;
++      struct omap_overlay_manager_info old_info;
++
++      old_info = mgr->info;
++      mgr->info = *info;
++
++      r = dss_check_manager(mgr);
++      if (r) {
++              mgr->info = old_info;
++              return r;
++      }
++
++      mgr->info_dirty = true;
++
++      return 0;
++}
++
++static void omap_dss_mgr_get_info(struct omap_overlay_manager *mgr,
++              struct omap_overlay_manager_info *info)
++{
++      *info = mgr->info;
++}
++
++static void omap_dss_add_overlay_manager(struct omap_overlay_manager *manager)
++{
++      ++num_managers;
++      list_add_tail(&manager->list, &manager_list);
++}
++
++int dss_init_overlay_managers(struct platform_device *pdev)
++{
++      int i, r;
++
++      spin_lock_init(&dss_cache.lock);
++
++      INIT_LIST_HEAD(&manager_list);
++
++      num_managers = 0;
++
++      for (i = 0; i < 2; ++i) {
++              struct omap_overlay_manager *mgr;
++              mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
++
++              BUG_ON(mgr == NULL);
++
++              switch (i) {
++              case 0:
++                      mgr->name = "lcd";
++                      mgr->id = OMAP_DSS_CHANNEL_LCD;
++                      mgr->supported_displays =
++                              OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
++                              OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI;
++                      break;
++              case 1:
++                      mgr->name = "tv";
++                      mgr->id = OMAP_DSS_CHANNEL_DIGIT;
++                      mgr->supported_displays = OMAP_DISPLAY_TYPE_VENC;
++                      break;
++              }
++
++              mgr->set_device = &omap_dss_set_device;
++              mgr->unset_device = &omap_dss_unset_device;
++              mgr->apply = &omap_dss_mgr_apply;
++              mgr->set_manager_info = &omap_dss_mgr_set_info;
++              mgr->get_manager_info = &omap_dss_mgr_get_info;
++              mgr->wait_for_go = &dss_mgr_wait_for_go;
++
++              mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC;
++
++              dss_overlay_setup_dispc_manager(mgr);
++
++              omap_dss_add_overlay_manager(mgr);
++
++              r = kobject_init_and_add(&mgr->kobj, &manager_ktype,
++                              &pdev->dev.kobj, "manager%d", i);
++
++              if (r) {
++                      DSSERR("failed to create sysfs file\n");
++                      continue;
++              }
++      }
++
++#ifdef L4_EXAMPLE
++      {
++              int omap_dss_mgr_apply_l4(struct omap_overlay_manager *mgr)
++              {
++                      DSSDBG("omap_dss_mgr_apply_l4(%s)\n", mgr->name);
++
++                      return 0;
++              }
++
++              struct omap_overlay_manager *mgr;
++              mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
++
++              BUG_ON(mgr == NULL);
++
++              mgr->name = "l4";
++              mgr->supported_displays =
++                      OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI;
++
++              mgr->set_device = &omap_dss_set_device;
++              mgr->unset_device = &omap_dss_unset_device;
++              mgr->apply = &omap_dss_mgr_apply_l4;
++              mgr->set_manager_info = &omap_dss_mgr_set_info;
++              mgr->get_manager_info = &omap_dss_mgr_get_info;
++
++              dss_overlay_setup_l4_manager(mgr);
++
++              omap_dss_add_overlay_manager(mgr);
++
++              r = kobject_init_and_add(&mgr->kobj, &manager_ktype,
++                              &pdev->dev.kobj, "managerl4");
++
++              if (r)
++                      DSSERR("failed to create sysfs file\n");
++      }
++#endif
++
++      return 0;
++}
++
++void dss_uninit_overlay_managers(struct platform_device *pdev)
++{
++      struct omap_overlay_manager *mgr;
++
++      while (!list_empty(&manager_list)) {
++              mgr = list_first_entry(&manager_list,
++                              struct omap_overlay_manager, list);
++              list_del(&mgr->list);
++              kobject_del(&mgr->kobj);
++              kobject_put(&mgr->kobj);
++              kfree(mgr);
++      }
++
++      num_managers = 0;
++}
++
++int omap_dss_get_num_overlay_managers(void)
++{
++      return num_managers;
++}
++EXPORT_SYMBOL(omap_dss_get_num_overlay_managers);
++
++struct omap_overlay_manager *omap_dss_get_overlay_manager(int num)
++{
++      int i = 0;
++      struct omap_overlay_manager *mgr;
++
++      list_for_each_entry(mgr, &manager_list, list) {
++              if (i++ == num)
++                      return mgr;
++      }
++
++      return NULL;
++}
++EXPORT_SYMBOL(omap_dss_get_overlay_manager);
++
+diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c
+new file mode 100644
+index 0000000..c7cb81b
+--- /dev/null
++++ b/drivers/video/omap2/dss/overlay.c
+@@ -0,0 +1,673 @@
++/*
++ * linux/drivers/video/omap2/dss/overlay.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "OVERLAY"
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/err.h>
++#include <linux/sysfs.h>
++#include <linux/kobject.h>
++#include <linux/platform_device.h>
++#include <linux/delay.h>
++
++#include <mach/display.h>
++
++#include "dss.h"
++
++static int num_overlays;
++static struct list_head overlay_list;
++
++static ssize_t overlay_name_show(struct omap_overlay *ovl, char *buf)
++{
++      return snprintf(buf, PAGE_SIZE, "%s\n", ovl->name);
++}
++
++static ssize_t overlay_manager_show(struct omap_overlay *ovl, char *buf)
++{
++      return snprintf(buf, PAGE_SIZE, "%s\n",
++                      ovl->manager ? ovl->manager->name : "<none>");
++}
++
++static ssize_t overlay_manager_store(struct omap_overlay *ovl, const char *buf,
++              size_t size)
++{
++      int i, r;
++      struct omap_overlay_manager *mgr = NULL;
++      struct omap_overlay_manager *old_mgr;
++      int len = size;
++
++      if (buf[size-1] == '\n')
++              --len;
++
++      if (len > 0) {
++              for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
++                      mgr = omap_dss_get_overlay_manager(i);
++
++                      if (strncmp(buf, mgr->name, len) == 0)
++                              break;
++
++                      mgr = NULL;
++              }
++      }
++
++      if (len > 0 && mgr == NULL)
++              return -EINVAL;
++
++      if (mgr)
++              DSSDBG("manager %s found\n", mgr->name);
++
++      if (mgr == ovl->manager)
++              return size;
++
++      old_mgr = ovl->manager;
++
++      /* detach old manager */
++      if (old_mgr) {
++              r = ovl->unset_manager(ovl);
++              if (r) {
++                      DSSERR("detach failed\n");
++                      return r;
++              }
++
++              r = old_mgr->apply(old_mgr);
++              if (r)
++                      return r;
++      }
++
++      if (mgr) {
++              r = ovl->set_manager(ovl, mgr);
++              if (r) {
++                      DSSERR("Failed to attach overlay\n");
++                      return r;
++              }
++
++              r = mgr->apply(mgr);
++              if (r)
++                      return r;
++      }
++
++      return size;
++}
++
++static ssize_t overlay_input_size_show(struct omap_overlay *ovl, char *buf)
++{
++      return snprintf(buf, PAGE_SIZE, "%d,%d\n",
++                      ovl->info.width, ovl->info.height);
++}
++
++static ssize_t overlay_screen_width_show(struct omap_overlay *ovl, char *buf)
++{
++      return snprintf(buf, PAGE_SIZE, "%d\n", ovl->info.screen_width);
++}
++
++static ssize_t overlay_position_show(struct omap_overlay *ovl, char *buf)
++{
++      return snprintf(buf, PAGE_SIZE, "%d,%d\n",
++                      ovl->info.pos_x, ovl->info.pos_y);
++}
++
++static ssize_t overlay_position_store(struct omap_overlay *ovl,
++              const char *buf, size_t size)
++{
++      int r;
++      char *last;
++      struct omap_overlay_info info;
++
++      ovl->get_overlay_info(ovl, &info);
++
++      info.pos_x = simple_strtoul(buf, &last, 10);
++      ++last;
++      if (last - buf >= size)
++              return -EINVAL;
++
++      info.pos_y = simple_strtoul(last, &last, 10);
++
++      r = ovl->set_overlay_info(ovl, &info);
++      if (r)
++              return r;
++
++      if (ovl->manager) {
++              r = ovl->manager->apply(ovl->manager);
++              if (r)
++                      return r;
++      }
++
++      return size;
++}
++
++static ssize_t overlay_output_size_show(struct omap_overlay *ovl, char *buf)
++{
++      return snprintf(buf, PAGE_SIZE, "%d,%d\n",
++                      ovl->info.out_width, ovl->info.out_height);
++}
++
++static ssize_t overlay_output_size_store(struct omap_overlay *ovl,
++              const char *buf, size_t size)
++{
++      int r;
++      char *last;
++      struct omap_overlay_info info;
++
++      ovl->get_overlay_info(ovl, &info);
++
++      info.out_width = simple_strtoul(buf, &last, 10);
++      ++last;
++      if (last - buf >= size)
++              return -EINVAL;
++
++      info.out_height = simple_strtoul(last, &last, 10);
++
++      r = ovl->set_overlay_info(ovl, &info);
++      if (r)
++              return r;
++
++      if (ovl->manager) {
++              r = ovl->manager->apply(ovl->manager);
++              if (r)
++                      return r;
++      }
++
++      return size;
++}
++
++static ssize_t overlay_enabled_show(struct omap_overlay *ovl, char *buf)
++{
++      return snprintf(buf, PAGE_SIZE, "%d\n", ovl->info.enabled);
++}
++
++static ssize_t overlay_enabled_store(struct omap_overlay *ovl, const char *buf,
++              size_t size)
++{
++      int r;
++      struct omap_overlay_info info;
++
++      ovl->get_overlay_info(ovl, &info);
++
++      info.enabled = simple_strtoul(buf, NULL, 10);
++
++      r = ovl->set_overlay_info(ovl, &info);
++      if (r)
++              return r;
++
++      if (ovl->manager) {
++              r = ovl->manager->apply(ovl->manager);
++              if (r)
++                      return r;
++      }
++
++      return size;
++}
++
++static ssize_t overlay_global_alpha_show(struct omap_overlay *ovl, char *buf)
++{
++      return snprintf(buf, PAGE_SIZE, "%d\n",
++                      ovl->info.global_alpha);
++}
++
++static ssize_t overlay_global_alpha_store(struct omap_overlay *ovl,
++              const char *buf, size_t size)
++{
++      int r;
++      struct omap_overlay_info info;
++
++      ovl->get_overlay_info(ovl, &info);
++
++      /* Video1 plane does not support global alpha
++       * to always make it 255 completely opaque
++       */
++      if (ovl->id == OMAP_DSS_VIDEO1)
++              info.global_alpha = 255;
++      else
++              info.global_alpha = simple_strtoul(buf, NULL, 10);
++
++      r = ovl->set_overlay_info(ovl, &info);
++      if (r)
++              return r;
++
++      if (ovl->manager) {
++              r = ovl->manager->apply(ovl->manager);
++              if (r)
++                      return r;
++      }
++
++      return size;
++}
++
++struct overlay_attribute {
++      struct attribute attr;
++      ssize_t (*show)(struct omap_overlay *, char *);
++      ssize_t (*store)(struct omap_overlay *, const char *, size_t);
++};
++
++#define OVERLAY_ATTR(_name, _mode, _show, _store) \
++      struct overlay_attribute overlay_attr_##_name = \
++      __ATTR(_name, _mode, _show, _store)
++
++static OVERLAY_ATTR(name, S_IRUGO, overlay_name_show, NULL);
++static OVERLAY_ATTR(manager, S_IRUGO|S_IWUSR,
++              overlay_manager_show, overlay_manager_store);
++static OVERLAY_ATTR(input_size, S_IRUGO, overlay_input_size_show, NULL);
++static OVERLAY_ATTR(screen_width, S_IRUGO, overlay_screen_width_show, NULL);
++static OVERLAY_ATTR(position, S_IRUGO|S_IWUSR,
++              overlay_position_show, overlay_position_store);
++static OVERLAY_ATTR(output_size, S_IRUGO|S_IWUSR,
++              overlay_output_size_show, overlay_output_size_store);
++static OVERLAY_ATTR(enabled, S_IRUGO|S_IWUSR,
++              overlay_enabled_show, overlay_enabled_store);
++static OVERLAY_ATTR(global_alpha, S_IRUGO|S_IWUSR,
++              overlay_global_alpha_show, overlay_global_alpha_store);
++
++static struct attribute *overlay_sysfs_attrs[] = {
++      &overlay_attr_name.attr,
++      &overlay_attr_manager.attr,
++      &overlay_attr_input_size.attr,
++      &overlay_attr_screen_width.attr,
++      &overlay_attr_position.attr,
++      &overlay_attr_output_size.attr,
++      &overlay_attr_enabled.attr,
++      &overlay_attr_global_alpha.attr,
++      NULL
++};
++
++static ssize_t overlay_attr_show(struct kobject *kobj, struct attribute *attr,
++              char *buf)
++{
++      struct omap_overlay *overlay;
++      struct overlay_attribute *overlay_attr;
++
++      overlay = container_of(kobj, struct omap_overlay, kobj);
++      overlay_attr = container_of(attr, struct overlay_attribute, attr);
++
++      if (!overlay_attr->show)
++              return -ENOENT;
++
++      return overlay_attr->show(overlay, buf);
++}
++
++static ssize_t overlay_attr_store(struct kobject *kobj, struct attribute *attr,
++              const char *buf, size_t size)
++{
++      struct omap_overlay *overlay;
++      struct overlay_attribute *overlay_attr;
++
++      overlay = container_of(kobj, struct omap_overlay, kobj);
++      overlay_attr = container_of(attr, struct overlay_attribute, attr);
++
++      if (!overlay_attr->store)
++              return -ENOENT;
++
++      return overlay_attr->store(overlay, buf, size);
++}
++
++static struct sysfs_ops overlay_sysfs_ops = {
++      .show = overlay_attr_show,
++      .store = overlay_attr_store,
++};
++
++static struct kobj_type overlay_ktype = {
++      .sysfs_ops = &overlay_sysfs_ops,
++      .default_attrs = overlay_sysfs_attrs,
++};
++
++/* Check if overlay parameters are compatible with display */
++int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev)
++{
++      struct omap_overlay_info *info;
++      u16 outw, outh;
++      u16 dw, dh;
++
++      if (!dssdev)
++              return 0;
++
++      if (!ovl->info.enabled)
++              return 0;
++
++      info = &ovl->info;
++
++      if (info->paddr == 0) {
++              DSSDBG("check_overlay failed: paddr 0\n");
++              return -EINVAL;
++      }
++
++      dssdev->get_resolution(dssdev, &dw, &dh);
++
++      DSSDBG("check_overlay %d: (%d,%d %dx%d -> %dx%d) disp (%dx%d)\n",
++                      ovl->id,
++                      info->pos_x, info->pos_y,
++                      info->width, info->height,
++                      info->out_width, info->out_height,
++                      dw, dh);
++
++      if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) {
++              outw = info->width;
++              outh = info->height;
++      } else {
++              if (info->out_width == 0)
++                      outw = info->width;
++              else
++                      outw = info->out_width;
++
++              if (info->out_height == 0)
++                      outh = info->height;
++              else
++                      outh = info->out_height;
++      }
++
++      if (dw < info->pos_x + outw) {
++              DSSDBG("check_overlay failed 1: %d < %d + %d\n",
++                              dw, info->pos_x, outw);
++              return -EINVAL;
++      }
++
++      if (dh < info->pos_y + outh) {
++              DSSDBG("check_overlay failed 2: %d < %d + %d\n",
++                              dh, info->pos_y, outh);
++              return -EINVAL;
++      }
++
++      if ((ovl->supported_modes & info->color_mode) == 0) {
++              DSSERR("overlay doesn't support mode %d\n", info->color_mode);
++              return -EINVAL;
++      }
++
++      return 0;
++}
++
++static int dss_ovl_set_overlay_info(struct omap_overlay *ovl,
++              struct omap_overlay_info *info)
++{
++      int r;
++      struct omap_overlay_info old_info;
++
++      old_info = ovl->info;
++      ovl->info = *info;
++
++      if (ovl->manager) {
++              r = dss_check_overlay(ovl, ovl->manager->device);
++              if (r) {
++                      ovl->info = old_info;
++                      return r;
++              }
++      }
++
++      ovl->info_dirty = true;
++
++      return 0;
++}
++
++static void dss_ovl_get_overlay_info(struct omap_overlay *ovl,
++              struct omap_overlay_info *info)
++{
++      *info = ovl->info;
++}
++
++static int dss_ovl_wait_for_go(struct omap_overlay *ovl)
++{
++      return dss_mgr_wait_for_go_ovl(ovl);
++}
++
++static int omap_dss_set_manager(struct omap_overlay *ovl,
++              struct omap_overlay_manager *mgr)
++{
++      if (!mgr)
++              return -EINVAL;
++
++      if (ovl->manager) {
++              DSSERR("overlay '%s' already has a manager '%s'\n",
++                              ovl->name, ovl->manager->name);
++              return -EINVAL;
++      }
++
++      if (ovl->info.enabled) {
++              DSSERR("overlay has to be disabled to change the manager\n");
++              return -EINVAL;
++      }
++
++      ovl->manager = mgr;
++
++      dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++      /* XXX: on manual update display, in auto update mode, a bug happens
++       * here. When an overlay is first enabled on LCD, then it's disabled,
++       * and the manager is changed to TV, we sometimes get SYNC_LOST_DIGIT
++       * errors. Waiting before changing the channel_out fixes it. I'm
++       * guessing that the overlay is still somehow being used for the LCD,
++       * but I don't understand how or why. */
++      msleep(40);
++      dispc_set_channel_out(ovl->id, mgr->id);
++      dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++      return 0;
++}
++
++static int omap_dss_unset_manager(struct omap_overlay *ovl)
++{
++      int r;
++
++      if (!ovl->manager) {
++              DSSERR("failed to detach overlay: manager not set\n");
++              return -EINVAL;
++      }
++
++      if (ovl->info.enabled) {
++              DSSERR("overlay has to be disabled to unset the manager\n");
++              return -EINVAL;
++      }
++
++      r = ovl->wait_for_go(ovl);
++      if (r)
++              return r;
++
++      ovl->manager = NULL;
++
++      return 0;
++}
++
++int omap_dss_get_num_overlays(void)
++{
++      return num_overlays;
++}
++EXPORT_SYMBOL(omap_dss_get_num_overlays);
++
++struct omap_overlay *omap_dss_get_overlay(int num)
++{
++      int i = 0;
++      struct omap_overlay *ovl;
++
++      list_for_each_entry(ovl, &overlay_list, list) {
++              if (i++ == num)
++                      return ovl;
++      }
++
++      return NULL;
++}
++EXPORT_SYMBOL(omap_dss_get_overlay);
++
++static void omap_dss_add_overlay(struct omap_overlay *overlay)
++{
++      ++num_overlays;
++      list_add_tail(&overlay->list, &overlay_list);
++}
++
++static struct omap_overlay *dispc_overlays[3];
++
++void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr)
++{
++      mgr->num_overlays = 3;
++      mgr->overlays = dispc_overlays;
++}
++
++#ifdef L4_EXAMPLE
++static struct omap_overlay *l4_overlays[1];
++void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr)
++{
++      mgr->num_overlays = 1;
++      mgr->overlays = l4_overlays;
++}
++#endif
++
++void dss_init_overlays(struct platform_device *pdev)
++{
++      int i, r;
++
++      INIT_LIST_HEAD(&overlay_list);
++
++      num_overlays = 0;
++
++      for (i = 0; i < 3; ++i) {
++              struct omap_overlay *ovl;
++              ovl = kzalloc(sizeof(*ovl), GFP_KERNEL);
++
++              BUG_ON(ovl == NULL);
++
++              switch (i) {
++              case 0:
++                      ovl->name = "gfx";
++                      ovl->id = OMAP_DSS_GFX;
++                      ovl->supported_modes = OMAP_DSS_COLOR_GFX_OMAP3;
++                      ovl->caps = OMAP_DSS_OVL_CAP_DISPC;
++                      ovl->info.global_alpha = 255;
++                      break;
++              case 1:
++                      ovl->name = "vid1";
++                      ovl->id = OMAP_DSS_VIDEO1;
++                      ovl->supported_modes = OMAP_DSS_COLOR_VID_OMAP3;
++                      ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
++                              OMAP_DSS_OVL_CAP_DISPC;
++                      ovl->info.global_alpha = 255;
++                      break;
++              case 2:
++                      ovl->name = "vid2";
++                      ovl->id = OMAP_DSS_VIDEO2;
++                      ovl->supported_modes = OMAP_DSS_COLOR_VID_OMAP3;
++                      ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
++                              OMAP_DSS_OVL_CAP_DISPC;
++                      ovl->info.global_alpha = 255;
++                      break;
++              }
++
++              ovl->set_manager = &omap_dss_set_manager;
++              ovl->unset_manager = &omap_dss_unset_manager;
++              ovl->set_overlay_info = &dss_ovl_set_overlay_info;
++              ovl->get_overlay_info = &dss_ovl_get_overlay_info;
++              ovl->wait_for_go = &dss_ovl_wait_for_go;
++
++              omap_dss_add_overlay(ovl);
++
++              r = kobject_init_and_add(&ovl->kobj, &overlay_ktype,
++                              &pdev->dev.kobj, "overlay%d", i);
++
++              if (r) {
++                      DSSERR("failed to create sysfs file\n");
++                      continue;
++              }
++
++              dispc_overlays[i] = ovl;
++      }
++
++#ifdef L4_EXAMPLE
++      {
++              struct omap_overlay *ovl;
++              ovl = kzalloc(sizeof(*ovl), GFP_KERNEL);
++
++              BUG_ON(ovl == NULL);
++
++              ovl->name = "l4";
++              ovl->supported_modes = OMAP_DSS_COLOR_RGB24U;
++
++              ovl->set_manager = &omap_dss_set_manager;
++              ovl->unset_manager = &omap_dss_unset_manager;
++              ovl->set_overlay_info = &dss_ovl_set_overlay_info;
++              ovl->get_overlay_info = &dss_ovl_get_overlay_info;
++
++              omap_dss_add_overlay(ovl);
++
++              r = kobject_init_and_add(&ovl->kobj, &overlay_ktype,
++                              &pdev->dev.kobj, "overlayl4");
++
++              if (r)
++                      DSSERR("failed to create sysfs file\n");
++
++              l4_overlays[0] = ovl;
++      }
++#endif
++}
++
++/* connect overlays to the new device, if not already connected. if force
++ * selected, connect always. */
++void dss_recheck_connections(struct omap_dss_device *dssdev, bool force)
++{
++      int i;
++      struct omap_overlay_manager *lcd_mgr;
++      struct omap_overlay_manager *tv_mgr;
++      struct omap_overlay_manager *mgr = NULL;
++
++      lcd_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_LCD);
++      tv_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_TV);
++
++      if (dssdev->type != OMAP_DISPLAY_TYPE_VENC) {
++              if (!lcd_mgr->device || force) {
++                      if (lcd_mgr->device)
++                              lcd_mgr->unset_device(lcd_mgr);
++                      lcd_mgr->set_device(lcd_mgr, dssdev);
++                      mgr = lcd_mgr;
++              }
++      }
++
++      if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) {
++              if (!tv_mgr->device || force) {
++                      if (tv_mgr->device)
++                              tv_mgr->unset_device(tv_mgr);
++                      tv_mgr->set_device(tv_mgr, dssdev);
++                      mgr = tv_mgr;
++              }
++      }
++
++      if (mgr) {
++              for (i = 0; i < 3; i++) {
++                      struct omap_overlay *ovl;
++                      ovl = omap_dss_get_overlay(i);
++                      if (!ovl->manager || force) {
++                              if (ovl->manager)
++                                      omap_dss_unset_manager(ovl);
++                              omap_dss_set_manager(ovl, mgr);
++                      }
++              }
++      }
++}
++
++void dss_uninit_overlays(struct platform_device *pdev)
++{
++      struct omap_overlay *ovl;
++
++      while (!list_empty(&overlay_list)) {
++              ovl = list_first_entry(&overlay_list,
++                              struct omap_overlay, list);
++              list_del(&ovl->list);
++              kobject_del(&ovl->kobj);
++              kobject_put(&ovl->kobj);
++              kfree(ovl);
++      }
++
++      num_overlays = 0;
++}
++
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-2.6.31/dss2/0009-OMAP-DSS2-DISPC.patch b/recipes/linux/linux-omap-2.6.31/dss2/0009-OMAP-DSS2-DISPC.patch
new file mode 100644 (file)
index 0000000..a558223
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.31/dss2/0009-OMAP-DSS2-DISPC.patch
@@ -0,0 +1,3204 @@
+From 8ec6585980444513ee55fbdf462dc36ca5fcbef4 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Fri, 7 Aug 2009 13:15:32 +0300
+Subject: [PATCH 09/18] OMAP: DSS2: DISPC
+
+This file implements DISPC (display controller) block of the OMAP DSS.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ drivers/video/omap2/dss/dispc.c | 3182 +++++++++++++++++++++++++++++++++++++++
+ 1 files changed, 3182 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/video/omap2/dss/dispc.c
+
+diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
+new file mode 100644
+index 0000000..d648475
+--- /dev/null
++++ b/drivers/video/omap2/dss/dispc.c
+@@ -0,0 +1,3182 @@
++/*
++ * linux/drivers/video/omap2/dss/dispc.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "DISPC"
++
++#include <linux/kernel.h>
++#include <linux/dma-mapping.h>
++#include <linux/vmalloc.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/jiffies.h>
++#include <linux/seq_file.h>
++#include <linux/delay.h>
++#include <linux/workqueue.h>
++
++#include <mach/sram.h>
++#include <mach/board.h>
++#include <mach/clock.h>
++
++#include <mach/display.h>
++
++#include "dss.h"
++
++/* DISPC */
++#define DISPC_BASE                    0x48050400
++
++#define DISPC_SZ_REGS                 SZ_1K
++
++struct dispc_reg { u16 idx; };
++
++#define DISPC_REG(idx)                        ((const struct dispc_reg) { idx })
++
++/* DISPC common */
++#define DISPC_REVISION                        DISPC_REG(0x0000)
++#define DISPC_SYSCONFIG                       DISPC_REG(0x0010)
++#define DISPC_SYSSTATUS                       DISPC_REG(0x0014)
++#define DISPC_IRQSTATUS                       DISPC_REG(0x0018)
++#define DISPC_IRQENABLE                       DISPC_REG(0x001C)
++#define DISPC_CONTROL                 DISPC_REG(0x0040)
++#define DISPC_CONFIG                  DISPC_REG(0x0044)
++#define DISPC_CAPABLE                 DISPC_REG(0x0048)
++#define DISPC_DEFAULT_COLOR0          DISPC_REG(0x004C)
++#define DISPC_DEFAULT_COLOR1          DISPC_REG(0x0050)
++#define DISPC_TRANS_COLOR0            DISPC_REG(0x0054)
++#define DISPC_TRANS_COLOR1            DISPC_REG(0x0058)
++#define DISPC_LINE_STATUS             DISPC_REG(0x005C)
++#define DISPC_LINE_NUMBER             DISPC_REG(0x0060)
++#define DISPC_TIMING_H                        DISPC_REG(0x0064)
++#define DISPC_TIMING_V                        DISPC_REG(0x0068)
++#define DISPC_POL_FREQ                        DISPC_REG(0x006C)
++#define DISPC_DIVISOR                 DISPC_REG(0x0070)
++#define DISPC_GLOBAL_ALPHA            DISPC_REG(0x0074)
++#define DISPC_SIZE_DIG                        DISPC_REG(0x0078)
++#define DISPC_SIZE_LCD                        DISPC_REG(0x007C)
++
++/* DISPC GFX plane */
++#define DISPC_GFX_BA0                 DISPC_REG(0x0080)
++#define DISPC_GFX_BA1                 DISPC_REG(0x0084)
++#define DISPC_GFX_POSITION            DISPC_REG(0x0088)
++#define DISPC_GFX_SIZE                        DISPC_REG(0x008C)
++#define DISPC_GFX_ATTRIBUTES          DISPC_REG(0x00A0)
++#define DISPC_GFX_FIFO_THRESHOLD      DISPC_REG(0x00A4)
++#define DISPC_GFX_FIFO_SIZE_STATUS    DISPC_REG(0x00A8)
++#define DISPC_GFX_ROW_INC             DISPC_REG(0x00AC)
++#define DISPC_GFX_PIXEL_INC           DISPC_REG(0x00B0)
++#define DISPC_GFX_WINDOW_SKIP         DISPC_REG(0x00B4)
++#define DISPC_GFX_TABLE_BA            DISPC_REG(0x00B8)
++
++#define DISPC_DATA_CYCLE1             DISPC_REG(0x01D4)
++#define DISPC_DATA_CYCLE2             DISPC_REG(0x01D8)
++#define DISPC_DATA_CYCLE3             DISPC_REG(0x01DC)
++
++#define DISPC_CPR_COEF_R              DISPC_REG(0x0220)
++#define DISPC_CPR_COEF_G              DISPC_REG(0x0224)
++#define DISPC_CPR_COEF_B              DISPC_REG(0x0228)
++
++#define DISPC_GFX_PRELOAD             DISPC_REG(0x022C)
++
++/* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
++#define DISPC_VID_REG(n, idx)         DISPC_REG(0x00BC + (n)*0x90 + idx)
++
++#define DISPC_VID_BA0(n)              DISPC_VID_REG(n, 0x0000)
++#define DISPC_VID_BA1(n)              DISPC_VID_REG(n, 0x0004)
++#define DISPC_VID_POSITION(n)         DISPC_VID_REG(n, 0x0008)
++#define DISPC_VID_SIZE(n)             DISPC_VID_REG(n, 0x000C)
++#define DISPC_VID_ATTRIBUTES(n)               DISPC_VID_REG(n, 0x0010)
++#define DISPC_VID_FIFO_THRESHOLD(n)   DISPC_VID_REG(n, 0x0014)
++#define DISPC_VID_FIFO_SIZE_STATUS(n) DISPC_VID_REG(n, 0x0018)
++#define DISPC_VID_ROW_INC(n)          DISPC_VID_REG(n, 0x001C)
++#define DISPC_VID_PIXEL_INC(n)                DISPC_VID_REG(n, 0x0020)
++#define DISPC_VID_FIR(n)              DISPC_VID_REG(n, 0x0024)
++#define DISPC_VID_PICTURE_SIZE(n)     DISPC_VID_REG(n, 0x0028)
++#define DISPC_VID_ACCU0(n)            DISPC_VID_REG(n, 0x002C)
++#define DISPC_VID_ACCU1(n)            DISPC_VID_REG(n, 0x0030)
++
++/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
++#define DISPC_VID_FIR_COEF_H(n, i)    DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
++/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
++#define DISPC_VID_FIR_COEF_HV(n, i)   DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
++/* coef index i = {0, 1, 2, 3, 4} */
++#define DISPC_VID_CONV_COEF(n, i)     DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
++/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
++#define DISPC_VID_FIR_COEF_V(n, i)    DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
++
++#define DISPC_VID_PRELOAD(n)          DISPC_REG(0x230 + (n)*0x04)
++
++
++#define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
++                                       DISPC_IRQ_OCP_ERR | \
++                                       DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
++                                       DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
++                                       DISPC_IRQ_SYNC_LOST | \
++                                       DISPC_IRQ_SYNC_LOST_DIGIT)
++
++#define DISPC_MAX_NR_ISRS             8
++
++struct omap_dispc_isr_data {
++      omap_dispc_isr_t        isr;
++      void                    *arg;
++      u32                     mask;
++};
++
++#define REG_GET(idx, start, end) \
++      FLD_GET(dispc_read_reg(idx), start, end)
++
++#define REG_FLD_MOD(idx, val, start, end)                             \
++      dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
++
++static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
++      DISPC_VID_ATTRIBUTES(0),
++      DISPC_VID_ATTRIBUTES(1) };
++
++static struct {
++      void __iomem    *base;
++
++      struct clk      *dpll4_m4_ck;
++
++      unsigned long   cache_req_pck;
++      unsigned long   cache_prate;
++      struct dispc_clock_info cache_cinfo;
++
++      u32     fifo_size[3];
++
++      spinlock_t irq_lock;
++      u32 irq_error_mask;
++      struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
++      u32 error_irqs;
++      struct work_struct error_work;
++
++      u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
++} dispc;
++
++static void _omap_dispc_set_irqs(void);
++
++static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
++{
++      __raw_writel(val, dispc.base + idx.idx);
++}
++
++static inline u32 dispc_read_reg(const struct dispc_reg idx)
++{
++      return __raw_readl(dispc.base + idx.idx);
++}
++
++#define SR(reg) \
++      dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
++#define RR(reg) \
++      dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
++
++void dispc_save_context(void)
++{
++      if (cpu_is_omap24xx())
++              return;
++
++      SR(SYSCONFIG);
++      SR(IRQENABLE);
++      SR(CONTROL);
++      SR(CONFIG);
++      SR(DEFAULT_COLOR0);
++      SR(DEFAULT_COLOR1);
++      SR(TRANS_COLOR0);
++      SR(TRANS_COLOR1);
++      SR(LINE_NUMBER);
++      SR(TIMING_H);
++      SR(TIMING_V);
++      SR(POL_FREQ);
++      SR(DIVISOR);
++      SR(GLOBAL_ALPHA);
++      SR(SIZE_DIG);
++      SR(SIZE_LCD);
++
++      SR(GFX_BA0);
++      SR(GFX_BA1);
++      SR(GFX_POSITION);
++      SR(GFX_SIZE);
++      SR(GFX_ATTRIBUTES);
++      SR(GFX_FIFO_THRESHOLD);
++      SR(GFX_ROW_INC);
++      SR(GFX_PIXEL_INC);
++      SR(GFX_WINDOW_SKIP);
++      SR(GFX_TABLE_BA);
++
++      SR(DATA_CYCLE1);
++      SR(DATA_CYCLE2);
++      SR(DATA_CYCLE3);
++
++      SR(CPR_COEF_R);
++      SR(CPR_COEF_G);
++      SR(CPR_COEF_B);
++
++      SR(GFX_PRELOAD);
++
++      /* VID1 */
++      SR(VID_BA0(0));
++      SR(VID_BA1(0));
++      SR(VID_POSITION(0));
++      SR(VID_SIZE(0));
++      SR(VID_ATTRIBUTES(0));
++      SR(VID_FIFO_THRESHOLD(0));
++      SR(VID_ROW_INC(0));
++      SR(VID_PIXEL_INC(0));
++      SR(VID_FIR(0));
++      SR(VID_PICTURE_SIZE(0));
++      SR(VID_ACCU0(0));
++      SR(VID_ACCU1(0));
++
++      SR(VID_FIR_COEF_H(0, 0));
++      SR(VID_FIR_COEF_H(0, 1));
++      SR(VID_FIR_COEF_H(0, 2));
++      SR(VID_FIR_COEF_H(0, 3));
++      SR(VID_FIR_COEF_H(0, 4));
++      SR(VID_FIR_COEF_H(0, 5));
++      SR(VID_FIR_COEF_H(0, 6));
++      SR(VID_FIR_COEF_H(0, 7));
++
++      SR(VID_FIR_COEF_HV(0, 0));
++      SR(VID_FIR_COEF_HV(0, 1));
++      SR(VID_FIR_COEF_HV(0, 2));
++      SR(VID_FIR_COEF_HV(0, 3));
++      SR(VID_FIR_COEF_HV(0, 4));
++      SR(VID_FIR_COEF_HV(0, 5));
++      SR(VID_FIR_COEF_HV(0, 6));
++      SR(VID_FIR_COEF_HV(0, 7));
++
++      SR(VID_CONV_COEF(0, 0));
++      SR(VID_CONV_COEF(0, 1));
++      SR(VID_CONV_COEF(0, 2));
++      SR(VID_CONV_COEF(0, 3));
++      SR(VID_CONV_COEF(0, 4));
++
++      SR(VID_FIR_COEF_V(0, 0));
++      SR(VID_FIR_COEF_V(0, 1));
++      SR(VID_FIR_COEF_V(0, 2));
++      SR(VID_FIR_COEF_V(0, 3));
++      SR(VID_FIR_COEF_V(0, 4));
++      SR(VID_FIR_COEF_V(0, 5));
++      SR(VID_FIR_COEF_V(0, 6));
++      SR(VID_FIR_COEF_V(0, 7));
++
++      SR(VID_PRELOAD(0));
++
++      /* VID2 */
++      SR(VID_BA0(1));
++      SR(VID_BA1(1));
++      SR(VID_POSITION(1));
++      SR(VID_SIZE(1));
++      SR(VID_ATTRIBUTES(1));
++      SR(VID_FIFO_THRESHOLD(1));
++      SR(VID_ROW_INC(1));
++      SR(VID_PIXEL_INC(1));
++      SR(VID_FIR(1));
++      SR(VID_PICTURE_SIZE(1));
++      SR(VID_ACCU0(1));
++      SR(VID_ACCU1(1));
++
++      SR(VID_FIR_COEF_H(1, 0));
++      SR(VID_FIR_COEF_H(1, 1));
++      SR(VID_FIR_COEF_H(1, 2));
++      SR(VID_FIR_COEF_H(1, 3));
++      SR(VID_FIR_COEF_H(1, 4));
++      SR(VID_FIR_COEF_H(1, 5));
++      SR(VID_FIR_COEF_H(1, 6));
++      SR(VID_FIR_COEF_H(1, 7));
++
++      SR(VID_FIR_COEF_HV(1, 0));
++      SR(VID_FIR_COEF_HV(1, 1));
++      SR(VID_FIR_COEF_HV(1, 2));
++      SR(VID_FIR_COEF_HV(1, 3));
++      SR(VID_FIR_COEF_HV(1, 4));
++      SR(VID_FIR_COEF_HV(1, 5));
++      SR(VID_FIR_COEF_HV(1, 6));
++      SR(VID_FIR_COEF_HV(1, 7));
++
++      SR(VID_CONV_COEF(1, 0));
++      SR(VID_CONV_COEF(1, 1));
++      SR(VID_CONV_COEF(1, 2));
++      SR(VID_CONV_COEF(1, 3));
++      SR(VID_CONV_COEF(1, 4));
++
++      SR(VID_FIR_COEF_V(1, 0));
++      SR(VID_FIR_COEF_V(1, 1));
++      SR(VID_FIR_COEF_V(1, 2));
++      SR(VID_FIR_COEF_V(1, 3));
++      SR(VID_FIR_COEF_V(1, 4));
++      SR(VID_FIR_COEF_V(1, 5));
++      SR(VID_FIR_COEF_V(1, 6));
++      SR(VID_FIR_COEF_V(1, 7));
++
++      SR(VID_PRELOAD(1));
++}
++
++void dispc_restore_context(void)
++{
++      RR(SYSCONFIG);
++      RR(IRQENABLE);
++      /*RR(CONTROL);*/
++      RR(CONFIG);
++      RR(DEFAULT_COLOR0);
++      RR(DEFAULT_COLOR1);
++      RR(TRANS_COLOR0);
++      RR(TRANS_COLOR1);
++      RR(LINE_NUMBER);
++      RR(TIMING_H);
++      RR(TIMING_V);
++      RR(POL_FREQ);
++      RR(DIVISOR);
++      RR(GLOBAL_ALPHA);
++      RR(SIZE_DIG);
++      RR(SIZE_LCD);
++
++      RR(GFX_BA0);
++      RR(GFX_BA1);
++      RR(GFX_POSITION);
++      RR(GFX_SIZE);
++      RR(GFX_ATTRIBUTES);
++      RR(GFX_FIFO_THRESHOLD);
++      RR(GFX_ROW_INC);
++      RR(GFX_PIXEL_INC);
++      RR(GFX_WINDOW_SKIP);
++      RR(GFX_TABLE_BA);
++
++      RR(DATA_CYCLE1);
++      RR(DATA_CYCLE2);
++      RR(DATA_CYCLE3);
++
++      RR(CPR_COEF_R);
++      RR(CPR_COEF_G);
++      RR(CPR_COEF_B);
++
++      RR(GFX_PRELOAD);
++
++      /* VID1 */
++      RR(VID_BA0(0));
++      RR(VID_BA1(0));
++      RR(VID_POSITION(0));
++      RR(VID_SIZE(0));
++      RR(VID_ATTRIBUTES(0));
++      RR(VID_FIFO_THRESHOLD(0));
++      RR(VID_ROW_INC(0));
++      RR(VID_PIXEL_INC(0));
++      RR(VID_FIR(0));
++      RR(VID_PICTURE_SIZE(0));
++      RR(VID_ACCU0(0));
++      RR(VID_ACCU1(0));
++
++      RR(VID_FIR_COEF_H(0, 0));
++      RR(VID_FIR_COEF_H(0, 1));
++      RR(VID_FIR_COEF_H(0, 2));
++      RR(VID_FIR_COEF_H(0, 3));
++      RR(VID_FIR_COEF_H(0, 4));
++      RR(VID_FIR_COEF_H(0, 5));
++      RR(VID_FIR_COEF_H(0, 6));
++      RR(VID_FIR_COEF_H(0, 7));
++
++      RR(VID_FIR_COEF_HV(0, 0));
++      RR(VID_FIR_COEF_HV(0, 1));
++      RR(VID_FIR_COEF_HV(0, 2));
++      RR(VID_FIR_COEF_HV(0, 3));
++      RR(VID_FIR_COEF_HV(0, 4));
++      RR(VID_FIR_COEF_HV(0, 5));
++      RR(VID_FIR_COEF_HV(0, 6));
++      RR(VID_FIR_COEF_HV(0, 7));
++
++      RR(VID_CONV_COEF(0, 0));
++      RR(VID_CONV_COEF(0, 1));
++      RR(VID_CONV_COEF(0, 2));
++      RR(VID_CONV_COEF(0, 3));
++      RR(VID_CONV_COEF(0, 4));
++
++      RR(VID_FIR_COEF_V(0, 0));
++      RR(VID_FIR_COEF_V(0, 1));
++      RR(VID_FIR_COEF_V(0, 2));
++      RR(VID_FIR_COEF_V(0, 3));
++      RR(VID_FIR_COEF_V(0, 4));
++      RR(VID_FIR_COEF_V(0, 5));
++      RR(VID_FIR_COEF_V(0, 6));
++      RR(VID_FIR_COEF_V(0, 7));
++
++      RR(VID_PRELOAD(0));
++
++      /* VID2 */
++      RR(VID_BA0(1));
++      RR(VID_BA1(1));
++      RR(VID_POSITION(1));
++      RR(VID_SIZE(1));
++      RR(VID_ATTRIBUTES(1));
++      RR(VID_FIFO_THRESHOLD(1));
++      RR(VID_ROW_INC(1));
++      RR(VID_PIXEL_INC(1));
++      RR(VID_FIR(1));
++      RR(VID_PICTURE_SIZE(1));
++      RR(VID_ACCU0(1));
++      RR(VID_ACCU1(1));
++
++      RR(VID_FIR_COEF_H(1, 0));
++      RR(VID_FIR_COEF_H(1, 1));
++      RR(VID_FIR_COEF_H(1, 2));
++      RR(VID_FIR_COEF_H(1, 3));
++      RR(VID_FIR_COEF_H(1, 4));
++      RR(VID_FIR_COEF_H(1, 5));
++      RR(VID_FIR_COEF_H(1, 6));
++      RR(VID_FIR_COEF_H(1, 7));
++
++      RR(VID_FIR_COEF_HV(1, 0));
++      RR(VID_FIR_COEF_HV(1, 1));
++      RR(VID_FIR_COEF_HV(1, 2));
++      RR(VID_FIR_COEF_HV(1, 3));
++      RR(VID_FIR_COEF_HV(1, 4));
++      RR(VID_FIR_COEF_HV(1, 5));
++      RR(VID_FIR_COEF_HV(1, 6));
++      RR(VID_FIR_COEF_HV(1, 7));
++
++      RR(VID_CONV_COEF(1, 0));
++      RR(VID_CONV_COEF(1, 1));
++      RR(VID_CONV_COEF(1, 2));
++      RR(VID_CONV_COEF(1, 3));
++      RR(VID_CONV_COEF(1, 4));
++
++      RR(VID_FIR_COEF_V(1, 0));
++      RR(VID_FIR_COEF_V(1, 1));
++      RR(VID_FIR_COEF_V(1, 2));
++      RR(VID_FIR_COEF_V(1, 3));
++      RR(VID_FIR_COEF_V(1, 4));
++      RR(VID_FIR_COEF_V(1, 5));
++      RR(VID_FIR_COEF_V(1, 6));
++      RR(VID_FIR_COEF_V(1, 7));
++
++      RR(VID_PRELOAD(1));
++
++      /* enable last, because LCD & DIGIT enable are here */
++      RR(CONTROL);
++}
++
++#undef SR
++#undef RR
++
++static inline void enable_clocks(bool enable)
++{
++      if (enable)
++              dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++      else
++              dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++}
++
++bool dispc_go_busy(enum omap_channel channel)
++{
++      int bit;
++
++      if (channel == OMAP_DSS_CHANNEL_LCD)
++              bit = 5; /* GOLCD */
++      else
++              bit = 6; /* GODIGIT */
++
++      return REG_GET(DISPC_CONTROL, bit, bit) == 1;
++}
++
++void dispc_go(enum omap_channel channel)
++{
++      int bit;
++
++      enable_clocks(1);
++
++      if (channel == OMAP_DSS_CHANNEL_LCD)
++              bit = 0; /* LCDENABLE */
++      else
++              bit = 1; /* DIGITALENABLE */
++
++      /* if the channel is not enabled, we don't need GO */
++      if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
++              goto end;
++
++      if (channel == OMAP_DSS_CHANNEL_LCD)
++              bit = 5; /* GOLCD */
++      else
++              bit = 6; /* GODIGIT */
++
++      if (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
++              DSSERR("GO bit not down for channel %d\n", channel);
++              goto end;
++      }
++
++      DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
++
++      REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
++end:
++      enable_clocks(0);
++}
++
++static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
++{
++      BUG_ON(plane == OMAP_DSS_GFX);
++
++      dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
++}
++
++static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
++{
++      BUG_ON(plane == OMAP_DSS_GFX);
++
++      dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
++}
++
++static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
++{
++      BUG_ON(plane == OMAP_DSS_GFX);
++
++      dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
++}
++
++static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
++              int vscaleup, int five_taps)
++{
++      /* Coefficients for horizontal up-sampling */
++      static const u32 coef_hup[8] = {
++              0x00800000,
++              0x0D7CF800,
++              0x1E70F5FF,
++              0x335FF5FE,
++              0xF74949F7,
++              0xF55F33FB,
++              0xF5701EFE,
++              0xF87C0DFF,
++      };
++
++      /* Coefficients for horizontal down-sampling */
++      static const u32 coef_hdown[8] = {
++              0x24382400,
++              0x28371FFE,
++              0x2C361BFB,
++              0x303516F9,
++              0x11343311,
++              0x1635300C,
++              0x1B362C08,
++              0x1F372804,
++      };
++
++      /* Coefficients for horizontal and vertical up-sampling */
++      static const u32 coef_hvup[2][8] = {
++              {
++              0x00800000,
++              0x037B02FF,
++              0x0C6F05FE,
++              0x205907FB,
++              0x00404000,
++              0x075920FE,
++              0x056F0CFF,
++              0x027B0300,
++              },
++              {
++              0x00800000,
++              0x0D7CF8FF,
++              0x1E70F5FE,
++              0x335FF5FB,
++              0xF7404000,
++              0xF55F33FE,
++              0xF5701EFF,
++              0xF87C0D00,
++              },
++      };
++
++      /* Coefficients for horizontal and vertical down-sampling */
++      static const u32 coef_hvdown[2][8] = {
++              {
++              0x24382400,
++              0x28391F04,
++              0x2D381B08,
++              0x3237170C,
++              0x123737F7,
++              0x173732F9,
++              0x1B382DFB,
++              0x1F3928FE,
++              },
++              {
++              0x24382400,
++              0x28371F04,
++              0x2C361B08,
++              0x3035160C,
++              0x113433F7,
++              0x163530F9,
++              0x1B362CFB,
++              0x1F3728FE,
++              },
++      };
++
++      /* Coefficients for vertical up-sampling */
++      static const u32 coef_vup[8] = {
++              0x00000000,
++              0x0000FF00,
++              0x0000FEFF,
++              0x0000FBFE,
++              0x000000F7,
++              0x0000FEFB,
++              0x0000FFFE,
++              0x000000FF,
++      };
++
++
++      /* Coefficients for vertical down-sampling */
++      static const u32 coef_vdown[8] = {
++              0x00000000,
++              0x000004FE,
++              0x000008FB,
++              0x00000CF9,
++              0x0000F711,
++              0x0000F90C,
++              0x0000FB08,
++              0x0000FE04,
++      };
++
++      const u32 *h_coef;
++      const u32 *hv_coef;
++      const u32 *hv_coef_mod;
++      const u32 *v_coef;
++      int i;
++
++      if (hscaleup)
++              h_coef = coef_hup;
++      else
++              h_coef = coef_hdown;
++
++      if (vscaleup) {
++              hv_coef = coef_hvup[five_taps];
++              v_coef = coef_vup;
++
++              if (hscaleup)
++                      hv_coef_mod = NULL;
++              else
++                      hv_coef_mod = coef_hvdown[five_taps];
++      } else {
++              hv_coef = coef_hvdown[five_taps];
++              v_coef = coef_vdown;
++
++              if (hscaleup)
++                      hv_coef_mod = coef_hvup[five_taps];
++              else
++                      hv_coef_mod = NULL;
++      }
++
++      for (i = 0; i < 8; i++) {
++              u32 h, hv;
++
++              h = h_coef[i];
++
++              hv = hv_coef[i];
++
++              if (hv_coef_mod) {
++                      hv &= 0xffffff00;
++                      hv |= (hv_coef_mod[i] & 0xff);
++              }
++
++              _dispc_write_firh_reg(plane, i, h);
++              _dispc_write_firhv_reg(plane, i, hv);
++      }
++
++      if (!five_taps)
++              return;
++
++      for (i = 0; i < 8; i++) {
++              u32 v;
++              v = v_coef[i];
++              _dispc_write_firv_reg(plane, i, v);
++      }
++}
++
++static void _dispc_setup_color_conv_coef(void)
++{
++      const struct color_conv_coef {
++              int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
++              int  full_range;
++      }  ctbl_bt601_5 = {
++              298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
++      };
++
++      const struct color_conv_coef *ct;
++
++#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
++
++      ct = &ctbl_bt601_5;
++
++      dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
++      dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy,  ct->rcb));
++      dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
++      dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
++      dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0,       ct->bcb));
++
++      dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
++      dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy,  ct->rcb));
++      dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
++      dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
++      dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0,       ct->bcb));
++
++#undef CVAL
++
++      REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
++      REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
++}
++
++
++static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
++{
++      const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
++              DISPC_VID_BA0(0),
++              DISPC_VID_BA0(1) };
++
++      dispc_write_reg(ba0_reg[plane], paddr);
++}
++
++static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
++{
++      const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
++                                    DISPC_VID_BA1(0),
++                                    DISPC_VID_BA1(1) };
++
++      dispc_write_reg(ba1_reg[plane], paddr);
++}
++
++static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
++{
++      const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
++                                    DISPC_VID_POSITION(0),
++                                    DISPC_VID_POSITION(1) };
++
++      u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
++      dispc_write_reg(pos_reg[plane], val);
++}
++
++static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
++{
++      const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
++                                    DISPC_VID_PICTURE_SIZE(0),
++                                    DISPC_VID_PICTURE_SIZE(1) };
++      u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
++      dispc_write_reg(siz_reg[plane], val);
++}
++
++static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
++{
++      u32 val;
++      const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
++                                    DISPC_VID_SIZE(1) };
++
++      BUG_ON(plane == OMAP_DSS_GFX);
++
++      val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
++      dispc_write_reg(vsi_reg[plane-1], val);
++}
++
++static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
++{
++
++      BUG_ON(plane == OMAP_DSS_VIDEO1);
++
++      if (plane == OMAP_DSS_GFX)
++              REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
++      else if (plane == OMAP_DSS_VIDEO2)
++              REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
++}
++
++static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
++{
++      const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
++                                   DISPC_VID_PIXEL_INC(0),
++                                   DISPC_VID_PIXEL_INC(1) };
++
++      dispc_write_reg(ri_reg[plane], inc);
++}
++
++static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
++{
++      const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
++                                   DISPC_VID_ROW_INC(0),
++                                   DISPC_VID_ROW_INC(1) };
++
++      dispc_write_reg(ri_reg[plane], inc);
++}
++
++static void _dispc_set_color_mode(enum omap_plane plane,
++              enum omap_color_mode color_mode)
++{
++      u32 m = 0;
++
++      switch (color_mode) {
++      case OMAP_DSS_COLOR_CLUT1:
++              m = 0x0; break;
++      case OMAP_DSS_COLOR_CLUT2:
++              m = 0x1; break;
++      case OMAP_DSS_COLOR_CLUT4:
++              m = 0x2; break;
++      case OMAP_DSS_COLOR_CLUT8:
++              m = 0x3; break;
++      case OMAP_DSS_COLOR_RGB12U:
++              m = 0x4; break;
++      case OMAP_DSS_COLOR_ARGB16:
++              m = 0x5; break;
++      case OMAP_DSS_COLOR_RGB16:
++              m = 0x6; break;
++      case OMAP_DSS_COLOR_RGB24U:
++              m = 0x8; break;
++      case OMAP_DSS_COLOR_RGB24P:
++              m = 0x9; break;
++      case OMAP_DSS_COLOR_YUV2:
++              m = 0xa; break;
++      case OMAP_DSS_COLOR_UYVY:
++              m = 0xb; break;
++      case OMAP_DSS_COLOR_ARGB32:
++              m = 0xc; break;
++      case OMAP_DSS_COLOR_RGBA32:
++              m = 0xd; break;
++      case OMAP_DSS_COLOR_RGBX32:
++              m = 0xe; break;
++      default:
++              BUG(); break;
++      }
++
++      REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
++}
++
++static void _dispc_set_channel_out(enum omap_plane plane,
++              enum omap_channel channel)
++{
++      int shift;
++      u32 val;
++
++      switch (plane) {
++      case OMAP_DSS_GFX:
++              shift = 8;
++              break;
++      case OMAP_DSS_VIDEO1:
++      case OMAP_DSS_VIDEO2:
++              shift = 16;
++              break;
++      default:
++              BUG();
++              return;
++      }
++
++      val = dispc_read_reg(dispc_reg_att[plane]);
++      val = FLD_MOD(val, channel, shift, shift);
++      dispc_write_reg(dispc_reg_att[plane], val);
++}
++
++void dispc_set_burst_size(enum omap_plane plane,
++              enum omap_burst_size burst_size)
++{
++      int shift;
++      u32 val;
++
++      enable_clocks(1);
++
++      switch (plane) {
++      case OMAP_DSS_GFX:
++              shift = 6;
++              break;
++      case OMAP_DSS_VIDEO1:
++      case OMAP_DSS_VIDEO2:
++              shift = 14;
++              break;
++      default:
++              BUG();
++              return;
++      }
++
++      val = dispc_read_reg(dispc_reg_att[plane]);
++      val = FLD_MOD(val, burst_size, shift+1, shift);
++      dispc_write_reg(dispc_reg_att[plane], val);
++
++      enable_clocks(0);
++}
++
++static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
++{
++      u32 val;
++
++      BUG_ON(plane == OMAP_DSS_GFX);
++
++      val = dispc_read_reg(dispc_reg_att[plane]);
++      val = FLD_MOD(val, enable, 9, 9);
++      dispc_write_reg(dispc_reg_att[plane], val);
++}
++
++void dispc_enable_replication(enum omap_plane plane, bool enable)
++{
++      int bit;
++
++      if (plane == OMAP_DSS_GFX)
++              bit = 5;
++      else
++              bit = 10;
++
++      enable_clocks(1);
++      REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit);
++      enable_clocks(0);
++}
++
++void dispc_set_lcd_size(u16 width, u16 height)
++{
++      u32 val;
++      BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
++      val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
++      enable_clocks(1);
++      dispc_write_reg(DISPC_SIZE_LCD, val);
++      enable_clocks(0);
++}
++
++void dispc_set_digit_size(u16 width, u16 height)
++{
++      u32 val;
++      BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
++      val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
++      enable_clocks(1);
++      dispc_write_reg(DISPC_SIZE_DIG, val);
++      enable_clocks(0);
++}
++
++static void dispc_read_plane_fifo_sizes(void)
++{
++      const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
++                                    DISPC_VID_FIFO_SIZE_STATUS(0),
++                                    DISPC_VID_FIFO_SIZE_STATUS(1) };
++      u32 size;
++      int plane;
++
++      enable_clocks(1);
++
++      for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
++              if (cpu_is_omap24xx())
++                      size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
++              else if (cpu_is_omap34xx())
++                      size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
++              else
++                      BUG();
++
++              dispc.fifo_size[plane] = size;
++      }
++
++      enable_clocks(0);
++}
++
++u32 dispc_get_plane_fifo_size(enum omap_plane plane)
++{
++      return dispc.fifo_size[plane];
++}
++
++void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
++{
++      const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
++                                     DISPC_VID_FIFO_THRESHOLD(0),
++                                     DISPC_VID_FIFO_THRESHOLD(1) };
++      enable_clocks(1);
++
++      DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
++                      plane,
++                      REG_GET(ftrs_reg[plane], 11, 0),
++                      REG_GET(ftrs_reg[plane], 27, 16),
++                      low, high);
++
++      if (cpu_is_omap24xx())
++              dispc_write_reg(ftrs_reg[plane],
++                              FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
++      else
++              dispc_write_reg(ftrs_reg[plane],
++                              FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
++
++      enable_clocks(0);
++}
++
++void dispc_enable_fifomerge(bool enable)
++{
++      enable_clocks(1);
++
++      DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
++      REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
++
++      enable_clocks(0);
++}
++
++static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
++{
++      u32 val;
++      const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
++                                    DISPC_VID_FIR(1) };
++
++      BUG_ON(plane == OMAP_DSS_GFX);
++
++      if (cpu_is_omap24xx())
++              val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
++      else
++              val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
++      dispc_write_reg(fir_reg[plane-1], val);
++}
++
++static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
++{
++      u32 val;
++      const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
++                                    DISPC_VID_ACCU0(1) };
++
++      BUG_ON(plane == OMAP_DSS_GFX);
++
++      val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
++      dispc_write_reg(ac0_reg[plane-1], val);
++}
++
++static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
++{
++      u32 val;
++      const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
++                                    DISPC_VID_ACCU1(1) };
++
++      BUG_ON(plane == OMAP_DSS_GFX);
++
++      val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
++      dispc_write_reg(ac1_reg[plane-1], val);
++}
++
++
++static void _dispc_set_scaling(enum omap_plane plane,
++              u16 orig_width, u16 orig_height,
++              u16 out_width, u16 out_height,
++              bool ilace, bool five_taps,
++              bool fieldmode)
++{
++      int fir_hinc;
++      int fir_vinc;
++      int hscaleup, vscaleup;
++      int accu0 = 0;
++      int accu1 = 0;
++      u32 l;
++
++      BUG_ON(plane == OMAP_DSS_GFX);
++
++      hscaleup = orig_width <= out_width;
++      vscaleup = orig_height <= out_height;
++
++      _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
++
++      if (!orig_width || orig_width == out_width)
++              fir_hinc = 0;
++      else
++              fir_hinc = 1024 * orig_width / out_width;
++
++      if (!orig_height || orig_height == out_height)
++              fir_vinc = 0;
++      else
++              fir_vinc = 1024 * orig_height / out_height;
++
++      _dispc_set_fir(plane, fir_hinc, fir_vinc);
++
++      l = dispc_read_reg(dispc_reg_att[plane]);
++      l &= ~((0x0f << 5) | (0x3 << 21));
++
++      l |= fir_hinc ? (1 << 5) : 0;
++      l |= fir_vinc ? (1 << 6) : 0;
++
++      l |= hscaleup ? 0 : (1 << 7);
++      l |= vscaleup ? 0 : (1 << 8);
++
++      l |= five_taps ? (1 << 21) : 0;
++      l |= five_taps ? (1 << 22) : 0;
++
++      dispc_write_reg(dispc_reg_att[plane], l);
++
++      /*
++       * field 0 = even field = bottom field
++       * field 1 = odd field = top field
++       */
++      if (ilace && !fieldmode) {
++              accu1 = 0;
++              accu0 = (fir_vinc / 2) & 0x3ff;
++              if (accu0 >= 1024/2) {
++                      accu1 = 1024/2;
++                      accu0 -= accu1;
++              }
++      }
++
++      _dispc_set_vid_accu0(plane, 0, accu0);
++      _dispc_set_vid_accu1(plane, 0, accu1);
++}
++
++static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
++              bool mirroring, enum omap_color_mode color_mode)
++{
++      if (color_mode == OMAP_DSS_COLOR_YUV2 ||
++                      color_mode == OMAP_DSS_COLOR_UYVY) {
++              int vidrot = 0;
++
++              if (mirroring) {
++                      switch (rotation) {
++                      case 0:
++                              vidrot = 2;
++                              break;
++                      case 1:
++                              vidrot = 1;
++                              break;
++                      case 2:
++                              vidrot = 0;
++                              break;
++                      case 3:
++                              vidrot = 3;
++                              break;
++                      }
++              } else {
++                      switch (rotation) {
++                      case 0:
++                              vidrot = 0;
++                              break;
++                      case 1:
++                              vidrot = 1;
++                              break;
++                      case 2:
++                              vidrot = 2;
++                              break;
++                      case 3:
++                              vidrot = 3;
++                              break;
++                      }
++              }
++
++              REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
++
++              if (rotation == 1 || rotation == 3)
++                      REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
++              else
++                      REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
++      } else {
++              REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
++              REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
++      }
++}
++
++static s32 pixinc(int pixels, u8 ps)
++{
++      if (pixels == 1)
++              return 1;
++      else if (pixels > 1)
++              return 1 + (pixels - 1) * ps;
++      else if (pixels < 0)
++              return 1 - (-pixels + 1) * ps;
++      else
++              BUG();
++}
++
++static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
++              u16 screen_width,
++              u16 width, u16 height,
++              enum omap_color_mode color_mode, bool fieldmode,
++              unsigned int field_offset,
++              unsigned *offset0, unsigned *offset1,
++              s32 *row_inc, s32 *pix_inc)
++{
++      u8 ps;
++
++      switch (color_mode) {
++      case OMAP_DSS_COLOR_RGB16:
++      case OMAP_DSS_COLOR_ARGB16:
++              ps = 2;
++              break;
++
++      case OMAP_DSS_COLOR_RGB24P:
++              ps = 3;
++              break;
++
++      case OMAP_DSS_COLOR_RGB24U:
++      case OMAP_DSS_COLOR_ARGB32:
++      case OMAP_DSS_COLOR_RGBA32:
++      case OMAP_DSS_COLOR_RGBX32:
++      case OMAP_DSS_COLOR_YUV2:
++      case OMAP_DSS_COLOR_UYVY:
++              ps = 4;
++              break;
++
++      default:
++              BUG();
++              return;
++      }
++
++      DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
++                      width, height);
++
++      /*
++       * field 0 = even field = bottom field
++       * field 1 = odd field = top field
++       */
++      switch (rotation + mirror * 4) {
++      case 0:
++      case 2:
++              /*
++               * If the pixel format is YUV or UYVY divide the width
++               * of the image by 2 for 0 and 180 degree rotation.
++               */
++              if (color_mode == OMAP_DSS_COLOR_YUV2 ||
++                      color_mode == OMAP_DSS_COLOR_UYVY)
++                      width = width >> 1;
++      case 1:
++      case 3:
++              *offset1 = 0;
++              if (field_offset)
++                      *offset0 = field_offset * screen_width * ps;
++              else
++                      *offset0 = 0;
++
++              *row_inc = pixinc(1 + (screen_width - width) +
++                              (fieldmode ? screen_width : 0),
++                              ps);
++              *pix_inc = pixinc(1, ps);
++              break;
++
++      case 4:
++      case 6:
++              /* If the pixel format is YUV or UYVY divide the width
++               * of the image by 2  for 0 degree and 180 degree
++               */
++              if (color_mode == OMAP_DSS_COLOR_YUV2 ||
++                      color_mode == OMAP_DSS_COLOR_UYVY)
++                      width = width >> 1;
++      case 5:
++      case 7:
++              *offset1 = 0;
++              if (field_offset)
++                      *offset0 = field_offset * screen_width * ps;
++              else
++                      *offset0 = 0;
++              *row_inc = pixinc(1 - (screen_width + width) -
++                              (fieldmode ? screen_width : 0),
++                              ps);
++              *pix_inc = pixinc(1, ps);
++              break;
++
++      default:
++              BUG();
++      }
++}
++
++static void calc_dma_rotation_offset(u8 rotation, bool mirror,
++              u16 screen_width,
++              u16 width, u16 height,
++              enum omap_color_mode color_mode, bool fieldmode,
++              unsigned int field_offset,
++              unsigned *offset0, unsigned *offset1,
++              s32 *row_inc, s32 *pix_inc)
++{
++      u8 ps;
++      u16 fbw, fbh;
++
++      switch (color_mode) {
++      case OMAP_DSS_COLOR_RGB16:
++      case OMAP_DSS_COLOR_ARGB16:
++              ps = 2;
++              break;
++
++      case OMAP_DSS_COLOR_RGB24P:
++              ps = 3;
++              break;
++
++      case OMAP_DSS_COLOR_RGB24U:
++      case OMAP_DSS_COLOR_ARGB32:
++      case OMAP_DSS_COLOR_RGBA32:
++      case OMAP_DSS_COLOR_RGBX32:
++              ps = 4;
++              break;
++
++      case OMAP_DSS_COLOR_YUV2:
++      case OMAP_DSS_COLOR_UYVY:
++              ps = 2;
++              break;
++      default:
++              BUG();
++              return;
++      }
++
++      DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
++                      width, height);
++
++      /* width & height are overlay sizes, convert to fb sizes */
++
++      if (rotation == 0 || rotation == 2) {
++              fbw = width;
++              fbh = height;
++      } else {
++              fbw = height;
++              fbh = width;
++      }
++
++      /*
++       * field 0 = even field = bottom field
++       * field 1 = odd field = top field
++       */
++      switch (rotation + mirror * 4) {
++      case 0:
++              *offset1 = 0;
++              if (field_offset)
++                      *offset0 = *offset1 + field_offset * screen_width * ps;
++              else
++                      *offset0 = *offset1;
++              *row_inc = pixinc(1 + (screen_width - fbw) +
++                              (fieldmode ? screen_width : 0),
++                              ps);
++              *pix_inc = pixinc(1, ps);
++              break;
++      case 1:
++              *offset1 = screen_width * (fbh - 1) * ps;
++              if (field_offset)
++                      *offset0 = *offset1 + field_offset * ps;
++              else
++                      *offset0 = *offset1;
++              *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
++                              (fieldmode ? 1 : 0), ps);
++              *pix_inc = pixinc(-screen_width, ps);
++              break;
++      case 2:
++              *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
++              if (field_offset)
++                      *offset0 = *offset1 - field_offset * screen_width * ps;
++              else
++                      *offset0 = *offset1;
++              *row_inc = pixinc(-1 -
++                              (screen_width - fbw) -
++                              (fieldmode ? screen_width : 0),
++                              ps);
++              *pix_inc = pixinc(-1, ps);
++              break;
++      case 3:
++              *offset1 = (fbw - 1) * ps;
++              if (field_offset)
++                      *offset0 = *offset1 - field_offset * ps;
++              else
++                      *offset0 = *offset1;
++              *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
++                              (fieldmode ? 1 : 0), ps);
++              *pix_inc = pixinc(screen_width, ps);
++              break;
++
++      /* mirroring */
++      case 0 + 4:
++              *offset1 = (fbw - 1) * ps;
++              if (field_offset)
++                      *offset0 = *offset1 + field_offset * screen_width * ps;
++              else
++                      *offset0 = *offset1;
++              *row_inc = pixinc(screen_width * 2 - 1 +
++                              (fieldmode ? screen_width : 0),
++                              ps);
++              *pix_inc = pixinc(-1, ps);
++              break;
++
++      case 1 + 4:
++              *offset1 = 0;
++              if (field_offset)
++                      *offset0 = *offset1 + field_offset * ps;
++              else
++                      *offset0 = *offset1;
++              *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
++                              (fieldmode ? 1 : 0),
++                              ps);
++              *pix_inc = pixinc(screen_width, ps);
++              break;
++
++      case 2 + 4:
++              *offset1 = screen_width * (fbh - 1) * ps;
++              if (field_offset)
++                      *offset0 = *offset1 - field_offset * screen_width * ps;
++              else
++                      *offset0 = *offset1;
++              *row_inc = pixinc(1 - screen_width * 2 -
++                              (fieldmode ? screen_width : 0),
++                              ps);
++              *pix_inc = pixinc(1, ps);
++              break;
++
++      case 3 + 4:
++              *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
++              if (field_offset)
++                      *offset0 = *offset1 - field_offset * ps;
++              else
++                      *offset0 = *offset1;
++              *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
++                              (fieldmode ? 1 : 0),
++                              ps);
++              *pix_inc = pixinc(-screen_width, ps);
++              break;
++
++      default:
++              BUG();
++      }
++}
++
++static unsigned long calc_fclk_five_taps(u16 width, u16 height,
++              u16 out_width, u16 out_height, enum omap_color_mode color_mode)
++{
++      u32 fclk = 0;
++      /* FIXME venc pclk? */
++      u64 tmp, pclk = dispc_pclk_rate();
++
++      if (height > out_height) {
++              /* FIXME get real display PPL */
++              unsigned int ppl = 800;
++
++              tmp = pclk * height * out_width;
++              do_div(tmp, 2 * out_height * ppl);
++              fclk = tmp;
++
++              if (height > 2 * out_height && ppl != out_width) {
++                      tmp = pclk * (height - 2 * out_height) * out_width;
++                      do_div(tmp, 2 * out_height * (ppl - out_width));
++                      fclk = max(fclk, (u32) tmp);
++              }
++      }
++
++      if (width > out_width) {
++              tmp = pclk * width;
++              do_div(tmp, out_width);
++              fclk = max(fclk, (u32) tmp);
++
++              if (color_mode == OMAP_DSS_COLOR_RGB24U)
++                      fclk <<= 1;
++      }
++
++      return fclk;
++}
++
++static unsigned long calc_fclk(u16 width, u16 height,
++              u16 out_width, u16 out_height)
++{
++      unsigned int hf, vf;
++
++      /*
++       * FIXME how to determine the 'A' factor
++       * for the no downscaling case ?
++       */
++
++      if (width > 3 * out_width)
++              hf = 4;
++      else if (width > 2 * out_width)
++              hf = 3;
++      else if (width > out_width)
++              hf = 2;
++      else
++              hf = 1;
++
++      if (height > out_height)
++              vf = 2;
++      else
++              vf = 1;
++
++      /* FIXME venc pclk? */
++      return dispc_pclk_rate() * vf * hf;
++}
++
++void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
++{
++      enable_clocks(1);
++      _dispc_set_channel_out(plane, channel_out);
++      enable_clocks(0);
++}
++
++static int _dispc_setup_plane(enum omap_plane plane,
++              u32 paddr, u16 screen_width,
++              u16 pos_x, u16 pos_y,
++              u16 width, u16 height,
++              u16 out_width, u16 out_height,
++              enum omap_color_mode color_mode,
++              bool ilace,
++              enum omap_dss_rotation_type rotation_type,
++              u8 rotation, int mirror,
++              u8 global_alpha)
++{
++      const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
++      bool five_taps = 0;
++      bool fieldmode = 0;
++      int cconv = 0;
++      unsigned offset0, offset1;
++      s32 row_inc;
++      s32 pix_inc;
++      u16 frame_height = height;
++      unsigned int field_offset = 0;
++
++      if (paddr == 0)
++              return -EINVAL;
++
++      if (ilace && height == out_height)
++              fieldmode = 1;
++
++      if (ilace) {
++              if (fieldmode)
++                      height /= 2;
++              pos_y /= 2;
++              out_height /= 2;
++
++              DSSDBG("adjusting for ilace: height %d, pos_y %d, "
++                              "out_height %d\n",
++                              height, pos_y, out_height);
++      }
++
++      if (plane == OMAP_DSS_GFX) {
++              if (width != out_width || height != out_height)
++                      return -EINVAL;
++
++              switch (color_mode) {
++              case OMAP_DSS_COLOR_ARGB16:
++              case OMAP_DSS_COLOR_RGB16:
++              case OMAP_DSS_COLOR_RGB24P:
++              case OMAP_DSS_COLOR_RGB24U:
++              case OMAP_DSS_COLOR_ARGB32:
++              case OMAP_DSS_COLOR_RGBA32:
++              case OMAP_DSS_COLOR_RGBX32:
++                      break;
++
++              default:
++                      return -EINVAL;
++              }
++      } else {
++              /* video plane */
++
++              unsigned long fclk = 0;
++
++              if (out_width < width / maxdownscale ||
++                 out_width > width * 8)
++                      return -EINVAL;
++
++              if (out_height < height / maxdownscale ||
++                 out_height > height * 8)
++                      return -EINVAL;
++
++              switch (color_mode) {
++              case OMAP_DSS_COLOR_RGB16:
++              case OMAP_DSS_COLOR_RGB24P:
++              case OMAP_DSS_COLOR_RGB24U:
++              case OMAP_DSS_COLOR_RGBX32:
++                      break;
++
++              case OMAP_DSS_COLOR_ARGB16:
++              case OMAP_DSS_COLOR_ARGB32:
++              case OMAP_DSS_COLOR_RGBA32:
++                      if (plane == OMAP_DSS_VIDEO1)
++                              return -EINVAL;
++                      break;
++
++              case OMAP_DSS_COLOR_YUV2:
++              case OMAP_DSS_COLOR_UYVY:
++                      cconv = 1;
++                      break;
++
++              default:
++                      return -EINVAL;
++              }
++
++              /* Must use 5-tap filter? */
++              five_taps = height > out_height * 2;
++
++              if (!five_taps) {
++                      fclk = calc_fclk(width, height,
++                                      out_width, out_height);
++
++                      /* Try 5-tap filter if 3-tap fclk is too high */
++                      if (cpu_is_omap34xx() && height > out_height &&
++                                      fclk > dispc_fclk_rate())
++                              five_taps = true;
++              }
++
++              if (width > (2048 >> five_taps))
++                      return -EINVAL;
++
++              if (five_taps)
++                      fclk = calc_fclk_five_taps(width, height,
++                                      out_width, out_height, color_mode);
++
++              DSSDBG("required fclk rate = %lu Hz\n", fclk);
++              DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
++
++              if (fclk > dispc_fclk_rate()) {
++                      DSSERR("failed to set up scaling, "
++                                      "required fclk rate = %lu Hz, "
++                                      "current fclk rate = %lu Hz\n",
++                                      fclk, dispc_fclk_rate());
++                      return -EINVAL;
++              }
++      }
++
++      if (ilace && !fieldmode) {
++              /*
++               * when downscaling the bottom field may have to start several
++               * source lines below the top field. Unfortunately ACCUI
++               * registers will only hold the fractional part of the offset
++               * so the integer part must be added to the base address of the
++               * bottom field.
++               */
++              if (!height || height == out_height)
++                      field_offset = 0;
++              else
++                      field_offset = height / out_height / 2;
++      }
++
++      /* Fields are independent but interleaved in memory. */
++      if (fieldmode)
++              field_offset = 1;
++
++      if (rotation_type == OMAP_DSS_ROT_DMA)
++              calc_dma_rotation_offset(rotation, mirror,
++                              screen_width, width, frame_height, color_mode,
++                              fieldmode, field_offset,
++                              &offset0, &offset1, &row_inc, &pix_inc);
++      else
++              calc_vrfb_rotation_offset(rotation, mirror,
++                              screen_width, width, frame_height, color_mode,
++                              fieldmode, field_offset,
++                              &offset0, &offset1, &row_inc, &pix_inc);
++
++      DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
++                      offset0, offset1, row_inc, pix_inc);
++
++      _dispc_set_color_mode(plane, color_mode);
++
++      _dispc_set_plane_ba0(plane, paddr + offset0);
++      _dispc_set_plane_ba1(plane, paddr + offset1);
++
++      _dispc_set_row_inc(plane, row_inc);
++      _dispc_set_pix_inc(plane, pix_inc);
++
++      DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
++                      out_width, out_height);
++
++      _dispc_set_plane_pos(plane, pos_x, pos_y);
++
++      _dispc_set_pic_size(plane, width, height);
++
++      if (plane != OMAP_DSS_GFX) {
++              _dispc_set_scaling(plane, width, height,
++                                 out_width, out_height,
++                                 ilace, five_taps, fieldmode);
++              _dispc_set_vid_size(plane, out_width, out_height);
++              _dispc_set_vid_color_conv(plane, cconv);
++      }
++
++      _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
++
++      if (plane != OMAP_DSS_VIDEO1)
++              _dispc_setup_global_alpha(plane, global_alpha);
++
++      return 0;
++}
++
++static void _dispc_enable_plane(enum omap_plane plane, bool enable)
++{
++      REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
++}
++
++static void dispc_disable_isr(void *data, u32 mask)
++{
++      struct completion *compl = data;
++      complete(compl);
++}
++
++static void _enable_lcd_out(bool enable)
++{
++      REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
++}
++
++void dispc_enable_lcd_out(bool enable)
++{
++      struct completion frame_done_completion;
++      bool is_on;
++      int r;
++
++      enable_clocks(1);
++
++      /* When we disable LCD output, we need to wait until frame is done.
++       * Otherwise the DSS is still working, and turning off the clocks
++       * prevents DSS from going to OFF mode */
++      is_on = REG_GET(DISPC_CONTROL, 0, 0);
++
++      if (!enable && is_on) {
++              init_completion(&frame_done_completion);
++
++              r = omap_dispc_register_isr(dispc_disable_isr,
++                              &frame_done_completion,
++                              DISPC_IRQ_FRAMEDONE);
++
++              if (r)
++                      DSSERR("failed to register FRAMEDONE isr\n");
++      }
++
++      _enable_lcd_out(enable);
++
++      if (!enable && is_on) {
++              if (!wait_for_completion_timeout(&frame_done_completion,
++                                      msecs_to_jiffies(100)))
++                      DSSERR("timeout waiting for FRAME DONE\n");
++
++              r = omap_dispc_unregister_isr(dispc_disable_isr,
++                              &frame_done_completion,
++                              DISPC_IRQ_FRAMEDONE);
++
++              if (r)
++                      DSSERR("failed to unregister FRAMEDONE isr\n");
++      }
++
++      enable_clocks(0);
++}
++
++static void _enable_digit_out(bool enable)
++{
++      REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
++}
++
++void dispc_enable_digit_out(bool enable)
++{
++      struct completion frame_done_completion;
++      int r;
++
++      enable_clocks(1);
++
++      if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
++              enable_clocks(0);
++              return;
++      }
++
++      if (enable) {
++              unsigned long flags;
++              /* When we enable digit output, we'll get an extra digit
++               * sync lost interrupt, that we need to ignore */
++              spin_lock_irqsave(&dispc.irq_lock, flags);
++              dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
++              _omap_dispc_set_irqs();
++              spin_unlock_irqrestore(&dispc.irq_lock, flags);
++      }
++
++      /* When we disable digit output, we need to wait until fields are done.
++       * Otherwise the DSS is still working, and turning off the clocks
++       * prevents DSS from going to OFF mode. And when enabling, we need to
++       * wait for the extra sync losts */
++      init_completion(&frame_done_completion);
++
++      r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
++                      DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
++      if (r)
++              DSSERR("failed to register EVSYNC isr\n");
++
++      _enable_digit_out(enable);
++
++      /* XXX I understand from TRM that we should only wait for the
++       * current field to complete. But it seems we have to wait
++       * for both fields */
++      if (!wait_for_completion_timeout(&frame_done_completion,
++                              msecs_to_jiffies(100)))
++              DSSERR("timeout waiting for EVSYNC\n");
++
++      if (!wait_for_completion_timeout(&frame_done_completion,
++                              msecs_to_jiffies(100)))
++              DSSERR("timeout waiting for EVSYNC\n");
++
++      r = omap_dispc_unregister_isr(dispc_disable_isr,
++                      &frame_done_completion,
++                      DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
++      if (r)
++              DSSERR("failed to unregister EVSYNC isr\n");
++
++      if (enable) {
++              unsigned long flags;
++              spin_lock_irqsave(&dispc.irq_lock, flags);
++              dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
++              dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
++              _omap_dispc_set_irqs();
++              spin_unlock_irqrestore(&dispc.irq_lock, flags);
++      }
++
++      enable_clocks(0);
++}
++
++void dispc_lcd_enable_signal_polarity(bool act_high)
++{
++      enable_clocks(1);
++      REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
++      enable_clocks(0);
++}
++
++void dispc_lcd_enable_signal(bool enable)
++{
++      enable_clocks(1);
++      REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
++      enable_clocks(0);
++}
++
++void dispc_pck_free_enable(bool enable)
++{
++      enable_clocks(1);
++      REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
++      enable_clocks(0);
++}
++
++void dispc_enable_fifohandcheck(bool enable)
++{
++      enable_clocks(1);
++      REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
++      enable_clocks(0);
++}
++
++
++void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
++{
++      int mode;
++
++      switch (type) {
++      case OMAP_DSS_LCD_DISPLAY_STN:
++              mode = 0;
++              break;
++
++      case OMAP_DSS_LCD_DISPLAY_TFT:
++              mode = 1;
++              break;
++
++      default:
++              BUG();
++              return;
++      }
++
++      enable_clocks(1);
++      REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
++      enable_clocks(0);
++}
++
++void dispc_set_loadmode(enum omap_dss_load_mode mode)
++{
++      enable_clocks(1);
++      REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
++      enable_clocks(0);
++}
++
++
++void dispc_set_default_color(enum omap_channel channel, u32 color)
++{
++      const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
++                              DISPC_DEFAULT_COLOR1 };
++
++      enable_clocks(1);
++      dispc_write_reg(def_reg[channel], color);
++      enable_clocks(0);
++}
++
++u32 dispc_get_default_color(enum omap_channel channel)
++{
++      const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
++                              DISPC_DEFAULT_COLOR1 };
++      u32 l;
++
++      BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
++             channel != OMAP_DSS_CHANNEL_LCD);
++
++      enable_clocks(1);
++      l = dispc_read_reg(def_reg[channel]);
++      enable_clocks(0);
++
++      return l;
++}
++
++void dispc_set_trans_key(enum omap_channel ch,
++              enum omap_dss_trans_key_type type,
++              u32 trans_key)
++{
++      const struct dispc_reg tr_reg[] = {
++              DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
++
++      enable_clocks(1);
++      if (ch == OMAP_DSS_CHANNEL_LCD)
++              REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
++      else /* OMAP_DSS_CHANNEL_DIGIT */
++              REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
++
++      dispc_write_reg(tr_reg[ch], trans_key);
++      enable_clocks(0);
++}
++
++void dispc_get_trans_key(enum omap_channel ch,
++              enum omap_dss_trans_key_type *type,
++              u32 *trans_key)
++{
++      const struct dispc_reg tr_reg[] = {
++              DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
++
++      enable_clocks(1);
++      if (type) {
++              if (ch == OMAP_DSS_CHANNEL_LCD)
++                      *type = REG_GET(DISPC_CONFIG, 11, 11);
++              else if (ch == OMAP_DSS_CHANNEL_DIGIT)
++                      *type = REG_GET(DISPC_CONFIG, 13, 13);
++              else
++                      BUG();
++      }
++
++      if (trans_key)
++              *trans_key = dispc_read_reg(tr_reg[ch]);
++      enable_clocks(0);
++}
++
++void dispc_enable_trans_key(enum omap_channel ch, bool enable)
++{
++      enable_clocks(1);
++      if (ch == OMAP_DSS_CHANNEL_LCD)
++              REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
++      else /* OMAP_DSS_CHANNEL_DIGIT */
++              REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
++      enable_clocks(0);
++}
++void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
++{
++      enable_clocks(1);
++      if (ch == OMAP_DSS_CHANNEL_LCD)
++              REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
++      else /* OMAP_DSS_CHANNEL_DIGIT */
++              REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
++      enable_clocks(0);
++}
++bool dispc_alpha_blending_enabled(enum omap_channel ch)
++{
++      bool enabled;
++
++      enable_clocks(1);
++      if (ch == OMAP_DSS_CHANNEL_LCD)
++              enabled = REG_GET(DISPC_CONFIG, 18, 18);
++      else if (ch == OMAP_DSS_CHANNEL_DIGIT)
++              enabled = REG_GET(DISPC_CONFIG, 18, 18);
++      else
++              BUG();
++      enable_clocks(0);
++
++      return enabled;
++
++}
++
++
++bool dispc_trans_key_enabled(enum omap_channel ch)
++{
++      bool enabled;
++
++      enable_clocks(1);
++      if (ch == OMAP_DSS_CHANNEL_LCD)
++              enabled = REG_GET(DISPC_CONFIG, 10, 10);
++      else if (ch == OMAP_DSS_CHANNEL_DIGIT)
++              enabled = REG_GET(DISPC_CONFIG, 12, 12);
++      else
++              BUG();
++      enable_clocks(0);
++
++      return enabled;
++}
++
++
++void dispc_set_tft_data_lines(u8 data_lines)
++{
++      int code;
++
++      switch (data_lines) {
++      case 12:
++              code = 0;
++              break;
++      case 16:
++              code = 1;
++              break;
++      case 18:
++              code = 2;
++              break;
++      case 24:
++              code = 3;
++              break;
++      default:
++              BUG();
++              return;
++      }
++
++      enable_clocks(1);
++      REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
++      enable_clocks(0);
++}
++
++void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
++{
++      u32 l;
++      int stallmode;
++      int gpout0 = 1;
++      int gpout1;
++
++      switch (mode) {
++      case OMAP_DSS_PARALLELMODE_BYPASS:
++              stallmode = 0;
++              gpout1 = 1;
++              break;
++
++      case OMAP_DSS_PARALLELMODE_RFBI:
++              stallmode = 1;
++              gpout1 = 0;
++              break;
++
++      case OMAP_DSS_PARALLELMODE_DSI:
++              stallmode = 1;
++              gpout1 = 1;
++              break;
++
++      default:
++              BUG();
++              return;
++      }
++
++      enable_clocks(1);
++
++      l = dispc_read_reg(DISPC_CONTROL);
++
++      l = FLD_MOD(l, stallmode, 11, 11);
++      l = FLD_MOD(l, gpout0, 15, 15);
++      l = FLD_MOD(l, gpout1, 16, 16);
++
++      dispc_write_reg(DISPC_CONTROL, l);
++
++      enable_clocks(0);
++}
++
++static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
++              int vsw, int vfp, int vbp)
++{
++      if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
++              if (hsw < 1 || hsw > 64 ||
++                              hfp < 1 || hfp > 256 ||
++                              hbp < 1 || hbp > 256 ||
++                              vsw < 1 || vsw > 64 ||
++                              vfp < 0 || vfp > 255 ||
++                              vbp < 0 || vbp > 255)
++                      return false;
++      } else {
++              if (hsw < 1 || hsw > 256 ||
++                              hfp < 1 || hfp > 4096 ||
++                              hbp < 1 || hbp > 4096 ||
++                              vsw < 1 || vsw > 256 ||
++                              vfp < 0 || vfp > 4095 ||
++                              vbp < 0 || vbp > 4095)
++                      return false;
++      }
++
++      return true;
++}
++
++bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
++{
++      return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
++                      timings->hbp, timings->vsw,
++                      timings->vfp, timings->vbp);
++}
++
++static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
++                                 int vsw, int vfp, int vbp)
++{
++      u32 timing_h, timing_v;
++
++      if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
++              timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
++                      FLD_VAL(hbp-1, 27, 20);
++
++              timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
++                      FLD_VAL(vbp, 27, 20);
++      } else {
++              timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
++                      FLD_VAL(hbp-1, 31, 20);
++
++              timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
++                      FLD_VAL(vbp, 31, 20);
++      }
++
++      enable_clocks(1);
++      dispc_write_reg(DISPC_TIMING_H, timing_h);
++      dispc_write_reg(DISPC_TIMING_V, timing_v);
++      enable_clocks(0);
++}
++
++/* change name to mode? */
++void dispc_set_lcd_timings(struct omap_video_timings *timings)
++{
++      unsigned xtot, ytot;
++      unsigned long ht, vt;
++
++      if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
++                              timings->hbp, timings->vsw,
++                              timings->vfp, timings->vbp))
++              BUG();
++
++      _dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
++                      timings->vsw, timings->vfp, timings->vbp);
++
++      dispc_set_lcd_size(timings->x_res, timings->y_res);
++
++      xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
++      ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
++
++      ht = (timings->pixel_clock * 1000) / xtot;
++      vt = (timings->pixel_clock * 1000) / xtot / ytot;
++
++      DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
++      DSSDBG("pck %u\n", timings->pixel_clock);
++      DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
++                      timings->hsw, timings->hfp, timings->hbp,
++                      timings->vsw, timings->vfp, timings->vbp);
++
++      DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
++}
++
++void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
++{
++      BUG_ON(lck_div < 1);
++      BUG_ON(pck_div < 2);
++
++      enable_clocks(1);
++      dispc_write_reg(DISPC_DIVISOR,
++                      FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
++      enable_clocks(0);
++}
++
++static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
++{
++      u32 l;
++      l = dispc_read_reg(DISPC_DIVISOR);
++      *lck_div = FLD_GET(l, 23, 16);
++      *pck_div = FLD_GET(l, 7, 0);
++}
++
++unsigned long dispc_fclk_rate(void)
++{
++      unsigned long r = 0;
++
++      if (dss_get_dispc_clk_source() == 0)
++              r = dss_clk_get_rate(DSS_CLK_FCK1);
++      else
++#ifdef CONFIG_OMAP2_DSS_DSI
++              r = dsi_get_dsi1_pll_rate();
++#else
++      BUG();
++#endif
++      return r;
++}
++
++unsigned long dispc_lclk_rate(void)
++{
++      int lcd;
++      unsigned long r;
++      u32 l;
++
++      l = dispc_read_reg(DISPC_DIVISOR);
++
++      lcd = FLD_GET(l, 23, 16);
++
++      r = dispc_fclk_rate();
++
++      return r / lcd;
++}
++
++unsigned long dispc_pclk_rate(void)
++{
++      int lcd, pcd;
++      unsigned long r;
++      u32 l;
++
++      l = dispc_read_reg(DISPC_DIVISOR);
++
++      lcd = FLD_GET(l, 23, 16);
++      pcd = FLD_GET(l, 7, 0);
++
++      r = dispc_fclk_rate();
++
++      return r / lcd / pcd;
++}
++
++void dispc_dump_clocks(struct seq_file *s)
++{
++      int lcd, pcd;
++
++      enable_clocks(1);
++
++      dispc_get_lcd_divisor(&lcd, &pcd);
++
++      seq_printf(s, "- dispc -\n");
++
++      seq_printf(s, "dispc fclk source = %s\n",
++                      dss_get_dispc_clk_source() == 0 ?
++                      "dss1_alwon_fclk" : "dsi1_pll_fclk");
++
++      seq_printf(s, "pixel clk = %lu / %d / %d = %lu\n",
++                      dispc_fclk_rate(),
++                      lcd, pcd,
++                      dispc_pclk_rate());
++
++      enable_clocks(0);
++}
++
++void dispc_dump_regs(struct seq_file *s)
++{
++#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
++
++      dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++      DUMPREG(DISPC_REVISION);
++      DUMPREG(DISPC_SYSCONFIG);
++      DUMPREG(DISPC_SYSSTATUS);
++      DUMPREG(DISPC_IRQSTATUS);
++      DUMPREG(DISPC_IRQENABLE);
++      DUMPREG(DISPC_CONTROL);
++      DUMPREG(DISPC_CONFIG);
++      DUMPREG(DISPC_CAPABLE);
++      DUMPREG(DISPC_DEFAULT_COLOR0);
++      DUMPREG(DISPC_DEFAULT_COLOR1);
++      DUMPREG(DISPC_TRANS_COLOR0);
++      DUMPREG(DISPC_TRANS_COLOR1);
++      DUMPREG(DISPC_LINE_STATUS);
++      DUMPREG(DISPC_LINE_NUMBER);
++      DUMPREG(DISPC_TIMING_H);
++      DUMPREG(DISPC_TIMING_V);
++      DUMPREG(DISPC_POL_FREQ);
++      DUMPREG(DISPC_DIVISOR);
++      DUMPREG(DISPC_GLOBAL_ALPHA);
++      DUMPREG(DISPC_SIZE_DIG);
++      DUMPREG(DISPC_SIZE_LCD);
++
++      DUMPREG(DISPC_GFX_BA0);
++      DUMPREG(DISPC_GFX_BA1);
++      DUMPREG(DISPC_GFX_POSITION);
++      DUMPREG(DISPC_GFX_SIZE);
++      DUMPREG(DISPC_GFX_ATTRIBUTES);
++      DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
++      DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
++      DUMPREG(DISPC_GFX_ROW_INC);
++      DUMPREG(DISPC_GFX_PIXEL_INC);
++      DUMPREG(DISPC_GFX_WINDOW_SKIP);
++      DUMPREG(DISPC_GFX_TABLE_BA);
++
++      DUMPREG(DISPC_DATA_CYCLE1);
++      DUMPREG(DISPC_DATA_CYCLE2);
++      DUMPREG(DISPC_DATA_CYCLE3);
++
++      DUMPREG(DISPC_CPR_COEF_R);
++      DUMPREG(DISPC_CPR_COEF_G);
++      DUMPREG(DISPC_CPR_COEF_B);
++
++      DUMPREG(DISPC_GFX_PRELOAD);
++
++      DUMPREG(DISPC_VID_BA0(0));
++      DUMPREG(DISPC_VID_BA1(0));
++      DUMPREG(DISPC_VID_POSITION(0));
++      DUMPREG(DISPC_VID_SIZE(0));
++      DUMPREG(DISPC_VID_ATTRIBUTES(0));
++      DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
++      DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
++      DUMPREG(DISPC_VID_ROW_INC(0));
++      DUMPREG(DISPC_VID_PIXEL_INC(0));
++      DUMPREG(DISPC_VID_FIR(0));
++      DUMPREG(DISPC_VID_PICTURE_SIZE(0));
++      DUMPREG(DISPC_VID_ACCU0(0));
++      DUMPREG(DISPC_VID_ACCU1(0));
++
++      DUMPREG(DISPC_VID_BA0(1));
++      DUMPREG(DISPC_VID_BA1(1));
++      DUMPREG(DISPC_VID_POSITION(1));
++      DUMPREG(DISPC_VID_SIZE(1));
++      DUMPREG(DISPC_VID_ATTRIBUTES(1));
++      DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
++      DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
++      DUMPREG(DISPC_VID_ROW_INC(1));
++      DUMPREG(DISPC_VID_PIXEL_INC(1));
++      DUMPREG(DISPC_VID_FIR(1));
++      DUMPREG(DISPC_VID_PICTURE_SIZE(1));
++      DUMPREG(DISPC_VID_ACCU0(1));
++      DUMPREG(DISPC_VID_ACCU1(1));
++
++      DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
++      DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
++      DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
++      DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
++      DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
++      DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
++      DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
++      DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
++      DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
++      DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
++      DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
++      DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
++      DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
++      DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
++      DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
++      DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
++      DUMPREG(DISPC_VID_CONV_COEF(0, 0));
++      DUMPREG(DISPC_VID_CONV_COEF(0, 1));
++      DUMPREG(DISPC_VID_CONV_COEF(0, 2));
++      DUMPREG(DISPC_VID_CONV_COEF(0, 3));
++      DUMPREG(DISPC_VID_CONV_COEF(0, 4));
++      DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
++      DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
++      DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
++      DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
++      DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
++      DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
++      DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
++      DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
++
++      DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
++      DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
++      DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
++      DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
++      DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
++      DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
++      DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
++      DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
++      DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
++      DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
++      DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
++      DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
++      DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
++      DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
++      DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
++      DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
++      DUMPREG(DISPC_VID_CONV_COEF(1, 0));
++      DUMPREG(DISPC_VID_CONV_COEF(1, 1));
++      DUMPREG(DISPC_VID_CONV_COEF(1, 2));
++      DUMPREG(DISPC_VID_CONV_COEF(1, 3));
++      DUMPREG(DISPC_VID_CONV_COEF(1, 4));
++      DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
++      DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
++      DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
++      DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
++      DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
++      DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
++      DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
++      DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
++
++      DUMPREG(DISPC_VID_PRELOAD(0));
++      DUMPREG(DISPC_VID_PRELOAD(1));
++
++      dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++#undef DUMPREG
++}
++
++static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
++                              bool ihs, bool ivs, u8 acbi, u8 acb)
++{
++      u32 l = 0;
++
++      DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
++                      onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
++
++      l |= FLD_VAL(onoff, 17, 17);
++      l |= FLD_VAL(rf, 16, 16);
++      l |= FLD_VAL(ieo, 15, 15);
++      l |= FLD_VAL(ipc, 14, 14);
++      l |= FLD_VAL(ihs, 13, 13);
++      l |= FLD_VAL(ivs, 12, 12);
++      l |= FLD_VAL(acbi, 11, 8);
++      l |= FLD_VAL(acb, 7, 0);
++
++      enable_clocks(1);
++      dispc_write_reg(DISPC_POL_FREQ, l);
++      enable_clocks(0);
++}
++
++void dispc_set_pol_freq(enum omap_panel_config config, u8 acbi, u8 acb)
++{
++      _dispc_set_pol_freq((config & OMAP_DSS_LCD_ONOFF) != 0,
++                      (config & OMAP_DSS_LCD_RF) != 0,
++                      (config & OMAP_DSS_LCD_IEO) != 0,
++                      (config & OMAP_DSS_LCD_IPC) != 0,
++                      (config & OMAP_DSS_LCD_IHS) != 0,
++                      (config & OMAP_DSS_LCD_IVS) != 0,
++                      acbi, acb);
++}
++
++void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
++              u16 *lck_div, u16 *pck_div)
++{
++      u16 pcd_min = is_tft ? 2 : 3;
++      unsigned long best_pck;
++      u16 best_ld, cur_ld;
++      u16 best_pd, cur_pd;
++
++      best_pck = 0;
++      best_ld = 0;
++      best_pd = 0;
++
++      for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
++              unsigned long lck = fck / cur_ld;
++
++              for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
++                      unsigned long pck = lck / cur_pd;
++                      long old_delta = abs(best_pck - req_pck);
++                      long new_delta = abs(pck - req_pck);
++
++                      if (best_pck == 0 || new_delta < old_delta) {
++                              best_pck = pck;
++                              best_ld = cur_ld;
++                              best_pd = cur_pd;
++
++                              if (pck == req_pck)
++                                      goto found;
++                      }
++
++                      if (pck < req_pck)
++                              break;
++              }
++
++              if (lck / pcd_min < req_pck)
++                      break;
++      }
++
++found:
++      *lck_div = best_ld;
++      *pck_div = best_pd;
++}
++
++int dispc_calc_clock_div(bool is_tft, unsigned long req_pck,
++              struct dispc_clock_info *cinfo)
++{
++      unsigned long prate;
++      struct dispc_clock_info cur, best;
++      int match = 0;
++      int min_fck_per_pck;
++      unsigned long fck_rate = dss_clk_get_rate(DSS_CLK_FCK1);
++
++      if (cpu_is_omap34xx())
++              prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
++      else
++              prate = 0;
++
++      if (req_pck == dispc.cache_req_pck &&
++                      ((cpu_is_omap34xx() && prate == dispc.cache_prate) ||
++                       dispc.cache_cinfo.fck == fck_rate)) {
++              DSSDBG("dispc clock info found from cache.\n");
++              *cinfo = dispc.cache_cinfo;
++              return 0;
++      }
++
++      min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
++
++      if (min_fck_per_pck &&
++              req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
++              DSSERR("Requested pixel clock not possible with the current "
++                              "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
++                              "the constraint off.\n");
++              min_fck_per_pck = 0;
++      }
++
++retry:
++      memset(&cur, 0, sizeof(cur));
++      memset(&best, 0, sizeof(best));
++
++      if (cpu_is_omap24xx()) {
++              /* XXX can we change the clock on omap2? */
++              cur.fck = dss_clk_get_rate(DSS_CLK_FCK1);
++              cur.fck_div = 1;
++
++              match = 1;
++
++              find_lck_pck_divs(is_tft, req_pck, cur.fck,
++                              &cur.lck_div, &cur.pck_div);
++
++              cur.lck = cur.fck / cur.lck_div;
++              cur.pck = cur.lck / cur.pck_div;
++
++              best = cur;
++
++              goto found;
++      } else if (cpu_is_omap34xx()) {
++              for (cur.fck_div = 16; cur.fck_div > 0; --cur.fck_div) {
++                      cur.fck = prate / cur.fck_div * 2;
++
++                      if (cur.fck > DISPC_MAX_FCK)
++                              continue;
++
++                      if (min_fck_per_pck &&
++                                      cur.fck < req_pck * min_fck_per_pck)
++                              continue;
++
++                      match = 1;
++
++                      find_lck_pck_divs(is_tft, req_pck, cur.fck,
++                                      &cur.lck_div, &cur.pck_div);
++
++                      cur.lck = cur.fck / cur.lck_div;
++                      cur.pck = cur.lck / cur.pck_div;
++
++                      if (abs(cur.pck - req_pck) < abs(best.pck - req_pck)) {
++                              best = cur;
++
++                              if (cur.pck == req_pck)
++                                      goto found;
++                      }
++              }
++      } else {
++              BUG();
++      }
++
++found:
++      if (!match) {
++              if (min_fck_per_pck) {
++                      DSSERR("Could not find suitable clock settings.\n"
++                                      "Turning FCK/PCK constraint off and"
++                                      "trying again.\n");
++                      min_fck_per_pck = 0;
++                      goto retry;
++              }
++
++              DSSERR("Could not find suitable clock settings.\n");
++
++              return -EINVAL;
++      }
++
++      if (cinfo)
++              *cinfo = best;
++
++      dispc.cache_req_pck = req_pck;
++      dispc.cache_prate = prate;
++      dispc.cache_cinfo = best;
++
++      return 0;
++}
++
++int dispc_set_clock_div(struct dispc_clock_info *cinfo)
++{
++      unsigned long prate;
++      int r;
++
++      if (cpu_is_omap34xx()) {
++              prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
++              DSSDBG("dpll4_m4 = %ld\n", prate);
++      }
++
++      DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
++      DSSDBG("lck = %ld (%d)\n", cinfo->lck, cinfo->lck_div);
++      DSSDBG("pck = %ld (%d)\n", cinfo->pck, cinfo->pck_div);
++
++      if (cpu_is_omap34xx()) {
++              r = clk_set_rate(dispc.dpll4_m4_ck, prate / cinfo->fck_div);
++              if (r)
++                      return r;
++      }
++
++      dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
++
++      return 0;
++}
++
++int dispc_get_clock_div(struct dispc_clock_info *cinfo)
++{
++      cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1);
++
++      if (cpu_is_omap34xx()) {
++              unsigned long prate;
++              prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
++              cinfo->fck_div = prate / (cinfo->fck / 2);
++      } else {
++              cinfo->fck_div = 0;
++      }
++
++      cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
++      cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
++
++      cinfo->lck = cinfo->fck / cinfo->lck_div;
++      cinfo->pck = cinfo->lck / cinfo->pck_div;
++
++      return 0;
++}
++
++/* dispc.irq_lock has to be locked by the caller */
++static void _omap_dispc_set_irqs(void)
++{
++      u32 mask;
++      u32 old_mask;
++      int i;
++      struct omap_dispc_isr_data *isr_data;
++
++      mask = dispc.irq_error_mask;
++
++      for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++              isr_data = &dispc.registered_isr[i];
++
++              if (isr_data->isr == NULL)
++                      continue;
++
++              mask |= isr_data->mask;
++      }
++
++      enable_clocks(1);
++
++      old_mask = dispc_read_reg(DISPC_IRQENABLE);
++      /* clear the irqstatus for newly enabled irqs */
++      dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
++
++      dispc_write_reg(DISPC_IRQENABLE, mask);
++
++      enable_clocks(0);
++}
++
++int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
++{
++      int i;
++      int ret;
++      unsigned long flags;
++      struct omap_dispc_isr_data *isr_data;
++
++      if (isr == NULL)
++              return -EINVAL;
++
++      spin_lock_irqsave(&dispc.irq_lock, flags);
++
++      /* check for duplicate entry */
++      for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++              isr_data = &dispc.registered_isr[i];
++              if (isr_data->isr == isr && isr_data->arg == arg &&
++                              isr_data->mask == mask) {
++                      ret = -EINVAL;
++                      goto err;
++              }
++      }
++
++      isr_data = NULL;
++      ret = -EBUSY;
++
++      for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++              isr_data = &dispc.registered_isr[i];
++
++              if (isr_data->isr != NULL)
++                      continue;
++
++              isr_data->isr = isr;
++              isr_data->arg = arg;
++              isr_data->mask = mask;
++              ret = 0;
++
++              break;
++      }
++
++      _omap_dispc_set_irqs();
++
++      spin_unlock_irqrestore(&dispc.irq_lock, flags);
++
++      return 0;
++err:
++      spin_unlock_irqrestore(&dispc.irq_lock, flags);
++
++      return ret;
++}
++EXPORT_SYMBOL(omap_dispc_register_isr);
++
++int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
++{
++      int i;
++      unsigned long flags;
++      int ret = -EINVAL;
++      struct omap_dispc_isr_data *isr_data;
++
++      spin_lock_irqsave(&dispc.irq_lock, flags);
++
++      for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++              isr_data = &dispc.registered_isr[i];
++              if (isr_data->isr != isr || isr_data->arg != arg ||
++                              isr_data->mask != mask)
++                      continue;
++
++              /* found the correct isr */
++
++              isr_data->isr = NULL;
++              isr_data->arg = NULL;
++              isr_data->mask = 0;
++
++              ret = 0;
++              break;
++      }
++
++      if (ret == 0)
++              _omap_dispc_set_irqs();
++
++      spin_unlock_irqrestore(&dispc.irq_lock, flags);
++
++      return ret;
++}
++EXPORT_SYMBOL(omap_dispc_unregister_isr);
++
++#ifdef DEBUG
++static void print_irq_status(u32 status)
++{
++      if ((status & dispc.irq_error_mask) == 0)
++              return;
++
++      printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
++
++#define PIS(x) \
++      if (status & DISPC_IRQ_##x) \
++              printk(#x " ");
++      PIS(GFX_FIFO_UNDERFLOW);
++      PIS(OCP_ERR);
++      PIS(VID1_FIFO_UNDERFLOW);
++      PIS(VID2_FIFO_UNDERFLOW);
++      PIS(SYNC_LOST);
++      PIS(SYNC_LOST_DIGIT);
++#undef PIS
++
++      printk("\n");
++}
++#endif
++
++/* Called from dss.c. Note that we don't touch clocks here,
++ * but we presume they are on because we got an IRQ. However,
++ * an irq handler may turn the clocks off, so we may not have
++ * clock later in the function. */
++void dispc_irq_handler(void)
++{
++      int i;
++      u32 irqstatus;
++      u32 handledirqs = 0;
++      u32 unhandled_errors;
++      struct omap_dispc_isr_data *isr_data;
++      struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
++
++      spin_lock(&dispc.irq_lock);
++
++      irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
++
++#ifdef DEBUG
++      if (dss_debug)
++              print_irq_status(irqstatus);
++#endif
++      /* Ack the interrupt. Do it here before clocks are possibly turned
++       * off */
++      dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
++
++      /* make a copy and unlock, so that isrs can unregister
++       * themselves */
++      memcpy(registered_isr, dispc.registered_isr,
++                      sizeof(registered_isr));
++
++      spin_unlock(&dispc.irq_lock);
++
++      for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++              isr_data = &registered_isr[i];
++
++              if (!isr_data->isr)
++                      continue;
++
++              if (isr_data->mask & irqstatus) {
++                      isr_data->isr(isr_data->arg, irqstatus);
++                      handledirqs |= isr_data->mask;
++              }
++      }
++
++      spin_lock(&dispc.irq_lock);
++
++      unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
++
++      if (unhandled_errors) {
++              dispc.error_irqs |= unhandled_errors;
++
++              dispc.irq_error_mask &= ~unhandled_errors;
++              _omap_dispc_set_irqs();
++
++              schedule_work(&dispc.error_work);
++      }
++
++      spin_unlock(&dispc.irq_lock);
++}
++
++static void dispc_error_worker(struct work_struct *work)
++{
++      int i;
++      u32 errors;
++      unsigned long flags;
++
++      spin_lock_irqsave(&dispc.irq_lock, flags);
++      errors = dispc.error_irqs;
++      dispc.error_irqs = 0;
++      spin_unlock_irqrestore(&dispc.irq_lock, flags);
++
++      if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
++              DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
++              for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
++                      struct omap_overlay *ovl;
++                      ovl = omap_dss_get_overlay(i);
++
++                      if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
++                              continue;
++
++                      if (ovl->id == 0) {
++                              dispc_enable_plane(ovl->id, 0);
++                              dispc_go(ovl->manager->id);
++                              mdelay(50);
++                              break;
++                      }
++              }
++      }
++
++      if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
++              DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
++              for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
++                      struct omap_overlay *ovl;
++                      ovl = omap_dss_get_overlay(i);
++
++                      if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
++                              continue;
++
++                      if (ovl->id == 1) {
++                              dispc_enable_plane(ovl->id, 0);
++                              dispc_go(ovl->manager->id);
++                              mdelay(50);
++                              break;
++                      }
++              }
++      }
++
++      if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
++              DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
++              for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
++                      struct omap_overlay *ovl;
++                      ovl = omap_dss_get_overlay(i);
++
++                      if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
++                              continue;
++
++                      if (ovl->id == 2) {
++                              dispc_enable_plane(ovl->id, 0);
++                              dispc_go(ovl->manager->id);
++                              mdelay(50);
++                              break;
++                      }
++              }
++      }
++
++      if (errors & DISPC_IRQ_SYNC_LOST) {
++              struct omap_overlay_manager *manager = NULL;
++              bool enable = false;
++
++              DSSERR("SYNC_LOST, disabling LCD\n");
++
++              for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
++                      struct omap_overlay_manager *mgr;
++                      mgr = omap_dss_get_overlay_manager(i);
++
++                      if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
++                              manager = mgr;
++                              enable = mgr->device->state ==
++                                              OMAP_DSS_DISPLAY_ACTIVE;
++                              mgr->device->disable(mgr->device);
++                              break;
++                      }
++              }
++
++              if (manager) {
++                      for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
++                              struct omap_overlay *ovl;
++                              ovl = omap_dss_get_overlay(i);
++
++                              if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
++                                      continue;
++
++                              if (ovl->id != 0 && ovl->manager == manager)
++                                      dispc_enable_plane(ovl->id, 0);
++                      }
++
++                      dispc_go(manager->id);
++                      mdelay(50);
++                      if (enable)
++                              manager->device->enable(manager->device);
++              }
++      }
++
++      if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
++              struct omap_overlay_manager *manager = NULL;
++              bool enable = false;
++
++              DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
++
++              for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
++                      struct omap_overlay_manager *mgr;
++                      mgr = omap_dss_get_overlay_manager(i);
++
++                      if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
++                              manager = mgr;
++                              enable = mgr->device->state ==
++                                              OMAP_DSS_DISPLAY_ACTIVE;
++                              mgr->device->disable(mgr->device);
++                              break;
++                      }
++              }
++
++              if (manager) {
++                      for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
++                              struct omap_overlay *ovl;
++                              ovl = omap_dss_get_overlay(i);
++
++                              if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
++                                      continue;
++
++                              if (ovl->id != 0 && ovl->manager == manager)
++                                      dispc_enable_plane(ovl->id, 0);
++                      }
++
++                      dispc_go(manager->id);
++                      mdelay(50);
++                      if (enable)
++                              manager->device->enable(manager->device);
++              }
++      }
++
++      if (errors & DISPC_IRQ_OCP_ERR) {
++              DSSERR("OCP_ERR\n");
++              for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
++                      struct omap_overlay_manager *mgr;
++                      mgr = omap_dss_get_overlay_manager(i);
++
++                      if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
++                              mgr->device->disable(mgr->device);
++              }
++      }
++
++      spin_lock_irqsave(&dispc.irq_lock, flags);
++      dispc.irq_error_mask |= errors;
++      _omap_dispc_set_irqs();
++      spin_unlock_irqrestore(&dispc.irq_lock, flags);
++}
++
++int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
++{
++      void dispc_irq_wait_handler(void *data, u32 mask)
++      {
++              complete((struct completion *)data);
++      }
++
++      int r;
++      DECLARE_COMPLETION_ONSTACK(completion);
++
++      r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
++                      irqmask);
++
++      if (r)
++              return r;
++
++      timeout = wait_for_completion_timeout(&completion, timeout);
++
++      omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
++
++      if (timeout == 0)
++              return -ETIMEDOUT;
++
++      if (timeout == -ERESTARTSYS)
++              return -ERESTARTSYS;
++
++      return 0;
++}
++
++int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
++              unsigned long timeout)
++{
++      void dispc_irq_wait_handler(void *data, u32 mask)
++      {
++              complete((struct completion *)data);
++      }
++
++      int r;
++      DECLARE_COMPLETION_ONSTACK(completion);
++
++      r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
++                      irqmask);
++
++      if (r)
++              return r;
++
++      timeout = wait_for_completion_interruptible_timeout(&completion,
++                      timeout);
++
++      omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
++
++      if (timeout == 0)
++              return -ETIMEDOUT;
++
++      if (timeout == -ERESTARTSYS)
++              return -ERESTARTSYS;
++
++      return 0;
++}
++
++#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
++void dispc_fake_vsync_irq(void)
++{
++      u32 irqstatus = DISPC_IRQ_VSYNC;
++      int i;
++
++      for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
++              struct omap_dispc_isr_data *isr_data;
++              isr_data = &dispc.registered_isr[i];
++
++              if (!isr_data->isr)
++                      continue;
++
++              if (isr_data->mask & irqstatus)
++                      isr_data->isr(isr_data->arg, irqstatus);
++      }
++}
++#endif
++
++static void _omap_dispc_initialize_irq(void)
++{
++      unsigned long flags;
++
++      spin_lock_irqsave(&dispc.irq_lock, flags);
++
++      memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
++
++      dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
++
++      /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
++       * so clear it */
++      dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
++
++      _omap_dispc_set_irqs();
++
++      spin_unlock_irqrestore(&dispc.irq_lock, flags);
++}
++
++void dispc_enable_sidle(void)
++{
++      REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
++}
++
++void dispc_disable_sidle(void)
++{
++      REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
++}
++
++static void _omap_dispc_initial_config(void)
++{
++      u32 l;
++
++      l = dispc_read_reg(DISPC_SYSCONFIG);
++      l = FLD_MOD(l, 2, 13, 12);      /* MIDLEMODE: smart standby */
++      l = FLD_MOD(l, 2, 4, 3);        /* SIDLEMODE: smart idle */
++      l = FLD_MOD(l, 1, 2, 2);        /* ENWAKEUP */
++      l = FLD_MOD(l, 1, 0, 0);        /* AUTOIDLE */
++      dispc_write_reg(DISPC_SYSCONFIG, l);
++
++      /* FUNCGATED */
++      REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
++
++      /* L3 firewall setting: enable access to OCM RAM */
++      if (cpu_is_omap24xx())
++              __raw_writel(0x402000b0, OMAP2_IO_ADDRESS(0x680050a0));
++
++      _dispc_setup_color_conv_coef();
++
++      dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
++
++      dispc_read_plane_fifo_sizes();
++}
++
++int dispc_init(void)
++{
++      u32 rev;
++
++      spin_lock_init(&dispc.irq_lock);
++
++      INIT_WORK(&dispc.error_work, dispc_error_worker);
++
++      dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
++      if (!dispc.base) {
++              DSSERR("can't ioremap DISPC\n");
++              return -ENOMEM;
++      }
++
++      if (cpu_is_omap34xx()) {
++              dispc.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
++              if (IS_ERR(dispc.dpll4_m4_ck)) {
++                      DSSERR("Failed to get dpll4_m4_ck\n");
++                      return -ENODEV;
++              }
++      }
++
++      enable_clocks(1);
++
++      _omap_dispc_initial_config();
++
++      _omap_dispc_initialize_irq();
++
++      dispc_save_context();
++
++      rev = dispc_read_reg(DISPC_REVISION);
++      printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
++             FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
++
++      enable_clocks(0);
++
++      return 0;
++}
++
++void dispc_exit(void)
++{
++      if (cpu_is_omap34xx())
++              clk_put(dispc.dpll4_m4_ck);
++      iounmap(dispc.base);
++}
++
++int dispc_enable_plane(enum omap_plane plane, bool enable)
++{
++      DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
++
++      enable_clocks(1);
++      _dispc_enable_plane(plane, enable);
++      enable_clocks(0);
++
++      return 0;
++}
++
++int dispc_setup_plane(enum omap_plane plane,
++                     u32 paddr, u16 screen_width,
++                     u16 pos_x, u16 pos_y,
++                     u16 width, u16 height,
++                     u16 out_width, u16 out_height,
++                     enum omap_color_mode color_mode,
++                     bool ilace,
++                     enum omap_dss_rotation_type rotation_type,
++                     u8 rotation, bool mirror, u8 global_alpha)
++{
++      int r = 0;
++
++      DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
++             "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
++             plane, paddr, screen_width, pos_x, pos_y,
++             width, height,
++             out_width, out_height,
++             ilace, color_mode,
++             rotation, mirror);
++
++      enable_clocks(1);
++
++      r = _dispc_setup_plane(plane,
++                         paddr, screen_width,
++                         pos_x, pos_y,
++                         width, height,
++                         out_width, out_height,
++                         color_mode, ilace,
++                         rotation_type,
++                         rotation, mirror,
++                         global_alpha);
++
++      enable_clocks(0);
++
++      return r;
++}
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-2.6.31/dss2/0010-OMAP-DSS2-DPI-driver.patch b/recipes/linux/linux-omap-2.6.31/dss2/0010-OMAP-DSS2-DPI-driver.patch
new file mode 100644 (file)
index 0000000..db6d780
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.31/dss2/0010-OMAP-DSS2-DPI-driver.patch
@@ -0,0 +1,410 @@
+From 544b715d21a38a64bcafe850e31ae0dfd5227e9f Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Fri, 7 Aug 2009 13:15:50 +0300
+Subject: [PATCH 10/18] OMAP: DSS2: DPI driver
+
+This implements MIPI DPI interface.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ drivers/video/omap2/dss/dpi.c |  388 +++++++++++++++++++++++++++++++++++++++++
+ 1 files changed, 388 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/video/omap2/dss/dpi.c
+
+diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c
+new file mode 100644
+index 0000000..b6543c8
+--- /dev/null
++++ b/drivers/video/omap2/dss/dpi.c
+@@ -0,0 +1,388 @@
++/*
++ * linux/drivers/video/omap2/dss/dpi.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "DPI"
++
++#include <linux/kernel.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/errno.h>
++
++#include <mach/board.h>
++#include <mach/display.h>
++#include <mach/cpu.h>
++
++#include "dss.h"
++
++static struct {
++      int update_enabled;
++} dpi;
++
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++static int dpi_set_dsi_clk(bool is_tft, unsigned long pck_req,
++              unsigned long *fck, int *lck_div, int *pck_div)
++{
++      struct dsi_clock_info cinfo;
++      int r;
++
++      r = dsi_pll_calc_pck(is_tft, pck_req, &cinfo);
++      if (r)
++              return r;
++
++      r = dsi_pll_program(&cinfo);
++      if (r)
++              return r;
++
++      dss_select_clk_source(0, 1);
++
++      dispc_set_lcd_divisor(cinfo.lck_div, cinfo.pck_div);
++
++      *fck = cinfo.dsi1_pll_fclk;
++      *lck_div = cinfo.lck_div;
++      *pck_div = cinfo.pck_div;
++
++      return 0;
++}
++#else
++static int dpi_set_dispc_clk(bool is_tft, unsigned long pck_req,
++              unsigned long *fck, int *lck_div, int *pck_div)
++{
++      struct dispc_clock_info cinfo;
++      int r;
++
++      r = dispc_calc_clock_div(is_tft, pck_req, &cinfo);
++      if (r)
++              return r;
++
++      r = dispc_set_clock_div(&cinfo);
++      if (r)
++              return r;
++
++      *fck = cinfo.fck;
++      *lck_div = cinfo.lck_div;
++      *pck_div = cinfo.pck_div;
++
++      return 0;
++}
++#endif
++
++static int dpi_set_mode(struct omap_dss_device *dssdev)
++{
++      struct omap_video_timings *t = &dssdev->panel.timings;
++      int lck_div, pck_div;
++      unsigned long fck;
++      unsigned long pck;
++      bool is_tft;
++      int r = 0;
++
++      dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++      dispc_set_pol_freq(dssdev->panel.config, dssdev->panel.acbi,
++                      dssdev->panel.acb);
++
++      is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
++
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++      r = dpi_set_dsi_clk(is_tft, t->pixel_clock * 1000,
++                      &fck, &lck_div, &pck_div);
++#else
++      r = dpi_set_dispc_clk(is_tft, t->pixel_clock * 1000,
++                      &fck, &lck_div, &pck_div);
++#endif
++      if (r)
++              goto err0;
++
++      pck = fck / lck_div / pck_div / 1000;
++
++      if (pck != t->pixel_clock) {
++              DSSWARN("Could not find exact pixel clock. "
++                              "Requested %d kHz, got %lu kHz\n",
++                              t->pixel_clock, pck);
++
++              t->pixel_clock = pck;
++      }
++
++      dispc_set_lcd_timings(t);
++
++err0:
++      dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++      return r;
++}
++
++static int dpi_basic_init(struct omap_dss_device *dssdev)
++{
++      bool is_tft;
++
++      is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
++
++      dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS);
++      dispc_set_lcd_display_type(is_tft ? OMAP_DSS_LCD_DISPLAY_TFT :
++                      OMAP_DSS_LCD_DISPLAY_STN);
++      dispc_set_tft_data_lines(dssdev->phy.dpi.data_lines);
++
++      return 0;
++}
++
++static int dpi_display_enable(struct omap_dss_device *dssdev)
++{
++      int r;
++
++      r = omap_dss_start_device(dssdev);
++      if (r) {
++              DSSERR("failed to start device\n");
++              goto err0;
++      }
++
++      if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
++              DSSERR("display already enabled\n");
++              r = -EINVAL;
++              goto err1;
++      }
++
++      dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++      r = dpi_basic_init(dssdev);
++      if (r)
++              goto err2;
++
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++      dss_clk_enable(DSS_CLK_FCK2);
++      r = dsi_pll_init(0, 1);
++      if (r)
++              goto err3;
++#endif
++      r = dpi_set_mode(dssdev);
++      if (r)
++              goto err4;
++
++      mdelay(2);
++
++      dispc_enable_lcd_out(1);
++
++      r = dssdev->driver->enable(dssdev);
++      if (r)
++              goto err5;
++
++      dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++      return 0;
++
++err5:
++      dispc_enable_lcd_out(0);
++err4:
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++      dsi_pll_uninit();
++err3:
++      dss_clk_disable(DSS_CLK_FCK2);
++#endif
++err2:
++      dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++err1:
++      omap_dss_stop_device(dssdev);
++err0:
++      return r;
++}
++
++static int dpi_display_resume(struct omap_dss_device *dssdev);
++
++static void dpi_display_disable(struct omap_dss_device *dssdev)
++{
++      if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED)
++              return;
++
++      if (dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED)
++              dpi_display_resume(dssdev);
++
++      dssdev->driver->disable(dssdev);
++
++      dispc_enable_lcd_out(0);
++
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++      dss_select_clk_source(0, 0);
++      dsi_pll_uninit();
++      dss_clk_disable(DSS_CLK_FCK2);
++#endif
++
++      dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++      dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
++
++      omap_dss_stop_device(dssdev);
++}
++
++static int dpi_display_suspend(struct omap_dss_device *dssdev)
++{
++      if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
++              return -EINVAL;
++
++      DSSDBG("dpi_display_suspend\n");
++
++      if (dssdev->driver->suspend)
++              dssdev->driver->suspend(dssdev);
++
++      dispc_enable_lcd_out(0);
++
++      dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++      dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED;
++
++      return 0;
++}
++
++static int dpi_display_resume(struct omap_dss_device *dssdev)
++{
++      if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED)
++              return -EINVAL;
++
++      DSSDBG("dpi_display_resume\n");
++
++      dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++      dispc_enable_lcd_out(1);
++
++      if (dssdev->driver->resume)
++              dssdev->driver->resume(dssdev);
++
++      dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++      return 0;
++}
++
++static void dpi_set_timings(struct omap_dss_device *dssdev,
++                      struct omap_video_timings *timings)
++{
++      DSSDBG("dpi_set_timings\n");
++      dssdev->panel.timings = *timings;
++      if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
++              dpi_set_mode(dssdev);
++              dispc_go(OMAP_DSS_CHANNEL_LCD);
++      }
++}
++
++static int dpi_check_timings(struct omap_dss_device *dssdev,
++                      struct omap_video_timings *timings)
++{
++      bool is_tft;
++      int r;
++      int lck_div, pck_div;
++      unsigned long fck;
++      unsigned long pck;
++
++      if (!dispc_lcd_timings_ok(timings))
++              return -EINVAL;
++
++      if (timings->pixel_clock == 0)
++              return -EINVAL;
++
++      is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
++
++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
++      {
++              struct dsi_clock_info cinfo;
++              r = dsi_pll_calc_pck(is_tft, timings->pixel_clock * 1000,
++                              &cinfo);
++
++              if (r)
++                      return r;
++
++              fck = cinfo.dsi1_pll_fclk;
++              lck_div = cinfo.lck_div;
++              pck_div = cinfo.pck_div;
++      }
++#else
++      {
++              struct dispc_clock_info cinfo;
++              r = dispc_calc_clock_div(is_tft, timings->pixel_clock * 1000,
++                              &cinfo);
++
++              if (r)
++                      return r;
++
++              fck = cinfo.fck;
++              lck_div = cinfo.lck_div;
++              pck_div = cinfo.pck_div;
++      }
++#endif
++
++      pck = fck / lck_div / pck_div / 1000;
++
++      timings->pixel_clock = pck;
++
++      return 0;
++}
++
++static void dpi_get_timings(struct omap_dss_device *dssdev,
++                      struct omap_video_timings *timings)
++{
++      *timings = dssdev->panel.timings;
++}
++
++static int dpi_display_set_update_mode(struct omap_dss_device *dssdev,
++              enum omap_dss_update_mode mode)
++{
++      if (mode == OMAP_DSS_UPDATE_MANUAL)
++              return -EINVAL;
++
++      if (mode == OMAP_DSS_UPDATE_DISABLED) {
++              dispc_enable_lcd_out(0);
++              dpi.update_enabled = 0;
++      } else {
++              dispc_enable_lcd_out(1);
++              dpi.update_enabled = 1;
++      }
++
++      return 0;
++}
++
++static enum omap_dss_update_mode dpi_display_get_update_mode(
++              struct omap_dss_device *dssdev)
++{
++      return dpi.update_enabled ? OMAP_DSS_UPDATE_AUTO :
++              OMAP_DSS_UPDATE_DISABLED;
++}
++
++int dpi_init_display(struct omap_dss_device *dssdev)
++{
++      DSSDBG("init_display\n");
++
++      dssdev->enable = dpi_display_enable;
++      dssdev->disable = dpi_display_disable;
++      dssdev->suspend = dpi_display_suspend;
++      dssdev->resume = dpi_display_resume;
++      dssdev->set_timings = dpi_set_timings;
++      dssdev->check_timings = dpi_check_timings;
++      dssdev->get_timings = dpi_get_timings;
++      dssdev->set_update_mode = dpi_display_set_update_mode;
++      dssdev->get_update_mode = dpi_display_get_update_mode;
++
++      return 0;
++}
++
++int dpi_init(void)
++{
++      return 0;
++}
++
++void dpi_exit(void)
++{
++}
++
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-2.6.31/dss2/0011-OMAP-DSS2-Video-encoder-driver.patch b/recipes/linux/linux-omap-2.6.31/dss2/0011-OMAP-DSS2-Video-encoder-driver.patch
new file mode 100644 (file)
index 0000000..f3cb9ab
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.31/dss2/0011-OMAP-DSS2-Video-encoder-driver.patch
@@ -0,0 +1,821 @@
+From e954e1ef739c39ffe671981ee8adbc7e9bb0249e Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Wed, 5 Aug 2009 16:18:06 +0300
+Subject: [PATCH 11/18] OMAP: DSS2: Video encoder driver
+
+VENC (video encoder) driver implements OMAP's analog S-Video/Composite
+TV-out.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Acked-by: Tony Lindgren <tony@atomide.com>
+---
+ drivers/video/omap2/dss/venc.c |  797 ++++++++++++++++++++++++++++++++++++++++
+ 1 files changed, 797 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/video/omap2/dss/venc.c
+
+diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c
+new file mode 100644
+index 0000000..cf7827e
+--- /dev/null
++++ b/drivers/video/omap2/dss/venc.c
+@@ -0,0 +1,797 @@
++/*
++ * linux/drivers/video/omap2/dss/venc.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * VENC settings from TI's DSS driver
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "VENC"
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/mutex.h>
++#include <linux/completion.h>
++#include <linux/delay.h>
++#include <linux/string.h>
++#include <linux/seq_file.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++
++#include <mach/display.h>
++#include <mach/cpu.h>
++
++#include "dss.h"
++
++#define VENC_BASE     0x48050C00
++
++/* Venc registers */
++#define VENC_REV_ID                           0x00
++#define VENC_STATUS                           0x04
++#define VENC_F_CONTROL                                0x08
++#define VENC_VIDOUT_CTRL                      0x10
++#define VENC_SYNC_CTRL                                0x14
++#define VENC_LLEN                             0x1C
++#define VENC_FLENS                            0x20
++#define VENC_HFLTR_CTRL                               0x24
++#define VENC_CC_CARR_WSS_CARR                 0x28
++#define VENC_C_PHASE                          0x2C
++#define VENC_GAIN_U                           0x30
++#define VENC_GAIN_V                           0x34
++#define VENC_GAIN_Y                           0x38
++#define VENC_BLACK_LEVEL                      0x3C
++#define VENC_BLANK_LEVEL                      0x40
++#define VENC_X_COLOR                          0x44
++#define VENC_M_CONTROL                                0x48
++#define VENC_BSTAMP_WSS_DATA                  0x4C
++#define VENC_S_CARR                           0x50
++#define VENC_LINE21                           0x54
++#define VENC_LN_SEL                           0x58
++#define VENC_L21__WC_CTL                      0x5C
++#define VENC_HTRIGGER_VTRIGGER                        0x60
++#define VENC_SAVID__EAVID                     0x64
++#define VENC_FLEN__FAL                                0x68
++#define VENC_LAL__PHASE_RESET                 0x6C
++#define VENC_HS_INT_START_STOP_X              0x70
++#define VENC_HS_EXT_START_STOP_X              0x74
++#define VENC_VS_INT_START_X                   0x78
++#define VENC_VS_INT_STOP_X__VS_INT_START_Y    0x7C
++#define VENC_VS_INT_STOP_Y__VS_EXT_START_X    0x80
++#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y    0x84
++#define VENC_VS_EXT_STOP_Y                    0x88
++#define VENC_AVID_START_STOP_X                        0x90
++#define VENC_AVID_START_STOP_Y                        0x94
++#define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
++#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X        0xA4
++#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y        0xA8
++#define VENC_TVDETGP_INT_START_STOP_X         0xB0
++#define VENC_TVDETGP_INT_START_STOP_Y         0xB4
++#define VENC_GEN_CTRL                         0xB8
++#define VENC_OUTPUT_CONTROL                   0xC4
++#define VENC_OUTPUT_TEST                      0xC8
++#define VENC_DAC_B__DAC_C                     0xC8
++
++struct venc_config {
++      u32 f_control;
++      u32 vidout_ctrl;
++      u32 sync_ctrl;
++      u32 llen;
++      u32 flens;
++      u32 hfltr_ctrl;
++      u32 cc_carr_wss_carr;
++      u32 c_phase;
++      u32 gain_u;
++      u32 gain_v;
++      u32 gain_y;
++      u32 black_level;
++      u32 blank_level;
++      u32 x_color;
++      u32 m_control;
++      u32 bstamp_wss_data;
++      u32 s_carr;
++      u32 line21;
++      u32 ln_sel;
++      u32 l21__wc_ctl;
++      u32 htrigger_vtrigger;
++      u32 savid__eavid;
++      u32 flen__fal;
++      u32 lal__phase_reset;
++      u32 hs_int_start_stop_x;
++      u32 hs_ext_start_stop_x;
++      u32 vs_int_start_x;
++      u32 vs_int_stop_x__vs_int_start_y;
++      u32 vs_int_stop_y__vs_ext_start_x;
++      u32 vs_ext_stop_x__vs_ext_start_y;
++      u32 vs_ext_stop_y;
++      u32 avid_start_stop_x;
++      u32 avid_start_stop_y;
++      u32 fid_int_start_x__fid_int_start_y;
++      u32 fid_int_offset_y__fid_ext_start_x;
++      u32 fid_ext_start_y__fid_ext_offset_y;
++      u32 tvdetgp_int_start_stop_x;
++      u32 tvdetgp_int_start_stop_y;
++      u32 gen_ctrl;
++};
++
++/* from TRM */
++static const struct venc_config venc_config_pal_trm = {
++      .f_control                              = 0,
++      .vidout_ctrl                            = 1,
++      .sync_ctrl                              = 0x40,
++      .llen                                   = 0x35F, /* 863 */
++      .flens                                  = 0x270, /* 624 */
++      .hfltr_ctrl                             = 0,
++      .cc_carr_wss_carr                       = 0x2F7225ED,
++      .c_phase                                = 0,
++      .gain_u                                 = 0x111,
++      .gain_v                                 = 0x181,
++      .gain_y                                 = 0x140,
++      .black_level                            = 0x3B,
++      .blank_level                            = 0x3B,
++      .x_color                                = 0x7,
++      .m_control                              = 0x2,
++      .bstamp_wss_data                        = 0x3F,
++      .s_carr                                 = 0x2A098ACB,
++      .line21                                 = 0,
++      .ln_sel                                 = 0x01290015,
++      .l21__wc_ctl                            = 0x0000F603,
++      .htrigger_vtrigger                      = 0,
++
++      .savid__eavid                           = 0x06A70108,
++      .flen__fal                              = 0x00180270,
++      .lal__phase_reset                       = 0x00040135,
++      .hs_int_start_stop_x                    = 0x00880358,
++      .hs_ext_start_stop_x                    = 0x000F035F,
++      .vs_int_start_x                         = 0x01A70000,
++      .vs_int_stop_x__vs_int_start_y          = 0x000001A7,
++      .vs_int_stop_y__vs_ext_start_x          = 0x01AF0000,
++      .vs_ext_stop_x__vs_ext_start_y          = 0x000101AF,
++      .vs_ext_stop_y                          = 0x00000025,
++      .avid_start_stop_x                      = 0x03530083,
++      .avid_start_stop_y                      = 0x026C002E,
++      .fid_int_start_x__fid_int_start_y       = 0x0001008A,
++      .fid_int_offset_y__fid_ext_start_x      = 0x002E0138,
++      .fid_ext_start_y__fid_ext_offset_y      = 0x01380001,
++
++      .tvdetgp_int_start_stop_x               = 0x00140001,
++      .tvdetgp_int_start_stop_y               = 0x00010001,
++      .gen_ctrl                               = 0x00FF0000,
++};
++
++/* from TRM */
++static const struct venc_config venc_config_ntsc_trm = {
++      .f_control                              = 0,
++      .vidout_ctrl                            = 1,
++      .sync_ctrl                              = 0x8040,
++      .llen                                   = 0x359,
++      .flens                                  = 0x20C,
++      .hfltr_ctrl                             = 0,
++      .cc_carr_wss_carr                       = 0x043F2631,
++      .c_phase                                = 0,
++      .gain_u                                 = 0x102,
++      .gain_v                                 = 0x16C,
++      .gain_y                                 = 0x12F,
++      .black_level                            = 0x43,
++      .blank_level                            = 0x38,
++      .x_color                                = 0x7,
++      .m_control                              = 0x1,
++      .bstamp_wss_data                        = 0x38,
++      .s_carr                                 = 0x21F07C1F,
++      .line21                                 = 0,
++      .ln_sel                                 = 0x01310011,
++      .l21__wc_ctl                            = 0x0000F003,
++      .htrigger_vtrigger                      = 0,
++
++      .savid__eavid                           = 0x069300F4,
++      .flen__fal                              = 0x0016020C,
++      .lal__phase_reset                       = 0x00060107,
++      .hs_int_start_stop_x                    = 0x008E0350,
++      .hs_ext_start_stop_x                    = 0x000F0359,
++      .vs_int_start_x                         = 0x01A00000,
++      .vs_int_stop_x__vs_int_start_y          = 0x020701A0,
++      .vs_int_stop_y__vs_ext_start_x          = 0x01AC0024,
++      .vs_ext_stop_x__vs_ext_start_y          = 0x020D01AC,
++      .vs_ext_stop_y                          = 0x00000006,
++      .avid_start_stop_x                      = 0x03480078,
++      .avid_start_stop_y                      = 0x02060024,
++      .fid_int_start_x__fid_int_start_y       = 0x0001008A,
++      .fid_int_offset_y__fid_ext_start_x      = 0x01AC0106,
++      .fid_ext_start_y__fid_ext_offset_y      = 0x01060006,
++
++      .tvdetgp_int_start_stop_x               = 0x00140001,
++      .tvdetgp_int_start_stop_y               = 0x00010001,
++      .gen_ctrl                               = 0x00F90000,
++};
++
++static const struct venc_config venc_config_pal_bdghi = {
++      .f_control                              = 0,
++      .vidout_ctrl                            = 0,
++      .sync_ctrl                              = 0,
++      .hfltr_ctrl                             = 0,
++      .x_color                                = 0,
++      .line21                                 = 0,
++      .ln_sel                                 = 21,
++      .htrigger_vtrigger                      = 0,
++      .tvdetgp_int_start_stop_x               = 0x00140001,
++      .tvdetgp_int_start_stop_y               = 0x00010001,
++      .gen_ctrl                               = 0x00FB0000,
++
++      .llen                                   = 864-1,
++      .flens                                  = 625-1,
++      .cc_carr_wss_carr                       = 0x2F7625ED,
++      .c_phase                                = 0xDF,
++      .gain_u                                 = 0x111,
++      .gain_v                                 = 0x181,
++      .gain_y                                 = 0x140,
++      .black_level                            = 0x3e,
++      .blank_level                            = 0x3e,
++      .m_control                              = 0<<2 | 1<<1,
++      .bstamp_wss_data                        = 0x42,
++      .s_carr                                 = 0x2a098acb,
++      .l21__wc_ctl                            = 0<<13 | 0x16<<8 | 0<<0,
++      .savid__eavid                           = 0x06A70108,
++      .flen__fal                              = 23<<16 | 624<<0,
++      .lal__phase_reset                       = 2<<17 | 310<<0,
++      .hs_int_start_stop_x                    = 0x00920358,
++      .hs_ext_start_stop_x                    = 0x000F035F,
++      .vs_int_start_x                         = 0x1a7<<16,
++      .vs_int_stop_x__vs_int_start_y          = 0x000601A7,
++      .vs_int_stop_y__vs_ext_start_x          = 0x01AF0036,
++      .vs_ext_stop_x__vs_ext_start_y          = 0x27101af,
++      .vs_ext_stop_y                          = 0x05,
++      .avid_start_stop_x                      = 0x03530082,
++      .avid_start_stop_y                      = 0x0270002E,
++      .fid_int_start_x__fid_int_start_y       = 0x0005008A,
++      .fid_int_offset_y__fid_ext_start_x      = 0x002E0138,
++      .fid_ext_start_y__fid_ext_offset_y      = 0x01380005,
++};
++
++const struct omap_video_timings omap_dss_pal_timings = {
++      .x_res          = 720,
++      .y_res          = 574,
++      .pixel_clock    = 13500,
++      .hsw            = 64,
++      .hfp            = 12,
++      .hbp            = 68,
++      .vsw            = 5,
++      .vfp            = 5,
++      .vbp            = 41,
++};
++EXPORT_SYMBOL(omap_dss_pal_timings);
++
++const struct omap_video_timings omap_dss_ntsc_timings = {
++      .x_res          = 720,
++      .y_res          = 482,
++      .pixel_clock    = 13500,
++      .hsw            = 64,
++      .hfp            = 16,
++      .hbp            = 58,
++      .vsw            = 6,
++      .vfp            = 6,
++      .vbp            = 31,
++};
++EXPORT_SYMBOL(omap_dss_ntsc_timings);
++
++static struct {
++      void __iomem *base;
++      struct mutex venc_lock;
++      u32 wss_data;
++      struct regulator *vdda_dac_reg;
++} venc;
++
++static inline void venc_write_reg(int idx, u32 val)
++{
++      __raw_writel(val, venc.base + idx);
++}
++
++static inline u32 venc_read_reg(int idx)
++{
++      u32 l = __raw_readl(venc.base + idx);
++      return l;
++}
++
++static void venc_write_config(const struct venc_config *config)
++{
++      DSSDBG("write venc conf\n");
++
++      venc_write_reg(VENC_LLEN, config->llen);
++      venc_write_reg(VENC_FLENS, config->flens);
++      venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
++      venc_write_reg(VENC_C_PHASE, config->c_phase);
++      venc_write_reg(VENC_GAIN_U, config->gain_u);
++      venc_write_reg(VENC_GAIN_V, config->gain_v);
++      venc_write_reg(VENC_GAIN_Y, config->gain_y);
++      venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
++      venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
++      venc_write_reg(VENC_M_CONTROL, config->m_control);
++      venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
++                      venc.wss_data);
++      venc_write_reg(VENC_S_CARR, config->s_carr);
++      venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
++      venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
++      venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
++      venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
++      venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
++      venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
++      venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
++      venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
++                     config->vs_int_stop_x__vs_int_start_y);
++      venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
++                     config->vs_int_stop_y__vs_ext_start_x);
++      venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
++                     config->vs_ext_stop_x__vs_ext_start_y);
++      venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
++      venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
++      venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
++      venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
++                     config->fid_int_start_x__fid_int_start_y);
++      venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
++                     config->fid_int_offset_y__fid_ext_start_x);
++      venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
++                     config->fid_ext_start_y__fid_ext_offset_y);
++
++      venc_write_reg(VENC_DAC_B__DAC_C,  venc_read_reg(VENC_DAC_B__DAC_C));
++      venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
++      venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
++      venc_write_reg(VENC_X_COLOR, config->x_color);
++      venc_write_reg(VENC_LINE21, config->line21);
++      venc_write_reg(VENC_LN_SEL, config->ln_sel);
++      venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
++      venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
++                     config->tvdetgp_int_start_stop_x);
++      venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
++                     config->tvdetgp_int_start_stop_y);
++      venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
++      venc_write_reg(VENC_F_CONTROL, config->f_control);
++      venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
++}
++
++static void venc_reset(void)
++{
++      int t = 1000;
++
++      venc_write_reg(VENC_F_CONTROL, 1<<8);
++      while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
++              if (--t == 0) {
++                      DSSERR("Failed to reset venc\n");
++                      return;
++              }
++      }
++
++      /* the magical sleep that makes things work */
++      msleep(20);
++}
++
++static void venc_enable_clocks(int enable)
++{
++      if (enable)
++              dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M |
++                              DSS_CLK_96M);
++      else
++              dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M |
++                              DSS_CLK_96M);
++}
++
++static const struct venc_config *venc_timings_to_config(
++              struct omap_video_timings *timings)
++{
++      if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
++              return &venc_config_pal_trm;
++
++      if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
++              return &venc_config_ntsc_trm;
++
++      BUG();
++}
++
++
++
++
++
++/* driver */
++static int venc_panel_probe(struct omap_dss_device *dssdev)
++{
++      dssdev->panel.timings = omap_dss_pal_timings;
++
++      return 0;
++}
++
++static void venc_panel_remove(struct omap_dss_device *dssdev)
++{
++}
++
++static int venc_panel_enable(struct omap_dss_device *dssdev)
++{
++      int r = 0;
++
++      /* wait couple of vsyncs until enabling the LCD */
++      msleep(50);
++
++      if (dssdev->platform_enable)
++              r = dssdev->platform_enable(dssdev);
++
++      return r;
++}
++
++static void venc_panel_disable(struct omap_dss_device *dssdev)
++{
++      if (dssdev->platform_disable)
++              dssdev->platform_disable(dssdev);
++
++      /* wait at least 5 vsyncs after disabling the LCD */
++
++      msleep(100);
++}
++
++static int venc_panel_suspend(struct omap_dss_device *dssdev)
++{
++      venc_panel_disable(dssdev);
++      return 0;
++}
++
++static int venc_panel_resume(struct omap_dss_device *dssdev)
++{
++      return venc_panel_enable(dssdev);
++}
++
++static struct omap_dss_driver venc_driver = {
++      .probe          = venc_panel_probe,
++      .remove         = venc_panel_remove,
++
++      .enable         = venc_panel_enable,
++      .disable        = venc_panel_disable,
++      .suspend        = venc_panel_suspend,
++      .resume         = venc_panel_resume,
++
++      .driver         = {
++              .name   = "venc",
++              .owner  = THIS_MODULE,
++      },
++};
++/* driver end */
++
++
++
++int venc_init(struct platform_device *pdev)
++{
++      u8 rev_id;
++
++      mutex_init(&venc.venc_lock);
++
++      venc.wss_data = 0;
++
++      venc.base = ioremap(VENC_BASE, SZ_1K);
++      if (!venc.base) {
++              DSSERR("can't ioremap VENC\n");
++              return -ENOMEM;
++      }
++
++      venc.vdda_dac_reg = regulator_get(&pdev->dev, "vdda_dac");
++      if (IS_ERR(venc.vdda_dac_reg)) {
++              iounmap(venc.base);
++              DSSERR("can't get VDDA_DAC regulator\n");
++              return PTR_ERR(venc.vdda_dac_reg);
++      }
++
++      venc_enable_clocks(1);
++
++      rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
++      printk(KERN_INFO "OMAP VENC rev %d\n", rev_id);
++
++      venc_enable_clocks(0);
++
++      return omap_dss_register_driver(&venc_driver);
++}
++
++void venc_exit(void)
++{
++      omap_dss_unregister_driver(&venc_driver);
++
++      regulator_put(venc.vdda_dac_reg);
++
++      iounmap(venc.base);
++}
++
++static void venc_power_on(struct omap_dss_device *dssdev)
++{
++      u32 l;
++
++      venc_enable_clocks(1);
++
++      venc_reset();
++      venc_write_config(venc_timings_to_config(&dssdev->panel.timings));
++
++      dss_set_venc_output(dssdev->phy.venc.type);
++      dss_set_dac_pwrdn_bgz(1);
++
++      l = 0;
++
++      if (dssdev->phy.venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
++              l |= 1 << 1;
++      else /* S-Video */
++              l |= (1 << 0) | (1 << 2);
++
++      if (dssdev->phy.venc.invert_polarity == false)
++              l |= 1 << 3;
++
++      venc_write_reg(VENC_OUTPUT_CONTROL, l);
++
++      dispc_set_digit_size(dssdev->panel.timings.x_res,
++                      dssdev->panel.timings.y_res/2);
++
++      regulator_enable(venc.vdda_dac_reg);
++
++      if (dssdev->platform_enable)
++              dssdev->platform_enable(dssdev);
++
++      dispc_enable_digit_out(1);
++}
++
++static void venc_power_off(struct omap_dss_device *dssdev)
++{
++      venc_write_reg(VENC_OUTPUT_CONTROL, 0);
++      dss_set_dac_pwrdn_bgz(0);
++
++      dispc_enable_digit_out(0);
++
++      if (dssdev->platform_disable)
++              dssdev->platform_disable(dssdev);
++
++      regulator_disable(venc.vdda_dac_reg);
++
++      venc_enable_clocks(0);
++}
++
++static int venc_enable_display(struct omap_dss_device *dssdev)
++{
++      int r = 0;
++
++      DSSDBG("venc_enable_display\n");
++
++      mutex_lock(&venc.venc_lock);
++
++      if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
++              r = -EINVAL;
++              goto err;
++      }
++
++      venc_power_on(dssdev);
++
++      venc.wss_data = 0;
++
++      dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
++err:
++      mutex_unlock(&venc.venc_lock);
++
++      return r;
++}
++
++static void venc_disable_display(struct omap_dss_device *dssdev)
++{
++      DSSDBG("venc_disable_display\n");
++
++      mutex_lock(&venc.venc_lock);
++
++      if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED)
++              goto end;
++
++      if (dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED) {
++              /* suspended is the same as disabled with venc */
++              dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
++              goto end;
++      }
++
++      venc_power_off(dssdev);
++
++      dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
++end:
++      mutex_unlock(&venc.venc_lock);
++}
++
++static int venc_display_suspend(struct omap_dss_device *dssdev)
++{
++      int r = 0;
++
++      DSSDBG("venc_display_suspend\n");
++
++      mutex_lock(&venc.venc_lock);
++
++      if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) {
++              r = -EINVAL;
++              goto err;
++      }
++
++      venc_power_off(dssdev);
++
++      dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED;
++err:
++      mutex_unlock(&venc.venc_lock);
++
++      return r;
++}
++
++static int venc_display_resume(struct omap_dss_device *dssdev)
++{
++      int r = 0;
++
++      DSSDBG("venc_display_resume\n");
++
++      mutex_lock(&venc.venc_lock);
++
++      if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) {
++              r = -EINVAL;
++              goto err;
++      }
++
++      venc_power_on(dssdev);
++
++      dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
++err:
++      mutex_unlock(&venc.venc_lock);
++
++      return r;
++}
++
++static void venc_get_timings(struct omap_dss_device *dssdev,
++                      struct omap_video_timings *timings)
++{
++      *timings = dssdev->panel.timings;
++}
++
++static void venc_set_timings(struct omap_dss_device *dssdev,
++                      struct omap_video_timings *timings)
++{
++      DSSDBG("venc_set_timings\n");
++
++      /* Reset WSS data when the TV standard changes. */
++      if (memcmp(&dssdev->panel.timings, timings, sizeof(*timings)))
++              venc.wss_data = 0;
++
++      dssdev->panel.timings = *timings;
++      if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
++              /* turn the venc off and on to get new timings to use */
++              venc_disable_display(dssdev);
++              venc_enable_display(dssdev);
++      }
++}
++
++static int venc_check_timings(struct omap_dss_device *dssdev,
++                      struct omap_video_timings *timings)
++{
++      DSSDBG("venc_check_timings\n");
++
++      if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
++              return 0;
++
++      if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
++              return 0;
++
++      return -EINVAL;
++}
++
++static u32 venc_get_wss(struct omap_dss_device *dssdev)
++{
++      /* Invert due to VENC_L21_WC_CTL:INV=1 */
++      return (venc.wss_data >> 8) ^ 0xfffff;
++}
++
++static int venc_set_wss(struct omap_dss_device *dssdev,       u32 wss)
++{
++      const struct venc_config *config;
++
++      DSSDBG("venc_set_wss\n");
++
++      mutex_lock(&venc.venc_lock);
++
++      config = venc_timings_to_config(&dssdev->panel.timings);
++
++      /* Invert due to VENC_L21_WC_CTL:INV=1 */
++      venc.wss_data = (wss ^ 0xfffff) << 8;
++
++      venc_enable_clocks(1);
++
++      venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
++                      venc.wss_data);
++
++      venc_enable_clocks(0);
++
++      mutex_unlock(&venc.venc_lock);
++
++      return 0;
++}
++
++static enum omap_dss_update_mode venc_display_get_update_mode(
++              struct omap_dss_device *dssdev)
++{
++      if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
++              return OMAP_DSS_UPDATE_AUTO;
++      else
++              return OMAP_DSS_UPDATE_DISABLED;
++}
++
++int venc_init_display(struct omap_dss_device *dssdev)
++{
++      DSSDBG("init_display\n");
++
++      dssdev->enable = venc_enable_display;
++      dssdev->disable = venc_disable_display;
++      dssdev->suspend = venc_display_suspend;
++      dssdev->resume = venc_display_resume;
++      dssdev->get_timings = venc_get_timings;
++      dssdev->set_timings = venc_set_timings;
++      dssdev->check_timings = venc_check_timings;
++      dssdev->get_wss = venc_get_wss;
++      dssdev->set_wss = venc_set_wss;
++      dssdev->get_update_mode = venc_display_get_update_mode;
++
++      return 0;
++}
++
++void venc_dump_regs(struct seq_file *s)
++{
++#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
++
++      venc_enable_clocks(1);
++
++      DUMPREG(VENC_F_CONTROL);
++      DUMPREG(VENC_VIDOUT_CTRL);
++      DUMPREG(VENC_SYNC_CTRL);
++      DUMPREG(VENC_LLEN);
++      DUMPREG(VENC_FLENS);
++      DUMPREG(VENC_HFLTR_CTRL);
++      DUMPREG(VENC_CC_CARR_WSS_CARR);
++      DUMPREG(VENC_C_PHASE);
++      DUMPREG(VENC_GAIN_U);
++      DUMPREG(VENC_GAIN_V);
++      DUMPREG(VENC_GAIN_Y);
++      DUMPREG(VENC_BLACK_LEVEL);
++      DUMPREG(VENC_BLANK_LEVEL);
++      DUMPREG(VENC_X_COLOR);
++      DUMPREG(VENC_M_CONTROL);
++      DUMPREG(VENC_BSTAMP_WSS_DATA);
++      DUMPREG(VENC_S_CARR);
++      DUMPREG(VENC_LINE21);
++      DUMPREG(VENC_LN_SEL);
++      DUMPREG(VENC_L21__WC_CTL);
++      DUMPREG(VENC_HTRIGGER_VTRIGGER);
++      DUMPREG(VENC_SAVID__EAVID);
++      DUMPREG(VENC_FLEN__FAL);
++      DUMPREG(VENC_LAL__PHASE_RESET);
++      DUMPREG(VENC_HS_INT_START_STOP_X);
++      DUMPREG(VENC_HS_EXT_START_STOP_X);
++      DUMPREG(VENC_VS_INT_START_X);
++      DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
++      DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
++      DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
++      DUMPREG(VENC_VS_EXT_STOP_Y);
++      DUMPREG(VENC_AVID_START_STOP_X);
++      DUMPREG(VENC_AVID_START_STOP_Y);
++      DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
++      DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
++      DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
++      DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
++      DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
++      DUMPREG(VENC_GEN_CTRL);
++      DUMPREG(VENC_OUTPUT_CONTROL);
++      DUMPREG(VENC_OUTPUT_TEST);
++
++      venc_enable_clocks(0);
++
++#undef DUMPREG
++}
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-2.6.31/dss2/0012-OMAP-DSS2-RFBI-driver.patch b/recipes/linux/linux-omap-2.6.31/dss2/0012-OMAP-DSS2-RFBI-driver.patch
new file mode 100644 (file)
index 0000000..7fe06c3
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.31/dss2/0012-OMAP-DSS2-RFBI-driver.patch
@@ -0,0 +1,1332 @@
+From 6770052329a65dd34cf0a9d6356b650aacb3a535 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Wed, 5 Aug 2009 16:18:31 +0300
+Subject: [PATCH 12/18] OMAP: DSS2: RFBI driver
+
+RFBI (Remote FrameBuffer Interface) implements MIPI DBI interface.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ drivers/video/omap2/dss/rfbi.c | 1310 ++++++++++++++++++++++++++++++++++++++++
+ 1 files changed, 1310 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/video/omap2/dss/rfbi.c
+
+diff --git a/drivers/video/omap2/dss/rfbi.c b/drivers/video/omap2/dss/rfbi.c
+new file mode 100644
+index 0000000..9dd2349
+--- /dev/null
++++ b/drivers/video/omap2/dss/rfbi.c
+@@ -0,0 +1,1310 @@
++/*
++ * linux/drivers/video/omap2/dss/rfbi.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "RFBI"
++
++#include <linux/kernel.h>
++#include <linux/dma-mapping.h>
++#include <linux/vmalloc.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/delay.h>
++#include <linux/kfifo.h>
++#include <linux/ktime.h>
++#include <linux/hrtimer.h>
++#include <linux/seq_file.h>
++
++#include <mach/board.h>
++#include <mach/display.h>
++#include "dss.h"
++
++/*#define MEASURE_PERF*/
++
++#define RFBI_BASE               0x48050800
++
++struct rfbi_reg { u16 idx; };
++
++#define RFBI_REG(idx)         ((const struct rfbi_reg) { idx })
++
++#define RFBI_REVISION         RFBI_REG(0x0000)
++#define RFBI_SYSCONFIG                RFBI_REG(0x0010)
++#define RFBI_SYSSTATUS                RFBI_REG(0x0014)
++#define RFBI_CONTROL          RFBI_REG(0x0040)
++#define RFBI_PIXEL_CNT                RFBI_REG(0x0044)
++#define RFBI_LINE_NUMBER      RFBI_REG(0x0048)
++#define RFBI_CMD              RFBI_REG(0x004c)
++#define RFBI_PARAM            RFBI_REG(0x0050)
++#define RFBI_DATA             RFBI_REG(0x0054)
++#define RFBI_READ             RFBI_REG(0x0058)
++#define RFBI_STATUS           RFBI_REG(0x005c)
++
++#define RFBI_CONFIG(n)                RFBI_REG(0x0060 + (n)*0x18)
++#define RFBI_ONOFF_TIME(n)    RFBI_REG(0x0064 + (n)*0x18)
++#define RFBI_CYCLE_TIME(n)    RFBI_REG(0x0068 + (n)*0x18)
++#define RFBI_DATA_CYCLE1(n)   RFBI_REG(0x006c + (n)*0x18)
++#define RFBI_DATA_CYCLE2(n)   RFBI_REG(0x0070 + (n)*0x18)
++#define RFBI_DATA_CYCLE3(n)   RFBI_REG(0x0074 + (n)*0x18)
++
++#define RFBI_VSYNC_WIDTH      RFBI_REG(0x0090)
++#define RFBI_HSYNC_WIDTH      RFBI_REG(0x0094)
++
++#define RFBI_CMD_FIFO_LEN_BYTES (16 * sizeof(struct update_param))
++
++#define REG_FLD_MOD(idx, val, start, end) \
++      rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end))
++
++/* To work around an RFBI transfer rate limitation */
++#define OMAP_RFBI_RATE_LIMIT    1
++
++enum omap_rfbi_cycleformat {
++      OMAP_DSS_RFBI_CYCLEFORMAT_1_1 = 0,
++      OMAP_DSS_RFBI_CYCLEFORMAT_2_1 = 1,
++      OMAP_DSS_RFBI_CYCLEFORMAT_3_1 = 2,
++      OMAP_DSS_RFBI_CYCLEFORMAT_3_2 = 3,
++};
++
++enum omap_rfbi_datatype {
++      OMAP_DSS_RFBI_DATATYPE_12 = 0,
++      OMAP_DSS_RFBI_DATATYPE_16 = 1,
++      OMAP_DSS_RFBI_DATATYPE_18 = 2,
++      OMAP_DSS_RFBI_DATATYPE_24 = 3,
++};
++
++enum omap_rfbi_parallelmode {
++      OMAP_DSS_RFBI_PARALLELMODE_8 = 0,
++      OMAP_DSS_RFBI_PARALLELMODE_9 = 1,
++      OMAP_DSS_RFBI_PARALLELMODE_12 = 2,
++      OMAP_DSS_RFBI_PARALLELMODE_16 = 3,
++};
++
++enum update_cmd {
++      RFBI_CMD_UPDATE = 0,
++      RFBI_CMD_SYNC   = 1,
++};
++
++static int rfbi_convert_timings(struct rfbi_timings *t);
++static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div);
++static void process_cmd_fifo(void);
++
++static struct {
++      void __iomem    *base;
++
++      unsigned long   l4_khz;
++
++      enum omap_rfbi_datatype datatype;
++      enum omap_rfbi_parallelmode parallelmode;
++
++      enum omap_rfbi_te_mode te_mode;
++      int te_enabled;
++
++      void (*framedone_callback)(void *data);
++      void *framedone_callback_data;
++
++      struct omap_dss_device *dssdev[2];
++
++      struct kfifo      *cmd_fifo;
++      spinlock_t        cmd_lock;
++      struct completion cmd_done;
++      atomic_t          cmd_fifo_full;
++      atomic_t          cmd_pending;
++#ifdef MEASURE_PERF
++      unsigned perf_bytes;
++      ktime_t perf_setup_time;
++      ktime_t perf_start_time;
++#endif
++} rfbi;
++
++struct update_region {
++      u16     x;
++      u16     y;
++      u16     w;
++      u16     h;
++};
++
++struct update_param {
++      u8 rfbi_module;
++      u8 cmd;
++
++      union {
++              struct update_region r;
++              struct completion *sync;
++      } par;
++};
++
++static inline void rfbi_write_reg(const struct rfbi_reg idx, u32 val)
++{
++      __raw_writel(val, rfbi.base + idx.idx);
++}
++
++static inline u32 rfbi_read_reg(const struct rfbi_reg idx)
++{
++      return __raw_readl(rfbi.base + idx.idx);
++}
++
++static void rfbi_enable_clocks(bool enable)
++{
++      if (enable)
++              dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++      else
++              dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++}
++
++void omap_rfbi_write_command(const void *buf, u32 len)
++{
++      rfbi_enable_clocks(1);
++      switch (rfbi.parallelmode) {
++      case OMAP_DSS_RFBI_PARALLELMODE_8:
++      {
++              const u8 *b = buf;
++              for (; len; len--)
++                      rfbi_write_reg(RFBI_CMD, *b++);
++              break;
++      }
++
++      case OMAP_DSS_RFBI_PARALLELMODE_16:
++      {
++              const u16 *w = buf;
++              BUG_ON(len & 1);
++              for (; len; len -= 2)
++                      rfbi_write_reg(RFBI_CMD, *w++);
++              break;
++      }
++
++      case OMAP_DSS_RFBI_PARALLELMODE_9:
++      case OMAP_DSS_RFBI_PARALLELMODE_12:
++      default:
++              BUG();
++      }
++      rfbi_enable_clocks(0);
++}
++EXPORT_SYMBOL(omap_rfbi_write_command);
++
++void omap_rfbi_read_data(void *buf, u32 len)
++{
++      rfbi_enable_clocks(1);
++      switch (rfbi.parallelmode) {
++      case OMAP_DSS_RFBI_PARALLELMODE_8:
++      {
++              u8 *b = buf;
++              for (; len; len--) {
++                      rfbi_write_reg(RFBI_READ, 0);
++                      *b++ = rfbi_read_reg(RFBI_READ);
++              }
++              break;
++      }
++
++      case OMAP_DSS_RFBI_PARALLELMODE_16:
++      {
++              u16 *w = buf;
++              BUG_ON(len & ~1);
++              for (; len; len -= 2) {
++                      rfbi_write_reg(RFBI_READ, 0);
++                      *w++ = rfbi_read_reg(RFBI_READ);
++              }
++              break;
++      }
++
++      case OMAP_DSS_RFBI_PARALLELMODE_9:
++      case OMAP_DSS_RFBI_PARALLELMODE_12:
++      default:
++              BUG();
++      }
++      rfbi_enable_clocks(0);
++}
++EXPORT_SYMBOL(omap_rfbi_read_data);
++
++void omap_rfbi_write_data(const void *buf, u32 len)
++{
++      rfbi_enable_clocks(1);
++      switch (rfbi.parallelmode) {
++      case OMAP_DSS_RFBI_PARALLELMODE_8:
++      {
++              const u8 *b = buf;
++              for (; len; len--)
++                      rfbi_write_reg(RFBI_PARAM, *b++);
++              break;
++      }
++
++      case OMAP_DSS_RFBI_PARALLELMODE_16:
++      {
++              const u16 *w = buf;
++              BUG_ON(len & 1);
++              for (; len; len -= 2)
++                      rfbi_write_reg(RFBI_PARAM, *w++);
++              break;
++      }
++
++      case OMAP_DSS_RFBI_PARALLELMODE_9:
++      case OMAP_DSS_RFBI_PARALLELMODE_12:
++      default:
++              BUG();
++
++      }
++      rfbi_enable_clocks(0);
++}
++EXPORT_SYMBOL(omap_rfbi_write_data);
++
++void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
++              u16 x, u16 y,
++              u16 w, u16 h)
++{
++      int start_offset = scr_width * y + x;
++      int horiz_offset = scr_width - w;
++      int i;
++
++      rfbi_enable_clocks(1);
++
++      if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
++         rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
++              const u16 __iomem *pd = buf;
++              pd += start_offset;
++
++              for (; h; --h) {
++                      for (i = 0; i < w; ++i) {
++                              const u8 __iomem *b = (const u8 __iomem *)pd;
++                              rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
++                              rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
++                              ++pd;
++                      }
++                      pd += horiz_offset;
++              }
++      } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_24 &&
++         rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
++              const u32 __iomem *pd = buf;
++              pd += start_offset;
++
++              for (; h; --h) {
++                      for (i = 0; i < w; ++i) {
++                              const u8 __iomem *b = (const u8 __iomem *)pd;
++                              rfbi_write_reg(RFBI_PARAM, __raw_readb(b+2));
++                              rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
++                              rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
++                              ++pd;
++                      }
++                      pd += horiz_offset;
++              }
++      } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
++         rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_16) {
++              const u16 __iomem *pd = buf;
++              pd += start_offset;
++
++              for (; h; --h) {
++                      for (i = 0; i < w; ++i) {
++                              rfbi_write_reg(RFBI_PARAM, __raw_readw(pd));
++                              ++pd;
++                      }
++                      pd += horiz_offset;
++              }
++      } else {
++              BUG();
++      }
++
++      rfbi_enable_clocks(0);
++}
++EXPORT_SYMBOL(omap_rfbi_write_pixels);
++
++#ifdef MEASURE_PERF
++static void perf_mark_setup(void)
++{
++      rfbi.perf_setup_time = ktime_get();
++}
++
++static void perf_mark_start(void)
++{
++      rfbi.perf_start_time = ktime_get();
++}
++
++static void perf_show(const char *name)
++{
++      ktime_t t, setup_time, trans_time;
++      u32 total_bytes;
++      u32 setup_us, trans_us, total_us;
++
++      t = ktime_get();
++
++      setup_time = ktime_sub(rfbi.perf_start_time, rfbi.perf_setup_time);
++      setup_us = (u32)ktime_to_us(setup_time);
++      if (setup_us == 0)
++              setup_us = 1;
++
++      trans_time = ktime_sub(t, rfbi.perf_start_time);
++      trans_us = (u32)ktime_to_us(trans_time);
++      if (trans_us == 0)
++              trans_us = 1;
++
++      total_us = setup_us + trans_us;
++
++      total_bytes = rfbi.perf_bytes;
++
++      DSSINFO("%s update %u us + %u us = %u us (%uHz), %u bytes, "
++                      "%u kbytes/sec\n",
++                      name,
++                      setup_us,
++                      trans_us,
++                      total_us,
++                      1000*1000 / total_us,
++                      total_bytes,
++                      total_bytes * 1000 / total_us);
++}
++#else
++#define perf_mark_setup()
++#define perf_mark_start()
++#define perf_show(x)
++#endif
++
++void rfbi_transfer_area(u16 width, u16 height,
++                           void (callback)(void *data), void *data)
++{
++      u32 l;
++
++      /*BUG_ON(callback == 0);*/
++      BUG_ON(rfbi.framedone_callback != NULL);
++
++      DSSDBG("rfbi_transfer_area %dx%d\n", width, height);
++
++      dispc_set_lcd_size(width, height);
++
++      dispc_enable_lcd_out(1);
++
++      rfbi.framedone_callback = callback;
++      rfbi.framedone_callback_data = data;
++
++      rfbi_enable_clocks(1);
++
++      rfbi_write_reg(RFBI_PIXEL_CNT, width * height);
++
++      l = rfbi_read_reg(RFBI_CONTROL);
++      l = FLD_MOD(l, 1, 0, 0); /* enable */
++      if (!rfbi.te_enabled)
++              l = FLD_MOD(l, 1, 4, 4); /* ITE */
++
++      perf_mark_start();
++
++      rfbi_write_reg(RFBI_CONTROL, l);
++}
++
++static void framedone_callback(void *data, u32 mask)
++{
++      void (*callback)(void *data);
++
++      DSSDBG("FRAMEDONE\n");
++
++      perf_show("DISPC");
++
++      REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0);
++
++      rfbi_enable_clocks(0);
++
++      callback = rfbi.framedone_callback;
++      rfbi.framedone_callback = NULL;
++
++      /*callback(rfbi.framedone_callback_data);*/
++
++      atomic_set(&rfbi.cmd_pending, 0);
++
++      process_cmd_fifo();
++}
++
++#if 1 /* VERBOSE */
++static void rfbi_print_timings(void)
++{
++      u32 l;
++      u32 time;
++
++      l = rfbi_read_reg(RFBI_CONFIG(0));
++      time = 1000000000 / rfbi.l4_khz;
++      if (l & (1 << 4))
++              time *= 2;
++
++      DSSDBG("Tick time %u ps\n", time);
++      l = rfbi_read_reg(RFBI_ONOFF_TIME(0));
++      DSSDBG("CSONTIME %d, CSOFFTIME %d, WEONTIME %d, WEOFFTIME %d, "
++              "REONTIME %d, REOFFTIME %d\n",
++              l & 0x0f, (l >> 4) & 0x3f, (l >> 10) & 0x0f, (l >> 14) & 0x3f,
++              (l >> 20) & 0x0f, (l >> 24) & 0x3f);
++
++      l = rfbi_read_reg(RFBI_CYCLE_TIME(0));
++      DSSDBG("WECYCLETIME %d, RECYCLETIME %d, CSPULSEWIDTH %d, "
++              "ACCESSTIME %d\n",
++              (l & 0x3f), (l >> 6) & 0x3f, (l >> 12) & 0x3f,
++              (l >> 22) & 0x3f);
++}
++#else
++static void rfbi_print_timings(void) {}
++#endif
++
++
++
++
++static u32 extif_clk_period;
++
++static inline unsigned long round_to_extif_ticks(unsigned long ps, int div)
++{
++      int bus_tick = extif_clk_period * div;
++      return (ps + bus_tick - 1) / bus_tick * bus_tick;
++}
++
++static int calc_reg_timing(struct rfbi_timings *t, int div)
++{
++      t->clk_div = div;
++
++      t->cs_on_time = round_to_extif_ticks(t->cs_on_time, div);
++
++      t->we_on_time = round_to_extif_ticks(t->we_on_time, div);
++      t->we_off_time = round_to_extif_ticks(t->we_off_time, div);
++      t->we_cycle_time = round_to_extif_ticks(t->we_cycle_time, div);
++
++      t->re_on_time = round_to_extif_ticks(t->re_on_time, div);
++      t->re_off_time = round_to_extif_ticks(t->re_off_time, div);
++      t->re_cycle_time = round_to_extif_ticks(t->re_cycle_time, div);
++
++      t->access_time = round_to_extif_ticks(t->access_time, div);
++      t->cs_off_time = round_to_extif_ticks(t->cs_off_time, div);
++      t->cs_pulse_width = round_to_extif_ticks(t->cs_pulse_width, div);
++
++      DSSDBG("[reg]cson %d csoff %d reon %d reoff %d\n",
++             t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
++      DSSDBG("[reg]weon %d weoff %d recyc %d wecyc %d\n",
++             t->we_on_time, t->we_off_time, t->re_cycle_time,
++             t->we_cycle_time);
++      DSSDBG("[reg]rdaccess %d cspulse %d\n",
++             t->access_time, t->cs_pulse_width);
++
++      return rfbi_convert_timings(t);
++}
++
++static int calc_extif_timings(struct rfbi_timings *t)
++{
++      u32 max_clk_div;
++      int div;
++
++      rfbi_get_clk_info(&extif_clk_period, &max_clk_div);
++      for (div = 1; div <= max_clk_div; div++) {
++              if (calc_reg_timing(t, div) == 0)
++                      break;
++      }
++
++      if (div <= max_clk_div)
++              return 0;
++
++      DSSERR("can't setup timings\n");
++      return -1;
++}
++
++
++void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t)
++{
++      int r;
++
++      if (!t->converted) {
++              r = calc_extif_timings(t);
++              if (r < 0)
++                      DSSERR("Failed to calc timings\n");
++      }
++
++      BUG_ON(!t->converted);
++
++      rfbi_enable_clocks(1);
++      rfbi_write_reg(RFBI_ONOFF_TIME(rfbi_module), t->tim[0]);
++      rfbi_write_reg(RFBI_CYCLE_TIME(rfbi_module), t->tim[1]);
++
++      /* TIMEGRANULARITY */
++      REG_FLD_MOD(RFBI_CONFIG(rfbi_module),
++                  (t->tim[2] ? 1 : 0), 4, 4);
++
++      rfbi_print_timings();
++      rfbi_enable_clocks(0);
++}
++
++static int ps_to_rfbi_ticks(int time, int div)
++{
++      unsigned long tick_ps;
++      int ret;
++
++      /* Calculate in picosecs to yield more exact results */
++      tick_ps = 1000000000 / (rfbi.l4_khz) * div;
++
++      ret = (time + tick_ps - 1) / tick_ps;
++
++      return ret;
++}
++
++#ifdef OMAP_RFBI_RATE_LIMIT
++unsigned long rfbi_get_max_tx_rate(void)
++{
++      unsigned long   l4_rate, dss1_rate;
++      int             min_l4_ticks = 0;
++      int             i;
++
++      /* According to TI this can't be calculated so make the
++       * adjustments for a couple of known frequencies and warn for
++       * others.
++       */
++      static const struct {
++              unsigned long l4_clk;           /* HZ */
++              unsigned long dss1_clk;         /* HZ */
++              unsigned long min_l4_ticks;
++      } ftab[] = {
++              { 55,   132,    7, },           /* 7.86 MPix/s */
++              { 110,  110,    12, },          /* 9.16 MPix/s */
++              { 110,  132,    10, },          /* 11   Mpix/s */
++              { 120,  120,    10, },          /* 12   Mpix/s */
++              { 133,  133,    10, },          /* 13.3 Mpix/s */
++      };
++
++      l4_rate = rfbi.l4_khz / 1000;
++      dss1_rate = dss_clk_get_rate(DSS_CLK_FCK1) / 1000000;
++
++      for (i = 0; i < ARRAY_SIZE(ftab); i++) {
++              /* Use a window instead of an exact match, to account
++               * for different DPLL multiplier / divider pairs.
++               */
++              if (abs(ftab[i].l4_clk - l4_rate) < 3 &&
++                  abs(ftab[i].dss1_clk - dss1_rate) < 3) {
++                      min_l4_ticks = ftab[i].min_l4_ticks;
++                      break;
++              }
++      }
++      if (i == ARRAY_SIZE(ftab)) {
++              /* Can't be sure, return anyway the maximum not
++               * rate-limited. This might cause a problem only for the
++               * tearing synchronisation.
++               */
++              DSSERR("can't determine maximum RFBI transfer rate\n");
++              return rfbi.l4_khz * 1000;
++      }
++      return rfbi.l4_khz * 1000 / min_l4_ticks;
++}
++#else
++int rfbi_get_max_tx_rate(void)
++{
++      return rfbi.l4_khz * 1000;
++}
++#endif
++
++static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
++{
++      *clk_period = 1000000000 / rfbi.l4_khz;
++      *max_clk_div = 2;
++}
++
++static int rfbi_convert_timings(struct rfbi_timings *t)
++{
++      u32 l;
++      int reon, reoff, weon, weoff, cson, csoff, cs_pulse;
++      int actim, recyc, wecyc;
++      int div = t->clk_div;
++
++      if (div <= 0 || div > 2)
++              return -1;
++
++      /* Make sure that after conversion it still holds that:
++       * weoff > weon, reoff > reon, recyc >= reoff, wecyc >= weoff,
++       * csoff > cson, csoff >= max(weoff, reoff), actim > reon
++       */
++      weon = ps_to_rfbi_ticks(t->we_on_time, div);
++      weoff = ps_to_rfbi_ticks(t->we_off_time, div);
++      if (weoff <= weon)
++              weoff = weon + 1;
++      if (weon > 0x0f)
++              return -1;
++      if (weoff > 0x3f)
++              return -1;
++
++      reon = ps_to_rfbi_ticks(t->re_on_time, div);
++      reoff = ps_to_rfbi_ticks(t->re_off_time, div);
++      if (reoff <= reon)
++              reoff = reon + 1;
++      if (reon > 0x0f)
++              return -1;
++      if (reoff > 0x3f)
++              return -1;
++
++      cson = ps_to_rfbi_ticks(t->cs_on_time, div);
++      csoff = ps_to_rfbi_ticks(t->cs_off_time, div);
++      if (csoff <= cson)
++              csoff = cson + 1;
++      if (csoff < max(weoff, reoff))
++              csoff = max(weoff, reoff);
++      if (cson > 0x0f)
++              return -1;
++      if (csoff > 0x3f)
++              return -1;
++
++      l =  cson;
++      l |= csoff << 4;
++      l |= weon  << 10;
++      l |= weoff << 14;
++      l |= reon  << 20;
++      l |= reoff << 24;
++
++      t->tim[0] = l;
++
++      actim = ps_to_rfbi_ticks(t->access_time, div);
++      if (actim <= reon)
++              actim = reon + 1;
++      if (actim > 0x3f)
++              return -1;
++
++      wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div);
++      if (wecyc < weoff)
++              wecyc = weoff;
++      if (wecyc > 0x3f)
++              return -1;
++
++      recyc = ps_to_rfbi_ticks(t->re_cycle_time, div);
++      if (recyc < reoff)
++              recyc = reoff;
++      if (recyc > 0x3f)
++              return -1;
++
++      cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div);
++      if (cs_pulse > 0x3f)
++              return -1;
++
++      l =  wecyc;
++      l |= recyc    << 6;
++      l |= cs_pulse << 12;
++      l |= actim    << 22;
++
++      t->tim[1] = l;
++
++      t->tim[2] = div - 1;
++
++      t->converted = 1;
++
++      return 0;
++}
++
++/* xxx FIX module selection missing */
++int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
++                           unsigned hs_pulse_time, unsigned vs_pulse_time,
++                           int hs_pol_inv, int vs_pol_inv, int extif_div)
++{
++      int hs, vs;
++      int min;
++      u32 l;
++
++      hs = ps_to_rfbi_ticks(hs_pulse_time, 1);
++      vs = ps_to_rfbi_ticks(vs_pulse_time, 1);
++      if (hs < 2)
++              return -EDOM;
++      if (mode == OMAP_DSS_RFBI_TE_MODE_2)
++              min = 2;
++      else /* OMAP_DSS_RFBI_TE_MODE_1 */
++              min = 4;
++      if (vs < min)
++              return -EDOM;
++      if (vs == hs)
++              return -EINVAL;
++      rfbi.te_mode = mode;
++      DSSDBG("setup_te: mode %d hs %d vs %d hs_inv %d vs_inv %d\n",
++              mode, hs, vs, hs_pol_inv, vs_pol_inv);
++
++      rfbi_enable_clocks(1);
++      rfbi_write_reg(RFBI_HSYNC_WIDTH, hs);
++      rfbi_write_reg(RFBI_VSYNC_WIDTH, vs);
++
++      l = rfbi_read_reg(RFBI_CONFIG(0));
++      if (hs_pol_inv)
++              l &= ~(1 << 21);
++      else
++              l |= 1 << 21;
++      if (vs_pol_inv)
++              l &= ~(1 << 20);
++      else
++              l |= 1 << 20;
++      rfbi_enable_clocks(0);
++
++      return 0;
++}
++EXPORT_SYMBOL(omap_rfbi_setup_te);
++
++/* xxx FIX module selection missing */
++int omap_rfbi_enable_te(bool enable, unsigned line)
++{
++      u32 l;
++
++      DSSDBG("te %d line %d mode %d\n", enable, line, rfbi.te_mode);
++      if (line > (1 << 11) - 1)
++              return -EINVAL;
++
++      rfbi_enable_clocks(1);
++      l = rfbi_read_reg(RFBI_CONFIG(0));
++      l &= ~(0x3 << 2);
++      if (enable) {
++              rfbi.te_enabled = 1;
++              l |= rfbi.te_mode << 2;
++      } else
++              rfbi.te_enabled = 0;
++      rfbi_write_reg(RFBI_CONFIG(0), l);
++      rfbi_write_reg(RFBI_LINE_NUMBER, line);
++      rfbi_enable_clocks(0);
++
++      return 0;
++}
++EXPORT_SYMBOL(omap_rfbi_enable_te);
++
++#if 0
++static void rfbi_enable_config(int enable1, int enable2)
++{
++      u32 l;
++      int cs = 0;
++
++      if (enable1)
++              cs |= 1<<0;
++      if (enable2)
++              cs |= 1<<1;
++
++      rfbi_enable_clocks(1);
++
++      l = rfbi_read_reg(RFBI_CONTROL);
++
++      l = FLD_MOD(l, cs, 3, 2);
++      l = FLD_MOD(l, 0, 1, 1);
++
++      rfbi_write_reg(RFBI_CONTROL, l);
++
++
++      l = rfbi_read_reg(RFBI_CONFIG(0));
++      l = FLD_MOD(l, 0, 3, 2); /* TRIGGERMODE: ITE */
++      /*l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
++      /*l |= FLD_VAL(0, 8, 7); */ /* L4FORMAT, 1pix/L4 */
++
++      l = FLD_MOD(l, 0, 16, 16); /* A0POLARITY */
++      l = FLD_MOD(l, 1, 20, 20); /* TE_VSYNC_POLARITY */
++      l = FLD_MOD(l, 1, 21, 21); /* HSYNCPOLARITY */
++
++      l = FLD_MOD(l, OMAP_DSS_RFBI_PARALLELMODE_8, 1, 0);
++      rfbi_write_reg(RFBI_CONFIG(0), l);
++
++      rfbi_enable_clocks(0);
++}
++#endif
++
++int rfbi_configure(int rfbi_module, int bpp, int lines)
++{
++      u32 l;
++      int cycle1 = 0, cycle2 = 0, cycle3 = 0;
++      enum omap_rfbi_cycleformat cycleformat;
++      enum omap_rfbi_datatype datatype;
++      enum omap_rfbi_parallelmode parallelmode;
++
++      switch (bpp) {
++      case 12:
++              datatype = OMAP_DSS_RFBI_DATATYPE_12;
++              break;
++      case 16:
++              datatype = OMAP_DSS_RFBI_DATATYPE_16;
++              break;
++      case 18:
++              datatype = OMAP_DSS_RFBI_DATATYPE_18;
++              break;
++      case 24:
++              datatype = OMAP_DSS_RFBI_DATATYPE_24;
++              break;
++      default:
++              BUG();
++              return 1;
++      }
++      rfbi.datatype = datatype;
++
++      switch (lines) {
++      case 8:
++              parallelmode = OMAP_DSS_RFBI_PARALLELMODE_8;
++              break;
++      case 9:
++              parallelmode = OMAP_DSS_RFBI_PARALLELMODE_9;
++              break;
++      case 12:
++              parallelmode = OMAP_DSS_RFBI_PARALLELMODE_12;
++              break;
++      case 16:
++              parallelmode = OMAP_DSS_RFBI_PARALLELMODE_16;
++              break;
++      default:
++              BUG();
++              return 1;
++      }
++      rfbi.parallelmode = parallelmode;
++
++      if ((bpp % lines) == 0) {
++              switch (bpp / lines) {
++              case 1:
++                      cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_1_1;
++                      break;
++              case 2:
++                      cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_2_1;
++                      break;
++              case 3:
++                      cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_1;
++                      break;
++              default:
++                      BUG();
++                      return 1;
++              }
++      } else if ((2 * bpp % lines) == 0) {
++              if ((2 * bpp / lines) == 3)
++                      cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_2;
++              else {
++                      BUG();
++                      return 1;
++              }
++      } else {
++              BUG();
++              return 1;
++      }
++
++      switch (cycleformat) {
++      case OMAP_DSS_RFBI_CYCLEFORMAT_1_1:
++              cycle1 = lines;
++              break;
++
++      case OMAP_DSS_RFBI_CYCLEFORMAT_2_1:
++              cycle1 = lines;
++              cycle2 = lines;
++              break;
++
++      case OMAP_DSS_RFBI_CYCLEFORMAT_3_1:
++              cycle1 = lines;
++              cycle2 = lines;
++              cycle3 = lines;
++              break;
++
++      case OMAP_DSS_RFBI_CYCLEFORMAT_3_2:
++              cycle1 = lines;
++              cycle2 = (lines / 2) | ((lines / 2) << 16);
++              cycle3 = (lines << 16);
++              break;
++      }
++
++      rfbi_enable_clocks(1);
++
++      REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */
++
++      l = 0;
++      l |= FLD_VAL(parallelmode, 1, 0);
++      l |= FLD_VAL(0, 3, 2);          /* TRIGGERMODE: ITE */
++      l |= FLD_VAL(0, 4, 4);          /* TIMEGRANULARITY */
++      l |= FLD_VAL(datatype, 6, 5);
++      /* l |= FLD_VAL(2, 8, 7); */    /* L4FORMAT, 2pix/L4 */
++      l |= FLD_VAL(0, 8, 7);  /* L4FORMAT, 1pix/L4 */
++      l |= FLD_VAL(cycleformat, 10, 9);
++      l |= FLD_VAL(0, 12, 11);        /* UNUSEDBITS */
++      l |= FLD_VAL(0, 16, 16);        /* A0POLARITY */
++      l |= FLD_VAL(0, 17, 17);        /* REPOLARITY */
++      l |= FLD_VAL(0, 18, 18);        /* WEPOLARITY */
++      l |= FLD_VAL(0, 19, 19);        /* CSPOLARITY */
++      l |= FLD_VAL(1, 20, 20);        /* TE_VSYNC_POLARITY */
++      l |= FLD_VAL(1, 21, 21);        /* HSYNCPOLARITY */
++      rfbi_write_reg(RFBI_CONFIG(rfbi_module), l);
++
++      rfbi_write_reg(RFBI_DATA_CYCLE1(rfbi_module), cycle1);
++      rfbi_write_reg(RFBI_DATA_CYCLE2(rfbi_module), cycle2);
++      rfbi_write_reg(RFBI_DATA_CYCLE3(rfbi_module), cycle3);
++
++
++      l = rfbi_read_reg(RFBI_CONTROL);
++      l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */
++      l = FLD_MOD(l, 0, 1, 1); /* clear bypass */
++      rfbi_write_reg(RFBI_CONTROL, l);
++
++
++      DSSDBG("RFBI config: bpp %d, lines %d, cycles: 0x%x 0x%x 0x%x\n",
++             bpp, lines, cycle1, cycle2, cycle3);
++
++      rfbi_enable_clocks(0);
++
++      return 0;
++}
++EXPORT_SYMBOL(rfbi_configure);
++
++static int rfbi_find_display(struct omap_dss_device *dssdev)
++{
++      if (dssdev == rfbi.dssdev[0])
++              return 0;
++
++      if (dssdev == rfbi.dssdev[1])
++              return 1;
++
++      BUG();
++      return -1;
++}
++
++
++static void signal_fifo_waiters(void)
++{
++      if (atomic_read(&rfbi.cmd_fifo_full) > 0) {
++              /* DSSDBG("SIGNALING: Fifo not full for waiter!\n"); */
++              complete(&rfbi.cmd_done);
++              atomic_dec(&rfbi.cmd_fifo_full);
++      }
++}
++
++/* returns 1 for async op, and 0 for sync op */
++static int do_update(struct omap_dss_device *dssdev, struct update_region *upd)
++{
++      u16 x = upd->x;
++      u16 y = upd->y;
++      u16 w = upd->w;
++      u16 h = upd->h;
++
++      perf_mark_setup();
++
++      if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
++              /*dssdev->driver->enable_te(dssdev, 1); */
++              dss_setup_partial_planes(dssdev, &x, &y, &w, &h);
++      }
++
++#ifdef MEASURE_PERF
++      rfbi.perf_bytes = w * h * 2; /* XXX always 16bit */
++#endif
++
++      dssdev->driver->setup_update(dssdev, x, y, w, h);
++
++      if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
++              rfbi_transfer_area(w, h, NULL, NULL);
++              return 1;
++      } else {
++              struct omap_overlay *ovl;
++              void __iomem *addr;
++              int scr_width;
++
++              ovl = dssdev->manager->overlays[0];
++              scr_width = ovl->info.screen_width;
++              addr = ovl->info.vaddr;
++
++              omap_rfbi_write_pixels(addr, scr_width, x, y, w, h);
++
++              perf_show("L4");
++
++              return 0;
++      }
++}
++
++static void process_cmd_fifo(void)
++{
++      int len;
++      struct update_param p;
++      struct omap_dss_device *dssdev;
++      unsigned long flags;
++
++      if (atomic_inc_return(&rfbi.cmd_pending) != 1)
++              return;
++
++      while (true) {
++              spin_lock_irqsave(rfbi.cmd_fifo->lock, flags);
++
++              len = __kfifo_get(rfbi.cmd_fifo, (unsigned char *)&p,
++                                sizeof(struct update_param));
++              if (len == 0) {
++                      DSSDBG("nothing more in fifo\n");
++                      atomic_set(&rfbi.cmd_pending, 0);
++                      spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
++                      break;
++              }
++
++              /* DSSDBG("fifo full %d\n", rfbi.cmd_fifo_full.counter);*/
++
++              spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
++
++              BUG_ON(len != sizeof(struct update_param));
++              BUG_ON(p.rfbi_module > 1);
++
++              dssdev = rfbi.dssdev[p.rfbi_module];
++
++              if (p.cmd == RFBI_CMD_UPDATE) {
++                      if (do_update(dssdev, &p.par.r))
++                              break; /* async op */
++              } else if (p.cmd == RFBI_CMD_SYNC) {
++                      DSSDBG("Signaling SYNC done!\n");
++                      complete(p.par.sync);
++              } else
++                      BUG();
++      }
++
++      signal_fifo_waiters();
++}
++
++static void rfbi_push_cmd(struct update_param *p)
++{
++      int ret;
++
++      while (1) {
++              unsigned long flags;
++              int available;
++
++              spin_lock_irqsave(rfbi.cmd_fifo->lock, flags);
++              available = RFBI_CMD_FIFO_LEN_BYTES -
++                      __kfifo_len(rfbi.cmd_fifo);
++
++/*            DSSDBG("%d bytes left in fifo\n", available); */
++              if (available < sizeof(struct update_param)) {
++                      DSSDBG("Going to wait because FIFO FULL..\n");
++                      spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
++                      atomic_inc(&rfbi.cmd_fifo_full);
++                      wait_for_completion(&rfbi.cmd_done);
++                      /*DSSDBG("Woke up because fifo not full anymore\n");*/
++                      continue;
++              }
++
++              ret = __kfifo_put(rfbi.cmd_fifo, (unsigned char *)p,
++                                sizeof(struct update_param));
++/*            DSSDBG("pushed %d bytes\n", ret);*/
++
++              spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
++
++              BUG_ON(ret != sizeof(struct update_param));
++
++              break;
++      }
++}
++
++static void rfbi_push_update(int rfbi_module, int x, int y, int w, int h)
++{
++      struct update_param p;
++
++      p.rfbi_module = rfbi_module;
++      p.cmd = RFBI_CMD_UPDATE;
++
++      p.par.r.x = x;
++      p.par.r.y = y;
++      p.par.r.w = w;
++      p.par.r.h = h;
++
++      DSSDBG("RFBI pushed %d,%d %dx%d\n", x, y, w, h);
++
++      rfbi_push_cmd(&p);
++
++      process_cmd_fifo();
++}
++
++static void rfbi_push_sync(int rfbi_module, struct completion *sync_comp)
++{
++      struct update_param p;
++
++      p.rfbi_module = rfbi_module;
++      p.cmd = RFBI_CMD_SYNC;
++      p.par.sync = sync_comp;
++
++      rfbi_push_cmd(&p);
++
++      DSSDBG("RFBI sync pushed to cmd fifo\n");
++
++      process_cmd_fifo();
++}
++
++void rfbi_dump_regs(struct seq_file *s)
++{
++#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r))
++
++      dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++      DUMPREG(RFBI_REVISION);
++      DUMPREG(RFBI_SYSCONFIG);
++      DUMPREG(RFBI_SYSSTATUS);
++      DUMPREG(RFBI_CONTROL);
++      DUMPREG(RFBI_PIXEL_CNT);
++      DUMPREG(RFBI_LINE_NUMBER);
++      DUMPREG(RFBI_CMD);
++      DUMPREG(RFBI_PARAM);
++      DUMPREG(RFBI_DATA);
++      DUMPREG(RFBI_READ);
++      DUMPREG(RFBI_STATUS);
++
++      DUMPREG(RFBI_CONFIG(0));
++      DUMPREG(RFBI_ONOFF_TIME(0));
++      DUMPREG(RFBI_CYCLE_TIME(0));
++      DUMPREG(RFBI_DATA_CYCLE1(0));
++      DUMPREG(RFBI_DATA_CYCLE2(0));
++      DUMPREG(RFBI_DATA_CYCLE3(0));
++
++      DUMPREG(RFBI_CONFIG(1));
++      DUMPREG(RFBI_ONOFF_TIME(1));
++      DUMPREG(RFBI_CYCLE_TIME(1));
++      DUMPREG(RFBI_DATA_CYCLE1(1));
++      DUMPREG(RFBI_DATA_CYCLE2(1));
++      DUMPREG(RFBI_DATA_CYCLE3(1));
++
++      DUMPREG(RFBI_VSYNC_WIDTH);
++      DUMPREG(RFBI_HSYNC_WIDTH);
++
++      dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++#undef DUMPREG
++}
++
++int rfbi_init(void)
++{
++      u32 rev;
++      u32 l;
++
++      spin_lock_init(&rfbi.cmd_lock);
++      rfbi.cmd_fifo = kfifo_alloc(RFBI_CMD_FIFO_LEN_BYTES, GFP_KERNEL,
++                                  &rfbi.cmd_lock);
++      if (IS_ERR(rfbi.cmd_fifo))
++              return -ENOMEM;
++
++      init_completion(&rfbi.cmd_done);
++      atomic_set(&rfbi.cmd_fifo_full, 0);
++      atomic_set(&rfbi.cmd_pending, 0);
++
++      rfbi.base = ioremap(RFBI_BASE, SZ_256);
++      if (!rfbi.base) {
++              DSSERR("can't ioremap RFBI\n");
++              return -ENOMEM;
++      }
++
++      rfbi_enable_clocks(1);
++
++      msleep(10);
++
++      rfbi.l4_khz = dss_clk_get_rate(DSS_CLK_ICK) / 1000;
++
++      /* Enable autoidle and smart-idle */
++      l = rfbi_read_reg(RFBI_SYSCONFIG);
++      l |= (1 << 0) | (2 << 3);
++      rfbi_write_reg(RFBI_SYSCONFIG, l);
++
++      rev = rfbi_read_reg(RFBI_REVISION);
++      printk(KERN_INFO "OMAP RFBI rev %d.%d\n",
++             FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
++
++      rfbi_enable_clocks(0);
++
++      return 0;
++}
++
++void rfbi_exit(void)
++{
++      DSSDBG("rfbi_exit\n");
++
++      kfifo_free(rfbi.cmd_fifo);
++
++      iounmap(rfbi.base);
++}
++
++/* struct omap_display support */
++static int rfbi_display_update(struct omap_dss_device *dssdev,
++                      u16 x, u16 y, u16 w, u16 h)
++{
++      int rfbi_module;
++
++      if (w == 0 || h == 0)
++              return 0;
++
++      rfbi_module = rfbi_find_display(dssdev);
++
++      rfbi_push_update(rfbi_module, x, y, w, h);
++
++      return 0;
++}
++
++static int rfbi_display_sync(struct omap_dss_device *dssdev)
++{
++      struct completion sync_comp;
++      int rfbi_module;
++
++      rfbi_module = rfbi_find_display(dssdev);
++
++      init_completion(&sync_comp);
++      rfbi_push_sync(rfbi_module, &sync_comp);
++      DSSDBG("Waiting for SYNC to happen...\n");
++      wait_for_completion(&sync_comp);
++      DSSDBG("Released from SYNC\n");
++      return 0;
++}
++
++static int rfbi_display_enable_te(struct omap_dss_device *dssdev, bool enable)
++{
++      dssdev->driver->enable_te(dssdev, enable);
++      return 0;
++}
++
++static int rfbi_display_enable(struct omap_dss_device *dssdev)
++{
++      int r;
++
++      r = omap_dss_start_device(dssdev);
++      if (r) {
++              DSSERR("failed to start device\n");
++              goto err0;
++      }
++
++      r = omap_dispc_register_isr(framedone_callback, NULL,
++                      DISPC_IRQ_FRAMEDONE);
++      if (r) {
++              DSSERR("can't get FRAMEDONE irq\n");
++              goto err1;
++      }
++
++      dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
++
++      dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_RFBI);
++
++      dispc_set_tft_data_lines(dssdev->ctrl.pixel_size);
++
++      rfbi_configure(dssdev->phy.rfbi.channel,
++                             dssdev->ctrl.pixel_size,
++                             dssdev->phy.rfbi.data_lines);
++
++      rfbi_set_timings(dssdev->phy.rfbi.channel,
++                       &dssdev->ctrl.rfbi_timings);
++
++
++      if (dssdev->driver->enable) {
++              r = dssdev->driver->enable(dssdev);
++              if (r)
++                      goto err2;
++      }
++
++      return 0;
++err2:
++      omap_dispc_unregister_isr(framedone_callback, NULL,
++                      DISPC_IRQ_FRAMEDONE);
++err1:
++      omap_dss_stop_device(dssdev);
++err0:
++      return r;
++}
++
++static void rfbi_display_disable(struct omap_dss_device *dssdev)
++{
++      dssdev->driver->disable(dssdev);
++      omap_dispc_unregister_isr(framedone_callback, NULL,
++                      DISPC_IRQ_FRAMEDONE);
++      omap_dss_stop_device(dssdev);
++}
++
++int rfbi_init_display(struct omap_dss_device *dssdev)
++{
++      dssdev->enable = rfbi_display_enable;
++      dssdev->disable = rfbi_display_disable;
++      dssdev->update = rfbi_display_update;
++      dssdev->sync = rfbi_display_sync;
++      dssdev->enable_te = rfbi_display_enable_te;
++
++      rfbi.dssdev[dssdev->phy.rfbi.channel] = dssdev;
++
++      dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
++
++      return 0;
++}
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-2.6.31/dss2/0013-OMAP-DSS2-SDI-driver.patch b/recipes/linux/linux-omap-2.6.31/dss2/0013-OMAP-DSS2-SDI-driver.patch
new file mode 100644 (file)
index 0000000..698d4fb
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.31/dss2/0013-OMAP-DSS2-SDI-driver.patch
@@ -0,0 +1,284 @@
+From 6191570efd848a073fcdfb619ba28cc0d66b2842 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Wed, 5 Aug 2009 16:18:44 +0300
+Subject: [PATCH 13/18] OMAP: DSS2: SDI driver
+
+SDI (Serial Display Interface) implements TI Flatlink 3G display
+interface.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ drivers/video/omap2/dss/sdi.c |  261 +++++++++++++++++++++++++++++++++++++++++
+ 1 files changed, 261 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/video/omap2/dss/sdi.c
+
+diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c
+new file mode 100644
+index 0000000..a9c727e
+--- /dev/null
++++ b/drivers/video/omap2/dss/sdi.c
+@@ -0,0 +1,261 @@
++/*
++ * linux/drivers/video/omap2/dss/sdi.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "SDI"
++
++#include <linux/kernel.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++
++#include <mach/board.h>
++#include <mach/display.h>
++#include "dss.h"
++
++static struct {
++      bool skip_init;
++      bool update_enabled;
++} sdi;
++
++static void sdi_basic_init(void)
++{
++      dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS);
++
++      dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
++      dispc_set_tft_data_lines(24);
++      dispc_lcd_enable_signal_polarity(1);
++}
++
++static int sdi_display_enable(struct omap_dss_device *dssdev)
++{
++      struct omap_video_timings *t = &dssdev->panel.timings;
++      struct dispc_clock_info cinfo;
++      u16 lck_div, pck_div;
++      unsigned long fck;
++      unsigned long pck;
++      int r;
++
++      r = omap_dss_start_device(dssdev);
++      if (r) {
++              DSSERR("failed to start device\n");
++              goto err0;
++      }
++
++      if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
++              DSSERR("dssdev already enabled\n");
++              r = -EINVAL;
++              goto err1;
++      }
++
++      /* In case of skip_init sdi_init has already enabled the clocks */
++      if (!sdi.skip_init)
++              dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++      sdi_basic_init();
++
++      /* 15.5.9.1.2 */
++      dssdev->panel.config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF;
++
++      dispc_set_pol_freq(dssdev->panel.config, dssdev->panel.acbi,
++                      dssdev->panel.acb);
++
++      if (!sdi.skip_init)
++              r = dispc_calc_clock_div(1, t->pixel_clock * 1000,
++                              &cinfo);
++      else
++              r = dispc_get_clock_div(&cinfo);
++
++      if (r)
++              goto err2;
++
++      fck = cinfo.fck;
++      lck_div = cinfo.lck_div;
++      pck_div = cinfo.pck_div;
++
++      pck = fck / lck_div / pck_div / 1000;
++
++      if (pck != t->pixel_clock) {
++              DSSWARN("Could not find exact pixel clock. Requested %d kHz, "
++                              "got %lu kHz\n",
++                              t->pixel_clock, pck);
++
++              t->pixel_clock = pck;
++      }
++
++
++      dispc_set_lcd_timings(t);
++
++      r = dispc_set_clock_div(&cinfo);
++      if (r)
++              goto err2;
++
++      if (!sdi.skip_init) {
++              dss_sdi_init(dssdev->phy.sdi.datapairs);
++              dss_sdi_enable();
++              mdelay(2);
++      }
++
++      dispc_enable_lcd_out(1);
++
++      if (dssdev->driver->enable) {
++              r = dssdev->driver->enable(dssdev);
++              if (r)
++                      goto err3;
++      }
++
++      dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++      sdi.skip_init = 0;
++
++      return 0;
++err3:
++      dispc_enable_lcd_out(0);
++err2:
++      dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++err1:
++      omap_dss_stop_device(dssdev);
++err0:
++      return r;
++}
++
++static int sdi_display_resume(struct omap_dss_device *dssdev);
++
++static void sdi_display_disable(struct omap_dss_device *dssdev)
++{
++      if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED)
++              return;
++
++      if (dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED)
++              sdi_display_resume(dssdev);
++
++      if (dssdev->driver->disable)
++              dssdev->driver->disable(dssdev);
++
++      dispc_enable_lcd_out(0);
++
++      dss_sdi_disable();
++
++      dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++      dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
++
++      omap_dss_stop_device(dssdev);
++}
++
++static int sdi_display_suspend(struct omap_dss_device *dssdev)
++{
++      if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
++              return -EINVAL;
++
++      if (dssdev->driver->suspend)
++              dssdev->driver->suspend(dssdev);
++
++      dispc_enable_lcd_out(0);
++
++      dss_sdi_disable();
++
++      dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++      dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED;
++
++      return 0;
++}
++
++static int sdi_display_resume(struct omap_dss_device *dssdev)
++{
++      if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED)
++              return -EINVAL;
++
++      dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++      dss_sdi_enable();
++      mdelay(2);
++
++      dispc_enable_lcd_out(1);
++
++      if (dssdev->driver->resume)
++              dssdev->driver->resume(dssdev);
++
++      dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++      return 0;
++}
++
++static int sdi_display_set_update_mode(struct omap_dss_device *dssdev,
++              enum omap_dss_update_mode mode)
++{
++      if (mode == OMAP_DSS_UPDATE_MANUAL)
++              return -EINVAL;
++
++      if (mode == OMAP_DSS_UPDATE_DISABLED) {
++              dispc_enable_lcd_out(0);
++              sdi.update_enabled = 0;
++      } else {
++              dispc_enable_lcd_out(1);
++              sdi.update_enabled = 1;
++      }
++
++      return 0;
++}
++
++static enum omap_dss_update_mode sdi_display_get_update_mode(
++              struct omap_dss_device *dssdev)
++{
++      return sdi.update_enabled ? OMAP_DSS_UPDATE_AUTO :
++              OMAP_DSS_UPDATE_DISABLED;
++}
++
++static void sdi_get_timings(struct omap_dss_device *dssdev,
++                      struct omap_video_timings *timings)
++{
++      *timings = dssdev->panel.timings;
++}
++
++int sdi_init_display(struct omap_dss_device *dssdev)
++{
++      DSSDBG("SDI init\n");
++
++      dssdev->enable = sdi_display_enable;
++      dssdev->disable = sdi_display_disable;
++      dssdev->suspend = sdi_display_suspend;
++      dssdev->resume = sdi_display_resume;
++      dssdev->set_update_mode = sdi_display_set_update_mode;
++      dssdev->get_update_mode = sdi_display_get_update_mode;
++      dssdev->get_timings = sdi_get_timings;
++
++      return 0;
++}
++
++int sdi_init(bool skip_init)
++{
++      /* we store this for first display enable, then clear it */
++      sdi.skip_init = skip_init;
++
++      /*
++       * Enable clocks already here, otherwise there would be a toggle
++       * of them until sdi_display_enable is called.
++       */
++      if (skip_init)
++              dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++      return 0;
++}
++
++void sdi_exit(void)
++{
++}
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-2.6.31/dss2/0014-OMAP-DSS2-DSI-driver.patch b/recipes/linux/linux-omap-2.6.31/dss2/0014-OMAP-DSS2-DSI-driver.patch
new file mode 100644 (file)
index 0000000..5102041
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.31/dss2/0014-OMAP-DSS2-DSI-driver.patch
@@ -0,0 +1,3531 @@
+From 1452422be43114972e71ac2bbb9e1055f4616602 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Wed, 5 Aug 2009 16:18:57 +0300
+Subject: [PATCH 14/18] OMAP: DSS2: DSI driver
+
+DSI (Display Serial Interface) driver implements MIPI DSI interface.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ drivers/video/omap2/dss/dsi.c | 3509 +++++++++++++++++++++++++++++++++++++++++
+ 1 files changed, 3509 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/video/omap2/dss/dsi.c
+
+diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
+new file mode 100644
+index 0000000..d43b9ce
+--- /dev/null
++++ b/drivers/video/omap2/dss/dsi.c
+@@ -0,0 +1,3509 @@
++/*
++ * linux/drivers/video/omap2/dss/dsi.c
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define DSS_SUBSYS_NAME "DSI"
++
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/mutex.h>
++#include <linux/seq_file.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/kthread.h>
++#include <linux/wait.h>
++
++#include <mach/board.h>
++#include <mach/display.h>
++#include <mach/clock.h>
++
++#include "dss.h"
++
++/*#define VERBOSE_IRQ*/
++
++#define DSI_BASE              0x4804FC00
++
++struct dsi_reg { u16 idx; };
++
++#define DSI_REG(idx)          ((const struct dsi_reg) { idx })
++
++#define DSI_SZ_REGS           SZ_1K
++/* DSI Protocol Engine */
++
++#define DSI_REVISION                  DSI_REG(0x0000)
++#define DSI_SYSCONFIG                 DSI_REG(0x0010)
++#define DSI_SYSSTATUS                 DSI_REG(0x0014)
++#define DSI_IRQSTATUS                 DSI_REG(0x0018)
++#define DSI_IRQENABLE                 DSI_REG(0x001C)
++#define DSI_CTRL                      DSI_REG(0x0040)
++#define DSI_COMPLEXIO_CFG1            DSI_REG(0x0048)
++#define DSI_COMPLEXIO_IRQ_STATUS      DSI_REG(0x004C)
++#define DSI_COMPLEXIO_IRQ_ENABLE      DSI_REG(0x0050)
++#define DSI_CLK_CTRL                  DSI_REG(0x0054)
++#define DSI_TIMING1                   DSI_REG(0x0058)
++#define DSI_TIMING2                   DSI_REG(0x005C)
++#define DSI_VM_TIMING1                        DSI_REG(0x0060)
++#define DSI_VM_TIMING2                        DSI_REG(0x0064)
++#define DSI_VM_TIMING3                        DSI_REG(0x0068)
++#define DSI_CLK_TIMING                        DSI_REG(0x006C)
++#define DSI_TX_FIFO_VC_SIZE           DSI_REG(0x0070)
++#define DSI_RX_FIFO_VC_SIZE           DSI_REG(0x0074)
++#define DSI_COMPLEXIO_CFG2            DSI_REG(0x0078)
++#define DSI_RX_FIFO_VC_FULLNESS               DSI_REG(0x007C)
++#define DSI_VM_TIMING4                        DSI_REG(0x0080)
++#define DSI_TX_FIFO_VC_EMPTINESS      DSI_REG(0x0084)
++#define DSI_VM_TIMING5                        DSI_REG(0x0088)
++#define DSI_VM_TIMING6                        DSI_REG(0x008C)
++#define DSI_VM_TIMING7                        DSI_REG(0x0090)
++#define DSI_STOPCLK_TIMING            DSI_REG(0x0094)
++#define DSI_VC_CTRL(n)                        DSI_REG(0x0100 + (n * 0x20))
++#define DSI_VC_TE(n)                  DSI_REG(0x0104 + (n * 0x20))
++#define DSI_VC_LONG_PACKET_HEADER(n)  DSI_REG(0x0108 + (n * 0x20))
++#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
++#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
++#define DSI_VC_IRQSTATUS(n)           DSI_REG(0x0118 + (n * 0x20))
++#define DSI_VC_IRQENABLE(n)           DSI_REG(0x011C + (n * 0x20))
++
++/* DSIPHY_SCP */
++
++#define DSI_DSIPHY_CFG0                       DSI_REG(0x200 + 0x0000)
++#define DSI_DSIPHY_CFG1                       DSI_REG(0x200 + 0x0004)
++#define DSI_DSIPHY_CFG2                       DSI_REG(0x200 + 0x0008)
++#define DSI_DSIPHY_CFG5                       DSI_REG(0x200 + 0x0014)
++
++/* DSI_PLL_CTRL_SCP */
++
++#define DSI_PLL_CONTROL                       DSI_REG(0x300 + 0x0000)
++#define DSI_PLL_STATUS                        DSI_REG(0x300 + 0x0004)
++#define DSI_PLL_GO                    DSI_REG(0x300 + 0x0008)
++#define DSI_PLL_CONFIGURATION1                DSI_REG(0x300 + 0x000C)
++#define DSI_PLL_CONFIGURATION2                DSI_REG(0x300 + 0x0010)
++
++#define REG_GET(idx, start, end) \
++      FLD_GET(dsi_read_reg(idx), start, end)
++
++#define REG_FLD_MOD(idx, val, start, end) \
++      dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
++
++/* Global interrupts */
++#define DSI_IRQ_VC0           (1 << 0)
++#define DSI_IRQ_VC1           (1 << 1)
++#define DSI_IRQ_VC2           (1 << 2)
++#define DSI_IRQ_VC3           (1 << 3)
++#define DSI_IRQ_WAKEUP                (1 << 4)
++#define DSI_IRQ_RESYNC                (1 << 5)
++#define DSI_IRQ_PLL_LOCK      (1 << 7)
++#define DSI_IRQ_PLL_UNLOCK    (1 << 8)
++#define DSI_IRQ_PLL_RECALL    (1 << 9)
++#define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
++#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
++#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
++#define DSI_IRQ_TE_TRIGGER    (1 << 16)
++#define DSI_IRQ_ACK_TRIGGER   (1 << 17)
++#define DSI_IRQ_SYNC_LOST     (1 << 18)
++#define DSI_IRQ_LDO_POWER_GOOD        (1 << 19)
++#define DSI_IRQ_TA_TIMEOUT    (1 << 20)
++#define DSI_IRQ_ERROR_MASK \
++      (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
++      DSI_IRQ_TA_TIMEOUT)
++#define DSI_IRQ_CHANNEL_MASK  0xf
++
++/* Virtual channel interrupts */
++#define DSI_VC_IRQ_CS         (1 << 0)
++#define DSI_VC_IRQ_ECC_CORR   (1 << 1)
++#define DSI_VC_IRQ_PACKET_SENT        (1 << 2)
++#define DSI_VC_IRQ_FIFO_TX_OVF        (1 << 3)
++#define DSI_VC_IRQ_FIFO_RX_OVF        (1 << 4)
++#define DSI_VC_IRQ_BTA                (1 << 5)
++#define DSI_VC_IRQ_ECC_NO_CORR        (1 << 6)
++#define DSI_VC_IRQ_FIFO_TX_UDF        (1 << 7)
++#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
++#define DSI_VC_IRQ_ERROR_MASK \
++      (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
++      DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
++      DSI_VC_IRQ_FIFO_TX_UDF)
++
++/* ComplexIO interrupts */
++#define DSI_CIO_IRQ_ERRSYNCESC1               (1 << 0)
++#define DSI_CIO_IRQ_ERRSYNCESC2               (1 << 1)
++#define DSI_CIO_IRQ_ERRSYNCESC3               (1 << 2)
++#define DSI_CIO_IRQ_ERRESC1           (1 << 5)
++#define DSI_CIO_IRQ_ERRESC2           (1 << 6)
++#define DSI_CIO_IRQ_ERRESC3           (1 << 7)
++#define DSI_CIO_IRQ_ERRCONTROL1               (1 << 10)
++#define DSI_CIO_IRQ_ERRCONTROL2               (1 << 11)
++#define DSI_CIO_IRQ_ERRCONTROL3               (1 << 12)
++#define DSI_CIO_IRQ_STATEULPS1                (1 << 15)
++#define DSI_CIO_IRQ_STATEULPS2                (1 << 16)
++#define DSI_CIO_IRQ_STATEULPS3                (1 << 17)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1        (1 << 20)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1        (1 << 21)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2        (1 << 22)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2        (1 << 23)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3        (1 << 24)
++#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3        (1 << 25)
++#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0        (1 << 30)
++#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1        (1 << 31)
++
++#define DSI_DT_DCS_SHORT_WRITE_0      0x05
++#define DSI_DT_DCS_SHORT_WRITE_1      0x15
++#define DSI_DT_DCS_READ                       0x06
++#define DSI_DT_SET_MAX_RET_PKG_SIZE   0x37
++#define DSI_DT_NULL_PACKET            0x09
++#define DSI_DT_DCS_LONG_WRITE         0x39
++
++#define DSI_DT_RX_ACK_WITH_ERR                0x02
++#define DSI_DT_RX_DCS_LONG_READ               0x1c
++#define DSI_DT_RX_SHORT_READ_1                0x21
++#define DSI_DT_RX_SHORT_READ_2                0x22
++
++#define FINT_MAX 2100000
++#define FINT_MIN 750000
++#define REGN_MAX (1 << 7)
++#define REGM_MAX ((1 << 11) - 1)
++#define REGM3_MAX (1 << 4)
++#define REGM4_MAX (1 << 4)
++
++enum fifo_size {
++      DSI_FIFO_SIZE_0         = 0,
++      DSI_FIFO_SIZE_32        = 1,
++      DSI_FIFO_SIZE_64        = 2,
++      DSI_FIFO_SIZE_96        = 3,
++      DSI_FIFO_SIZE_128       = 4,
++};
++
++enum dsi_vc_mode {
++      DSI_VC_MODE_L4 = 0,
++      DSI_VC_MODE_VP,
++};
++
++struct dsi_update_region {
++      bool dirty;
++      u16 x, y, w, h;
++      struct omap_dss_device *device;
++};
++
++static struct
++{
++      void __iomem    *base;
++
++      unsigned long   dsi1_pll_fclk;  /* Hz */
++      unsigned long   dsi2_pll_fclk;  /* Hz */
++      unsigned long   dsiphy;         /* Hz */
++      unsigned long   ddr_clk;        /* Hz */
++
++      struct regulator *vdds_dsi_reg;
++
++      struct {
++              enum dsi_vc_mode mode;
++              struct omap_dss_device *dssdev;
++              enum fifo_size fifo_size;
++              int dest_per;   /* destination peripheral 0-3 */
++      } vc[4];
++
++      struct mutex lock;
++      struct mutex bus_lock;
++
++      unsigned pll_locked;
++
++      struct completion bta_completion;
++
++      struct task_struct *thread;
++      wait_queue_head_t waitqueue;
++
++      spinlock_t update_lock;
++      bool framedone_received;
++      struct dsi_update_region update_region;
++      struct dsi_update_region active_update_region;
++      struct completion update_completion;
++
++      enum omap_dss_update_mode user_update_mode;
++      enum omap_dss_update_mode update_mode;
++      bool te_enabled;
++      bool use_ext_te;
++
++      unsigned long cache_req_pck;
++      unsigned long cache_clk_freq;
++      struct dsi_clock_info cache_cinfo;
++
++      u32             errors;
++      spinlock_t      errors_lock;
++#ifdef DEBUG
++      ktime_t perf_setup_time;
++      ktime_t perf_start_time;
++      ktime_t perf_start_time_auto;
++      int perf_measure_frames;
++#endif
++      int debug_read;
++      int debug_write;
++} dsi;
++
++#ifdef DEBUG
++static unsigned int dsi_perf;
++module_param_named(dsi_perf, dsi_perf, bool, 0644);
++#endif
++
++static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
++{
++      __raw_writel(val, dsi.base + idx.idx);
++}
++
++static inline u32 dsi_read_reg(const struct dsi_reg idx)
++{
++      return __raw_readl(dsi.base + idx.idx);
++}
++
++
++void dsi_save_context(void)
++{
++}
++
++void dsi_restore_context(void)
++{
++}
++
++void dsi_bus_lock(void)
++{
++      mutex_lock(&dsi.bus_lock);
++}
++EXPORT_SYMBOL(dsi_bus_lock);
++
++void dsi_bus_unlock(void)
++{
++      mutex_unlock(&dsi.bus_lock);
++}
++EXPORT_SYMBOL(dsi_bus_unlock);
++
++static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
++              int value)
++{
++      int t = 100000;
++
++      while (REG_GET(idx, bitnum, bitnum) != value) {
++              if (--t == 0)
++                      return !value;
++      }
++
++      return value;
++}
++
++#ifdef DEBUG
++static void dsi_perf_mark_setup(void)
++{
++      dsi.perf_setup_time = ktime_get();
++}
++
++static void dsi_perf_mark_start(void)
++{
++      dsi.perf_start_time = ktime_get();
++}
++
++static void dsi_perf_mark_start_auto(void)
++{
++      dsi.perf_measure_frames = 0;
++      dsi.perf_start_time_auto = ktime_get();
++}
++
++static void dsi_perf_show(const char *name)
++{
++      ktime_t t, setup_time, trans_time;
++      u32 total_bytes;
++      u32 setup_us, trans_us, total_us;
++
++      if (!dsi_perf)
++              return;
++
++      if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED)
++              return;
++
++      t = ktime_get();
++
++      setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
++      setup_us = (u32)ktime_to_us(setup_time);
++      if (setup_us == 0)
++              setup_us = 1;
++
++      trans_time = ktime_sub(t, dsi.perf_start_time);
++      trans_us = (u32)ktime_to_us(trans_time);
++      if (trans_us == 0)
++              trans_us = 1;
++
++      total_us = setup_us + trans_us;
++
++      total_bytes = dsi.active_update_region.w *
++              dsi.active_update_region.h *
++              dsi.active_update_region.device->ctrl.pixel_size / 8;
++
++      if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) {
++              static u32 s_total_trans_us, s_total_setup_us;
++              static u32 s_min_trans_us = 0xffffffff, s_min_setup_us;
++              static u32 s_max_trans_us, s_max_setup_us;
++              const int numframes = 100;
++              ktime_t total_time_auto;
++              u32 total_time_auto_us;
++
++              dsi.perf_measure_frames++;
++
++              if (setup_us < s_min_setup_us)
++                      s_min_setup_us = setup_us;
++
++              if (setup_us > s_max_setup_us)
++                      s_max_setup_us = setup_us;
++
++              s_total_setup_us += setup_us;
++
++              if (trans_us < s_min_trans_us)
++                      s_min_trans_us = trans_us;
++
++              if (trans_us > s_max_trans_us)
++                      s_max_trans_us = trans_us;
++
++              s_total_trans_us += trans_us;
++
++              if (dsi.perf_measure_frames < numframes)
++                      return;
++
++              total_time_auto = ktime_sub(t, dsi.perf_start_time_auto);
++              total_time_auto_us = (u32)ktime_to_us(total_time_auto);
++
++              printk(KERN_INFO "DSI(%s): %u fps, setup %u/%u/%u, "
++                              "trans %u/%u/%u\n",
++                              name,
++                              1000 * 1000 * numframes / total_time_auto_us,
++                              s_min_setup_us,
++                              s_max_setup_us,
++                              s_total_setup_us / numframes,
++                              s_min_trans_us,
++                              s_max_trans_us,
++                              s_total_trans_us / numframes);
++
++              s_total_setup_us = 0;
++              s_min_setup_us = 0xffffffff;
++              s_max_setup_us = 0;
++              s_total_trans_us = 0;
++              s_min_trans_us = 0xffffffff;
++              s_max_trans_us = 0;
++              dsi_perf_mark_start_auto();
++      } else {
++              printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
++                              "%u bytes, %u kbytes/sec\n",
++                              name,
++                              setup_us,
++                              trans_us,
++                              total_us,
++                              1000*1000 / total_us,
++                              total_bytes,
++                              total_bytes * 1000 / total_us);
++      }
++}
++#else
++#define dsi_perf_mark_setup()
++#define dsi_perf_mark_start()
++#define dsi_perf_mark_start_auto()
++#define dsi_perf_show(x)
++#endif
++
++static void print_irq_status(u32 status)
++{
++#ifndef VERBOSE_IRQ
++      if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
++              return;
++#endif
++      printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
++
++#define PIS(x) \
++      if (status & DSI_IRQ_##x) \
++              printk(#x " ");
++#ifdef VERBOSE_IRQ
++      PIS(VC0);
++      PIS(VC1);
++      PIS(VC2);
++      PIS(VC3);
++#endif
++      PIS(WAKEUP);
++      PIS(RESYNC);
++      PIS(PLL_LOCK);
++      PIS(PLL_UNLOCK);
++      PIS(PLL_RECALL);
++      PIS(COMPLEXIO_ERR);
++      PIS(HS_TX_TIMEOUT);
++      PIS(LP_RX_TIMEOUT);
++      PIS(TE_TRIGGER);
++      PIS(ACK_TRIGGER);
++      PIS(SYNC_LOST);
++      PIS(LDO_POWER_GOOD);
++      PIS(TA_TIMEOUT);
++#undef PIS
++
++      printk("\n");
++}
++
++static void print_irq_status_vc(int channel, u32 status)
++{
++#ifndef VERBOSE_IRQ
++      if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
++              return;
++#endif
++      printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
++
++#define PIS(x) \
++      if (status & DSI_VC_IRQ_##x) \
++              printk(#x " ");
++      PIS(CS);
++      PIS(ECC_CORR);
++#ifdef VERBOSE_IRQ
++      PIS(PACKET_SENT);
++#endif
++      PIS(FIFO_TX_OVF);
++      PIS(FIFO_RX_OVF);
++      PIS(BTA);
++      PIS(ECC_NO_CORR);
++      PIS(FIFO_TX_UDF);
++      PIS(PP_BUSY_CHANGE);
++#undef PIS
++      printk("\n");
++}
++
++static void print_irq_status_cio(u32 status)
++{
++      printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
++
++#define PIS(x) \
++      if (status & DSI_CIO_IRQ_##x) \
++              printk(#x " ");
++      PIS(ERRSYNCESC1);
++      PIS(ERRSYNCESC2);
++      PIS(ERRSYNCESC3);
++      PIS(ERRESC1);
++      PIS(ERRESC2);
++      PIS(ERRESC3);
++      PIS(ERRCONTROL1);
++      PIS(ERRCONTROL2);
++      PIS(ERRCONTROL3);
++      PIS(STATEULPS1);
++      PIS(STATEULPS2);
++      PIS(STATEULPS3);
++      PIS(ERRCONTENTIONLP0_1);
++      PIS(ERRCONTENTIONLP1_1);
++      PIS(ERRCONTENTIONLP0_2);
++      PIS(ERRCONTENTIONLP1_2);
++      PIS(ERRCONTENTIONLP0_3);
++      PIS(ERRCONTENTIONLP1_3);
++      PIS(ULPSACTIVENOT_ALL0);
++      PIS(ULPSACTIVENOT_ALL1);
++#undef PIS
++
++      printk("\n");
++}
++
++static int debug_irq;
++
++/* called from dss */
++void dsi_irq_handler(void)
++{
++      u32 irqstatus, vcstatus, ciostatus;
++      int i;
++
++      irqstatus = dsi_read_reg(DSI_IRQSTATUS);
++
++      if (irqstatus & DSI_IRQ_ERROR_MASK) {
++              DSSERR("DSI error, irqstatus %x\n", irqstatus);
++              print_irq_status(irqstatus);
++              spin_lock(&dsi.errors_lock);
++              dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK;
++              spin_unlock(&dsi.errors_lock);
++      } else if (debug_irq) {
++              print_irq_status(irqstatus);
++      }
++
++      for (i = 0; i < 4; ++i) {
++              if ((irqstatus & (1<<i)) == 0)
++                      continue;
++
++              vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
++
++              if (vcstatus & DSI_VC_IRQ_BTA)
++                      complete(&dsi.bta_completion);
++
++              if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
++                      DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
++                                     i, vcstatus);
++                      print_irq_status_vc(i, vcstatus);
++              } else if (debug_irq) {
++                      print_irq_status_vc(i, vcstatus);
++              }
++
++              dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
++      }
++
++      if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
++              ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
++
++              dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
++
++              DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
++              print_irq_status_cio(ciostatus);
++      }
++
++      dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
++}
++
++
++static void _dsi_initialize_irq(void)
++{
++      u32 l;
++      int i;
++
++      /* disable all interrupts */
++      dsi_write_reg(DSI_IRQENABLE, 0);
++      for (i = 0; i < 4; ++i)
++              dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
++      dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
++
++      /* clear interrupt status */
++      l = dsi_read_reg(DSI_IRQSTATUS);
++      dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
++
++      for (i = 0; i < 4; ++i) {
++              l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
++              dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
++      }
++
++      l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
++      dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
++
++      /* enable error irqs */
++      l = DSI_IRQ_ERROR_MASK;
++      dsi_write_reg(DSI_IRQENABLE, l);
++
++      l = DSI_VC_IRQ_ERROR_MASK;
++      for (i = 0; i < 4; ++i)
++              dsi_write_reg(DSI_VC_IRQENABLE(i), l);
++
++      /* XXX zonda responds incorrectly, causing control error:
++         Exit from LP-ESC mode to LP11 uses wrong transition states on the
++         data lines LP0 and LN0. */
++      dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE,
++                      -1 & (~DSI_CIO_IRQ_ERRCONTROL2));
++}
++
++static u32 dsi_get_errors(void)
++{
++      unsigned long flags;
++      u32 e;
++      spin_lock_irqsave(&dsi.errors_lock, flags);
++      e = dsi.errors;
++      dsi.errors = 0;
++      spin_unlock_irqrestore(&dsi.errors_lock, flags);
++      return e;
++}
++
++static void dsi_vc_enable_bta_irq(int channel)
++{
++      u32 l;
++
++      dsi_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA);
++
++      l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
++      l |= DSI_VC_IRQ_BTA;
++      dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
++}
++
++static void dsi_vc_disable_bta_irq(int channel)
++{
++      u32 l;
++
++      l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
++      l &= ~DSI_VC_IRQ_BTA;
++      dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
++}
++
++/* DSI func clock. this could also be DSI2_PLL_FCLK */
++static inline void enable_clocks(bool enable)
++{
++      if (enable)
++              dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++      else
++              dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++}
++
++/* source clock for DSI PLL. this could also be PCLKFREE */
++static inline void dsi_enable_pll_clock(bool enable)
++{
++      if (enable)
++              dss_clk_enable(DSS_CLK_FCK2);
++      else
++              dss_clk_disable(DSS_CLK_FCK2);
++
++      if (enable && dsi.pll_locked) {
++              if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
++                      DSSERR("cannot lock PLL when enabling clocks\n");
++      }
++}
++
++#ifdef DEBUG
++static void _dsi_print_reset_status(void)
++{
++      u32 l;
++
++      if (!dss_debug)
++              return;
++
++      /* A dummy read using the SCP interface to any DSIPHY register is
++       * required after DSIPHY reset to complete the reset of the DSI complex
++       * I/O. */
++      l = dsi_read_reg(DSI_DSIPHY_CFG5);
++
++      printk(KERN_DEBUG "DSI resets: ");
++
++      l = dsi_read_reg(DSI_PLL_STATUS);
++      printk("PLL (%d) ", FLD_GET(l, 0, 0));
++
++      l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
++      printk("CIO (%d) ", FLD_GET(l, 29, 29));
++
++      l = dsi_read_reg(DSI_DSIPHY_CFG5);
++      printk("PHY (%x, %d, %d, %d)\n",
++                      FLD_GET(l, 28, 26),
++                      FLD_GET(l, 29, 29),
++                      FLD_GET(l, 30, 30),
++                      FLD_GET(l, 31, 31));
++}
++#else
++#define _dsi_print_reset_status()
++#endif
++
++static inline int dsi_if_enable(bool enable)
++{
++      DSSDBG("dsi_if_enable(%d)\n", enable);
++
++      enable = enable ? 1 : 0;
++      REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
++
++      if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
++                      DSSERR("Failed to set dsi_if_enable to %d\n", enable);
++                      return -EIO;
++      }
++
++      return 0;
++}
++
++static unsigned long dsi_fclk_rate(void)
++{
++      unsigned long r;
++
++      if (dss_get_dsi_clk_source() == 0) {
++              /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
++              r = dss_clk_get_rate(DSS_CLK_FCK1);
++      } else {
++              /* DSI FCLK source is DSI2_PLL_FCLK */
++              r = dsi.dsi2_pll_fclk;
++      }
++
++      return r;
++}
++
++static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
++{
++      unsigned n;
++      unsigned long dsi_fclk;
++      unsigned long lp_clk, lp_clk_req;
++
++      dsi_fclk = dsi_fclk_rate();
++
++      lp_clk_req = dssdev->phy.dsi.lp_clk_hz;
++
++      for (n = 1; n < (1 << 13) - 1; ++n) {
++              lp_clk = dsi_fclk / 2 / n;
++              if (lp_clk <= lp_clk_req)
++                      break;
++      }
++
++      if (n == (1 << 13) - 1) {
++              DSSERR("Failed to find LP_CLK_DIVISOR\n");
++              return -EINVAL;
++      }
++
++      DSSDBG("LP_CLK_DIV %u, LP_CLK %lu (req %lu)\n", n, lp_clk, lp_clk_req);
++
++      REG_FLD_MOD(DSI_CLK_CTRL, n, 12, 0);    /* LP_CLK_DIVISOR */
++      if (dsi_fclk > 30*1000*1000)
++              REG_FLD_MOD(DSI_CLK_CTRL, 1, 21, 21); /* LP_RX_SYNCHRO_ENABLE */
++
++      return 0;
++}
++
++
++enum dsi_pll_power_state {
++      DSI_PLL_POWER_OFF       = 0x0,
++      DSI_PLL_POWER_ON_HSCLK  = 0x1,
++      DSI_PLL_POWER_ON_ALL    = 0x2,
++      DSI_PLL_POWER_ON_DIV    = 0x3,
++};
++
++static int dsi_pll_power(enum dsi_pll_power_state state)
++{
++      int t = 0;
++
++      REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30);       /* PLL_PWR_CMD */
++
++      /* PLL_PWR_STATUS */
++      while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
++              udelay(1);
++              if (t++ > 1000) {
++                      DSSERR("Failed to set DSI PLL power mode to %d\n",
++                                      state);
++                      return -ENODEV;
++              }
++      }
++
++      return 0;
++}
++
++int dsi_pll_calc_pck(bool is_tft, unsigned long req_pck,
++              struct dsi_clock_info *cinfo)
++{
++      struct dsi_clock_info cur, best;
++      int min_fck_per_pck;
++      int match = 0;
++      unsigned long dss_clk_fck2;
++
++      dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2);
++
++      if (req_pck == dsi.cache_req_pck &&
++                      dsi.cache_cinfo.clkin == dss_clk_fck2) {
++              DSSDBG("DSI clock info found from cache\n");
++              *cinfo = dsi.cache_cinfo;
++              return 0;
++      }
++
++      min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
++
++      if (min_fck_per_pck &&
++              req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
++              DSSERR("Requested pixel clock not possible with the current "
++                              "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
++                              "the constraint off.\n");
++              min_fck_per_pck = 0;
++      }
++
++      DSSDBG("dsi_pll_calc\n");
++
++retry:
++      memset(&best, 0, sizeof(best));
++
++      memset(&cur, 0, sizeof(cur));
++      cur.clkin = dss_clk_fck2;
++      cur.use_dss2_fck = 1;
++      cur.highfreq = 0;
++
++      /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
++      /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
++      /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
++      for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
++              if (cur.highfreq == 0)
++                      cur.fint = cur.clkin / cur.regn;
++              else
++                      cur.fint = cur.clkin / (2 * cur.regn);
++
++              if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
++                      continue;
++
++              /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
++              for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
++                      unsigned long a, b;
++
++                      a = 2 * cur.regm * (cur.clkin/1000);
++                      b = cur.regn * (cur.highfreq + 1);
++                      cur.dsiphy = a / b * 1000;
++
++                      if (cur.dsiphy > 1800 * 1000 * 1000)
++                              break;
++
++                      /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3  < 173MHz */
++                      for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
++                                      ++cur.regm3) {
++                              cur.dsi1_pll_fclk = cur.dsiphy / cur.regm3;
++
++                              /* this will narrow down the search a bit,
++                               * but still give pixclocks below what was
++                               * requested */
++                              if (cur.dsi1_pll_fclk  < req_pck)
++                                      break;
++
++                              if (cur.dsi1_pll_fclk > DISPC_MAX_FCK)
++                                      continue;
++
++                              if (min_fck_per_pck &&
++                                      cur.dsi1_pll_fclk <
++                                              req_pck * min_fck_per_pck)
++                                      continue;
++
++                              match = 1;
++
++                              find_lck_pck_divs(is_tft, req_pck,
++                                              cur.dsi1_pll_fclk,
++                                              &cur.lck_div,
++                                              &cur.pck_div);
++
++                              cur.lck = cur.dsi1_pll_fclk / cur.lck_div;
++                              cur.pck = cur.lck / cur.pck_div;
++
++                              if (abs(cur.pck - req_pck) <
++                                              abs(best.pck - req_pck)) {
++                                      best = cur;
++
++                                      if (cur.pck == req_pck)
++                                              goto found;
++                              }
++                      }
++              }
++      }
++found:
++      if (!match) {
++              if (min_fck_per_pck) {
++                      DSSERR("Could not find suitable clock settings.\n"
++                                      "Turning FCK/PCK constraint off and"
++                                      "trying again.\n");
++                      min_fck_per_pck = 0;
++                      goto retry;
++              }
++
++              DSSERR("Could not find suitable clock settings.\n");
++
++              return -EINVAL;
++      }
++
++      /* DSI2_PLL_FCLK (regm4) is not used. Set it to something sane. */
++      best.regm4 = best.dsiphy / 48000000;
++      if (best.regm4 > REGM4_MAX)
++              best.regm4 = REGM4_MAX;
++      else if (best.regm4 == 0)
++              best.regm4 = 1;
++      best.dsi2_pll_fclk = best.dsiphy / best.regm4;
++
++      if (cinfo)
++              *cinfo = best;
++
++      dsi.cache_req_pck = req_pck;
++      dsi.cache_clk_freq = 0;
++      dsi.cache_cinfo = best;
++
++      return 0;
++}
++
++static int dsi_pll_calc_ddrfreq(unsigned long clk_freq,
++              struct dsi_clock_info *cinfo)
++{
++      struct dsi_clock_info cur, best;
++      const bool use_dss2_fck = 1;
++      unsigned long datafreq;
++      unsigned long dss_clk_fck2;
++
++      DSSDBG("dsi_pll_calc_ddrfreq\n");
++
++      dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2);
++
++      if (clk_freq == dsi.cache_clk_freq &&
++                      dsi.cache_cinfo.clkin == dss_clk_fck2) {
++              DSSDBG("DSI clock info found from cache\n");
++              *cinfo = dsi.cache_cinfo;
++              return 0;
++      }
++
++      datafreq = clk_freq * 4;
++
++      memset(&best, 0, sizeof(best));
++
++      memset(&cur, 0, sizeof(cur));
++      cur.use_dss2_fck = use_dss2_fck;
++      if (use_dss2_fck) {
++              cur.clkin = dss_clk_fck2;
++              cur.highfreq = 0;
++      } else {
++              cur.clkin = dispc_pclk_rate();
++              if (cur.clkin < 32000000)
++                      cur.highfreq = 0;
++              else
++                      cur.highfreq = 1;
++      }
++
++      /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
++      /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
++      /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
++      for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
++              if (cur.highfreq == 0)
++                      cur.fint = cur.clkin / cur.regn;
++              else
++                      cur.fint = cur.clkin / (2 * cur.regn);
++
++              if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
++                      continue;
++
++              /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
++              for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
++                      unsigned long a, b;
++
++                      a = 2 * cur.regm * (cur.clkin/1000);
++                      b = cur.regn * (cur.highfreq + 1);
++                      cur.dsiphy = a / b * 1000;
++
++                      if (cur.dsiphy > 1800 * 1000 * 1000)
++                              break;
++
++                      if (abs(cur.dsiphy - datafreq) <
++                                      abs(best.dsiphy - datafreq)) {
++                              best = cur;
++                              /* DSSDBG("best %ld\n", best.dsiphy); */
++                      }
++
++                      if (cur.dsiphy == datafreq)
++                              goto found;
++              }
++      }
++found:
++      /* DSI1_PLL_FCLK (regm3) is not used. Set it to something sane. */
++      best.regm3 = best.dsiphy / 48000000;
++      if (best.regm3 > REGM3_MAX)
++              best.regm3 = REGM3_MAX;
++      else if (best.regm3 == 0)
++              best.regm3 = 1;
++      best.dsi1_pll_fclk = best.dsiphy / best.regm3;
++
++      /* DSI2_PLL_FCLK (regm4) is not used. Set it to something sane. */
++      best.regm4 = best.dsiphy / 48000000;
++      if (best.regm4 > REGM4_MAX)
++              best.regm4 = REGM4_MAX;
++      else if (best.regm4 == 0)
++              best.regm4 = 1;
++      best.dsi2_pll_fclk = best.dsiphy / best.regm4;
++
++      if (cinfo)
++              *cinfo = best;
++
++      dsi.cache_clk_freq = clk_freq;
++      dsi.cache_req_pck = 0;
++      dsi.cache_cinfo = best;
++
++      return 0;
++}
++
++int dsi_pll_program(struct dsi_clock_info *cinfo)
++{
++      int r = 0;
++      u32 l;
++
++      DSSDBG("dsi_pll_program\n");
++
++      dsi.dsiphy = cinfo->dsiphy;
++      dsi.ddr_clk = dsi.dsiphy / 4;
++      dsi.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
++      dsi.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
++
++      DSSDBG("DSI Fint %ld\n", cinfo->fint);
++
++      DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
++                      cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
++                      cinfo->clkin,
++                      cinfo->highfreq);
++
++      /* DSIPHY == CLKIN4DDR */
++      DSSDBG("DSIPHY = 2 * %d / %d * %lu / %d = %lu\n",
++                      cinfo->regm,
++                      cinfo->regn,
++                      cinfo->clkin,
++                      cinfo->highfreq + 1,
++                      cinfo->dsiphy);
++
++      DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
++                      dsi.dsiphy / 1000 / 1000 / 2);
++
++      DSSDBG("Clock lane freq %ld Hz\n", dsi.ddr_clk);
++
++      DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
++                      cinfo->regm3, cinfo->dsi1_pll_fclk);
++      DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
++                      cinfo->regm4, cinfo->dsi2_pll_fclk);
++
++      REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
++
++      l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
++      l = FLD_MOD(l, 1, 0, 0);                /* DSI_PLL_STOPMODE */
++      l = FLD_MOD(l, cinfo->regn - 1, 7, 1);  /* DSI_PLL_REGN */
++      l = FLD_MOD(l, cinfo->regm, 18, 8);     /* DSI_PLL_REGM */
++      l = FLD_MOD(l, cinfo->regm3 - 1, 22, 19);       /* DSI_CLOCK_DIV */
++      l = FLD_MOD(l, cinfo->regm4 - 1, 26, 23);       /* DSIPROTO_CLOCK_DIV */
++      dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
++
++      l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
++      l = FLD_MOD(l, 7, 4, 1);                /* DSI_PLL_FREQSEL */
++      /* DSI_PLL_CLKSEL */
++      l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1, 11, 11);
++      l = FLD_MOD(l, cinfo->highfreq, 12, 12);        /* DSI_PLL_HIGHFREQ */
++      l = FLD_MOD(l, 1, 13, 13);              /* DSI_PLL_REFEN */
++      l = FLD_MOD(l, 0, 14, 14);              /* DSIPHY_CLKINEN */
++      l = FLD_MOD(l, 1, 20, 20);              /* DSI_HSDIVBYPASS */
++      dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
++
++      REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
++
++      if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
++              DSSERR("dsi pll go bit not going down.\n");
++              r = -EIO;
++              goto err;
++      }
++
++      if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
++              DSSERR("cannot lock PLL\n");
++              r = -EIO;
++              goto err;
++      }
++
++      dsi.pll_locked = 1;
++
++      l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
++      l = FLD_MOD(l, 0, 0, 0);        /* DSI_PLL_IDLE */
++      l = FLD_MOD(l, 0, 5, 5);        /* DSI_PLL_PLLLPMODE */
++      l = FLD_MOD(l, 0, 6, 6);        /* DSI_PLL_LOWCURRSTBY */
++      l = FLD_MOD(l, 0, 7, 7);        /* DSI_PLL_TIGHTPHASELOCK */
++      l = FLD_MOD(l, 0, 8, 8);        /* DSI_PLL_DRIFTGUARDEN */
++      l = FLD_MOD(l, 0, 10, 9);       /* DSI_PLL_LOCKSEL */
++      l = FLD_MOD(l, 1, 13, 13);      /* DSI_PLL_REFEN */
++      l = FLD_MOD(l, 1, 14, 14);      /* DSIPHY_CLKINEN */
++      l = FLD_MOD(l, 0, 15, 15);      /* DSI_BYPASSEN */
++      l = FLD_MOD(l, 1, 16, 16);      /* DSS_CLOCK_EN */
++      l = FLD_MOD(l, 0, 17, 17);      /* DSS_CLOCK_PWDN */
++      l = FLD_MOD(l, 1, 18, 18);      /* DSI_PROTO_CLOCK_EN */
++      l = FLD_MOD(l, 0, 19, 19);      /* DSI_PROTO_CLOCK_PWDN */
++      l = FLD_MOD(l, 0, 20, 20);      /* DSI_HSDIVBYPASS */
++      dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
++
++      DSSDBG("PLL config done\n");
++err:
++      return r;
++}
++
++int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
++{
++      int r = 0;
++      enum dsi_pll_power_state pwstate;
++      struct dispc_clock_info cinfo;
++
++      DSSDBG("PLL init\n");
++
++      enable_clocks(1);
++      dsi_enable_pll_clock(1);
++
++      /* XXX this should be calculated depending on the screen size,
++       * required framerate and DSI speed.
++       * For now 48MHz is enough for 864x480@60 with 360Mbps/lane
++       * with two lanes */
++      r = dispc_calc_clock_div(1, 48 * 1000 * 1000, &cinfo);
++      if (r)
++              goto err0;
++
++      r = dispc_set_clock_div(&cinfo);
++      if (r) {
++              DSSERR("Failed to set basic clocks\n");
++              goto err0;
++      }
++
++      r = regulator_enable(dsi.vdds_dsi_reg);
++      if (r)
++              goto err0;
++
++      /* XXX PLL does not come out of reset without this... */
++      dispc_pck_free_enable(1);
++
++      if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
++              DSSERR("PLL not coming out of reset.\n");
++              r = -ENODEV;
++              goto err1;
++      }
++
++      /* XXX ... but if left on, we get problems when planes do not
++       * fill the whole display. No idea about this */
++      dispc_pck_free_enable(0);
++
++      if (enable_hsclk && enable_hsdiv)
++              pwstate = DSI_PLL_POWER_ON_ALL;
++      else if (enable_hsclk)
++              pwstate = DSI_PLL_POWER_ON_HSCLK;
++      else if (enable_hsdiv)
++              pwstate = DSI_PLL_POWER_ON_DIV;
++      else
++              pwstate = DSI_PLL_POWER_OFF;
++
++      r = dsi_pll_power(pwstate);
++
++      if (r)
++              goto err1;
++
++      DSSDBG("PLL init done\n");
++
++      return 0;
++err1:
++      regulator_disable(dsi.vdds_dsi_reg);
++err0:
++      enable_clocks(0);
++      dsi_enable_pll_clock(0);
++      return r;
++}
++
++void dsi_pll_uninit(void)
++{
++      enable_clocks(0);
++      dsi_enable_pll_clock(0);
++
++      dsi.pll_locked = 0;
++      dsi_pll_power(DSI_PLL_POWER_OFF);
++      regulator_disable(dsi.vdds_dsi_reg);
++      DSSDBG("PLL uninit done\n");
++}
++
++unsigned long dsi_get_dsi1_pll_rate(void)
++{
++      return dsi.dsi1_pll_fclk;
++}
++
++unsigned long dsi_get_dsi2_pll_rate(void)
++{
++      return dsi.dsi2_pll_fclk;
++}
++
++void dsi_dump_clocks(struct seq_file *s)
++{
++      int clksel;
++
++      enable_clocks(1);
++
++      clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
++
++      seq_printf(s, "- dsi -\n");
++
++      seq_printf(s, "dsi fclk source = %s\n",
++                      dss_get_dsi_clk_source() == 0 ?
++                      "dss1_alwon_fclk" : "dsi2_pll_fclk");
++
++      seq_printf(s, "dsi pll source = %s\n",
++                      clksel == 0 ?
++                      "dss2_alwon_fclk" : "pclkfree");
++
++      seq_printf(s,   "DSIPHY\t\t%lu\nDDR_CLK\t\t%lu\n",
++                      dsi.dsiphy, dsi.ddr_clk);
++
++      seq_printf(s,   "dsi1_pll_fck\t%lu (%s)\n"
++                      "dsi2_pll_fck\t%lu (%s)\n",
++                      dsi.dsi1_pll_fclk,
++                      dss_get_dispc_clk_source() == 0 ? "off" : "on",
++                      dsi.dsi2_pll_fclk,
++                      dss_get_dsi_clk_source() == 0 ? "off" : "on");
++
++      enable_clocks(0);
++}
++
++void dsi_dump_regs(struct seq_file *s)
++{
++#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
++
++      dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
++
++      DUMPREG(DSI_REVISION);
++      DUMPREG(DSI_SYSCONFIG);
++      DUMPREG(DSI_SYSSTATUS);
++      DUMPREG(DSI_IRQSTATUS);
++      DUMPREG(DSI_IRQENABLE);
++      DUMPREG(DSI_CTRL);
++      DUMPREG(DSI_COMPLEXIO_CFG1);
++      DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
++      DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
++      DUMPREG(DSI_CLK_CTRL);
++      DUMPREG(DSI_TIMING1);
++      DUMPREG(DSI_TIMING2);
++      DUMPREG(DSI_VM_TIMING1);
++      DUMPREG(DSI_VM_TIMING2);
++      DUMPREG(DSI_VM_TIMING3);
++      DUMPREG(DSI_CLK_TIMING);
++      DUMPREG(DSI_TX_FIFO_VC_SIZE);
++      DUMPREG(DSI_RX_FIFO_VC_SIZE);
++      DUMPREG(DSI_COMPLEXIO_CFG2);
++      DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
++      DUMPREG(DSI_VM_TIMING4);
++      DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
++      DUMPREG(DSI_VM_TIMING5);
++      DUMPREG(DSI_VM_TIMING6);
++      DUMPREG(DSI_VM_TIMING7);
++      DUMPREG(DSI_STOPCLK_TIMING);
++
++      DUMPREG(DSI_VC_CTRL(0));
++      DUMPREG(DSI_VC_TE(0));
++      DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
++      DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
++      DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
++      DUMPREG(DSI_VC_IRQSTATUS(0));
++      DUMPREG(DSI_VC_IRQENABLE(0));
++
++      DUMPREG(DSI_VC_CTRL(1));
++      DUMPREG(DSI_VC_TE(1));
++      DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
++      DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
++      DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
++      DUMPREG(DSI_VC_IRQSTATUS(1));
++      DUMPREG(DSI_VC_IRQENABLE(1));
++
++      DUMPREG(DSI_VC_CTRL(2));
++      DUMPREG(DSI_VC_TE(2));
++      DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
++      DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
++      DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
++      DUMPREG(DSI_VC_IRQSTATUS(2));
++      DUMPREG(DSI_VC_IRQENABLE(2));
++
++      DUMPREG(DSI_VC_CTRL(3));
++      DUMPREG(DSI_VC_TE(3));
++      DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
++      DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
++      DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
++      DUMPREG(DSI_VC_IRQSTATUS(3));
++      DUMPREG(DSI_VC_IRQENABLE(3));
++
++      DUMPREG(DSI_DSIPHY_CFG0);
++      DUMPREG(DSI_DSIPHY_CFG1);
++      DUMPREG(DSI_DSIPHY_CFG2);
++      DUMPREG(DSI_DSIPHY_CFG5);
++
++      DUMPREG(DSI_PLL_CONTROL);
++      DUMPREG(DSI_PLL_STATUS);
++      DUMPREG(DSI_PLL_GO);
++      DUMPREG(DSI_PLL_CONFIGURATION1);
++      DUMPREG(DSI_PLL_CONFIGURATION2);
++
++      dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
++#undef DUMPREG
++}
++
++enum dsi_complexio_power_state {
++      DSI_COMPLEXIO_POWER_OFF         = 0x0,
++      DSI_COMPLEXIO_POWER_ON          = 0x1,
++      DSI_COMPLEXIO_POWER_ULPS        = 0x2,
++};
++
++static int dsi_complexio_power(enum dsi_complexio_power_state state)
++{
++      int t = 0;
++
++      /* PWR_CMD */
++      REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
++
++      /* PWR_STATUS */
++      while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
++              udelay(1);
++              if (t++ > 1000) {
++                      DSSERR("failed to set complexio power state to "
++                                      "%d\n", state);
++                      return -ENODEV;
++              }
++      }
++
++      return 0;
++}
++
++static void dsi_complexio_config(struct omap_dss_device *dssdev)
++{
++      u32 r;
++
++      int clk_lane   = dssdev->phy.dsi.clk_lane;
++      int data1_lane = dssdev->phy.dsi.data1_lane;
++      int data2_lane = dssdev->phy.dsi.data2_lane;
++      int clk_pol    = dssdev->phy.dsi.clk_pol;
++      int data1_pol  = dssdev->phy.dsi.data1_pol;
++      int data2_pol  = dssdev->phy.dsi.data2_pol;
++
++      r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
++      r = FLD_MOD(r, clk_lane, 2, 0);
++      r = FLD_MOD(r, clk_pol, 3, 3);
++      r = FLD_MOD(r, data1_lane, 6, 4);
++      r = FLD_MOD(r, data1_pol, 7, 7);
++      r = FLD_MOD(r, data2_lane, 10, 8);
++      r = FLD_MOD(r, data2_pol, 11, 11);
++      dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
++
++      /* The configuration of the DSI complex I/O (number of data lanes,
++         position, differential order) should not be changed while
++         DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
++         the hardware to take into account a new configuration of the complex
++         I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
++         follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
++         then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
++         DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
++         DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
++         DSI complex I/O configuration is unknown. */
++
++      /*
++      REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
++      REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
++      REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
++      REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
++      */
++}
++
++static inline unsigned ns2ddr(unsigned ns)
++{
++      /* convert time in ns to ddr ticks, rounding up */
++      return (ns * (dsi.ddr_clk/1000/1000) + 999) / 1000;
++}
++
++static inline unsigned ddr2ns(unsigned ddr)
++{
++      return ddr * 1000 * 1000 / (dsi.ddr_clk / 1000);
++}
++
++static void dsi_complexio_timings(void)
++{
++      u32 r;
++      u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
++      u32 tlpx_half, tclk_trail, tclk_zero;
++      u32 tclk_prepare;
++
++      /* calculate timings */
++
++      /* 1 * DDR_CLK = 2 * UI */
++
++      /* min 40ns + 4*UI      max 85ns + 6*UI */
++      ths_prepare = ns2ddr(70) + 2;
++
++      /* min 145ns + 10*UI */
++      ths_prepare_ths_zero = ns2ddr(175) + 2;
++
++      /* min max(8*UI, 60ns+4*UI) */
++      ths_trail = ns2ddr(60) + 5;
++
++      /* min 100ns */
++      ths_exit = ns2ddr(145);
++
++      /* tlpx min 50n */
++      tlpx_half = ns2ddr(25);
++
++      /* min 60ns */
++      tclk_trail = ns2ddr(60) + 2;
++
++      /* min 38ns, max 95ns */
++      tclk_prepare = ns2ddr(65);
++
++      /* min tclk-prepare + tclk-zero = 300ns */
++      tclk_zero = ns2ddr(260);
++
++      DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
++              ths_prepare, ddr2ns(ths_prepare),
++              ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
++      DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
++                      ths_trail, ddr2ns(ths_trail),
++                      ths_exit, ddr2ns(ths_exit));
++
++      DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
++                      "tclk_zero %u (%uns)\n",
++                      tlpx_half, ddr2ns(tlpx_half),
++                      tclk_trail, ddr2ns(tclk_trail),
++                      tclk_zero, ddr2ns(tclk_zero));
++      DSSDBG("tclk_prepare %u (%uns)\n",
++                      tclk_prepare, ddr2ns(tclk_prepare));
++
++      /* program timings */
++
++      r = dsi_read_reg(DSI_DSIPHY_CFG0);
++      r = FLD_MOD(r, ths_prepare, 31, 24);
++      r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
++      r = FLD_MOD(r, ths_trail, 15, 8);
++      r = FLD_MOD(r, ths_exit, 7, 0);
++      dsi_write_reg(DSI_DSIPHY_CFG0, r);
++
++      r = dsi_read_reg(DSI_DSIPHY_CFG1);
++      r = FLD_MOD(r, tlpx_half, 22, 16);
++      r = FLD_MOD(r, tclk_trail, 15, 8);
++      r = FLD_MOD(r, tclk_zero, 7, 0);
++      dsi_write_reg(DSI_DSIPHY_CFG1, r);
++
++      r = dsi_read_reg(DSI_DSIPHY_CFG2);
++      r = FLD_MOD(r, tclk_prepare, 7, 0);
++      dsi_write_reg(DSI_DSIPHY_CFG2, r);
++}
++
++
++static int dsi_complexio_init(struct omap_dss_device *dssdev)
++{
++      int r = 0;
++
++      DSSDBG("dsi_complexio_init\n");
++
++      /* CIO_CLK_ICG, enable L3 clk to CIO */
++      REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
++
++      /* A dummy read using the SCP interface to any DSIPHY register is
++       * required after DSIPHY reset to complete the reset of the DSI complex
++       * I/O. */
++      dsi_read_reg(DSI_DSIPHY_CFG5);
++
++      if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
++              DSSERR("ComplexIO PHY not coming out of reset.\n");
++              r = -ENODEV;
++              goto err;
++      }
++
++      dsi_complexio_config(dssdev);
++
++      r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
++
++      if (r)
++              goto err;
++
++      if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
++              DSSERR("ComplexIO not coming out of reset.\n");
++              r = -ENODEV;
++              goto err;
++      }
++
++      if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
++              DSSERR("ComplexIO LDO power down.\n");
++              r = -ENODEV;
++              goto err;
++      }
++
++      dsi_complexio_timings();
++
++      /*
++         The configuration of the DSI complex I/O (number of data lanes,
++         position, differential order) should not be changed while
++         DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
++         hardware to recognize a new configuration of the complex I/O (done
++         in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
++         this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
++         reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
++         LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
++         bit to 1. If the sequence is not followed, the DSi complex I/O
++         configuration is undetermined.
++         */
++      dsi_if_enable(1);
++      dsi_if_enable(0);
++      REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
++      dsi_if_enable(1);
++      dsi_if_enable(0);
++
++      DSSDBG("CIO init done\n");
++err:
++      return r;
++}
++
++static void dsi_complexio_uninit(void)
++{
++      dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
++}
++
++static int _dsi_wait_reset(void)
++{
++      int i = 0;
++
++      while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
++              if (i++ > 5) {
++                      DSSERR("soft reset failed\n");
++                      return -ENODEV;
++              }
++              udelay(1);
++      }
++
++      return 0;
++}
++
++static int _dsi_reset(void)
++{
++      /* Soft reset */
++      REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
++      return _dsi_wait_reset();
++}
++
++
++static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
++              enum fifo_size size3, enum fifo_size size4)
++{
++      u32 r = 0;
++      int add = 0;
++      int i;
++
++      dsi.vc[0].fifo_size = size1;
++      dsi.vc[1].fifo_size = size2;
++      dsi.vc[2].fifo_size = size3;
++      dsi.vc[3].fifo_size = size4;
++
++      for (i = 0; i < 4; i++) {
++              u8 v;
++              int size = dsi.vc[i].fifo_size;
++
++              if (add + size > 4) {
++                      DSSERR("Illegal FIFO configuration\n");
++                      BUG();
++              }
++
++              v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
++              r |= v << (8 * i);
++              /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
++              add += size;
++      }
++
++      dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
++}
++
++static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
++              enum fifo_size size3, enum fifo_size size4)
++{
++      u32 r = 0;
++      int add = 0;
++      int i;
++
++      dsi.vc[0].fifo_size = size1;
++      dsi.vc[1].fifo_size = size2;
++      dsi.vc[2].fifo_size = size3;
++      dsi.vc[3].fifo_size = size4;
++
++      for (i = 0; i < 4; i++) {
++              u8 v;
++              int size = dsi.vc[i].fifo_size;
++
++              if (add + size > 4) {
++                      DSSERR("Illegal FIFO configuration\n");
++                      BUG();
++              }
++
++              v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
++              r |= v << (8 * i);
++              /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
++              add += size;
++      }
++
++      dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
++}
++
++static int dsi_force_tx_stop_mode_io(void)
++{
++      u32 r;
++
++      r = dsi_read_reg(DSI_TIMING1);
++      r = FLD_MOD(r, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
++      dsi_write_reg(DSI_TIMING1, r);
++
++      if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
++              DSSERR("TX_STOP bit not going down\n");
++              return -EIO;
++      }
++
++      return 0;
++}
++
++static void dsi_vc_print_status(int channel)
++{
++      u32 r;
++
++      r = dsi_read_reg(DSI_VC_CTRL(channel));
++      DSSDBG("vc %d: TX_FIFO_NOT_EMPTY %d, BTA_EN %d, VC_BUSY %d, "
++                      "TX_FIFO_FULL %d, RX_FIFO_NOT_EMPTY %d, ",
++                      channel,
++                      FLD_GET(r, 5, 5),
++                      FLD_GET(r, 6, 6),
++                      FLD_GET(r, 15, 15),
++                      FLD_GET(r, 16, 16),
++                      FLD_GET(r, 20, 20));
++
++      r = dsi_read_reg(DSI_TX_FIFO_VC_EMPTINESS);
++      DSSDBG("EMPTINESS %d\n", (r >> (8 * channel)) & 0xff);
++}
++
++static int dsi_vc_enable(int channel, bool enable)
++{
++      if (dsi.update_mode != OMAP_DSS_UPDATE_AUTO)
++              DSSDBG("dsi_vc_enable channel %d, enable %d\n",
++                              channel, enable);
++
++      enable = enable ? 1 : 0;
++
++      REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
++
++      if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
++                      DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
++                      return -EIO;
++      }
++
++      return 0;
++}
++
++static void dsi_vc_initial_config(int channel)
++{
++      u32 r;
++
++      DSSDBGF("%d", channel);
++
++      r = dsi_read_reg(DSI_VC_CTRL(channel));
++
++      if (FLD_GET(r, 15, 15)) /* VC_BUSY */
++              DSSERR("VC(%d) busy when trying to configure it!\n",
++                              channel);
++
++      r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
++      r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN  */
++      r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
++      r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
++      r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
++      r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
++      r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
++
++      r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
++      r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
++
++      dsi_write_reg(DSI_VC_CTRL(channel), r);
++
++      dsi.vc[channel].mode = DSI_VC_MODE_L4;
++}
++
++static void dsi_vc_config_l4(int channel)
++{
++      if (dsi.vc[channel].mode == DSI_VC_MODE_L4)
++              return;
++
++      DSSDBGF("%d", channel);
++
++      dsi_vc_enable(channel, 0);
++
++      if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */
++              DSSERR("vc(%d) busy when trying to config for L4\n", channel);
++
++      REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
++
++      dsi_vc_enable(channel, 1);
++
++      dsi.vc[channel].mode = DSI_VC_MODE_L4;
++}
++
++static void dsi_vc_config_vp(int channel)
++{
++      if (dsi.vc[channel].mode == DSI_VC_MODE_VP)
++              return;
++
++      DSSDBGF("%d", channel);
++
++      dsi_vc_enable(channel, 0);
++
++      if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */
++              DSSERR("vc(%d) busy when trying to config for VP\n", channel);
++
++      REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */
++
++      dsi_vc_enable(channel, 1);
++
++      dsi.vc[channel].mode = DSI_VC_MODE_VP;
++}
++
++
++static void dsi_vc_enable_hs(int channel, bool enable)
++{
++      DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
++
++      dsi_vc_enable(channel, 0);
++      dsi_if_enable(0);
++
++      REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
++
++      dsi_vc_enable(channel, 1);
++      dsi_if_enable(1);
++
++      dsi_force_tx_stop_mode_io();
++}
++
++static void dsi_vc_flush_long_data(int channel)
++{
++      while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
++              u32 val;
++              val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
++              DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
++                              (val >> 0) & 0xff,
++                              (val >> 8) & 0xff,
++                              (val >> 16) & 0xff,
++                              (val >> 24) & 0xff);
++      }
++}
++
++static void dsi_show_rx_ack_with_err(u16 err)
++{
++      DSSERR("\tACK with ERROR (%#x):\n", err);
++      if (err & (1 << 0))
++              DSSERR("\t\tSoT Error\n");
++      if (err & (1 << 1))
++              DSSERR("\t\tSoT Sync Error\n");
++      if (err & (1 << 2))
++              DSSERR("\t\tEoT Sync Error\n");
++      if (err & (1 << 3))
++              DSSERR("\t\tEscape Mode Entry Command Error\n");
++      if (err & (1 << 4))
++              DSSERR("\t\tLP Transmit Sync Error\n");
++      if (err & (1 << 5))
++              DSSERR("\t\tHS Receive Timeout Error\n");
++      if (err & (1 << 6))
++              DSSERR("\t\tFalse Control Error\n");
++      if (err & (1 << 7))
++              DSSERR("\t\t(reserved7)\n");
++      if (err & (1 << 8))
++              DSSERR("\t\tECC Error, single-bit (corrected)\n");
++      if (err & (1 << 9))
++              DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
++      if (err & (1 << 10))
++              DSSERR("\t\tChecksum Error\n");
++      if (err & (1 << 11))
++              DSSERR("\t\tData type not recognized\n");
++      if (err & (1 << 12))
++              DSSERR("\t\tInvalid VC ID\n");
++      if (err & (1 << 13))
++              DSSERR("\t\tInvalid Transmission Length\n");
++      if (err & (1 << 14))
++              DSSERR("\t\t(reserved14)\n");
++      if (err & (1 << 15))
++              DSSERR("\t\tDSI Protocol Violation\n");
++}
++
++static u16 dsi_vc_flush_receive_data(int channel)
++{
++      /* RX_FIFO_NOT_EMPTY */
++      while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
++              u32 val;
++              u8 dt;
++              val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
++              DSSDBG("\trawval %#08x\n", val);
++              dt = FLD_GET(val, 5, 0);
++              if (dt == DSI_DT_RX_ACK_WITH_ERR) {
++                      u16 err = FLD_GET(val, 23, 8);
++                      dsi_show_rx_ack_with_err(err);
++              } else if (dt == DSI_DT_RX_SHORT_READ_1) {
++                      DSSDBG("\tDCS short response, 1 byte: %#x\n",
++                                      FLD_GET(val, 23, 8));
++              } else if (dt == DSI_DT_RX_SHORT_READ_2) {
++                      DSSDBG("\tDCS short response, 2 byte: %#x\n",
++                                      FLD_GET(val, 23, 8));
++              } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
++                      DSSDBG("\tDCS long response, len %d\n",
++                                      FLD_GET(val, 23, 8));
++                      dsi_vc_flush_long_data(channel);
++              } else {
++                      DSSERR("\tunknown datatype 0x%02x\n", dt);
++              }
++      }
++      return 0;
++}
++
++static int dsi_vc_send_bta(int channel)
++{
++      if (dsi.update_mode != OMAP_DSS_UPDATE_AUTO &&
++                      (dsi.debug_write || dsi.debug_read))
++              DSSDBG("dsi_vc_send_bta %d\n", channel);
++
++      WARN_ON(!mutex_is_locked(&dsi.bus_lock));
++
++      if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {    /* RX_FIFO_NOT_EMPTY */
++              DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
++              dsi_vc_flush_receive_data(channel);
++      }
++
++      REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
++
++      return 0;
++}
++
++int dsi_vc_send_bta_sync(int channel)
++{
++      int r = 0;
++      u32 err;
++
++      INIT_COMPLETION(dsi.bta_completion);
++
++      dsi_vc_enable_bta_irq(channel);
++
++      r = dsi_vc_send_bta(channel);
++      if (r)
++              goto err;
++
++      if (wait_for_completion_timeout(&dsi.bta_completion,
++                              msecs_to_jiffies(500)) == 0) {
++              DSSERR("Failed to receive BTA\n");
++              r = -EIO;
++              goto err;
++      }
++
++      err = dsi_get_errors();
++      if (err) {
++              DSSERR("Error while sending BTA: %x\n", err);
++              r = -EIO;
++              goto err;
++      }
++err:
++      dsi_vc_disable_bta_irq(channel);
++
++      return r;
++}
++EXPORT_SYMBOL(dsi_vc_send_bta_sync);
++
++static inline void dsi_vc_write_long_header(int channel, u8 data_type,
++              u16 len, u8 ecc)
++{
++      u32 val;
++      u8 data_id;
++
++      WARN_ON(!mutex_is_locked(&dsi.bus_lock));
++
++      /*data_id = data_type | channel << 6; */
++      data_id = data_type | dsi.vc[channel].dest_per << 6;
++
++      val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
++              FLD_VAL(ecc, 31, 24);
++
++      dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
++}
++
++static inline void dsi_vc_write_long_payload(int channel,
++              u8 b1, u8 b2, u8 b3, u8 b4)
++{
++      u32 val;
++
++      val = b4 << 24 | b3 << 16 | b2 << 8  | b1 << 0;
++
++/*    DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
++                      b1, b2, b3, b4, val); */
++
++      dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
++}
++
++static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
++              u8 ecc)
++{
++      /*u32 val; */
++      int i;
++      u8 *p;
++      int r = 0;
++      u8 b1, b2, b3, b4;
++
++      if (dsi.debug_write)
++              DSSDBG("dsi_vc_send_long, %d bytes\n", len);
++
++      /* len + header */
++      if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
++              DSSERR("unable to send long packet: packet too long.\n");
++              return -EINVAL;
++      }
++
++      dsi_vc_config_l4(channel);
++
++      dsi_vc_write_long_header(channel, data_type, len, ecc);
++
++      /*dsi_vc_print_status(0); */
++
++      p = data;
++      for (i = 0; i < len >> 2; i++) {
++              if (dsi.debug_write)
++                      DSSDBG("\tsending full packet %d\n", i);
++              /*dsi_vc_print_status(0); */
++
++              b1 = *p++;
++              b2 = *p++;
++              b3 = *p++;
++              b4 = *p++;
++
++              dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
++      }
++
++      i = len % 4;
++      if (i) {
++              b1 = 0; b2 = 0; b3 = 0;
++
++              if (dsi.debug_write)
++                      DSSDBG("\tsending remainder bytes %d\n", i);
++
++              switch (i) {
++              case 3:
++                      b1 = *p++;
++                      b2 = *p++;
++                      b3 = *p++;
++                      break;
++              case 2:
++                      b1 = *p++;
++                      b2 = *p++;
++                      break;
++              case 1:
++                      b1 = *p++;
++                      break;
++              }
++
++              dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
++      }
++
++      return r;
++}
++
++static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
++{
++      u32 r;
++      u8 data_id;
++
++      WARN_ON(!mutex_is_locked(&dsi.bus_lock));
++
++      if (dsi.debug_write)
++              DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
++                              channel,
++                              data_type, data & 0xff, (data >> 8) & 0xff);
++
++      dsi_vc_config_l4(channel);
++
++      if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
++              DSSERR("ERROR FIFO FULL, aborting transfer\n");
++              return -EINVAL;
++      }
++
++      data_id = data_type | channel << 6;
++
++      r = (data_id << 0) | (data << 8) | (ecc << 24);
++
++      dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
++
++      return 0;
++}
++
++int dsi_vc_send_null(int channel)
++{
++      u8 nullpkg[] = {0, 0, 0, 0};
++      return dsi_vc_send_long(0, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
++}
++EXPORT_SYMBOL(dsi_vc_send_null);
++
++int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
++{
++      int r;
++
++      BUG_ON(len == 0);
++
++      if (len == 1) {
++              r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
++                              data[0], 0);
++      } else if (len == 2) {
++              r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
++                              data[0] | (data[1] << 8), 0);
++      } else {
++              /* 0x39 = DCS Long Write */
++              r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
++                              data, len, 0);
++      }
++
++      return r;
++}
++EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
++
++int dsi_vc_dcs_write(int channel, u8 *data, int len)
++{
++      int r;
++
++      r = dsi_vc_dcs_write_nosync(channel, data, len);
++      if (r)
++              return r;
++
++      r = dsi_vc_send_bta_sync(channel);
++
++      return r;
++}
++EXPORT_SYMBOL(dsi_vc_dcs_write);
++
++int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
++{
++      u32 val;
++      u8 dt;
++      int r;
++
++      if (dsi.debug_read)
++              DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %u)\n", channel, dcs_cmd);
++
++      r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
++      if (r)
++              return r;
++
++      r = dsi_vc_send_bta_sync(channel);
++      if (r)
++              return r;
++
++      /* RX_FIFO_NOT_EMPTY */
++      if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) {
++              DSSERR("RX fifo empty when trying to read.\n");
++              return -EIO;
++      }
++
++      val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
++      if (dsi.debug_read)
++              DSSDBG("\theader: %08x\n", val);
++      dt = FLD_GET(val, 5, 0);
++      if (dt == DSI_DT_RX_ACK_WITH_ERR) {
++              u16 err = FLD_GET(val, 23, 8);
++              dsi_show_rx_ack_with_err(err);
++              return -EIO;
++
++      } else if (dt == DSI_DT_RX_SHORT_READ_1) {
++              u8 data = FLD_GET(val, 15, 8);
++              if (dsi.debug_read)
++                      DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
++
++              if (buflen < 1)
++                      return -EIO;
++
++              buf[0] = data;
++
++              return 1;
++      } else if (dt == DSI_DT_RX_SHORT_READ_2) {
++              u16 data = FLD_GET(val, 23, 8);
++              if (dsi.debug_read)
++                      DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
++
++              if (buflen < 2)
++                      return -EIO;
++
++              buf[0] = data & 0xff;
++              buf[1] = (data >> 8) & 0xff;
++
++              return 2;
++      } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
++              int w;
++              int len = FLD_GET(val, 23, 8);
++              if (dsi.debug_read)
++                      DSSDBG("\tDCS long response, len %d\n", len);
++
++              if (len > buflen)
++                      return -EIO;
++
++              /* two byte checksum ends the packet, not included in len */
++              for (w = 0; w < len + 2;) {
++                      int b;
++                      val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
++                      if (dsi.debug_read)
++                              DSSDBG("\t\t%02x %02x %02x %02x\n",
++                                              (val >> 0) & 0xff,
++                                              (val >> 8) & 0xff,
++                                              (val >> 16) & 0xff,
++                                              (val >> 24) & 0xff);
++
++                      for (b = 0; b < 4; ++b) {
++                              if (w < len)
++                                      buf[w] = (val >> (b * 8)) & 0xff;
++                              /* we discard the 2 byte checksum */
++                              ++w;
++                      }
++              }
++
++              return len;
++
++      } else {
++              DSSERR("\tunknown datatype 0x%02x\n", dt);
++              return -EIO;
++      }
++}
++EXPORT_SYMBOL(dsi_vc_dcs_read);
++
++
++int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
++{
++      return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
++                      len, 0);
++}
++EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
++
++
++static int dsi_set_lp_rx_timeout(int ns, int x4, int x16)
++{
++      u32 r;
++      unsigned long fck;
++      int ticks;
++
++      /* ticks in DSI_FCK */
++
++      fck = dsi_fclk_rate();
++      ticks = (fck / 1000 / 1000) * ns / 1000;
++
++      if (ticks > 0x1fff) {
++              DSSERR("LP_TX_TO too high\n");
++              return -EINVAL;
++      }
++
++      r = dsi_read_reg(DSI_TIMING2);
++      r = FLD_MOD(r, 1, 15, 15);      /* LP_RX_TO */
++      r = FLD_MOD(r, x16, 14, 14);    /* LP_RX_TO_X16 */
++      r = FLD_MOD(r, x4, 13, 13);     /* LP_RX_TO_X4 */
++      r = FLD_MOD(r, ticks, 12, 0);   /* LP_RX_COUNTER */
++      dsi_write_reg(DSI_TIMING2, r);
++
++      DSSDBG("LP_RX_TO %ld ns (%#x ticks)\n",
++                      (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
++                      (fck / 1000 / 1000),
++                      ticks);
++
++      return 0;
++}
++
++static int dsi_set_ta_timeout(int ns, int x8, int x16)
++{
++      u32 r;
++      unsigned long fck;
++      int ticks;
++
++      /* ticks in DSI_FCK */
++
++      fck = dsi_fclk_rate();
++      ticks = (fck / 1000 / 1000) * ns / 1000;
++
++      if (ticks > 0x1fff) {
++              DSSERR("TA_TO too high\n");
++              return -EINVAL;
++      }
++
++      r = dsi_read_reg(DSI_TIMING1);
++      r = FLD_MOD(r, 1, 31, 31);      /* TA_TO */
++      r = FLD_MOD(r, x16, 30, 30);    /* TA_TO_X16 */
++      r = FLD_MOD(r, x8, 29, 29);     /* TA_TO_X8 */
++      r = FLD_MOD(r, ticks, 28, 16);  /* TA_TO_COUNTER */
++      dsi_write_reg(DSI_TIMING1, r);
++
++      DSSDBG("TA_TO %ld ns (%#x ticks)\n",
++                      (ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1) * 1000) /
++                      (fck / 1000 / 1000),
++                      ticks);
++
++      return 0;
++}
++
++static int dsi_set_stop_state_counter(int ns, int x4, int x16)
++{
++      u32 r;
++      unsigned long fck;
++      int ticks;
++
++      /* ticks in DSI_FCK */
++
++      fck = dsi_fclk_rate();
++      ticks = (fck / 1000 / 1000) * ns / 1000;
++
++      if (ticks > 0x1fff) {
++              DSSERR("STOP_STATE_COUNTER_IO too high\n");
++              return -EINVAL;
++      }
++
++      r = dsi_read_reg(DSI_TIMING1);
++      r = FLD_MOD(r, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
++      r = FLD_MOD(r, x16, 14, 14);    /* STOP_STATE_X16_IO */
++      r = FLD_MOD(r, x4, 13, 13);     /* STOP_STATE_X4_IO */
++      r = FLD_MOD(r, ticks, 12, 0);   /* STOP_STATE_COUNTER_IO */
++      dsi_write_reg(DSI_TIMING1, r);
++
++      DSSDBG("STOP_STATE_COUNTER %ld ns (%#x ticks)\n",
++                      (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
++                      (fck / 1000 / 1000),
++                      ticks);
++
++      return 0;
++}
++
++static int dsi_set_hs_tx_timeout(int ns, int x4, int x16)
++{
++      u32 r;
++      unsigned long fck;
++      int ticks;
++
++      /* ticks in TxByteClkHS */
++
++      fck = dsi.ddr_clk / 4;
++      ticks = (fck / 1000 / 1000) * ns / 1000;
++
++      if (ticks > 0x1fff) {
++              DSSERR("HS_TX_TO too high\n");
++              return -EINVAL;
++      }
++
++      r = dsi_read_reg(DSI_TIMING2);
++      r = FLD_MOD(r, 1, 31, 31);      /* HS_TX_TO */
++      r = FLD_MOD(r, x16, 30, 30);    /* HS_TX_TO_X16 */
++      r = FLD_MOD(r, x4, 29, 29);     /* HS_TX_TO_X8 (4 really) */
++      r = FLD_MOD(r, ticks, 28, 16);  /* HS_TX_TO_COUNTER */
++      dsi_write_reg(DSI_TIMING2, r);
++
++      DSSDBG("HS_TX_TO %ld ns (%#x ticks)\n",
++                      (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
++                      (fck / 1000 / 1000),
++                      ticks);
++
++      return 0;
++}
++static int dsi_proto_config(struct omap_dss_device *dssdev)
++{
++      u32 r;
++      int buswidth = 0;
++      int div;
++
++      dsi_config_tx_fifo(DSI_FIFO_SIZE_128,
++                      DSI_FIFO_SIZE_0,
++                      DSI_FIFO_SIZE_0,
++                      DSI_FIFO_SIZE_0);
++
++      dsi_config_rx_fifo(DSI_FIFO_SIZE_128,
++                      DSI_FIFO_SIZE_0,
++                      DSI_FIFO_SIZE_0,
++                      DSI_FIFO_SIZE_0);
++
++      /* XXX what values for the timeouts? */
++      dsi_set_stop_state_counter(1000, 0, 0);
++
++      dsi_set_ta_timeout(50000, 1, 1);
++
++      /* 3000ns * 16 */
++      dsi_set_lp_rx_timeout(3000, 0, 1);
++
++      /* 10000ns * 4 */
++      dsi_set_hs_tx_timeout(10000, 1, 0);
++
++      switch (dssdev->ctrl.pixel_size) {
++      case 16:
++              buswidth = 0;
++              break;
++      case 18:
++              buswidth = 1;
++              break;
++      case 24:
++              buswidth = 2;
++              break;
++      default:
++              BUG();
++      }
++
++      r = dsi_read_reg(DSI_CTRL);
++      r = FLD_MOD(r, 1, 1, 1);        /* CS_RX_EN */
++      r = FLD_MOD(r, 1, 2, 2);        /* ECC_RX_EN */
++      r = FLD_MOD(r, 1, 3, 3);        /* TX_FIFO_ARBITRATION */
++
++      div = dispc_lclk_rate() / dispc_pclk_rate();
++      r = FLD_MOD(r, div == 2 ? 0 : 1, 4, 4); /* VP_CLK_RATIO */
++      r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
++      r = FLD_MOD(r, 0, 8, 8);        /* VP_CLK_POL */
++      r = FLD_MOD(r, 2, 13, 12);      /* LINE_BUFFER, 2 lines */
++      r = FLD_MOD(r, 1, 14, 14);      /* TRIGGER_RESET_MODE */
++      r = FLD_MOD(r, 1, 19, 19);      /* EOT_ENABLE */
++      r = FLD_MOD(r, 1, 24, 24);      /* DCS_CMD_ENABLE */
++      r = FLD_MOD(r, 0, 25, 25);      /* DCS_CMD_CODE, 1=start, 0=continue */
++
++      dsi_write_reg(DSI_CTRL, r);
++
++      dsi_vc_initial_config(0);
++
++      /* set all vc targets to peripheral 0 */
++      dsi.vc[0].dest_per = 0;
++      dsi.vc[1].dest_per = 0;
++      dsi.vc[2].dest_per = 0;
++      dsi.vc[3].dest_per = 0;
++
++      return 0;
++}
++
++static void dsi_proto_timings(struct omap_dss_device *dssdev)
++{
++      unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
++      unsigned tclk_pre, tclk_post;
++      unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
++      unsigned ths_trail, ths_exit;
++      unsigned ddr_clk_pre, ddr_clk_post;
++      unsigned enter_hs_mode_lat, exit_hs_mode_lat;
++      unsigned ths_eot;
++      u32 r;
++
++      r = dsi_read_reg(DSI_DSIPHY_CFG0);
++      ths_prepare = FLD_GET(r, 31, 24);
++      ths_prepare_ths_zero = FLD_GET(r, 23, 16);
++      ths_zero = ths_prepare_ths_zero - ths_prepare;
++      ths_trail = FLD_GET(r, 15, 8);
++      ths_exit = FLD_GET(r, 7, 0);
++
++      r = dsi_read_reg(DSI_DSIPHY_CFG1);
++      tlpx = FLD_GET(r, 22, 16) * 2;
++      tclk_trail = FLD_GET(r, 15, 8);
++      tclk_zero = FLD_GET(r, 7, 0);
++
++      r = dsi_read_reg(DSI_DSIPHY_CFG2);
++      tclk_prepare = FLD_GET(r, 7, 0);
++
++      /* min 8*UI */
++      tclk_pre = 20;
++      /* min 60ns + 52*UI */
++      tclk_post = ns2ddr(60) + 26;
++
++      /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
++      if (dssdev->phy.dsi.data1_lane != 0 &&
++                      dssdev->phy.dsi.data2_lane != 0)
++              ths_eot = 2;
++      else
++              ths_eot = 4;
++
++      ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
++                      4);
++      ddr_clk_post = DIV_ROUND_UP(tclk_post + tclk_trail, 4) + ths_eot;
++
++      BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
++      BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
++
++      r = dsi_read_reg(DSI_CLK_TIMING);
++      r = FLD_MOD(r, ddr_clk_pre, 15, 8);
++      r = FLD_MOD(r, ddr_clk_post, 7, 0);
++      dsi_write_reg(DSI_CLK_TIMING, r);
++
++      DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
++                      ddr_clk_pre,
++                      ddr_clk_post);
++
++      enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
++              DIV_ROUND_UP(ths_prepare, 4) +
++              DIV_ROUND_UP(ths_zero + 3, 4);
++
++      exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
++
++      r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
++              FLD_VAL(exit_hs_mode_lat, 15, 0);
++      dsi_write_reg(DSI_VM_TIMING7, r);
++
++      DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
++                      enter_hs_mode_lat, exit_hs_mode_lat);
++}
++
++
++#define DSI_DECL_VARS \
++      int __dsi_cb = 0; u32 __dsi_cv = 0;
++
++#define DSI_FLUSH(ch) \
++      if (__dsi_cb > 0) { \
++              /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
++              dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
++              __dsi_cb = __dsi_cv = 0; \
++      }
++
++#define DSI_PUSH(ch, data) \
++      do { \
++              __dsi_cv |= (data) << (__dsi_cb * 8); \
++              /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
++              if (++__dsi_cb > 3) \
++                      DSI_FLUSH(ch); \
++      } while (0)
++
++static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
++                      int x, int y, int w, int h)
++{
++      /* Note: supports only 24bit colors in 32bit container */
++      int first = 1;
++      int fifo_stalls = 0;
++      int max_dsi_packet_size;
++      int max_data_per_packet;
++      int max_pixels_per_packet;
++      int pixels_left;
++      int bytespp = dssdev->ctrl.pixel_size / 8;
++      int scr_width;
++      u32 __iomem *data;
++      int start_offset;
++      int horiz_inc;
++      int current_x;
++      struct omap_overlay *ovl;
++
++      debug_irq = 0;
++
++      DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
++                      x, y, w, h);
++
++      ovl = dssdev->manager->overlays[0];
++
++      if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
++              return -EINVAL;
++
++      if (dssdev->ctrl.pixel_size != 24)
++              return -EINVAL;
++
++      scr_width = ovl->info.screen_width;
++      data = ovl->info.vaddr;
++
++      start_offset = scr_width * y + x;
++      horiz_inc = scr_width - w;
++      current_x = x;
++
++      /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
++       * in fifo */
++
++      /* When using CPU, max long packet size is TX buffer size */
++      max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
++
++      /* we seem to get better perf if we divide the tx fifo to half,
++         and while the other half is being sent, we fill the other half
++         max_dsi_packet_size /= 2; */
++
++      max_data_per_packet = max_dsi_packet_size - 4 - 1;
++
++      max_pixels_per_packet = max_data_per_packet / bytespp;
++
++      DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
++
++      pixels_left = w * h;
++
++      DSSDBG("total pixels %d\n", pixels_left);
++
++      data += start_offset;
++
++      while (pixels_left > 0) {
++              /* 0x2c = write_memory_start */
++              /* 0x3c = write_memory_continue */
++              u8 dcs_cmd = first ? 0x2c : 0x3c;
++              int pixels;
++              DSI_DECL_VARS;
++              first = 0;
++
++#if 1
++              /* using fifo not empty */
++              /* TX_FIFO_NOT_EMPTY */
++              while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
++                      udelay(1);
++                      fifo_stalls++;
++                      if (fifo_stalls > 0xfffff) {
++                              DSSERR("fifo stalls overflow, pixels left %d\n",
++                                              pixels_left);
++                              dsi_if_enable(0);
++                              return -EIO;
++                      }
++              }
++#elif 1
++              /* using fifo emptiness */
++              while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
++                              max_dsi_packet_size) {
++                      fifo_stalls++;
++                      if (fifo_stalls > 0xfffff) {
++                              DSSERR("fifo stalls overflow, pixels left %d\n",
++                                             pixels_left);
++                              dsi_if_enable(0);
++                              return -EIO;
++                      }
++              }
++#else
++              while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
++                      fifo_stalls++;
++                      if (fifo_stalls > 0xfffff) {
++                              DSSERR("fifo stalls overflow, pixels left %d\n",
++                                             pixels_left);
++                              dsi_if_enable(0);
++                              return -EIO;
++                      }
++              }
++#endif
++              pixels = min(max_pixels_per_packet, pixels_left);
++
++              pixels_left -= pixels;
++
++              dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
++                              1 + pixels * bytespp, 0);
++
++              DSI_PUSH(0, dcs_cmd);
++
++              while (pixels-- > 0) {
++                      u32 pix = __raw_readl(data++);
++
++                      DSI_PUSH(0, (pix >> 16) & 0xff);
++                      DSI_PUSH(0, (pix >> 8) & 0xff);
++                      DSI_PUSH(0, (pix >> 0) & 0xff);
++
++                      current_x++;
++                      if (current_x == x+w) {
++                              current_x = x;
++                              data += horiz_inc;
++                      }
++              }
++
++              DSI_FLUSH(0);
++      }
++
++      return 0;
++}
++
++static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
++              u16 x, u16 y, u16 w, u16 h)
++{
++      int bytespp = dssdev->ctrl.pixel_size / 8;
++      int len;
++      int total_len;
++      int packet_payload;
++      int packet_len;
++      u32 l;
++      bool use_te_trigger;
++      const int channel = 0;
++
++      use_te_trigger = dsi.te_enabled && !dsi.use_ext_te;
++
++      if (dsi.update_mode != OMAP_DSS_UPDATE_AUTO)
++              DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
++                              x, y, w, h);
++
++      len = w * h * bytespp;
++
++      /* XXX: one packet could be longer, I think? Line buffer is
++       * 1024 x 24bits, but we have to put DCS cmd there also.
++       * 1023 * 3 should work, but causes strange color effects. */
++      packet_payload = min(w, (u16)1020) * bytespp;
++
++      packet_len = packet_payload + 1;        /* 1 byte for DCS cmd */
++      total_len = (len / packet_payload) * packet_len;
++
++      if (len % packet_payload)
++              total_len += (len % packet_payload) + 1;
++
++      if (0)
++              dsi_vc_print_status(1);
++
++      l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
++      dsi_write_reg(DSI_VC_TE(channel), l);
++
++      dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0);
++
++      if (use_te_trigger)
++              l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
++      else
++              l = FLD_MOD(l, 1, 31, 31); /* TE_START */
++      dsi_write_reg(DSI_VC_TE(channel), l);
++
++      /* We put SIDLEMODE to no-idle for the duration of the transfer,
++       * because DSS interrupts are not capable of waking up the CPU and the
++       * framedone interrupt could be delayed for quite a long time. I think
++       * the same goes for any DSS interrupts, but for some reason I have not
++       * seen the problem anywhere else than here.
++       */
++      dispc_disable_sidle();
++
++      dss_start_update(dssdev);
++
++      if (use_te_trigger) {
++              /* disable LP_RX_TO, so that we can receive TE.  Time to wait
++               * for TE is longer than the timer allows */
++              REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
++
++              dsi_vc_send_bta(channel);
++      }
++}
++
++static void dsi_framedone_irq_callback(void *data, u32 mask)
++{
++      /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
++       * turns itself off. However, DSI still has the pixels in its buffers,
++       * and is sending the data.
++       */
++
++      /* SIDLEMODE back to smart-idle */
++      dispc_enable_sidle();
++
++      dsi.framedone_received = true;
++      wake_up(&dsi.waitqueue);
++}
++
++static void dsi_set_update_region(struct omap_dss_device *dssdev,
++              u16 x, u16 y, u16 w, u16 h)
++{
++      spin_lock(&dsi.update_lock);
++      if (dsi.update_region.dirty) {
++              dsi.update_region.x = min(x, dsi.update_region.x);
++              dsi.update_region.y = min(y, dsi.update_region.y);
++              dsi.update_region.w = max(w, dsi.update_region.w);
++              dsi.update_region.h = max(h, dsi.update_region.h);
++      } else {
++              dsi.update_region.x = x;
++              dsi.update_region.y = y;
++              dsi.update_region.w = w;
++              dsi.update_region.h = h;
++      }
++
++      dsi.update_region.device = dssdev;
++      dsi.update_region.dirty = true;
++
++      spin_unlock(&dsi.update_lock);
++
++}
++
++static void dsi_start_auto_update(struct omap_dss_device *dssdev)
++{
++      u16 w, h;
++      int i;
++
++      DSSDBG("starting auto update\n");
++
++      /* In automatic mode the overlay settings are applied like on DPI/SDI.
++       * Mark the overlays dirty, so that we get the overlays configured, as
++       * manual mode has left them in bad shape after config partia planes */
++      for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
++              struct omap_overlay *ovl;
++              ovl = omap_dss_get_overlay(i);
++              if (ovl->manager == dssdev->manager)
++                      ovl->info_dirty = true;
++      }
++      dssdev->manager->apply(dssdev->manager);
++
++      dssdev->get_resolution(dssdev, &w, &h);
++
++      dsi_set_update_region(dssdev, 0, 0, w, h);
++
++      dsi_perf_mark_start_auto();
++
++      wake_up(&dsi.waitqueue);
++}
++
++static int dsi_set_te(struct omap_dss_device *dssdev, bool enable)
++{
++      int r;
++      r = dssdev->driver->enable_te(dssdev, enable);
++      /* XXX for some reason, DSI TE breaks if we don't wait here.
++       * Panel bug? Needs more studying */
++      msleep(100);
++      return r;
++}
++
++static void dsi_handle_framedone(void)
++{
++      int r;
++      const int channel = 0;
++      bool use_te_trigger;
++
++      use_te_trigger = dsi.te_enabled && !dsi.use_ext_te;
++
++      if (dsi.update_mode != OMAP_DSS_UPDATE_AUTO)
++              DSSDBG("FRAMEDONE\n");
++
++      if (use_te_trigger) {
++              /* enable LP_RX_TO again after the TE */
++              REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
++      }
++
++      /* Send BTA after the frame. We need this for the TE to work, as TE
++       * trigger is only sent for BTAs without preceding packet. Thus we need
++       * to BTA after the pixel packets so that next BTA will cause TE
++       * trigger.
++       *
++       * This is not needed when TE is not in use, but we do it anyway to
++       * make sure that the transfer has been completed. It would be more
++       * optimal, but more complex, to wait only just before starting next
++       * transfer. */
++      r = dsi_vc_send_bta_sync(channel);
++      if (r)
++              DSSERR("BTA after framedone failed\n");
++
++#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
++      dispc_fake_vsync_irq();
++#endif
++}
++
++static int dsi_update_thread(void *data)
++{
++      unsigned long timeout;
++      struct omap_dss_device *device;
++      u16 x, y, w, h;
++
++      while (1) {
++              bool sched;
++
++              wait_event_interruptible(dsi.waitqueue,
++                              dsi.update_mode == OMAP_DSS_UPDATE_AUTO ||
++                              (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL &&
++                               dsi.update_region.dirty == true) ||
++                              kthread_should_stop());
++
++              if (kthread_should_stop())
++                      break;
++
++              dsi_bus_lock();
++
++              if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED ||
++                              kthread_should_stop()) {
++                      dsi_bus_unlock();
++                      break;
++              }
++
++              dsi_perf_mark_setup();
++
++              if (dsi.update_region.dirty) {
++                      spin_lock(&dsi.update_lock);
++                      dsi.active_update_region = dsi.update_region;
++                      dsi.update_region.dirty = false;
++                      spin_unlock(&dsi.update_lock);
++              }
++
++              device = dsi.active_update_region.device;
++              x = dsi.active_update_region.x;
++              y = dsi.active_update_region.y;
++              w = dsi.active_update_region.w;
++              h = dsi.active_update_region.h;
++
++              if (device->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
++
++                      if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL) {
++                              dss_setup_partial_planes(device,
++                                              &x, &y, &w, &h);
++#if 1
++                              /* XXX there seems to be a bug in this driver
++                               * or OMAP hardware.  Some updates with certain
++                               * widths and x coordinates fail. These widths
++                               * are always odd, so "fix" it here for now */
++                              if (w & 1) {
++                                      u16 dw, dh;
++                                      device->get_resolution(device,
++                                                      &dw, &dh);
++                                      if (x + w == dw)
++                                              x &= ~1;
++                                      ++w;
++
++                                      dss_setup_partial_planes(device,
++                                                      &x, &y, &w, &h);
++                              }
++#endif
++                      }
++
++                      dispc_set_lcd_size(w, h);
++              }
++
++              if (dsi.active_update_region.dirty) {
++                      dsi.active_update_region.dirty = false;
++                      /* XXX TODO we don't need to send the coords, if they
++                       * are the same that are already programmed to the
++                       * panel. That should speed up manual update a bit */
++                      device->driver->setup_update(device, x, y, w, h);
++              }
++
++              dsi_perf_mark_start();
++
++              if (device->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
++                      dsi_vc_config_vp(0);
++
++                      if (dsi.te_enabled && dsi.use_ext_te)
++                              device->driver->wait_for_te(device);
++
++                      dsi.framedone_received = false;
++
++                      dsi_update_screen_dispc(device, x, y, w, h);
++
++                      /* wait for framedone */
++                      timeout = msecs_to_jiffies(1000);
++                      timeout = wait_event_timeout(dsi.waitqueue,
++                                      dsi.framedone_received == true,
++                                      timeout);
++
++                      if (timeout == 0) {
++                              DSSERR("framedone timeout\n");
++                              DSSERR("failed update %d,%d %dx%d\n",
++                                              x, y, w, h);
++
++                              dispc_enable_sidle();
++                              dispc_enable_lcd_out(0);
++                      } else {
++                              dsi_handle_framedone();
++                              dsi_perf_show("DISPC");
++                      }
++              } else {
++                      dsi_update_screen_l4(device, x, y, w, h);
++                      dsi_perf_show("L4");
++              }
++
++              sched = atomic_read(&dsi.bus_lock.count) < 0;
++
++              complete_all(&dsi.update_completion);
++
++              dsi_bus_unlock();
++
++              /* XXX We need to give others chance to get the bus lock. Is
++               * there a better way for this? */
++              if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO && sched)
++                      schedule_timeout_interruptible(1);
++      }
++
++      DSSDBG("update thread exiting\n");
++
++      return 0;
++}
++
++
++
++/* Display funcs */
++
++static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
++{
++      int r;
++
++      r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL,
++                      DISPC_IRQ_FRAMEDONE);
++      if (r) {
++              DSSERR("can't get FRAMEDONE irq\n");
++              return r;
++      }
++
++      dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
++
++      dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI);
++      dispc_enable_fifohandcheck(1);
++
++      dispc_set_tft_data_lines(dssdev->ctrl.pixel_size);
++
++      {
++              struct omap_video_timings timings = {
++                      .hsw            = 1,
++                      .hfp            = 1,
++                      .hbp            = 1,
++                      .vsw            = 1,
++                      .vfp            = 0,
++                      .vbp            = 0,
++              };
++
++              dispc_set_lcd_timings(&timings);
++      }
++
++      return 0;
++}
++
++static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
++{
++      omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL,
++                      DISPC_IRQ_FRAMEDONE);
++}
++
++static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
++{
++      struct dsi_clock_info cinfo;
++      int r;
++
++      _dsi_print_reset_status();
++
++      r = dsi_pll_init(1, 0);
++      if (r)
++              goto err0;
++
++      r = dsi_pll_calc_ddrfreq(dssdev->phy.dsi.ddr_clk_hz, &cinfo);
++      if (r)
++              goto err1;
++
++      r = dsi_pll_program(&cinfo);
++      if (r)
++              goto err1;
++
++      DSSDBG("PLL OK\n");
++
++      r = dsi_complexio_init(dssdev);
++      if (r)
++              goto err1;
++
++      _dsi_print_reset_status();
++
++      dsi_proto_timings(dssdev);
++      dsi_set_lp_clk_divisor(dssdev);
++
++      if (1)
++              _dsi_print_reset_status();
++
++      r = dsi_proto_config(dssdev);
++      if (r)
++              goto err2;
++
++      /* enable interface */
++      dsi_vc_enable(0, 1);
++      dsi_if_enable(1);
++      dsi_force_tx_stop_mode_io();
++
++      if (dssdev->driver->enable) {
++              r = dssdev->driver->enable(dssdev);
++              if (r)
++                      goto err3;
++      }
++
++      /* enable high-speed after initial config */
++      dsi_vc_enable_hs(0, 1);
++
++      return 0;
++err3:
++      dsi_if_enable(0);
++err2:
++      dsi_complexio_uninit();
++err1:
++      dsi_pll_uninit();
++err0:
++      return r;
++}
++
++static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
++{
++      if (dssdev->driver->disable)
++              dssdev->driver->disable(dssdev);
++
++      dsi_complexio_uninit();
++      dsi_pll_uninit();
++}
++
++static int dsi_core_init(void)
++{
++      /* Autoidle */
++      REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
++
++      /* ENWAKEUP */
++      REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
++
++      /* SIDLEMODE smart-idle */
++      REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
++
++      _dsi_initialize_irq();
++
++      return 0;
++}
++
++static int dsi_display_enable(struct omap_dss_device *dssdev)
++{
++      int r = 0;
++
++      DSSDBG("dsi_display_enable\n");
++
++      mutex_lock(&dsi.lock);
++      dsi_bus_lock();
++
++      r = omap_dss_start_device(dssdev);
++      if (r) {
++              DSSERR("failed to start device\n");
++              goto err0;
++      }
++
++      if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
++              DSSERR("dssdev already enabled\n");
++              r = -EINVAL;
++              goto err1;
++      }
++
++      enable_clocks(1);
++      dsi_enable_pll_clock(1);
++
++      r = _dsi_reset();
++      if (r)
++              goto err2;
++
++      dsi_core_init();
++
++      r = dsi_display_init_dispc(dssdev);
++      if (r)
++              goto err2;
++
++      r = dsi_display_init_dsi(dssdev);
++      if (r)
++              goto err3;
++
++      dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++      dsi.use_ext_te = dssdev->phy.dsi.ext_te;
++      r = dsi_set_te(dssdev, dsi.te_enabled);
++      if (r)
++              goto err3;
++
++      dsi.update_mode = dsi.user_update_mode;
++      if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO)
++              dsi_start_auto_update(dssdev);
++
++      dsi_bus_unlock();
++      mutex_unlock(&dsi.lock);
++
++      return 0;
++
++err3:
++      dsi_display_uninit_dispc(dssdev);
++err2:
++      enable_clocks(0);
++      dsi_enable_pll_clock(0);
++err1:
++      omap_dss_stop_device(dssdev);
++err0:
++      dsi_bus_unlock();
++      mutex_unlock(&dsi.lock);
++      DSSDBG("dsi_display_enable FAILED\n");
++      return r;
++}
++
++static void dsi_display_disable(struct omap_dss_device *dssdev)
++{
++      DSSDBG("dsi_display_disable\n");
++
++      mutex_lock(&dsi.lock);
++      dsi_bus_lock();
++
++      if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED ||
++                      dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED)
++              goto end;
++
++      dsi.update_mode = OMAP_DSS_UPDATE_DISABLED;
++      dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
++
++      dsi_display_uninit_dispc(dssdev);
++
++      dsi_display_uninit_dsi(dssdev);
++
++      enable_clocks(0);
++      dsi_enable_pll_clock(0);
++
++      omap_dss_stop_device(dssdev);
++end:
++      dsi_bus_unlock();
++      mutex_unlock(&dsi.lock);
++}
++
++static int dsi_display_suspend(struct omap_dss_device *dssdev)
++{
++      DSSDBG("dsi_display_suspend\n");
++
++      mutex_lock(&dsi.lock);
++      dsi_bus_lock();
++
++      if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED ||
++                      dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED)
++              goto end;
++
++      dsi.update_mode = OMAP_DSS_UPDATE_DISABLED;
++      dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED;
++
++      dsi_display_uninit_dispc(dssdev);
++
++      dsi_display_uninit_dsi(dssdev);
++
++      enable_clocks(0);
++      dsi_enable_pll_clock(0);
++end:
++      dsi_bus_unlock();
++      mutex_unlock(&dsi.lock);
++
++      return 0;
++}
++
++static int dsi_display_resume(struct omap_dss_device *dssdev)
++{
++      int r;
++
++      DSSDBG("dsi_display_resume\n");
++
++      mutex_lock(&dsi.lock);
++      dsi_bus_lock();
++
++      if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) {
++              DSSERR("dssdev not suspended\n");
++              r = -EINVAL;
++              goto err0;
++      }
++
++      enable_clocks(1);
++      dsi_enable_pll_clock(1);
++
++      r = _dsi_reset();
++      if (r)
++              goto err1;
++
++      dsi_core_init();
++
++      r = dsi_display_init_dispc(dssdev);
++      if (r)
++              goto err1;
++
++      r = dsi_display_init_dsi(dssdev);
++      if (r)
++              goto err2;
++
++      dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
++
++      r = dsi_set_te(dssdev, dsi.te_enabled);
++      if (r)
++              goto err2;
++
++      dsi.update_mode = dsi.user_update_mode;
++      if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO)
++              dsi_start_auto_update(dssdev);
++
++      dsi_bus_unlock();
++      mutex_unlock(&dsi.lock);
++
++      return 0;
++
++err2:
++      dsi_display_uninit_dispc(dssdev);
++err1:
++      enable_clocks(0);
++      dsi_enable_pll_clock(0);
++err0:
++      dsi_bus_unlock();
++      mutex_unlock(&dsi.lock);
++      DSSDBG("dsi_display_resume FAILED\n");
++      return r;
++}
++
++static int dsi_display_update(struct omap_dss_device *dssdev,
++                      u16 x, u16 y, u16 w, u16 h)
++{
++      int r = 0;
++      u16 dw, dh;
++
++      DSSDBG("dsi_display_update(%d,%d %dx%d)\n", x, y, w, h);
++
++      mutex_lock(&dsi.lock);
++
++      if (dsi.update_mode != OMAP_DSS_UPDATE_MANUAL)
++              goto end;
++
++      if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
++              goto end;
++
++      dssdev->get_resolution(dssdev, &dw, &dh);
++
++      if  (x > dw || y > dh)
++              goto end;
++
++      if (x + w > dw)
++              w = dw - x;
++
++      if (y + h > dh)
++              h = dh - y;
++
++      if (w == 0 || h == 0)
++              goto end;
++
++      dsi_set_update_region(dssdev, x, y, w, h);
++
++      wake_up(&dsi.waitqueue);
++
++end:
++      mutex_unlock(&dsi.lock);
++
++      return r;
++}
++
++static int dsi_display_sync(struct omap_dss_device *dssdev)
++{
++      bool wait;
++
++      DSSDBG("dsi_display_sync()\n");
++
++      mutex_lock(&dsi.lock);
++      dsi_bus_lock();
++
++      if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL &&
++                      dsi.update_region.dirty) {
++              INIT_COMPLETION(dsi.update_completion);
++              wait = true;
++      } else {
++              wait = false;
++      }
++
++      dsi_bus_unlock();
++      mutex_unlock(&dsi.lock);
++
++      if (wait)
++              wait_for_completion_interruptible(&dsi.update_completion);
++
++      DSSDBG("dsi_display_sync() done\n");
++      return 0;
++}
++
++static int dsi_display_set_update_mode(struct omap_dss_device *dssdev,
++              enum omap_dss_update_mode mode)
++{
++      DSSDBGF("%d", mode);
++
++      mutex_lock(&dsi.lock);
++      dsi_bus_lock();
++
++      if (dsi.update_mode != mode) {
++              dsi.user_update_mode = mode;
++              dsi.update_mode = mode;
++
++              if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE &&
++                              mode == OMAP_DSS_UPDATE_AUTO)
++                      dsi_start_auto_update(dssdev);
++      }
++
++      dsi_bus_unlock();
++      mutex_unlock(&dsi.lock);
++
++      return 0;
++}
++
++static enum omap_dss_update_mode dsi_display_get_update_mode(
++              struct omap_dss_device *dssdev)
++{
++      return dsi.update_mode;
++}
++
++
++static int dsi_display_enable_te(struct omap_dss_device *dssdev, bool enable)
++{
++      int r = 0;
++
++      DSSDBGF("%d", enable);
++
++      if (!dssdev->driver->enable_te)
++              return -ENOENT;
++
++      dsi_bus_lock();
++
++      dsi.te_enabled = enable;
++
++      if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
++              goto end;
++
++      r = dsi_set_te(dssdev, enable);
++end:
++      dsi_bus_unlock();
++
++      return r;
++}
++
++static int dsi_display_get_te(struct omap_dss_device *dssdev)
++{
++      return dsi.te_enabled;
++}
++
++static int dsi_display_set_rotate(struct omap_dss_device *dssdev, u8 rotate)
++{
++
++      DSSDBGF("%d", rotate);
++
++      if (!dssdev->driver->set_rotate || !dssdev->driver->get_rotate)
++              return -EINVAL;
++
++      dsi_bus_lock();
++      dssdev->driver->set_rotate(dssdev, rotate);
++      if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) {
++              u16 w, h;
++              /* the display dimensions may have changed, so set a new
++               * update region */
++              dssdev->get_resolution(dssdev, &w, &h);
++              dsi_set_update_region(dssdev, 0, 0, w, h);
++      }
++      dsi_bus_unlock();
++
++      return 0;
++}
++
++static u8 dsi_display_get_rotate(struct omap_dss_device *dssdev)
++{
++      if (!dssdev->driver->set_rotate || !dssdev->driver->get_rotate)
++              return 0;
++
++      return dssdev->driver->get_rotate(dssdev);
++}
++
++static int dsi_display_set_mirror(struct omap_dss_device *dssdev, bool mirror)
++{
++      DSSDBGF("%d", mirror);
++
++      if (!dssdev->driver->set_mirror || !dssdev->driver->get_mirror)
++              return -EINVAL;
++
++      dsi_bus_lock();
++      dssdev->driver->set_mirror(dssdev, mirror);
++      dsi_bus_unlock();
++
++      return 0;
++}
++
++static bool dsi_display_get_mirror(struct omap_dss_device *dssdev)
++{
++      if (!dssdev->driver->set_mirror || !dssdev->driver->get_mirror)
++              return 0;
++
++      return dssdev->driver->get_mirror(dssdev);
++}
++
++static int dsi_display_run_test(struct omap_dss_device *dssdev, int test_num)
++{
++      int r;
++
++      if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
++              return -EIO;
++
++      DSSDBGF("%d", test_num);
++
++      dsi_bus_lock();
++
++      /* run test first in low speed mode */
++      dsi_vc_enable_hs(0, 0);
++
++      if (dssdev->driver->run_test) {
++              r = dssdev->driver->run_test(dssdev, test_num);
++              if (r)
++                      goto end;
++      }
++
++      /* then in high speed */
++      dsi_vc_enable_hs(0, 1);
++
++      if (dssdev->driver->run_test) {
++              r = dssdev->driver->run_test(dssdev, test_num);
++              if (r)
++                      goto end;
++      }
++
++end:
++      dsi_vc_enable_hs(0, 1);
++
++      dsi_bus_unlock();
++
++      return r;
++}
++
++static int dsi_display_memory_read(struct omap_dss_device *dssdev,
++              void *buf, size_t size,
++              u16 x, u16 y, u16 w, u16 h)
++{
++      int r;
++
++      DSSDBGF("");
++
++      if (!dssdev->driver->memory_read)
++              return -EINVAL;
++
++      if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
++              return -EIO;
++
++      dsi_bus_lock();
++
++      r = dssdev->driver->memory_read(dssdev, buf, size,
++                      x, y, w, h);
++
++      dsi_bus_unlock();
++
++      return r;
++}
++
++void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
++              u32 fifo_size, enum omap_burst_size *burst_size,
++              u32 *fifo_low, u32 *fifo_high)
++{
++      unsigned burst_size_bytes;
++
++      *burst_size = OMAP_DSS_BURST_16x32;
++      burst_size_bytes = 16 * 32 / 8;
++
++      *fifo_high = fifo_size - burst_size_bytes;
++      *fifo_low = 0;
++}
++
++int dsi_init_display(struct omap_dss_device *dssdev)
++{
++      DSSDBG("DSI init\n");
++
++      dssdev->enable = dsi_display_enable;
++      dssdev->disable = dsi_display_disable;
++      dssdev->suspend = dsi_display_suspend;
++      dssdev->resume = dsi_display_resume;
++      dssdev->update = dsi_display_update;
++      dssdev->sync = dsi_display_sync;
++      dssdev->set_update_mode = dsi_display_set_update_mode;
++      dssdev->get_update_mode = dsi_display_get_update_mode;
++      dssdev->enable_te = dsi_display_enable_te;
++      dssdev->get_te = dsi_display_get_te;
++
++      dssdev->get_rotate = dsi_display_get_rotate;
++      dssdev->set_rotate = dsi_display_set_rotate;
++
++      dssdev->get_mirror = dsi_display_get_mirror;
++      dssdev->set_mirror = dsi_display_set_mirror;
++
++      dssdev->run_test = dsi_display_run_test;
++      dssdev->memory_read = dsi_display_memory_read;
++
++      dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
++
++      dsi.vc[0].dssdev = dssdev;
++      dsi.vc[1].dssdev = dssdev;
++
++      return 0;
++}
++
++int dsi_init(struct platform_device *pdev)
++{
++      u32 rev;
++      struct sched_param param = {
++              .sched_priority = MAX_USER_RT_PRIO-1
++      };
++
++      spin_lock_init(&dsi.errors_lock);
++      dsi.errors = 0;
++
++      /* XXX fail properly */
++
++      init_completion(&dsi.bta_completion);
++      init_completion(&dsi.update_completion);
++
++      dsi.thread = kthread_create(dsi_update_thread, NULL, "dsi");
++      if (IS_ERR(dsi.thread)) {
++              DSSERR("cannot create kthread\n");
++              return PTR_ERR(dsi.thread);
++      }
++      sched_setscheduler(dsi.thread, SCHED_FIFO, &param);
++
++      init_waitqueue_head(&dsi.waitqueue);
++      spin_lock_init(&dsi.update_lock);
++
++      mutex_init(&dsi.lock);
++      mutex_init(&dsi.bus_lock);
++
++      dsi.update_mode = OMAP_DSS_UPDATE_DISABLED;
++      dsi.user_update_mode = OMAP_DSS_UPDATE_DISABLED;
++
++      dsi.base = ioremap(DSI_BASE, DSI_SZ_REGS);
++      if (!dsi.base) {
++              DSSERR("can't ioremap DSI\n");
++              return -ENOMEM;
++      }
++
++      dsi.vdds_dsi_reg = regulator_get(&pdev->dev, "vdds_dsi");
++      if (IS_ERR(dsi.vdds_dsi_reg)) {
++              iounmap(dsi.base);
++              DSSERR("can't get VDDS_DSI regulator\n");
++              return PTR_ERR(dsi.vdds_dsi_reg);
++      }
++
++      enable_clocks(1);
++
++      rev = dsi_read_reg(DSI_REVISION);
++      printk(KERN_INFO "OMAP DSI rev %d.%d\n",
++             FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
++
++      enable_clocks(0);
++
++      wake_up_process(dsi.thread);
++
++      return 0;
++}
++
++void dsi_exit(void)
++{
++      kthread_stop(dsi.thread);
++
++      regulator_put(dsi.vdds_dsi_reg);
++
++      iounmap(dsi.base);
++
++      DSSDBG("omap_dsi_exit\n");
++}
++
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-2.6.31/dss2/0015-OMAP-DSS2-omapfb-driver.patch b/recipes/linux/linux-omap-2.6.31/dss2/0015-OMAP-DSS2-omapfb-driver.patch
new file mode 100644 (file)
index 0000000..a3ccb74
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.31/dss2/0015-OMAP-DSS2-omapfb-driver.patch
@@ -0,0 +1,3801 @@
+From 13656d59fba28e21311ae0478b6c222339367e72 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Tue, 4 Aug 2009 16:12:50 +0300
+Subject: [PATCH 15/18] OMAP: DSS2: omapfb driver
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ arch/arm/plat-omap/fb.c                   |   39 +-
+ drivers/video/omap/Kconfig                |    5 +-
+ drivers/video/omap2/Kconfig               |    1 +
+ drivers/video/omap2/Makefile              |    1 +
+ drivers/video/omap2/omapfb/Kconfig        |   37 +
+ drivers/video/omap2/omapfb/Makefile       |    2 +
+ drivers/video/omap2/omapfb/omapfb-ioctl.c |  727 ++++++++++
+ drivers/video/omap2/omapfb/omapfb-main.c  | 2137 +++++++++++++++++++++++++++++
+ drivers/video/omap2/omapfb/omapfb-sysfs.c |  507 +++++++
+ drivers/video/omap2/omapfb/omapfb.h       |  146 ++
+ include/linux/omapfb.h                    |   45 +
+ 11 files changed, 3644 insertions(+), 3 deletions(-)
+ create mode 100644 drivers/video/omap2/omapfb/Kconfig
+ create mode 100644 drivers/video/omap2/omapfb/Makefile
+ create mode 100644 drivers/video/omap2/omapfb/omapfb-ioctl.c
+ create mode 100644 drivers/video/omap2/omapfb/omapfb-main.c
+ create mode 100644 drivers/video/omap2/omapfb/omapfb-sysfs.c
+ create mode 100644 drivers/video/omap2/omapfb/omapfb.h
+
+diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
+index 40615a6..70fbeae 100644
+--- a/arch/arm/plat-omap/fb.c
++++ b/arch/arm/plat-omap/fb.c
+@@ -327,7 +327,33 @@ static inline int omap_init_fb(void)
+ 
+ arch_initcall(omap_init_fb);
+ 
+-#else
++#elif defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
++
++static u64 omap_fb_dma_mask = ~(u32)0;
++static struct omapfb_platform_data omapfb_config;
++
++static struct platform_device omap_fb_device = {
++      .name           = "omapfb",
++      .id             = -1,
++      .dev = {
++              .dma_mask               = &omap_fb_dma_mask,
++              .coherent_dma_mask      = ~(u32)0,
++              .platform_data          = &omapfb_config,
++      },
++      .num_resources = 0,
++};
++
++void omapfb_set_platform_data(struct omapfb_platform_data *data)
++{
++      omapfb_config = *data;
++}
++
++static inline int omap_init_fb(void)
++{
++      return platform_device_register(&omap_fb_device);
++}
++
++arch_initcall(omap_init_fb);
+ 
+ void omapfb_reserve_sdram(void) {}
+ unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
+@@ -339,5 +365,16 @@ unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
+       return 0;
+ }
+ 
++#else
++
++void omapfb_reserve_sdram(void) {}
++unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
++                                unsigned long sram_vstart,
++                                unsigned long sram_size,
++                                unsigned long start_avail,
++                                unsigned long size_avail)
++{
++      return 0;
++}
+ 
+ #endif
+diff --git a/drivers/video/omap/Kconfig b/drivers/video/omap/Kconfig
+index 4440885..0c8f3a5 100644
+--- a/drivers/video/omap/Kconfig
++++ b/drivers/video/omap/Kconfig
+@@ -1,6 +1,7 @@
+ config FB_OMAP
+       tristate "OMAP frame buffer support (EXPERIMENTAL)"
+-      depends on FB && ARCH_OMAP
++      depends on FB && ARCH_OMAP && (OMAP2_DSS = "n")
++
+       select FB_CFB_FILLRECT
+       select FB_CFB_COPYAREA
+       select FB_CFB_IMAGEBLIT
+@@ -9,7 +10,7 @@ config FB_OMAP
+ 
+ config FB_OMAP_BOOTLOADER_INIT
+       bool "Check bootloader initialization"
+-      depends on FB_OMAP
++      depends on FB_OMAP || FB_OMAP2
+       help
+         Say Y here if you want to enable checking if the bootloader has
+         already initialized the display controller. In this case the
+diff --git a/drivers/video/omap2/Kconfig b/drivers/video/omap2/Kconfig
+index 55b4c42..3e60d7e 100644
+--- a/drivers/video/omap2/Kconfig
++++ b/drivers/video/omap2/Kconfig
+@@ -5,3 +5,4 @@ config OMAP2_VRFB
+       bool
+ 
+ source "drivers/video/omap2/dss/Kconfig"
++source "drivers/video/omap2/omapfb/Kconfig"
+diff --git a/drivers/video/omap2/Makefile b/drivers/video/omap2/Makefile
+index ee0644f..3ba6ef5 100644
+--- a/drivers/video/omap2/Makefile
++++ b/drivers/video/omap2/Makefile
+@@ -2,3 +2,4 @@ obj-$(CONFIG_OMAP2_VRAM) += vram.o
+ obj-$(CONFIG_OMAP2_VRFB) += vrfb.o
+ 
+ obj-y += dss/
++obj-y += omapfb/
+diff --git a/drivers/video/omap2/omapfb/Kconfig b/drivers/video/omap2/omapfb/Kconfig
+new file mode 100644
+index 0000000..bb694cc
+--- /dev/null
++++ b/drivers/video/omap2/omapfb/Kconfig
+@@ -0,0 +1,37 @@
++menuconfig FB_OMAP2
++        tristate "OMAP2/3 frame buffer support (EXPERIMENTAL)"
++        depends on FB && OMAP2_DSS
++
++      select OMAP2_VRAM
++      select OMAP2_VRFB
++        select FB_CFB_FILLRECT
++        select FB_CFB_COPYAREA
++        select FB_CFB_IMAGEBLIT
++        help
++          Frame buffer driver for OMAP2/3 based boards.
++
++config FB_OMAP2_DEBUG_SUPPORT
++      bool "Debug support for OMAP2/3 FB"
++      default y
++      depends on FB_OMAP2
++      help
++        Support for debug output. You have to enable the actual printing
++        with debug module parameter.
++
++config FB_OMAP2_FORCE_AUTO_UPDATE
++      bool "Force main display to automatic update mode"
++      depends on FB_OMAP2
++      help
++        Forces main display to automatic update mode (if possible),
++        and also enables tearsync (if possible). By default
++        displays that support manual update are started in manual
++        update mode.
++
++config FB_OMAP2_NUM_FBS
++      int "Number of framebuffers"
++      range 1 10
++      default 3
++      depends on FB_OMAP2
++      help
++        Select the number of framebuffers created. OMAP2/3 has 3 overlays
++        so normally this would be 3.
+diff --git a/drivers/video/omap2/omapfb/Makefile b/drivers/video/omap2/omapfb/Makefile
+new file mode 100644
+index 0000000..51c2e00
+--- /dev/null
++++ b/drivers/video/omap2/omapfb/Makefile
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_FB_OMAP2) += omapfb.o
++omapfb-y := omapfb-main.o omapfb-sysfs.o omapfb-ioctl.o
+diff --git a/drivers/video/omap2/omapfb/omapfb-ioctl.c b/drivers/video/omap2/omapfb/omapfb-ioctl.c
+new file mode 100644
+index 0000000..70fb64e
+--- /dev/null
++++ b/drivers/video/omap2/omapfb/omapfb-ioctl.c
+@@ -0,0 +1,727 @@
++/*
++ * linux/drivers/video/omap2/omapfb-ioctl.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/fb.h>
++#include <linux/device.h>
++#include <linux/uaccess.h>
++#include <linux/platform_device.h>
++#include <linux/mm.h>
++#include <linux/omapfb.h>
++#include <linux/vmalloc.h>
++
++#include <mach/display.h>
++#include <mach/vrfb.h>
++#include <mach/vram.h>
++
++#include "omapfb.h"
++
++static int omapfb_setup_plane(struct fb_info *fbi, struct omapfb_plane_info *pi)
++{
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      struct omapfb2_device *fbdev = ofbi->fbdev;
++      struct omap_dss_device *display = fb2display(fbi);
++      struct omap_overlay *ovl;
++      struct omap_overlay_info info;
++      int r = 0;
++
++      DBG("omapfb_setup_plane\n");
++
++      if (ofbi->num_overlays != 1) {
++              r = -EINVAL;
++              goto out;
++      }
++
++      /* XXX uses only the first overlay */
++      ovl = ofbi->overlays[0];
++
++      if (pi->enabled && !ofbi->region.size) {
++              /*
++               * This plane's memory was freed, can't enable it
++               * until it's reallocated.
++               */
++              r = -EINVAL;
++              goto out;
++      }
++
++      ovl->get_overlay_info(ovl, &info);
++
++      info.pos_x = pi->pos_x;
++      info.pos_y = pi->pos_y;
++      info.out_width = pi->out_width;
++      info.out_height = pi->out_height;
++      info.enabled = pi->enabled;
++
++      r = ovl->set_overlay_info(ovl, &info);
++      if (r)
++              goto out;
++
++      if (ovl->manager) {
++              r = ovl->manager->apply(ovl->manager);
++              if (r)
++                      goto out;
++      }
++
++      if (display) {
++              u16 w, h;
++
++              if (display->sync)
++                      display->sync(display);
++
++              display->get_resolution(display, &w, &h);
++
++              if (display->update)
++                      display->update(display, 0, 0, w, h);
++      }
++
++out:
++      if (r)
++              dev_err(fbdev->dev, "setup_plane failed\n");
++      return r;
++}
++
++static int omapfb_query_plane(struct fb_info *fbi, struct omapfb_plane_info *pi)
++{
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++
++      if (ofbi->num_overlays != 1) {
++              memset(pi, 0, sizeof(*pi));
++      } else {
++              struct omap_overlay_info *ovli;
++              struct omap_overlay *ovl;
++
++              ovl = ofbi->overlays[0];
++              ovli = &ovl->info;
++
++              pi->pos_x = ovli->pos_x;
++              pi->pos_y = ovli->pos_y;
++              pi->enabled = ovli->enabled;
++              pi->channel_out = 0; /* xxx */
++              pi->mirror = 0;
++              pi->out_width = ovli->out_width;
++              pi->out_height = ovli->out_height;
++      }
++
++      return 0;
++}
++
++static int omapfb_setup_mem(struct fb_info *fbi, struct omapfb_mem_info *mi)
++{
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      struct omapfb2_device *fbdev = ofbi->fbdev;
++      struct omapfb2_mem_region *rg;
++      int r, i;
++      size_t size;
++
++      if (mi->type > OMAPFB_MEMTYPE_MAX)
++              return -EINVAL;
++
++      size = PAGE_ALIGN(mi->size);
++
++      rg = &ofbi->region;
++
++      for (i = 0; i < ofbi->num_overlays; i++) {
++              if (ofbi->overlays[i]->info.enabled)
++                      return -EBUSY;
++      }
++
++      if (rg->size != size || rg->type != mi->type) {
++              r = omapfb_realloc_fbmem(fbi, size, mi->type);
++              if (r) {
++                      dev_err(fbdev->dev, "realloc fbmem failed\n");
++                      return r;
++              }
++      }
++
++      return 0;
++}
++
++static int omapfb_query_mem(struct fb_info *fbi, struct omapfb_mem_info *mi)
++{
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      struct omapfb2_mem_region *rg;
++
++      rg = &ofbi->region;
++      memset(mi, 0, sizeof(*mi));
++
++      mi->size = rg->size;
++      mi->type = rg->type;
++
++      return 0;
++}
++
++static int omapfb_update_window(struct fb_info *fbi,
++              u32 x, u32 y, u32 w, u32 h)
++{
++      struct omap_dss_device *display = fb2display(fbi);
++      u16 dw, dh;
++
++      if (!display)
++              return 0;
++
++      if (w == 0 || h == 0)
++              return 0;
++
++      display->get_resolution(display, &dw, &dh);
++
++      if (x + w > dw || y + h > dh)
++              return -EINVAL;
++
++      display->update(display, x, y, w, h);
++
++      return 0;
++}
++
++static int omapfb_set_update_mode(struct fb_info *fbi,
++                                 enum omapfb_update_mode mode)
++{
++      struct omap_dss_device *display = fb2display(fbi);
++      enum omap_dss_update_mode um;
++      int r;
++
++      if (!display || !display->set_update_mode)
++              return -EINVAL;
++
++      switch (mode) {
++      case OMAPFB_UPDATE_DISABLED:
++              um = OMAP_DSS_UPDATE_DISABLED;
++              break;
++
++      case OMAPFB_AUTO_UPDATE:
++              um = OMAP_DSS_UPDATE_AUTO;
++              break;
++
++      case OMAPFB_MANUAL_UPDATE:
++              um = OMAP_DSS_UPDATE_MANUAL;
++              break;
++
++      default:
++              return -EINVAL;
++      }
++
++      r = display->set_update_mode(display, um);
++
++      return r;
++}
++
++static int omapfb_get_update_mode(struct fb_info *fbi,
++              enum omapfb_update_mode *mode)
++{
++      struct omap_dss_device *display = fb2display(fbi);
++      enum omap_dss_update_mode m;
++
++      if (!display || !display->get_update_mode)
++              return -EINVAL;
++
++      m = display->get_update_mode(display);
++
++      switch (m) {
++      case OMAP_DSS_UPDATE_DISABLED:
++              *mode = OMAPFB_UPDATE_DISABLED;
++              break;
++      case OMAP_DSS_UPDATE_AUTO:
++              *mode = OMAPFB_AUTO_UPDATE;
++              break;
++      case OMAP_DSS_UPDATE_MANUAL:
++              *mode = OMAPFB_MANUAL_UPDATE;
++              break;
++      default:
++              BUG();
++      }
++
++      return 0;
++}
++
++/* XXX this color key handling is a hack... */
++static struct omapfb_color_key omapfb_color_keys[2];
++
++static int _omapfb_set_color_key(struct omap_overlay_manager *mgr,
++              struct omapfb_color_key *ck)
++{
++      struct omap_overlay_manager_info info;
++      enum omap_dss_trans_key_type kt;
++      int r;
++
++      mgr->get_manager_info(mgr, &info);
++
++      if (ck->key_type == OMAPFB_COLOR_KEY_DISABLED) {
++              info.trans_enabled = false;
++              omapfb_color_keys[mgr->id] = *ck;
++
++              r = mgr->set_manager_info(mgr, &info);
++              if (r)
++                      return r;
++
++              r = mgr->apply(mgr);
++
++              return r;
++      }
++
++      switch (ck->key_type) {
++      case OMAPFB_COLOR_KEY_GFX_DST:
++              kt = OMAP_DSS_COLOR_KEY_GFX_DST;
++              break;
++      case OMAPFB_COLOR_KEY_VID_SRC:
++              kt = OMAP_DSS_COLOR_KEY_VID_SRC;
++              break;
++      default:
++              return -EINVAL;
++      }
++
++      info.default_color = ck->background;
++      info.trans_key = ck->trans_key;
++      info.trans_key_type = kt;
++      info.trans_enabled = true;
++
++      omapfb_color_keys[mgr->id] = *ck;
++
++      r = mgr->set_manager_info(mgr, &info);
++      if (r)
++              return r;
++
++      r = mgr->apply(mgr);
++
++      return r;
++}
++
++static int omapfb_set_color_key(struct fb_info *fbi,
++              struct omapfb_color_key *ck)
++{
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      struct omapfb2_device *fbdev = ofbi->fbdev;
++      int r;
++      int i;
++      struct omap_overlay_manager *mgr = NULL;
++
++      omapfb_lock(fbdev);
++
++      for (i = 0; i < ofbi->num_overlays; i++) {
++              if (ofbi->overlays[i]->manager) {
++                      mgr = ofbi->overlays[i]->manager;
++                      break;
++              }
++      }
++
++      if (!mgr) {
++              r = -EINVAL;
++              goto err;
++      }
++
++      r = _omapfb_set_color_key(mgr, ck);
++err:
++      omapfb_unlock(fbdev);
++
++      return r;
++}
++
++static int omapfb_get_color_key(struct fb_info *fbi,
++              struct omapfb_color_key *ck)
++{
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      struct omapfb2_device *fbdev = ofbi->fbdev;
++      struct omap_overlay_manager *mgr = NULL;
++      int r = 0;
++      int i;
++
++      omapfb_lock(fbdev);
++
++      for (i = 0; i < ofbi->num_overlays; i++) {
++              if (ofbi->overlays[i]->manager) {
++                      mgr = ofbi->overlays[i]->manager;
++                      break;
++              }
++      }
++
++      if (!mgr) {
++              r = -EINVAL;
++              goto err;
++      }
++
++      *ck = omapfb_color_keys[mgr->id];
++err:
++      omapfb_unlock(fbdev);
++
++      return r;
++}
++
++static int omapfb_memory_read(struct fb_info *fbi,
++              struct omapfb_memory_read *mr)
++{
++      struct omap_dss_device *display = fb2display(fbi);
++      void *buf;
++      int r;
++
++      if (!display || !display->memory_read)
++              return -ENOENT;
++
++      if (!access_ok(VERIFY_WRITE, mr->buffer, mr->buffer_size))
++              return -EFAULT;
++
++      if (mr->w * mr->h * 3 > mr->buffer_size)
++              return -EINVAL;
++
++      buf = vmalloc(mr->buffer_size);
++      if (!buf) {
++              DBG("vmalloc failed\n");
++              return -ENOMEM;
++      }
++
++      r = display->memory_read(display, buf, mr->buffer_size,
++                      mr->x, mr->y, mr->w, mr->h);
++
++      if (r > 0) {
++              if (copy_to_user(mr->buffer, buf, mr->buffer_size))
++                      r = -EFAULT;
++      }
++
++      vfree(buf);
++
++      return r;
++}
++
++static int omapfb_get_ovl_colormode(struct omapfb2_device *fbdev,
++                           struct omapfb_ovl_colormode *mode)
++{
++      int ovl_idx = mode->overlay_idx;
++      int mode_idx = mode->mode_idx;
++      struct omap_overlay *ovl;
++      enum omap_color_mode supported_modes;
++      struct fb_var_screeninfo var;
++      int i;
++
++      if (ovl_idx >= fbdev->num_overlays)
++              return -ENODEV;
++      ovl = fbdev->overlays[ovl_idx];
++      supported_modes = ovl->supported_modes;
++
++      mode_idx = mode->mode_idx;
++
++      for (i = 0; i < sizeof(supported_modes) * 8; i++) {
++              if (!(supported_modes & (1 << i)))
++                      continue;
++              /*
++               * It's possible that the FB doesn't support a mode
++               * that is supported by the overlay, so call the
++               * following here.
++               */
++              if (dss_mode_to_fb_mode(1 << i, &var) < 0)
++                      continue;
++
++              mode_idx--;
++              if (mode_idx < 0)
++                      break;
++      }
++
++      if (i == sizeof(supported_modes) * 8)
++              return -ENOENT;
++
++      mode->bits_per_pixel = var.bits_per_pixel;
++      mode->nonstd = var.nonstd;
++      mode->red = var.red;
++      mode->green = var.green;
++      mode->blue = var.blue;
++      mode->transp = var.transp;
++
++      return 0;
++}
++
++static int omapfb_wait_for_go(struct fb_info *fbi)
++{
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      int r = 0;
++      int i;
++
++      for (i = 0; i < ofbi->num_overlays; ++i) {
++              struct omap_overlay *ovl = ofbi->overlays[i];
++              r = ovl->wait_for_go(ovl);
++              if (r)
++                      break;
++      }
++
++      return r;
++}
++
++int omapfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg)
++{
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      struct omapfb2_device *fbdev = ofbi->fbdev;
++      struct omap_dss_device *display = fb2display(fbi);
++
++      union {
++              struct omapfb_update_window_old uwnd_o;
++              struct omapfb_update_window     uwnd;
++              struct omapfb_plane_info        plane_info;
++              struct omapfb_caps              caps;
++              struct omapfb_mem_info          mem_info;
++              struct omapfb_color_key         color_key;
++              struct omapfb_ovl_colormode     ovl_colormode;
++              enum omapfb_update_mode         update_mode;
++              int test_num;
++              struct omapfb_memory_read       memory_read;
++              struct omapfb_vram_info         vram_info;
++      } p;
++
++      int r = 0;
++
++      switch (cmd) {
++      case OMAPFB_SYNC_GFX:
++              DBG("ioctl SYNC_GFX\n");
++              if (!display || !display->sync) {
++                      /* DSS1 never returns an error here, so we neither */
++                      /*r = -EINVAL;*/
++                      break;
++              }
++
++              r = display->sync(display);
++              break;
++
++      case OMAPFB_UPDATE_WINDOW_OLD:
++              DBG("ioctl UPDATE_WINDOW_OLD\n");
++              if (!display || !display->update) {
++                      r = -EINVAL;
++                      break;
++              }
++
++              if (copy_from_user(&p.uwnd_o,
++                                      (void __user *)arg,
++                                      sizeof(p.uwnd_o))) {
++                      r = -EFAULT;
++                      break;
++              }
++
++              r = omapfb_update_window(fbi, p.uwnd_o.x, p.uwnd_o.y,
++                              p.uwnd_o.width, p.uwnd_o.height);
++              break;
++
++      case OMAPFB_UPDATE_WINDOW:
++              DBG("ioctl UPDATE_WINDOW\n");
++              if (!display || !display->update) {
++                      r = -EINVAL;
++                      break;
++              }
++
++              if (copy_from_user(&p.uwnd, (void __user *)arg,
++                                      sizeof(p.uwnd))) {
++                      r = -EFAULT;
++                      break;
++              }
++
++              r = omapfb_update_window(fbi, p.uwnd.x, p.uwnd.y,
++                              p.uwnd.width, p.uwnd.height);
++              break;
++
++      case OMAPFB_SETUP_PLANE:
++              DBG("ioctl SETUP_PLANE\n");
++              if (copy_from_user(&p.plane_info, (void __user *)arg,
++                                      sizeof(p.plane_info)))
++                      r = -EFAULT;
++              else
++                      r = omapfb_setup_plane(fbi, &p.plane_info);
++              break;
++
++      case OMAPFB_QUERY_PLANE:
++              DBG("ioctl QUERY_PLANE\n");
++              r = omapfb_query_plane(fbi, &p.plane_info);
++              if (r < 0)
++                      break;
++              if (copy_to_user((void __user *)arg, &p.plane_info,
++                                      sizeof(p.plane_info)))
++                      r = -EFAULT;
++              break;
++
++      case OMAPFB_SETUP_MEM:
++              DBG("ioctl SETUP_MEM\n");
++              if (copy_from_user(&p.mem_info, (void __user *)arg,
++                                      sizeof(p.mem_info)))
++                      r = -EFAULT;
++              else
++                      r = omapfb_setup_mem(fbi, &p.mem_info);
++              break;
++
++      case OMAPFB_QUERY_MEM:
++              DBG("ioctl QUERY_MEM\n");
++              r = omapfb_query_mem(fbi, &p.mem_info);
++              if (r < 0)
++                      break;
++              if (copy_to_user((void __user *)arg, &p.mem_info,
++                                      sizeof(p.mem_info)))
++                      r = -EFAULT;
++              break;
++
++      case OMAPFB_GET_CAPS:
++              DBG("ioctl GET_CAPS\n");
++              if (!display) {
++                      r = -EINVAL;
++                      break;
++              }
++
++              memset(&p.caps, 0, sizeof(p.caps));
++              p.caps.ctrl = display->caps;
++
++              if (copy_to_user((void __user *)arg, &p.caps, sizeof(p.caps)))
++                      r = -EFAULT;
++              break;
++
++      case OMAPFB_GET_OVERLAY_COLORMODE:
++              DBG("ioctl GET_OVERLAY_COLORMODE\n");
++              if (copy_from_user(&p.ovl_colormode, (void __user *)arg,
++                                 sizeof(p.ovl_colormode))) {
++                      r = -EFAULT;
++                      break;
++              }
++              r = omapfb_get_ovl_colormode(fbdev, &p.ovl_colormode);
++              if (r < 0)
++                      break;
++              if (copy_to_user((void __user *)arg, &p.ovl_colormode,
++                               sizeof(p.ovl_colormode)))
++                      r = -EFAULT;
++              break;
++
++      case OMAPFB_SET_UPDATE_MODE:
++              DBG("ioctl SET_UPDATE_MODE\n");
++              if (get_user(p.update_mode, (int __user *)arg))
++                      r = -EFAULT;
++              else
++                      r = omapfb_set_update_mode(fbi, p.update_mode);
++              break;
++
++      case OMAPFB_GET_UPDATE_MODE:
++              DBG("ioctl GET_UPDATE_MODE\n");
++              r = omapfb_get_update_mode(fbi, &p.update_mode);
++              if (r)
++                      break;
++              if (put_user(p.update_mode,
++                                      (enum omapfb_update_mode __user *)arg))
++                      r = -EFAULT;
++              break;
++
++      case OMAPFB_SET_COLOR_KEY:
++              DBG("ioctl SET_COLOR_KEY\n");
++              if (copy_from_user(&p.color_key, (void __user *)arg,
++                                 sizeof(p.color_key)))
++                      r = -EFAULT;
++              else
++                      r = omapfb_set_color_key(fbi, &p.color_key);
++              break;
++
++      case OMAPFB_GET_COLOR_KEY:
++              DBG("ioctl GET_COLOR_KEY\n");
++              r = omapfb_get_color_key(fbi, &p.color_key);
++              if (r)
++                      break;
++              if (copy_to_user((void __user *)arg, &p.color_key,
++                               sizeof(p.color_key)))
++                      r = -EFAULT;
++              break;
++
++      case OMAPFB_WAITFORVSYNC:
++              DBG("ioctl WAITFORVSYNC\n");
++              if (!display) {
++                      r = -EINVAL;
++                      break;
++              }
++
++              r = display->wait_vsync(display);
++              break;
++
++      case OMAPFB_WAITFORGO:
++              DBG("ioctl WAITFORGO\n");
++              if (!display) {
++                      r = -EINVAL;
++                      break;
++              }
++
++              r = omapfb_wait_for_go(fbi);
++              break;
++
++      /* LCD and CTRL tests do the same thing for backward
++       * compatibility */
++      case OMAPFB_LCD_TEST:
++              DBG("ioctl LCD_TEST\n");
++              if (get_user(p.test_num, (int __user *)arg)) {
++                      r = -EFAULT;
++                      break;
++              }
++              if (!display || !display->run_test) {
++                      r = -EINVAL;
++                      break;
++              }
++
++              r = display->run_test(display, p.test_num);
++
++              break;
++
++      case OMAPFB_CTRL_TEST:
++              DBG("ioctl CTRL_TEST\n");
++              if (get_user(p.test_num, (int __user *)arg)) {
++                      r = -EFAULT;
++                      break;
++              }
++              if (!display || !display->run_test) {
++                      r = -EINVAL;
++                      break;
++              }
++
++              r = display->run_test(display, p.test_num);
++
++              break;
++
++      case OMAPFB_MEMORY_READ:
++              DBG("ioctl MEMORY_READ\n");
++
++              if (copy_from_user(&p.memory_read, (void __user *)arg,
++                                      sizeof(p.memory_read))) {
++                      r = -EFAULT;
++                      break;
++              }
++
++              r = omapfb_memory_read(fbi, &p.memory_read);
++
++              break;
++
++      case OMAPFB_GET_VRAM_INFO: {
++              unsigned long vram, free, largest;
++
++              DBG("ioctl GET_VRAM_INFO\n");
++
++              omap_vram_get_info(&vram, &free, &largest);
++              p.vram_info.total = vram;
++              p.vram_info.free = free;
++              p.vram_info.largest_free_block = largest;
++
++              if (copy_to_user((void __user *)arg, &p.vram_info,
++                                      sizeof(p.vram_info)))
++                      r = -EFAULT;
++              break;
++      }
++
++      default:
++              dev_err(fbdev->dev, "Unknown ioctl 0x%x\n", cmd);
++              r = -EINVAL;
++      }
++
++      if (r < 0)
++              DBG("ioctl failed: %d\n", r);
++
++      return r;
++}
++
++
+diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
+new file mode 100644
+index 0000000..7f5ec3b
+--- /dev/null
++++ b/drivers/video/omap2/omapfb/omapfb-main.c
+@@ -0,0 +1,2137 @@
++/*
++ * linux/drivers/video/omap2/omapfb-main.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/fb.h>
++#include <linux/dma-mapping.h>
++#include <linux/vmalloc.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/omapfb.h>
++
++#include <mach/display.h>
++#include <mach/vram.h>
++#include <mach/vrfb.h>
++
++#include "omapfb.h"
++
++#define MODULE_NAME     "omapfb"
++
++#define OMAPFB_PLANE_XRES_MIN         8
++#define OMAPFB_PLANE_YRES_MIN         8
++
++static char *def_mode;
++static char *def_vram;
++static int def_vrfb;
++static int def_rotate;
++static int def_mirror;
++
++#ifdef DEBUG
++unsigned int omapfb_debug;
++module_param_named(debug, omapfb_debug, bool, 0644);
++static unsigned int omapfb_test_pattern;
++module_param_named(test, omapfb_test_pattern, bool, 0644);
++#endif
++
++static int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi);
++
++#ifdef DEBUG
++static void draw_pixel(struct fb_info *fbi, int x, int y, unsigned color)
++{
++      struct fb_var_screeninfo *var = &fbi->var;
++      struct fb_fix_screeninfo *fix = &fbi->fix;
++      void __iomem *addr = fbi->screen_base;
++      const unsigned bytespp = var->bits_per_pixel >> 3;
++      const unsigned line_len = fix->line_length / bytespp;
++
++      int r = (color >> 16) & 0xff;
++      int g = (color >> 8) & 0xff;
++      int b = (color >> 0) & 0xff;
++
++      if (var->bits_per_pixel == 16) {
++              u16 __iomem *p = (u16 __iomem *)addr;
++              p += y * line_len + x;
++
++              r = r * 32 / 256;
++              g = g * 64 / 256;
++              b = b * 32 / 256;
++
++              __raw_writew((r << 11) | (g << 5) | (b << 0), p);
++      } else if (var->bits_per_pixel == 24) {
++              u8 __iomem *p = (u8 __iomem *)addr;
++              p += (y * line_len + x) * 3;
++
++              __raw_writeb(b, p + 0);
++              __raw_writeb(g, p + 1);
++              __raw_writeb(r, p + 2);
++      } else if (var->bits_per_pixel == 32) {
++              u32 __iomem *p = (u32 __iomem *)addr;
++              p += y * line_len + x;
++              __raw_writel(color, p);
++      }
++}
++
++static void fill_fb(struct fb_info *fbi)
++{
++      struct fb_var_screeninfo *var = &fbi->var;
++      const short w = var->xres_virtual;
++      const short h = var->yres_virtual;
++      void __iomem *addr = fbi->screen_base;
++      int y, x;
++
++      if (!addr)
++              return;
++
++      DBG("fill_fb %dx%d, line_len %d bytes\n", w, h, fbi->fix.line_length);
++
++      for (y = 0; y < h; y++) {
++              for (x = 0; x < w; x++) {
++                      if (x < 20 && y < 20)
++                              draw_pixel(fbi, x, y, 0xffffff);
++                      else if (x < 20 && (y > 20 && y < h - 20))
++                              draw_pixel(fbi, x, y, 0xff);
++                      else if (y < 20 && (x > 20 && x < w - 20))
++                              draw_pixel(fbi, x, y, 0xff00);
++                      else if (x > w - 20 && (y > 20 && y < h - 20))
++                              draw_pixel(fbi, x, y, 0xff0000);
++                      else if (y > h - 20 && (x > 20 && x < w - 20))
++                              draw_pixel(fbi, x, y, 0xffff00);
++                      else if (x == 20 || x == w - 20 ||
++                                      y == 20 || y == h - 20)
++                              draw_pixel(fbi, x, y, 0xffffff);
++                      else if (x == y || w - x == h - y)
++                              draw_pixel(fbi, x, y, 0xff00ff);
++                      else if (w - x == y || x == h - y)
++                              draw_pixel(fbi, x, y, 0x00ffff);
++                      else if (x > 20 && y > 20 && x < w - 20 && y < h - 20) {
++                              int t = x * 3 / w;
++                              unsigned r = 0, g = 0, b = 0;
++                              unsigned c;
++                              if (var->bits_per_pixel == 16) {
++                                      if (t == 0)
++                                              b = (y % 32) * 256 / 32;
++                                      else if (t == 1)
++                                              g = (y % 64) * 256 / 64;
++                                      else if (t == 2)
++                                              r = (y % 32) * 256 / 32;
++                              } else {
++                                      if (t == 0)
++                                              b = (y % 256);
++                                      else if (t == 1)
++                                              g = (y % 256);
++                                      else if (t == 2)
++                                              r = (y % 256);
++                              }
++                              c = (r << 16) | (g << 8) | (b << 0);
++                              draw_pixel(fbi, x, y, c);
++                      } else {
++                              draw_pixel(fbi, x, y, 0);
++                      }
++              }
++      }
++}
++#endif
++
++static unsigned omapfb_get_vrfb_offset(struct omapfb_info *ofbi, int rot)
++{
++      struct vrfb *vrfb = &ofbi->region.vrfb;
++      unsigned offset;
++
++      switch (rot) {
++      case FB_ROTATE_UR:
++              offset = 0;
++              break;
++      case FB_ROTATE_CW:
++              offset = vrfb->yoffset;
++              break;
++      case FB_ROTATE_UD:
++              offset = vrfb->yoffset * OMAP_VRFB_LINE_LEN + vrfb->xoffset;
++              break;
++      case FB_ROTATE_CCW:
++              offset = vrfb->xoffset * OMAP_VRFB_LINE_LEN;
++              break;
++      default:
++              BUG();
++      }
++
++      offset *= vrfb->bytespp;
++
++      return offset;
++}
++
++static u32 omapfb_get_region_rot_paddr(struct omapfb_info *ofbi, int rot)
++{
++      if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
++              return ofbi->region.vrfb.paddr[rot]
++                      + omapfb_get_vrfb_offset(ofbi, rot);
++      } else {
++              return ofbi->region.paddr;
++      }
++}
++
++static u32 omapfb_get_region_paddr(struct omapfb_info *ofbi)
++{
++      if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
++              return ofbi->region.vrfb.paddr[0];
++      else
++              return ofbi->region.paddr;
++}
++
++static void __iomem *omapfb_get_region_vaddr(struct omapfb_info *ofbi)
++{
++      if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
++              return ofbi->region.vrfb.vaddr[0];
++      else
++              return ofbi->region.vaddr;
++}
++
++static struct omapfb_colormode omapfb_colormodes[] = {
++      {
++              .dssmode = OMAP_DSS_COLOR_UYVY,
++              .bits_per_pixel = 16,
++              .nonstd = OMAPFB_COLOR_YUV422,
++      }, {
++              .dssmode = OMAP_DSS_COLOR_YUV2,
++              .bits_per_pixel = 16,
++              .nonstd = OMAPFB_COLOR_YUY422,
++      }, {
++              .dssmode = OMAP_DSS_COLOR_ARGB16,
++              .bits_per_pixel = 16,
++              .red    = { .length = 4, .offset = 8, .msb_right = 0 },
++              .green  = { .length = 4, .offset = 4, .msb_right = 0 },
++              .blue   = { .length = 4, .offset = 0, .msb_right = 0 },
++              .transp = { .length = 4, .offset = 12, .msb_right = 0 },
++      }, {
++              .dssmode = OMAP_DSS_COLOR_RGB16,
++              .bits_per_pixel = 16,
++              .red    = { .length = 5, .offset = 11, .msb_right = 0 },
++              .green  = { .length = 6, .offset = 5, .msb_right = 0 },
++              .blue   = { .length = 5, .offset = 0, .msb_right = 0 },
++              .transp = { .length = 0, .offset = 0, .msb_right = 0 },
++      }, {
++              .dssmode = OMAP_DSS_COLOR_RGB24P,
++              .bits_per_pixel = 24,
++              .red    = { .length = 8, .offset = 16, .msb_right = 0 },
++              .green  = { .length = 8, .offset = 8, .msb_right = 0 },
++              .blue   = { .length = 8, .offset = 0, .msb_right = 0 },
++              .transp = { .length = 0, .offset = 0, .msb_right = 0 },
++      }, {
++              .dssmode = OMAP_DSS_COLOR_RGB24U,
++              .bits_per_pixel = 32,
++              .red    = { .length = 8, .offset = 16, .msb_right = 0 },
++              .green  = { .length = 8, .offset = 8, .msb_right = 0 },
++              .blue   = { .length = 8, .offset = 0, .msb_right = 0 },
++              .transp = { .length = 0, .offset = 0, .msb_right = 0 },
++      }, {
++              .dssmode = OMAP_DSS_COLOR_ARGB32,
++              .bits_per_pixel = 32,
++              .red    = { .length = 8, .offset = 16, .msb_right = 0 },
++              .green  = { .length = 8, .offset = 8, .msb_right = 0 },
++              .blue   = { .length = 8, .offset = 0, .msb_right = 0 },
++              .transp = { .length = 8, .offset = 24, .msb_right = 0 },
++      }, {
++              .dssmode = OMAP_DSS_COLOR_RGBA32,
++              .bits_per_pixel = 32,
++              .red    = { .length = 8, .offset = 24, .msb_right = 0 },
++              .green  = { .length = 8, .offset = 16, .msb_right = 0 },
++              .blue   = { .length = 8, .offset = 8, .msb_right = 0 },
++              .transp = { .length = 8, .offset = 0, .msb_right = 0 },
++      }, {
++              .dssmode = OMAP_DSS_COLOR_RGBX32,
++              .bits_per_pixel = 32,
++              .red    = { .length = 8, .offset = 24, .msb_right = 0 },
++              .green  = { .length = 8, .offset = 16, .msb_right = 0 },
++              .blue   = { .length = 8, .offset = 8, .msb_right = 0 },
++              .transp = { .length = 0, .offset = 0, .msb_right = 0 },
++      },
++};
++
++static bool cmp_var_to_colormode(struct fb_var_screeninfo *var,
++              struct omapfb_colormode *color)
++{
++      bool cmp_component(struct fb_bitfield *f1, struct fb_bitfield *f2)
++      {
++              return f1->length == f2->length &&
++                      f1->offset == f2->offset &&
++                      f1->msb_right == f2->msb_right;
++      }
++
++      if (var->bits_per_pixel == 0 ||
++                      var->red.length == 0 ||
++                      var->blue.length == 0 ||
++                      var->green.length == 0)
++              return 0;
++
++      return var->bits_per_pixel == color->bits_per_pixel &&
++              cmp_component(&var->red, &color->red) &&
++              cmp_component(&var->green, &color->green) &&
++              cmp_component(&var->blue, &color->blue) &&
++              cmp_component(&var->transp, &color->transp);
++}
++
++static void assign_colormode_to_var(struct fb_var_screeninfo *var,
++              struct omapfb_colormode *color)
++{
++      var->bits_per_pixel = color->bits_per_pixel;
++      var->nonstd = color->nonstd;
++      var->red = color->red;
++      var->green = color->green;
++      var->blue = color->blue;
++      var->transp = color->transp;
++}
++
++static enum omap_color_mode fb_mode_to_dss_mode(struct fb_var_screeninfo *var)
++{
++      enum omap_color_mode dssmode;
++      int i;
++
++      /* first match with nonstd field */
++      if (var->nonstd) {
++              for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) {
++                      struct omapfb_colormode *mode = &omapfb_colormodes[i];
++                      if (var->nonstd == mode->nonstd) {
++                              assign_colormode_to_var(var, mode);
++                              return mode->dssmode;
++                      }
++              }
++
++              return -EINVAL;
++      }
++
++      /* then try exact match of bpp and colors */
++      for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) {
++              struct omapfb_colormode *mode = &omapfb_colormodes[i];
++              if (cmp_var_to_colormode(var, mode)) {
++                      assign_colormode_to_var(var, mode);
++                      return mode->dssmode;
++              }
++      }
++
++      /* match with bpp if user has not filled color fields
++       * properly */
++      switch (var->bits_per_pixel) {
++      case 1:
++              dssmode = OMAP_DSS_COLOR_CLUT1;
++              break;
++      case 2:
++              dssmode = OMAP_DSS_COLOR_CLUT2;
++              break;
++      case 4:
++              dssmode = OMAP_DSS_COLOR_CLUT4;
++              break;
++      case 8:
++              dssmode = OMAP_DSS_COLOR_CLUT8;
++              break;
++      case 12:
++              dssmode = OMAP_DSS_COLOR_RGB12U;
++              break;
++      case 16:
++              dssmode = OMAP_DSS_COLOR_RGB16;
++              break;
++      case 24:
++              dssmode = OMAP_DSS_COLOR_RGB24P;
++              break;
++      case 32:
++              dssmode = OMAP_DSS_COLOR_RGB24U;
++              break;
++      default:
++              return -EINVAL;
++      }
++
++      for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) {
++              struct omapfb_colormode *mode = &omapfb_colormodes[i];
++              if (dssmode == mode->dssmode) {
++                      assign_colormode_to_var(var, mode);
++                      return mode->dssmode;
++              }
++      }
++
++      return -EINVAL;
++}
++
++int dss_mode_to_fb_mode(enum omap_color_mode dssmode,
++                      struct fb_var_screeninfo *var)
++{
++      int i;
++
++      for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) {
++              struct omapfb_colormode *mode = &omapfb_colormodes[i];
++              if (dssmode == mode->dssmode) {
++                      assign_colormode_to_var(var, mode);
++                      return 0;
++              }
++      }
++      return -ENOENT;
++}
++
++void set_fb_fix(struct fb_info *fbi)
++{
++      struct fb_fix_screeninfo *fix = &fbi->fix;
++      struct fb_var_screeninfo *var = &fbi->var;
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      struct omapfb2_mem_region *rg = &ofbi->region;
++
++      DBG("set_fb_fix\n");
++
++      /* used by open/write in fbmem.c */
++      fbi->screen_base = (char __iomem *)omapfb_get_region_vaddr(ofbi);
++
++      DBG("changing rotation to %d\n", var->rotate);
++
++      /* used by mmap in fbmem.c */
++      if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
++              switch (var->nonstd) {
++              case OMAPFB_COLOR_YUV422:
++              case OMAPFB_COLOR_YUY422:
++                      fix->line_length =
++                              (OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 2;
++                      break;
++              default:
++                      fix->line_length =
++                              (OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 3;
++                      break;
++              }
++      } else
++              fix->line_length =
++                      (var->xres_virtual * var->bits_per_pixel) >> 3;
++      fix->smem_start = omapfb_get_region_paddr(ofbi);
++      fix->smem_len = rg->size;
++
++      fix->type = FB_TYPE_PACKED_PIXELS;
++
++      if (var->nonstd)
++              fix->visual = FB_VISUAL_PSEUDOCOLOR;
++      else {
++              switch (var->bits_per_pixel) {
++              case 32:
++              case 24:
++              case 16:
++              case 12:
++                      fix->visual = FB_VISUAL_TRUECOLOR;
++                      /* 12bpp is stored in 16 bits */
++                      break;
++              case 1:
++              case 2:
++              case 4:
++              case 8:
++                      fix->visual = FB_VISUAL_PSEUDOCOLOR;
++                      break;
++              }
++      }
++
++      fix->accel = FB_ACCEL_NONE;
++
++      fix->xpanstep = 1;
++      fix->ypanstep = 1;
++
++      if (rg->size && ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
++              unsigned bytespp;
++              bool yuv_mode;
++              enum omap_color_mode mode;
++
++              mode = fb_mode_to_dss_mode(var);
++
++              bytespp = var->bits_per_pixel >> 3;
++
++              if (mode == OMAP_DSS_COLOR_YUV2 || mode == OMAP_DSS_COLOR_UYVY)
++                      yuv_mode = true;
++              else
++                      yuv_mode = false;
++
++              omap_vrfb_setup(&rg->vrfb, rg->paddr,
++                              var->xres_virtual,
++                              var->yres_virtual,
++                              bytespp, yuv_mode);
++      }
++}
++
++/* check new var and possibly modify it to be ok */
++int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var)
++{
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      struct omap_dss_device *display = fb2display(fbi);
++      unsigned long max_frame_size;
++      unsigned long line_size;
++      int xres_min, yres_min;
++      int xres_max, yres_max;
++      enum omap_color_mode mode = 0;
++      int i;
++      int bytespp;
++
++      DBG("check_fb_var %d\n", ofbi->id);
++
++      if (ofbi->region.size == 0)
++              return 0;
++
++      mode = fb_mode_to_dss_mode(var);
++      if (mode < 0) {
++              DBG("cannot convert var to omap dss mode\n");
++              return -EINVAL;
++      }
++
++      for (i = 0; i < ofbi->num_overlays; ++i) {
++              if ((ofbi->overlays[i]->supported_modes & mode) == 0) {
++                      DBG("invalid mode\n");
++                      return -EINVAL;
++              }
++      }
++
++      if (var->rotate < 0 || var->rotate > 3)
++              return -EINVAL;
++
++      xres_min = OMAPFB_PLANE_XRES_MIN;
++      xres_max = 2048;
++      yres_min = OMAPFB_PLANE_YRES_MIN;
++      yres_max = 2048;
++
++      bytespp = var->bits_per_pixel >> 3;
++
++      /* XXX: some applications seem to set virtual res to 0. */
++      if (var->xres_virtual == 0)
++              var->xres_virtual = var->xres;
++
++      if (var->yres_virtual == 0)
++              var->yres_virtual = var->yres;
++
++      if (var->xres_virtual < xres_min || var->yres_virtual < yres_min)
++              return -EINVAL;
++
++      if (var->xres < xres_min)
++              var->xres = xres_min;
++      if (var->yres < yres_min)
++              var->yres = yres_min;
++      if (var->xres > xres_max)
++              var->xres = xres_max;
++      if (var->yres > yres_max)
++              var->yres = yres_max;
++
++      if (var->xres > var->xres_virtual)
++              var->xres = var->xres_virtual;
++      if (var->yres > var->yres_virtual)
++              var->yres = var->yres_virtual;
++
++      if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
++              line_size = OMAP_VRFB_LINE_LEN * bytespp;
++      else
++              line_size = var->xres_virtual * bytespp;
++
++      max_frame_size = ofbi->region.size;
++
++      DBG("max frame size %lu, line size %lu\n", max_frame_size, line_size);
++
++      if (line_size * var->yres_virtual > max_frame_size) {
++              DBG("can't fit FB into memory, reducing y\n");
++              var->yres_virtual = max_frame_size / line_size;
++
++              if (var->yres_virtual < yres_min)
++                      var->yres_virtual = yres_min;
++
++              if (var->yres > var->yres_virtual)
++                      var->yres = var->yres_virtual;
++      }
++
++      if (line_size * var->yres_virtual > max_frame_size) {
++              DBG("can't fit FB into memory, reducing x\n");
++              if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
++                      return -EINVAL;
++
++              var->xres_virtual = max_frame_size / var->yres_virtual /
++                      bytespp;
++
++              if (var->xres_virtual < xres_min)
++                      var->xres_virtual = xres_min;
++
++              if (var->xres > var->xres_virtual)
++                      var->xres = var->xres_virtual;
++
++              line_size = var->xres_virtual * bytespp;
++      }
++
++      if (line_size * var->yres_virtual > max_frame_size) {
++              DBG("cannot fit FB to memory\n");
++              return -EINVAL;
++      }
++
++      if (var->xres + var->xoffset > var->xres_virtual)
++              var->xoffset = var->xres_virtual - var->xres;
++      if (var->yres + var->yoffset > var->yres_virtual)
++              var->yoffset = var->yres_virtual - var->yres;
++
++      DBG("xres = %d, yres = %d, vxres = %d, vyres = %d\n",
++                      var->xres, var->yres,
++                      var->xres_virtual, var->yres_virtual);
++
++      var->height             = -1;
++      var->width              = -1;
++      var->grayscale          = 0;
++
++      if (display && display->get_timings) {
++              struct omap_video_timings timings;
++              display->get_timings(display, &timings);
++
++              /* pixclock in ps, the rest in pixclock */
++              var->pixclock = timings.pixel_clock != 0 ?
++                      KHZ2PICOS(timings.pixel_clock) :
++                      0;
++              var->left_margin = timings.hfp;
++              var->right_margin = timings.hbp;
++              var->upper_margin = timings.vfp;
++              var->lower_margin = timings.vbp;
++              var->hsync_len = timings.hsw;
++              var->vsync_len = timings.vsw;
++      } else {
++              var->pixclock = 0;
++              var->left_margin = 0;
++              var->right_margin = 0;
++              var->upper_margin = 0;
++              var->lower_margin = 0;
++              var->hsync_len = 0;
++              var->vsync_len = 0;
++      }
++
++      /* TODO: get these from panel->config */
++      var->vmode              = FB_VMODE_NONINTERLACED;
++      var->sync               = 0;
++
++      return 0;
++}
++
++/*
++ * ---------------------------------------------------------------------------
++ * fbdev framework callbacks
++ * ---------------------------------------------------------------------------
++ */
++static int omapfb_open(struct fb_info *fbi, int user)
++{
++      return 0;
++}
++
++static int omapfb_release(struct fb_info *fbi, int user)
++{
++#if 0
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      struct omapfb2_device *fbdev = ofbi->fbdev;
++      struct omap_dss_device *display = fb2display(fbi);
++
++      DBG("Closing fb with plane index %d\n", ofbi->id);
++
++      omapfb_lock(fbdev);
++
++      if (display && display->get_update_mode && display->update) {
++              /* XXX this update should be removed, I think. But it's
++               * good for debugging */
++              if (display->get_update_mode(display) ==
++                              OMAP_DSS_UPDATE_MANUAL) {
++                      u16 w, h;
++
++                      if (display->sync)
++                              display->sync(display);
++
++                      display->get_resolution(display, &w, &h);
++                      display->update(display, 0, 0, w, h);
++              }
++      }
++
++      if (display && display->sync)
++              display->sync(display);
++
++      omapfb_unlock(fbdev);
++#endif
++      return 0;
++}
++
++/* setup overlay according to the fb */
++static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
++              u16 posx, u16 posy, u16 outw, u16 outh)
++{
++      int r = 0;
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      struct fb_var_screeninfo *var = &fbi->var;
++      struct fb_fix_screeninfo *fix = &fbi->fix;
++      enum omap_color_mode mode = 0;
++      int offset;
++      u32 data_start_p;
++      void __iomem *data_start_v;
++      struct omap_overlay_info info;
++      int xres, yres;
++      int screen_width;
++      int mirror;
++      int rotation = var->rotate;
++      int i;
++
++      for (i = 0; i < ofbi->num_overlays; i++) {
++              if (ovl != ofbi->overlays[i])
++                      continue;
++
++              rotation = (rotation + ofbi->rotation[i]) % 4;
++              break;
++      }
++
++      DBG("setup_overlay %d, posx %d, posy %d, outw %d, outh %d\n", ofbi->id,
++                      posx, posy, outw, outh);
++
++      if (rotation == FB_ROTATE_CW || rotation == FB_ROTATE_CCW) {
++              xres = var->yres;
++              yres = var->xres;
++      } else {
++              xres = var->xres;
++              yres = var->yres;
++      }
++
++      offset = ((var->yoffset * var->xres_virtual +
++                              var->xoffset) * var->bits_per_pixel) >> 3;
++
++      if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
++              data_start_p = omapfb_get_region_rot_paddr(ofbi, rotation);
++              data_start_v = NULL;
++      } else {
++              data_start_p = omapfb_get_region_paddr(ofbi);
++              data_start_v = omapfb_get_region_vaddr(ofbi);
++      }
++
++      data_start_p += offset;
++      data_start_v += offset;
++
++      mode = fb_mode_to_dss_mode(var);
++
++      if (mode == -EINVAL) {
++              DBG("fb_mode_to_dss_mode failed");
++              r = -EINVAL;
++              goto err;
++      }
++
++      switch (var->nonstd) {
++      case OMAPFB_COLOR_YUV422:
++      case OMAPFB_COLOR_YUY422:
++              if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
++                      screen_width = fix->line_length
++                              / (var->bits_per_pixel >> 2);
++                      break;
++              }
++      default:
++              screen_width = fix->line_length / (var->bits_per_pixel >> 3);
++              break;
++      }
++
++      ovl->get_overlay_info(ovl, &info);
++
++      if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
++              mirror = 0;
++      else
++              mirror = ofbi->mirror;
++
++      info.paddr = data_start_p;
++      info.vaddr = data_start_v;
++      info.screen_width = screen_width;
++      info.width = xres;
++      info.height = yres;
++      info.color_mode = mode;
++      info.rotation_type = ofbi->rotation_type;
++      info.rotation = rotation;
++      info.mirror = mirror;
++
++      info.pos_x = posx;
++      info.pos_y = posy;
++      info.out_width = outw;
++      info.out_height = outh;
++
++      r = ovl->set_overlay_info(ovl, &info);
++      if (r) {
++              DBG("ovl->setup_overlay_info failed\n");
++              goto err;
++      }
++
++      return 0;
++
++err:
++      DBG("setup_overlay failed\n");
++      return r;
++}
++
++/* apply var to the overlay */
++int omapfb_apply_changes(struct fb_info *fbi, int init)
++{
++      int r = 0;
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      struct fb_var_screeninfo *var = &fbi->var;
++      struct omap_overlay *ovl;
++      u16 posx, posy;
++      u16 outw, outh;
++      int i;
++
++#ifdef DEBUG
++      if (omapfb_test_pattern)
++              fill_fb(fbi);
++#endif
++
++      for (i = 0; i < ofbi->num_overlays; i++) {
++              ovl = ofbi->overlays[i];
++
++              DBG("apply_changes, fb %d, ovl %d\n", ofbi->id, ovl->id);
++
++              if (ofbi->region.size == 0) {
++                      /* the fb is not available. disable the overlay */
++                      omapfb_overlay_enable(ovl, 0);
++                      if (!init && ovl->manager)
++                              ovl->manager->apply(ovl->manager);
++                      continue;
++              }
++
++              if (init || (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) {
++                      int rotation = (var->rotate + ofbi->rotation[i]) % 4;
++                      if (rotation == FB_ROTATE_CW ||
++                                      rotation == FB_ROTATE_CCW) {
++                              outw = var->yres;
++                              outh = var->xres;
++                      } else {
++                              outw = var->xres;
++                              outh = var->yres;
++                      }
++              } else {
++                      outw = ovl->info.out_width;
++                      outh = ovl->info.out_height;
++              }
++
++              if (init) {
++                      posx = 0;
++                      posy = 0;
++              } else {
++                      posx = ovl->info.pos_x;
++                      posy = ovl->info.pos_y;
++              }
++
++              r = omapfb_setup_overlay(fbi, ovl, posx, posy, outw, outh);
++              if (r)
++                      goto err;
++
++              if (!init && ovl->manager)
++                      ovl->manager->apply(ovl->manager);
++      }
++      return 0;
++err:
++      DBG("apply_changes failed\n");
++      return r;
++}
++
++/* checks var and eventually tweaks it to something supported,
++ * DO NOT MODIFY PAR */
++static int omapfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi)
++{
++      int r;
++
++      DBG("check_var(%d)\n", FB2OFB(fbi)->id);
++
++      r = check_fb_var(fbi, var);
++
++      return r;
++}
++
++/* set the video mode according to info->var */
++static int omapfb_set_par(struct fb_info *fbi)
++{
++      int r;
++
++      DBG("set_par(%d)\n", FB2OFB(fbi)->id);
++
++      set_fb_fix(fbi);
++      r = omapfb_apply_changes(fbi, 0);
++
++      return r;
++}
++
++static int omapfb_pan_display(struct fb_var_screeninfo *var,
++              struct fb_info *fbi)
++{
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      int r = 0;
++
++      DBG("pan_display(%d)\n", ofbi->id);
++
++      if (var->xoffset != fbi->var.xoffset ||
++          var->yoffset != fbi->var.yoffset) {
++              struct fb_var_screeninfo new_var;
++
++              new_var = fbi->var;
++              new_var.xoffset = var->xoffset;
++              new_var.yoffset = var->yoffset;
++
++              r = check_fb_var(fbi, &new_var);
++
++              if (r == 0) {
++                      fbi->var = new_var;
++                      set_fb_fix(fbi);
++                      r = omapfb_apply_changes(fbi, 0);
++              }
++      }
++
++      return r;
++}
++
++static void mmap_user_open(struct vm_area_struct *vma)
++{
++      struct omapfb_info *ofbi = (struct omapfb_info *)vma->vm_private_data;
++
++      atomic_inc(&ofbi->map_count);
++}
++
++static void mmap_user_close(struct vm_area_struct *vma)
++{
++      struct omapfb_info *ofbi = (struct omapfb_info *)vma->vm_private_data;
++
++      atomic_dec(&ofbi->map_count);
++}
++
++static struct vm_operations_struct mmap_user_ops = {
++      .open = mmap_user_open,
++      .close = mmap_user_close,
++};
++
++static int omapfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
++{
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      struct fb_fix_screeninfo *fix = &fbi->fix;
++      unsigned long off;
++      unsigned long start;
++      u32 len;
++
++      if (vma->vm_end - vma->vm_start == 0)
++              return 0;
++      if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
++              return -EINVAL;
++      off = vma->vm_pgoff << PAGE_SHIFT;
++
++      start = omapfb_get_region_paddr(ofbi);
++      len = fix->smem_len;
++      if (off >= len)
++              return -EINVAL;
++      if ((vma->vm_end - vma->vm_start + off) > len)
++              return -EINVAL;
++
++      off += start;
++
++      DBG("user mmap region start %lx, len %d, off %lx\n", start, len, off);
++
++      vma->vm_pgoff = off >> PAGE_SHIFT;
++      vma->vm_flags |= VM_IO | VM_RESERVED;
++      vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++      vma->vm_ops = &mmap_user_ops;
++      vma->vm_private_data = ofbi;
++      if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
++                           vma->vm_end - vma->vm_start, vma->vm_page_prot))
++              return -EAGAIN;
++      /* vm_ops.open won't be called for mmap itself. */
++      atomic_inc(&ofbi->map_count);
++      return 0;
++}
++
++/* Store a single color palette entry into a pseudo palette or the hardware
++ * palette if one is available. For now we support only 16bpp and thus store
++ * the entry only to the pseudo palette.
++ */
++static int _setcolreg(struct fb_info *fbi, u_int regno, u_int red, u_int green,
++              u_int blue, u_int transp, int update_hw_pal)
++{
++      /*struct omapfb_info *ofbi = FB2OFB(fbi);*/
++      /*struct omapfb2_device *fbdev = ofbi->fbdev;*/
++      struct fb_var_screeninfo *var = &fbi->var;
++      int r = 0;
++
++      enum omapfb_color_format mode = OMAPFB_COLOR_RGB24U; /* XXX */
++
++      /*switch (plane->color_mode) {*/
++      switch (mode) {
++      case OMAPFB_COLOR_YUV422:
++      case OMAPFB_COLOR_YUV420:
++      case OMAPFB_COLOR_YUY422:
++              r = -EINVAL;
++              break;
++      case OMAPFB_COLOR_CLUT_8BPP:
++      case OMAPFB_COLOR_CLUT_4BPP:
++      case OMAPFB_COLOR_CLUT_2BPP:
++      case OMAPFB_COLOR_CLUT_1BPP:
++              /*
++                 if (fbdev->ctrl->setcolreg)
++                 r = fbdev->ctrl->setcolreg(regno, red, green, blue,
++                 transp, update_hw_pal);
++                 */
++              /* Fallthrough */
++              r = -EINVAL;
++              break;
++      case OMAPFB_COLOR_RGB565:
++      case OMAPFB_COLOR_RGB444:
++      case OMAPFB_COLOR_RGB24P:
++      case OMAPFB_COLOR_RGB24U:
++              if (r != 0)
++                      break;
++
++              if (regno < 0) {
++                      r = -EINVAL;
++                      break;
++              }
++
++              if (regno < 16) {
++                      u16 pal;
++                      pal = ((red >> (16 - var->red.length)) <<
++                                      var->red.offset) |
++                              ((green >> (16 - var->green.length)) <<
++                               var->green.offset) |
++                              (blue >> (16 - var->blue.length));
++                      ((u32 *)(fbi->pseudo_palette))[regno] = pal;
++              }
++              break;
++      default:
++              BUG();
++      }
++      return r;
++}
++
++static int omapfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
++              u_int transp, struct fb_info *info)
++{
++      DBG("setcolreg\n");
++
++      return _setcolreg(info, regno, red, green, blue, transp, 1);
++}
++
++static int omapfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
++{
++      int count, index, r;
++      u16 *red, *green, *blue, *transp;
++      u16 trans = 0xffff;
++
++      DBG("setcmap\n");
++
++      red     = cmap->red;
++      green   = cmap->green;
++      blue    = cmap->blue;
++      transp  = cmap->transp;
++      index   = cmap->start;
++
++      for (count = 0; count < cmap->len; count++) {
++              if (transp)
++                      trans = *transp++;
++              r = _setcolreg(info, index++, *red++, *green++, *blue++, trans,
++                              count == cmap->len - 1);
++              if (r != 0)
++                      return r;
++      }
++
++      return 0;
++}
++
++static void omapfb_vrfb_suspend_all(struct omapfb2_device *fbdev)
++{
++      int i;
++
++      for (i = 0; i < fbdev->num_fbs; i++) {
++              struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
++
++              if (ofbi->region.vrfb.vaddr[0])
++                      omap_vrfb_suspend_ctx(&ofbi->region.vrfb);
++      }
++}
++
++static void omapfb_vrfb_resume_all(struct omapfb2_device *fbdev)
++{
++      int i;
++
++      for (i = 0; i < fbdev->num_fbs; i++) {
++              struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
++
++              if (ofbi->region.vrfb.vaddr[0])
++                      omap_vrfb_resume_ctx(&ofbi->region.vrfb);
++      }
++}
++
++static int omapfb_blank(int blank, struct fb_info *fbi)
++{
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      struct omapfb2_device *fbdev = ofbi->fbdev;
++      struct omap_dss_device *display = fb2display(fbi);
++      int do_update = 0;
++      int r = 0;
++
++      omapfb_lock(fbdev);
++
++      switch (blank) {
++      case FB_BLANK_UNBLANK:
++              if (display->state != OMAP_DSS_DISPLAY_SUSPENDED)
++                      goto exit;
++
++              omapfb_vrfb_resume_all(fbdev);
++
++              if (display->resume)
++                      r = display->resume(display);
++
++              if (r == 0 && display->get_update_mode &&
++                              display->get_update_mode(display) ==
++                              OMAP_DSS_UPDATE_MANUAL)
++                      do_update = 1;
++
++              break;
++
++      case FB_BLANK_NORMAL:
++              /* FB_BLANK_NORMAL could be implemented.
++               * Needs DSS additions. */
++      case FB_BLANK_VSYNC_SUSPEND:
++      case FB_BLANK_HSYNC_SUSPEND:
++      case FB_BLANK_POWERDOWN:
++              if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
++                      goto exit;
++
++              if (display->suspend)
++                      r = display->suspend(display);
++
++              omapfb_vrfb_suspend_all(fbdev);
++
++              break;
++
++      default:
++              r = -EINVAL;
++      }
++
++exit:
++      omapfb_unlock(fbdev);
++
++      if (r == 0 && do_update && display->update) {
++              u16 w, h;
++              display->get_resolution(display, &w, &h);
++
++              r = display->update(display, 0, 0, w, h);
++      }
++
++      return r;
++}
++
++#if 0
++/* XXX fb_read and fb_write are needed for VRFB */
++ssize_t omapfb_write(struct fb_info *info, const char __user *buf,
++              size_t count, loff_t *ppos)
++{
++      DBG("omapfb_write %d, %lu\n", count, (unsigned long)*ppos);
++      /* XXX needed for VRFB */
++      return count;
++}
++#endif
++
++static struct fb_ops omapfb_ops = {
++      .owner          = THIS_MODULE,
++      .fb_open        = omapfb_open,
++      .fb_release     = omapfb_release,
++      .fb_fillrect    = cfb_fillrect,
++      .fb_copyarea    = cfb_copyarea,
++      .fb_imageblit   = cfb_imageblit,
++      .fb_blank       = omapfb_blank,
++      .fb_ioctl       = omapfb_ioctl,
++      .fb_check_var   = omapfb_check_var,
++      .fb_set_par     = omapfb_set_par,
++      .fb_pan_display = omapfb_pan_display,
++      .fb_mmap        = omapfb_mmap,
++      .fb_setcolreg   = omapfb_setcolreg,
++      .fb_setcmap     = omapfb_setcmap,
++      /*.fb_write     = omapfb_write,*/
++};
++
++static void omapfb_free_fbmem(struct fb_info *fbi)
++{
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      struct omapfb2_device *fbdev = ofbi->fbdev;
++      struct omapfb2_mem_region *rg;
++
++      rg = &ofbi->region;
++
++      if (rg->paddr)
++              if (omap_vram_free(rg->paddr, rg->size))
++                      dev_err(fbdev->dev, "VRAM FREE failed\n");
++
++      if (rg->vaddr)
++              iounmap(rg->vaddr);
++
++      if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
++              /* unmap the 0 angle rotation */
++              if (rg->vrfb.vaddr[0]) {
++                      iounmap(rg->vrfb.vaddr[0]);
++                      omap_vrfb_release_ctx(&rg->vrfb);
++              }
++      }
++
++      rg->vaddr = NULL;
++      rg->paddr = 0;
++      rg->alloc = 0;
++      rg->size = 0;
++}
++
++static void clear_fb_info(struct fb_info *fbi)
++{
++      memset(&fbi->var, 0, sizeof(fbi->var));
++      memset(&fbi->fix, 0, sizeof(fbi->fix));
++      strlcpy(fbi->fix.id, MODULE_NAME, sizeof(fbi->fix.id));
++}
++
++static int omapfb_free_all_fbmem(struct omapfb2_device *fbdev)
++{
++      int i;
++
++      DBG("free all fbmem\n");
++
++      for (i = 0; i < fbdev->num_fbs; i++) {
++              struct fb_info *fbi = fbdev->fbs[i];
++              omapfb_free_fbmem(fbi);
++              clear_fb_info(fbi);
++      }
++
++      return 0;
++}
++
++static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
++              unsigned long paddr)
++{
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      struct omapfb2_device *fbdev = ofbi->fbdev;
++      struct omapfb2_mem_region *rg;
++      void __iomem *vaddr;
++      int r;
++
++      rg = &ofbi->region;
++      memset(rg, 0, sizeof(*rg));
++
++      size = PAGE_ALIGN(size);
++
++      if (!paddr) {
++              DBG("allocating %lu bytes for fb %d\n", size, ofbi->id);
++              r = omap_vram_alloc(OMAP_VRAM_MEMTYPE_SDRAM, size, &paddr);
++      } else {
++              DBG("reserving %lu bytes at %lx for fb %d\n", size, paddr,
++                              ofbi->id);
++              r = omap_vram_reserve(paddr, size);
++      }
++
++      if (r) {
++              dev_err(fbdev->dev, "failed to allocate framebuffer\n");
++              return -ENOMEM;
++      }
++
++      if (ofbi->rotation_type != OMAP_DSS_ROT_VRFB) {
++              vaddr = ioremap_wc(paddr, size);
++
++              if (!vaddr) {
++                      dev_err(fbdev->dev, "failed to ioremap framebuffer\n");
++                      omap_vram_free(paddr, size);
++                      return -ENOMEM;
++              }
++
++              DBG("allocated VRAM paddr %lx, vaddr %p\n", paddr, vaddr);
++      } else {
++              void __iomem *va;
++
++              r = omap_vrfb_request_ctx(&rg->vrfb);
++              if (r) {
++                      dev_err(fbdev->dev, "vrfb create ctx failed\n");
++                      return r;
++              }
++
++              /* only ioremap the 0 angle view */
++              va = ioremap_wc(rg->vrfb.paddr[0], size);
++
++              if (!va) {
++                      printk(KERN_ERR "vrfb: ioremap failed\n");
++                      omap_vrfb_release_ctx(&rg->vrfb);
++                      return -ENOMEM;
++              }
++
++              DBG("ioremapped vrfb area 0 to %p\n", va);
++
++              rg->vrfb.vaddr[0] = va;
++
++              vaddr = NULL;
++      }
++
++      rg->paddr = paddr;
++      rg->vaddr = vaddr;
++      rg->size = size;
++      rg->alloc = 1;
++
++      return 0;
++}
++
++/* allocate fbmem using display resolution as reference */
++static int omapfb_alloc_fbmem_display(struct fb_info *fbi, unsigned long size,
++              unsigned long paddr)
++{
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      struct omap_dss_device *display;
++      int bytespp;
++
++      display =  fb2display(fbi);
++
++      if (!display)
++              return 0;
++
++      switch (display->get_recommended_bpp(display)) {
++      case 16:
++              bytespp = 2;
++              break;
++      case 24:
++              bytespp = 4;
++              break;
++      default:
++              bytespp = 4;
++              break;
++      }
++
++      if (!size) {
++              u16 w, h;
++
++              display->get_resolution(display, &w, &h);
++
++              if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
++#ifdef DEBUG
++                      int oldw = w, oldh = h;
++#endif
++
++                      omap_vrfb_adjust_size(&w, &h, bytespp);
++
++                      /* Because we change the resolution of the 0 degree
++                       * view, we need to alloc max(w, h) for height */
++                      h = max(w, h);
++                      w = OMAP_VRFB_LINE_LEN;
++
++                      DBG("adjusting fb mem size for VRFB, %dx%d -> %dx%d\n",
++                                      oldw, oldh, w, h);
++              }
++
++              size = w * h * bytespp;
++      }
++
++      if (!size)
++              return 0;
++
++      return omapfb_alloc_fbmem(fbi, size, paddr);
++}
++
++static enum omap_color_mode fb_format_to_dss_mode(enum omapfb_color_format fmt)
++{
++      enum omap_color_mode mode;
++
++      switch (fmt) {
++      case OMAPFB_COLOR_RGB565:
++              mode = OMAP_DSS_COLOR_RGB16;
++              break;
++      case OMAPFB_COLOR_YUV422:
++              mode = OMAP_DSS_COLOR_YUV2;
++              break;
++      case OMAPFB_COLOR_CLUT_8BPP:
++              mode = OMAP_DSS_COLOR_CLUT8;
++              break;
++      case OMAPFB_COLOR_CLUT_4BPP:
++              mode = OMAP_DSS_COLOR_CLUT4;
++              break;
++      case OMAPFB_COLOR_CLUT_2BPP:
++              mode = OMAP_DSS_COLOR_CLUT2;
++              break;
++      case OMAPFB_COLOR_CLUT_1BPP:
++              mode = OMAP_DSS_COLOR_CLUT1;
++              break;
++      case OMAPFB_COLOR_RGB444:
++              mode = OMAP_DSS_COLOR_RGB12U;
++              break;
++      case OMAPFB_COLOR_YUY422:
++              mode = OMAP_DSS_COLOR_UYVY;
++              break;
++      case OMAPFB_COLOR_ARGB16:
++              mode = OMAP_DSS_COLOR_ARGB16;
++              break;
++      case OMAPFB_COLOR_RGB24U:
++              mode = OMAP_DSS_COLOR_RGB24U;
++              break;
++      case OMAPFB_COLOR_RGB24P:
++              mode = OMAP_DSS_COLOR_RGB24P;
++              break;
++      case OMAPFB_COLOR_ARGB32:
++              mode = OMAP_DSS_COLOR_ARGB32;
++              break;
++      case OMAPFB_COLOR_RGBA32:
++              mode = OMAP_DSS_COLOR_RGBA32;
++              break;
++      case OMAPFB_COLOR_RGBX32:
++              mode = OMAP_DSS_COLOR_RGBX32;
++              break;
++      default:
++              mode = -EINVAL;
++      }
++
++      return mode;
++}
++
++static int omapfb_parse_vram_param(const char *param, int max_entries,
++              unsigned long *sizes, unsigned long *paddrs)
++{
++      int fbnum;
++      unsigned long size;
++      unsigned long paddr = 0;
++      char *p, *start;
++
++      start = (char *)param;
++
++      while (1) {
++              p = start;
++
++              fbnum = simple_strtoul(p, &p, 10);
++
++              if (p == param)
++                      return -EINVAL;
++
++              if (*p != ':')
++                      return -EINVAL;
++
++              if (fbnum >= max_entries)
++                      return -EINVAL;
++
++              size = memparse(p + 1, &p);
++
++              if (!size)
++                      return -EINVAL;
++
++              paddr = 0;
++
++              if (*p == '@') {
++                      paddr = simple_strtoul(p + 1, &p, 16);
++
++                      if (!paddr)
++                              return -EINVAL;
++
++              }
++
++              paddrs[fbnum] = paddr;
++              sizes[fbnum] = size;
++
++              if (*p == 0)
++                      break;
++
++              if (*p != ',')
++                      return -EINVAL;
++
++              ++p;
++
++              start = p;
++      }
++
++      return 0;
++}
++
++static int omapfb_allocate_all_fbs(struct omapfb2_device *fbdev)
++{
++      int i, r;
++      unsigned long vram_sizes[10];
++      unsigned long vram_paddrs[10];
++
++      memset(&vram_sizes, 0, sizeof(vram_sizes));
++      memset(&vram_paddrs, 0, sizeof(vram_paddrs));
++
++      if (def_vram && omapfb_parse_vram_param(def_vram, 10,
++                              vram_sizes, vram_paddrs)) {
++              dev_err(fbdev->dev, "failed to parse vram parameter\n");
++
++              memset(&vram_sizes, 0, sizeof(vram_sizes));
++              memset(&vram_paddrs, 0, sizeof(vram_paddrs));
++      }
++
++      if (fbdev->dev->platform_data) {
++              struct omapfb_platform_data *opd;
++              opd = fbdev->dev->platform_data;
++              for (i = 0; i < opd->mem_desc.region_cnt; ++i) {
++                      if (!vram_sizes[i]) {
++                              unsigned long size;
++                              unsigned long paddr;
++
++                              size = opd->mem_desc.region[i].size;
++                              paddr = opd->mem_desc.region[i].paddr;
++
++                              vram_sizes[i] = size;
++                              vram_paddrs[i] = paddr;
++                      }
++              }
++      }
++
++      for (i = 0; i < fbdev->num_fbs; i++) {
++              /* allocate memory automatically only for fb0, or if
++               * excplicitly defined with vram or plat data option */
++              if (i == 0 || vram_sizes[i] != 0) {
++                      r = omapfb_alloc_fbmem_display(fbdev->fbs[i],
++                                      vram_sizes[i], vram_paddrs[i]);
++
++                      if (r)
++                              return r;
++              }
++      }
++
++      for (i = 0; i < fbdev->num_fbs; i++) {
++              struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
++              struct omapfb2_mem_region *rg;
++              rg = &ofbi->region;
++
++              DBG("region%d phys %08x virt %p size=%lu\n",
++                              i,
++                              rg->paddr,
++                              rg->vaddr,
++                              rg->size);
++      }
++
++      return 0;
++}
++
++int omapfb_realloc_fbmem(struct fb_info *fbi, unsigned long size, int type)
++{
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      struct omapfb2_device *fbdev = ofbi->fbdev;
++      struct omap_dss_device *display = fb2display(fbi);
++      struct omapfb2_mem_region *rg = &ofbi->region;
++      unsigned long old_size = rg->size;
++      unsigned long old_paddr = rg->paddr;
++      int old_type = rg->type;
++      int r;
++
++      if (type > OMAPFB_MEMTYPE_MAX)
++              return -EINVAL;
++
++      size = PAGE_ALIGN(size);
++
++      if (old_size == size && old_type == type)
++              return 0;
++
++      if (display && display->sync)
++                      display->sync(display);
++
++      omapfb_free_fbmem(fbi);
++
++      if (size == 0) {
++              clear_fb_info(fbi);
++              return 0;
++      }
++
++      r = omapfb_alloc_fbmem(fbi, size, 0);
++
++      if (r) {
++              if (old_size)
++                      omapfb_alloc_fbmem(fbi, old_size, old_paddr);
++
++              if (rg->size == 0)
++                      clear_fb_info(fbi);
++
++              return r;
++      }
++
++      if (old_size == size)
++              return 0;
++
++      if (old_size == 0) {
++              DBG("initializing fb %d\n", ofbi->id);
++              r = omapfb_fb_init(fbdev, fbi);
++              if (r) {
++                      DBG("omapfb_fb_init failed\n");
++                      goto err;
++              }
++              r = omapfb_apply_changes(fbi, 1);
++              if (r) {
++                      DBG("omapfb_apply_changes failed\n");
++                      goto err;
++              }
++      } else {
++              struct fb_var_screeninfo new_var;
++              memcpy(&new_var, &fbi->var, sizeof(new_var));
++              r = check_fb_var(fbi, &new_var);
++              if (r)
++                      goto err;
++              memcpy(&fbi->var, &new_var, sizeof(fbi->var));
++              set_fb_fix(fbi);
++      }
++
++      return 0;
++err:
++      omapfb_free_fbmem(fbi);
++      clear_fb_info(fbi);
++      return r;
++}
++
++/* initialize fb_info, var, fix to something sane based on the display */
++static int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi)
++{
++      struct fb_var_screeninfo *var = &fbi->var;
++      struct omap_dss_device *display = fb2display(fbi);
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      int r = 0;
++
++      fbi->fbops = &omapfb_ops;
++      fbi->flags = FBINFO_FLAG_DEFAULT;
++      fbi->pseudo_palette = fbdev->pseudo_palette;
++
++      if (ofbi->region.size == 0) {
++              clear_fb_info(fbi);
++              return 0;
++      }
++
++      var->nonstd = 0;
++      var->bits_per_pixel = 0;
++
++      var->rotate = def_rotate;
++
++      /*
++       * Check if there is a default color format set in the board file,
++       * and use this format instead the default deducted from the
++       * display bpp.
++       */
++      if (fbdev->dev->platform_data) {
++              struct omapfb_platform_data *opd;
++              int id = ofbi->id;
++
++              opd = fbdev->dev->platform_data;
++              if (opd->mem_desc.region[id].format_used) {
++                      enum omap_color_mode mode;
++                      enum omapfb_color_format format;
++
++                      format = opd->mem_desc.region[id].format;
++                      mode = fb_format_to_dss_mode(format);
++                      if (mode < 0) {
++                              r = mode;
++                              goto err;
++                      }
++                      r = dss_mode_to_fb_mode(mode, var);
++                      if (r < 0)
++                              goto err;
++              }
++      }
++
++      if (display) {
++              u16 w, h;
++              int rotation = (var->rotate + ofbi->rotation[0]) % 4;
++
++              display->get_resolution(display, &w, &h);
++
++              if (rotation == FB_ROTATE_CW ||
++                              rotation == FB_ROTATE_CCW) {
++                      var->xres = h;
++                      var->yres = w;
++              } else {
++                      var->xres = w;
++                      var->yres = h;
++              }
++
++              var->xres_virtual = var->xres;
++              var->yres_virtual = var->yres;
++
++              if (!var->bits_per_pixel) {
++                      switch (display->get_recommended_bpp(display)) {
++                      case 16:
++                              var->bits_per_pixel = 16;
++                              break;
++                      case 24:
++                              var->bits_per_pixel = 32;
++                              break;
++                      default:
++                              dev_err(fbdev->dev, "illegal display "
++                                              "bpp\n");
++                              return -EINVAL;
++                      }
++              }
++      } else {
++              /* if there's no display, let's just guess some basic values */
++              var->xres = 320;
++              var->yres = 240;
++              var->xres_virtual = var->xres;
++              var->yres_virtual = var->yres;
++              if (!var->bits_per_pixel)
++                      var->bits_per_pixel = 16;
++      }
++
++      r = check_fb_var(fbi, var);
++      if (r)
++              goto err;
++
++      set_fb_fix(fbi);
++
++      r = fb_alloc_cmap(&fbi->cmap, 256, 0);
++      if (r)
++              dev_err(fbdev->dev, "unable to allocate color map memory\n");
++
++err:
++      return r;
++}
++
++static void fbinfo_cleanup(struct omapfb2_device *fbdev, struct fb_info *fbi)
++{
++      fb_dealloc_cmap(&fbi->cmap);
++}
++
++
++static void omapfb_free_resources(struct omapfb2_device *fbdev)
++{
++      int i;
++
++      DBG("free_resources\n");
++
++      if (fbdev == NULL)
++              return;
++
++      for (i = 0; i < fbdev->num_fbs; i++)
++              unregister_framebuffer(fbdev->fbs[i]);
++
++      /* free the reserved fbmem */
++      omapfb_free_all_fbmem(fbdev);
++
++      for (i = 0; i < fbdev->num_fbs; i++) {
++              fbinfo_cleanup(fbdev, fbdev->fbs[i]);
++              framebuffer_release(fbdev->fbs[i]);
++      }
++
++      for (i = 0; i < fbdev->num_displays; i++) {
++              if (fbdev->displays[i]->state != OMAP_DSS_DISPLAY_DISABLED)
++                      fbdev->displays[i]->disable(fbdev->displays[i]);
++
++              omap_dss_put_device(fbdev->displays[i]);
++      }
++
++      dev_set_drvdata(fbdev->dev, NULL);
++      kfree(fbdev);
++}
++
++static int omapfb_create_framebuffers(struct omapfb2_device *fbdev)
++{
++      int r, i;
++
++      fbdev->num_fbs = 0;
++
++      DBG("create %d framebuffers\n", CONFIG_FB_OMAP2_NUM_FBS);
++
++      /* allocate fb_infos */
++      for (i = 0; i < CONFIG_FB_OMAP2_NUM_FBS; i++) {
++              struct fb_info *fbi;
++              struct omapfb_info *ofbi;
++
++              fbi = framebuffer_alloc(sizeof(struct omapfb_info),
++                              fbdev->dev);
++
++              if (fbi == NULL) {
++                      dev_err(fbdev->dev,
++                              "unable to allocate memory for plane info\n");
++                      return -ENOMEM;
++              }
++
++              clear_fb_info(fbi);
++
++              fbdev->fbs[i] = fbi;
++
++              ofbi = FB2OFB(fbi);
++              ofbi->fbdev = fbdev;
++              ofbi->id = i;
++
++              /* assign these early, so that fb alloc can use them */
++              ofbi->rotation_type = def_vrfb ? OMAP_DSS_ROT_VRFB :
++                      OMAP_DSS_ROT_DMA;
++              ofbi->mirror = def_mirror;
++
++              fbdev->num_fbs++;
++      }
++
++      DBG("fb_infos allocated\n");
++
++      /* assign overlays for the fbs */
++      for (i = 0; i < min(fbdev->num_fbs, fbdev->num_overlays); i++) {
++              struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
++
++              ofbi->overlays[0] = fbdev->overlays[i];
++              ofbi->num_overlays = 1;
++      }
++
++      /* allocate fb memories */
++      r = omapfb_allocate_all_fbs(fbdev);
++      if (r) {
++              dev_err(fbdev->dev, "failed to allocate fbmem\n");
++              return r;
++      }
++
++      DBG("fbmems allocated\n");
++
++      /* setup fb_infos */
++      for (i = 0; i < fbdev->num_fbs; i++) {
++              r = omapfb_fb_init(fbdev, fbdev->fbs[i]);
++              if (r) {
++                      dev_err(fbdev->dev, "failed to setup fb_info\n");
++                      return r;
++              }
++      }
++
++      DBG("fb_infos initialized\n");
++
++      for (i = 0; i < fbdev->num_fbs; i++) {
++              r = register_framebuffer(fbdev->fbs[i]);
++              if (r != 0) {
++                      dev_err(fbdev->dev,
++                              "registering framebuffer %d failed\n", i);
++                      return r;
++              }
++      }
++
++      DBG("framebuffers registered\n");
++
++      for (i = 0; i < fbdev->num_fbs; i++) {
++              r = omapfb_apply_changes(fbdev->fbs[i], 1);
++              if (r) {
++                      dev_err(fbdev->dev, "failed to change mode\n");
++                      return r;
++              }
++      }
++
++      DBG("create sysfs for fbs\n");
++      r = omapfb_create_sysfs(fbdev);
++      if (r) {
++              dev_err(fbdev->dev, "failed to create sysfs entries\n");
++              return r;
++      }
++
++      /* Enable fb0 */
++      if (fbdev->num_fbs > 0) {
++              struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[0]);
++
++              if (ofbi->num_overlays > 0) {
++                      struct omap_overlay *ovl = ofbi->overlays[0];
++
++                      r = omapfb_overlay_enable(ovl, 1);
++
++                      if (r) {
++                              dev_err(fbdev->dev,
++                                              "failed to enable overlay\n");
++                              return r;
++                      }
++              }
++      }
++
++      DBG("create_framebuffers done\n");
++
++      return 0;
++}
++
++static int omapfb_mode_to_timings(const char *mode_str,
++              struct omap_video_timings *timings, u8 *bpp)
++{
++      struct fb_info fbi;
++      struct fb_var_screeninfo var;
++      struct fb_ops fbops;
++      int r;
++
++#ifdef CONFIG_OMAP2_DSS_VENC
++      if (strcmp(mode_str, "pal") == 0) {
++              *timings = omap_dss_pal_timings;
++              *bpp = 0;
++              return 0;
++      } else if (strcmp(mode_str, "ntsc") == 0) {
++              *timings = omap_dss_ntsc_timings;
++              *bpp = 0;
++              return 0;
++      }
++#endif
++
++      /* this is quite a hack, but I wanted to use the modedb and for
++       * that we need fb_info and var, so we create dummy ones */
++
++      memset(&fbi, 0, sizeof(fbi));
++      memset(&var, 0, sizeof(var));
++      memset(&fbops, 0, sizeof(fbops));
++      fbi.fbops = &fbops;
++
++      r = fb_find_mode(&var, &fbi, mode_str, NULL, 0, NULL, 24);
++
++      if (r != 0) {
++              timings->pixel_clock = PICOS2KHZ(var.pixclock);
++              timings->hfp = var.left_margin;
++              timings->hbp = var.right_margin;
++              timings->vfp = var.upper_margin;
++              timings->vbp = var.lower_margin;
++              timings->hsw = var.hsync_len;
++              timings->vsw = var.vsync_len;
++              timings->x_res = var.xres;
++              timings->y_res = var.yres;
++
++              switch (var.bits_per_pixel) {
++              case 16:
++                      *bpp = 16;
++                      break;
++              case 24:
++              case 32:
++              default:
++                      *bpp = 24;
++                      break;
++              }
++
++              return 0;
++      } else {
++              return -EINVAL;
++      }
++}
++
++static int omapfb_set_def_mode(struct omap_dss_device *display, char *mode_str)
++{
++      int r;
++      u8 bpp;
++      struct omap_video_timings timings;
++
++      r = omapfb_mode_to_timings(mode_str, &timings, &bpp);
++      if (r)
++              return r;
++
++      display->panel.recommended_bpp = bpp;
++
++      if (!display->check_timings || !display->set_timings)
++              return -EINVAL;
++
++      r = display->check_timings(display, &timings);
++      if (r)
++              return r;
++
++      display->set_timings(display, &timings);
++
++      return 0;
++}
++
++static int omapfb_parse_def_modes(struct omapfb2_device *fbdev)
++{
++      char *str, *options, *this_opt;
++      int r = 0;
++
++      str = kmalloc(strlen(def_mode) + 1, GFP_KERNEL);
++      strcpy(str, def_mode);
++      options = str;
++
++      while (!r && (this_opt = strsep(&options, ",")) != NULL) {
++              char *p, *display_str, *mode_str;
++              struct omap_dss_device *display;
++              int i;
++
++              p = strchr(this_opt, ':');
++              if (!p) {
++                      r = -EINVAL;
++                      break;
++              }
++
++              *p = 0;
++              display_str = this_opt;
++              mode_str = p + 1;
++
++              display = NULL;
++              for (i = 0; i < fbdev->num_displays; ++i) {
++                      if (strcmp(fbdev->displays[i]->name,
++                                              display_str) == 0) {
++                              display = fbdev->displays[i];
++                              break;
++                      }
++              }
++
++              if (!display) {
++                      r = -EINVAL;
++                      break;
++              }
++
++              r = omapfb_set_def_mode(display, mode_str);
++              if (r)
++                      break;
++      }
++
++      kfree(str);
++
++      return r;
++}
++
++static int omapfb_probe(struct platform_device *pdev)
++{
++      struct omapfb2_device *fbdev = NULL;
++      int r = 0;
++      int i;
++      struct omap_overlay *ovl;
++      struct omap_dss_device *def_display;
++      struct omap_dss_device *dssdev;
++
++      DBG("omapfb_probe\n");
++
++      if (pdev->num_resources != 0) {
++              dev_err(&pdev->dev, "probed for an unknown device\n");
++              r = -ENODEV;
++              goto err0;
++      }
++
++      fbdev = kzalloc(sizeof(struct omapfb2_device), GFP_KERNEL);
++      if (fbdev == NULL) {
++              r = -ENOMEM;
++              goto err0;
++      }
++
++      mutex_init(&fbdev->mtx);
++
++      fbdev->dev = &pdev->dev;
++      platform_set_drvdata(pdev, fbdev);
++
++      fbdev->num_displays = 0;
++      dssdev = NULL;
++      for_each_dss_dev(dssdev) {
++              omap_dss_get_device(dssdev);
++              fbdev->displays[fbdev->num_displays++] = dssdev;
++      }
++
++      if (fbdev->num_displays == 0) {
++              dev_err(&pdev->dev, "no displays\n");
++              r = -EINVAL;
++              goto cleanup;
++      }
++
++      fbdev->num_overlays = omap_dss_get_num_overlays();
++      for (i = 0; i < fbdev->num_overlays; i++)
++              fbdev->overlays[i] = omap_dss_get_overlay(i);
++
++      fbdev->num_managers = omap_dss_get_num_overlay_managers();
++      for (i = 0; i < fbdev->num_managers; i++)
++              fbdev->managers[i] = omap_dss_get_overlay_manager(i);
++
++      if (def_mode && strlen(def_mode) > 0) {
++              if (omapfb_parse_def_modes(fbdev))
++                      dev_warn(&pdev->dev, "cannot parse default modes\n");
++      }
++
++      r = omapfb_create_framebuffers(fbdev);
++      if (r)
++              goto cleanup;
++
++      for (i = 0; i < fbdev->num_managers; i++) {
++              struct omap_overlay_manager *mgr;
++              mgr = fbdev->managers[i];
++              r = mgr->apply(mgr);
++              if (r)
++                      dev_warn(fbdev->dev, "failed to apply dispc config\n");
++      }
++
++      DBG("mgr->apply'ed\n");
++
++      /* gfx overlay should be the default one. find a display
++       * connected to that, and use it as default display */
++      ovl = omap_dss_get_overlay(0);
++      if (ovl->manager && ovl->manager->device) {
++              def_display = ovl->manager->device;
++      } else {
++              dev_warn(&pdev->dev, "cannot find default display\n");
++              def_display = NULL;
++      }
++
++      if (def_display) {
++              u16 w, h;
++              r = def_display->enable(def_display);
++              if (r)
++                      dev_warn(fbdev->dev, "Failed to enable display '%s'\n",
++                                      def_display->name);
++
++              /* set the update mode */
++              if (def_display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
++#ifdef CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE
++                      if (def_display->enable_te)
++                              def_display->enable_te(def_display, 1);
++                      if (def_display->set_update_mode)
++                              def_display->set_update_mode(def_display,
++                                              OMAP_DSS_UPDATE_AUTO);
++#else /* MANUAL_UPDATE */
++                      if (def_display->enable_te)
++                              def_display->enable_te(def_display, 0);
++                      if (def_display->set_update_mode)
++                              def_display->set_update_mode(def_display,
++                                              OMAP_DSS_UPDATE_MANUAL);
++
++                      def_display->get_resolution(def_display, &w, &h);
++                      def_display->update(def_display, 0, 0, w, h);
++#endif
++              } else {
++                      if (def_display->set_update_mode)
++                              def_display->set_update_mode(def_display,
++                                              OMAP_DSS_UPDATE_AUTO);
++              }
++      }
++
++      return 0;
++
++cleanup:
++      omapfb_free_resources(fbdev);
++err0:
++      dev_err(&pdev->dev, "failed to setup omapfb\n");
++      return r;
++}
++
++static int omapfb_remove(struct platform_device *pdev)
++{
++      struct omapfb2_device *fbdev = platform_get_drvdata(pdev);
++
++      /* FIXME: wait till completion of pending events */
++
++      omapfb_remove_sysfs(fbdev);
++
++      omapfb_free_resources(fbdev);
++
++      return 0;
++}
++
++static struct platform_driver omapfb_driver = {
++      .probe          = omapfb_probe,
++      .remove         = omapfb_remove,
++      .driver         = {
++              .name   = "omapfb",
++              .owner  = THIS_MODULE,
++      },
++};
++
++static int __init omapfb_init(void)
++{
++      DBG("omapfb_init\n");
++
++      if (platform_driver_register(&omapfb_driver)) {
++              printk(KERN_ERR "failed to register omapfb driver\n");
++              return -ENODEV;
++      }
++
++      return 0;
++}
++
++static void __exit omapfb_exit(void)
++{
++      DBG("omapfb_exit\n");
++      platform_driver_unregister(&omapfb_driver);
++}
++
++module_param_named(mode, def_mode, charp, 0);
++module_param_named(vram, def_vram, charp, 0);
++module_param_named(rotate, def_rotate, int, 0);
++module_param_named(vrfb, def_vrfb, bool, 0);
++module_param_named(mirror, def_mirror, bool, 0);
++
++/* late_initcall to let panel/ctrl drivers loaded first.
++ * I guess better option would be a more dynamic approach,
++ * so that omapfb reacts to new panels when they are loaded */
++late_initcall(omapfb_init);
++/*module_init(omapfb_init);*/
++module_exit(omapfb_exit);
++
++MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
++MODULE_DESCRIPTION("OMAP2/3 Framebuffer");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/video/omap2/omapfb/omapfb-sysfs.c b/drivers/video/omap2/omapfb/omapfb-sysfs.c
+new file mode 100644
+index 0000000..ef30e0e
+--- /dev/null
++++ b/drivers/video/omap2/omapfb/omapfb-sysfs.c
+@@ -0,0 +1,507 @@
++/*
++ * linux/drivers/video/omap2/omapfb-sysfs.c
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/fb.h>
++#include <linux/sysfs.h>
++#include <linux/device.h>
++#include <linux/uaccess.h>
++#include <linux/platform_device.h>
++#include <linux/kernel.h>
++#include <linux/mm.h>
++#include <linux/omapfb.h>
++
++#include <mach/display.h>
++#include <mach/vrfb.h>
++
++#include "omapfb.h"
++
++static ssize_t show_rotate_type(struct device *dev,
++              struct device_attribute *attr, char *buf)
++{
++      struct fb_info *fbi = dev_get_drvdata(dev);
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++
++      return snprintf(buf, PAGE_SIZE, "%d\n", ofbi->rotation_type);
++}
++
++static ssize_t store_rotate_type(struct device *dev,
++              struct device_attribute *attr,
++              const char *buf, size_t count)
++{
++      struct fb_info *fbi = dev_get_drvdata(dev);
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      enum omap_dss_rotation_type rot_type;
++      int r;
++
++      rot_type = simple_strtoul(buf, NULL, 0);
++
++      if (rot_type != OMAP_DSS_ROT_DMA && rot_type != OMAP_DSS_ROT_VRFB)
++              return -EINVAL;
++
++      lock_fb_info(fbi);
++
++      r = 0;
++      if (rot_type == ofbi->rotation_type)
++              goto out;
++
++      if (ofbi->region.size) {
++              r = -EBUSY;
++              goto out;
++      }
++
++      ofbi->rotation_type = rot_type;
++
++      /*
++       * Since the VRAM for this FB is not allocated at the moment we don't
++       * need to do any further parameter checking at this point.
++       */
++out:
++      unlock_fb_info(fbi);
++
++      return r ? r : count;
++}
++
++
++static ssize_t show_mirror(struct device *dev,
++              struct device_attribute *attr, char *buf)
++{
++      struct fb_info *fbi = dev_get_drvdata(dev);
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++
++      return snprintf(buf, PAGE_SIZE, "%d\n", ofbi->mirror);
++}
++
++static ssize_t store_mirror(struct device *dev,
++              struct device_attribute *attr,
++              const char *buf, size_t count)
++{
++      struct fb_info *fbi = dev_get_drvdata(dev);
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      bool mirror;
++      int r;
++      struct fb_var_screeninfo new_var;
++
++      mirror = simple_strtoul(buf, NULL, 0);
++
++      if (mirror != 0 && mirror != 1)
++              return -EINVAL;
++
++      lock_fb_info(fbi);
++
++      ofbi->mirror = mirror;
++
++      memcpy(&new_var, &fbi->var, sizeof(new_var));
++      r = check_fb_var(fbi, &new_var);
++      if (r)
++              goto out;
++      memcpy(&fbi->var, &new_var, sizeof(fbi->var));
++
++      set_fb_fix(fbi);
++
++      r = omapfb_apply_changes(fbi, 0);
++      if (r)
++              goto out;
++
++      r = count;
++out:
++      unlock_fb_info(fbi);
++
++      return r;
++}
++
++static ssize_t show_overlays(struct device *dev,
++              struct device_attribute *attr, char *buf)
++{
++      struct fb_info *fbi = dev_get_drvdata(dev);
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      struct omapfb2_device *fbdev = ofbi->fbdev;
++      ssize_t l = 0;
++      int t;
++
++      omapfb_lock(fbdev);
++      lock_fb_info(fbi);
++
++      for (t = 0; t < ofbi->num_overlays; t++) {
++              struct omap_overlay *ovl = ofbi->overlays[t];
++              int ovlnum;
++
++              for (ovlnum = 0; ovlnum < fbdev->num_overlays; ++ovlnum)
++                      if (ovl == fbdev->overlays[ovlnum])
++                              break;
++
++              l += snprintf(buf + l, PAGE_SIZE - l, "%s%d",
++                              t == 0 ? "" : ",", ovlnum);
++      }
++
++      l += snprintf(buf + l, PAGE_SIZE - l, "\n");
++
++      unlock_fb_info(fbi);
++      omapfb_unlock(fbdev);
++
++      return l;
++}
++
++static struct omapfb_info *get_overlay_fb(struct omapfb2_device *fbdev,
++              struct omap_overlay *ovl)
++{
++      int i, t;
++
++      for (i = 0; i < fbdev->num_fbs; i++) {
++              struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
++
++              for (t = 0; t < ofbi->num_overlays; t++) {
++                      if (ofbi->overlays[t] == ovl)
++                              return ofbi;
++              }
++      }
++
++      return NULL;
++}
++
++static ssize_t store_overlays(struct device *dev, struct device_attribute *attr,
++              const char *buf, size_t count)
++{
++      struct fb_info *fbi = dev_get_drvdata(dev);
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      struct omapfb2_device *fbdev = ofbi->fbdev;
++      struct omap_overlay *ovls[OMAPFB_MAX_OVL_PER_FB];
++      struct omap_overlay *ovl;
++      int num_ovls, r, i;
++      int len;
++      bool added = false;
++
++      num_ovls = 0;
++
++      len = strlen(buf);
++      if (buf[len - 1] == '\n')
++              len = len - 1;
++
++      omapfb_lock(fbdev);
++      lock_fb_info(fbi);
++
++      if (len > 0) {
++              char *p = (char *)buf;
++              int ovlnum;
++
++              while (p < buf + len) {
++                      int found;
++                      if (num_ovls == OMAPFB_MAX_OVL_PER_FB) {
++                              r = -EINVAL;
++                              goto out;
++                      }
++
++                      ovlnum = simple_strtoul(p, &p, 0);
++                      if (ovlnum > fbdev->num_overlays) {
++                              r = -EINVAL;
++                              goto out;
++                      }
++
++                      found = 0;
++                      for (i = 0; i < num_ovls; ++i) {
++                              if (ovls[i] == fbdev->overlays[ovlnum]) {
++                                      found = 1;
++                                      break;
++                              }
++                      }
++
++                      if (!found)
++                              ovls[num_ovls++] = fbdev->overlays[ovlnum];
++
++                      p++;
++              }
++      }
++
++      for (i = 0; i < num_ovls; ++i) {
++              struct omapfb_info *ofbi2 = get_overlay_fb(fbdev, ovls[i]);
++              if (ofbi2 && ofbi2 != ofbi) {
++                      dev_err(fbdev->dev, "overlay already in use\n");
++                      r = -EINVAL;
++                      goto out;
++              }
++      }
++
++      /* detach unused overlays */
++      for (i = 0; i < ofbi->num_overlays; ++i) {
++              int t, found;
++
++              ovl = ofbi->overlays[i];
++
++              found = 0;
++
++              for (t = 0; t < num_ovls; ++t) {
++                      if (ovl == ovls[t]) {
++                              found = 1;
++                              break;
++                      }
++              }
++
++              if (found)
++                      continue;
++
++              DBG("detaching %d\n", ofbi->overlays[i]->id);
++
++              omapfb_overlay_enable(ovl, 0);
++
++              if (ovl->manager)
++                      ovl->manager->apply(ovl->manager);
++
++              for (t = i + 1; t < ofbi->num_overlays; t++) {
++                      ofbi->rotation[t-1] = ofbi->rotation[t];
++                      ofbi->overlays[t-1] = ofbi->overlays[t];
++              }
++
++              ofbi->num_overlays--;
++              i--;
++      }
++
++      for (i = 0; i < num_ovls; ++i) {
++              int t, found;
++
++              ovl = ovls[i];
++
++              found = 0;
++
++              for (t = 0; t < ofbi->num_overlays; ++t) {
++                      if (ovl == ofbi->overlays[t]) {
++                              found = 1;
++                              break;
++                      }
++              }
++
++              if (found)
++                      continue;
++              ofbi->rotation[ofbi->num_overlays] = 0;
++              ofbi->overlays[ofbi->num_overlays++] = ovl;
++
++              added = true;
++      }
++
++      if (added) {
++              r = omapfb_apply_changes(fbi, 0);
++              if (r)
++                      goto out;
++      }
++
++      r = count;
++out:
++      unlock_fb_info(fbi);
++      omapfb_unlock(fbdev);
++
++      return r;
++}
++
++static ssize_t show_overlays_rotate(struct device *dev,
++              struct device_attribute *attr, char *buf)
++{
++      struct fb_info *fbi = dev_get_drvdata(dev);
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      ssize_t l = 0;
++      int t;
++
++      lock_fb_info(fbi);
++
++      for (t = 0; t < ofbi->num_overlays; t++) {
++              l += snprintf(buf + l, PAGE_SIZE - l, "%s%d",
++                              t == 0 ? "" : ",", ofbi->rotation[t]);
++      }
++
++      l += snprintf(buf + l, PAGE_SIZE - l, "\n");
++
++      unlock_fb_info(fbi);
++
++      return l;
++}
++
++static ssize_t store_overlays_rotate(struct device *dev,
++              struct device_attribute *attr, const char *buf, size_t count)
++{
++      struct fb_info *fbi = dev_get_drvdata(dev);
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      int num_ovls = 0, r, i;
++      int len;
++      bool changed = false;
++      u8 rotation[OMAPFB_MAX_OVL_PER_FB];
++
++      len = strlen(buf);
++      if (buf[len - 1] == '\n')
++              len = len - 1;
++
++      lock_fb_info(fbi);
++
++      if (len > 0) {
++              char *p = (char *)buf;
++
++              while (p < buf + len) {
++                      int rot;
++
++                      if (num_ovls == ofbi->num_overlays) {
++                              r = -EINVAL;
++                              goto out;
++                      }
++
++                      rot = simple_strtoul(p, &p, 0);
++                      if (rot < 0 || rot > 3) {
++                              r = -EINVAL;
++                              goto out;
++                      }
++
++                      if (ofbi->rotation[num_ovls] != rot)
++                              changed = true;
++
++                      rotation[num_ovls++] = rot;
++
++                      p++;
++              }
++      }
++
++      if (num_ovls != ofbi->num_overlays) {
++              r = -EINVAL;
++              goto out;
++      }
++
++      if (changed) {
++              for (i = 0; i < num_ovls; ++i)
++                      ofbi->rotation[i] = rotation[i];
++
++              r = omapfb_apply_changes(fbi, 0);
++              if (r)
++                      goto out;
++
++              /* FIXME error handling? */
++      }
++
++      r = count;
++out:
++      unlock_fb_info(fbi);
++
++      return r;
++}
++
++static ssize_t show_size(struct device *dev,
++              struct device_attribute *attr, char *buf)
++{
++      struct fb_info *fbi = dev_get_drvdata(dev);
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++
++      return snprintf(buf, PAGE_SIZE, "%lu\n", ofbi->region.size);
++}
++
++static ssize_t store_size(struct device *dev, struct device_attribute *attr,
++              const char *buf, size_t count)
++{
++      struct fb_info *fbi = dev_get_drvdata(dev);
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      unsigned long size;
++      int r;
++      int i;
++
++      size = PAGE_ALIGN(simple_strtoul(buf, NULL, 0));
++
++      lock_fb_info(fbi);
++
++      for (i = 0; i < ofbi->num_overlays; i++) {
++              if (ofbi->overlays[i]->info.enabled) {
++                      r = -EBUSY;
++                      goto out;
++              }
++      }
++
++      if (size != ofbi->region.size) {
++              r = omapfb_realloc_fbmem(fbi, size, ofbi->region.type);
++              if (r) {
++                      dev_err(dev, "realloc fbmem failed\n");
++                      goto out;
++              }
++      }
++
++      r = count;
++out:
++      unlock_fb_info(fbi);
++
++      return r;
++}
++
++static ssize_t show_phys(struct device *dev,
++              struct device_attribute *attr, char *buf)
++{
++      struct fb_info *fbi = dev_get_drvdata(dev);
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++
++      return snprintf(buf, PAGE_SIZE, "%0x\n", ofbi->region.paddr);
++}
++
++static ssize_t show_virt(struct device *dev,
++              struct device_attribute *attr, char *buf)
++{
++      struct fb_info *fbi = dev_get_drvdata(dev);
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++
++      return snprintf(buf, PAGE_SIZE, "%p\n", ofbi->region.vaddr);
++}
++
++static struct device_attribute omapfb_attrs[] = {
++      __ATTR(rotate_type, S_IRUGO | S_IWUSR, show_rotate_type,
++                      store_rotate_type),
++      __ATTR(mirror, S_IRUGO | S_IWUSR, show_mirror, store_mirror),
++      __ATTR(size, S_IRUGO | S_IWUSR, show_size, store_size),
++      __ATTR(overlays, S_IRUGO | S_IWUSR, show_overlays, store_overlays),
++      __ATTR(overlays_rotate, S_IRUGO | S_IWUSR, show_overlays_rotate,
++                      store_overlays_rotate),
++      __ATTR(phys_addr, S_IRUGO, show_phys, NULL),
++      __ATTR(virt_addr, S_IRUGO, show_virt, NULL),
++};
++
++int omapfb_create_sysfs(struct omapfb2_device *fbdev)
++{
++      int i;
++      int r;
++
++      DBG("create sysfs for fbs\n");
++      for (i = 0; i < fbdev->num_fbs; i++) {
++              int t;
++              for (t = 0; t < ARRAY_SIZE(omapfb_attrs); t++) {
++                      r = device_create_file(fbdev->fbs[i]->dev,
++                                      &omapfb_attrs[t]);
++
++                      if (r) {
++                              dev_err(fbdev->dev, "failed to create sysfs "
++                                              "file\n");
++                              return r;
++                      }
++              }
++      }
++
++      return 0;
++}
++
++void omapfb_remove_sysfs(struct omapfb2_device *fbdev)
++{
++      int i, t;
++
++      DBG("remove sysfs for fbs\n");
++      for (i = 0; i < fbdev->num_fbs; i++) {
++              for (t = 0; t < ARRAY_SIZE(omapfb_attrs); t++)
++                      device_remove_file(fbdev->fbs[i]->dev,
++                                      &omapfb_attrs[t]);
++      }
++}
++
+diff --git a/drivers/video/omap2/omapfb/omapfb.h b/drivers/video/omap2/omapfb/omapfb.h
+new file mode 100644
+index 0000000..d9ee986
+--- /dev/null
++++ b/drivers/video/omap2/omapfb/omapfb.h
+@@ -0,0 +1,146 @@
++/*
++ * linux/drivers/video/omap2/omapfb.h
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * Some code and ideas taken from drivers/video/omap/ driver
++ * by Imre Deak.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef __DRIVERS_VIDEO_OMAP2_OMAPFB_H__
++#define __DRIVERS_VIDEO_OMAP2_OMAPFB_H__
++
++#ifdef CONFIG_FB_OMAP2_DEBUG_SUPPORT
++#define DEBUG
++#endif
++
++#include <mach/display.h>
++
++#ifdef DEBUG
++extern unsigned int omapfb_debug;
++#define DBG(format, ...) \
++      if (omapfb_debug) \
++              printk(KERN_DEBUG "OMAPFB: " format, ## __VA_ARGS__)
++#else
++#define DBG(format, ...)
++#endif
++
++#define FB2OFB(fb_info) ((struct omapfb_info *)(fb_info->par))
++
++/* max number of overlays to which a framebuffer data can be direct */
++#define OMAPFB_MAX_OVL_PER_FB 3
++
++struct omapfb2_mem_region {
++      u32             paddr;
++      void __iomem    *vaddr;
++      struct vrfb     vrfb;
++      unsigned long   size;
++      u8              type;           /* OMAPFB_PLANE_MEM_* */
++      bool            alloc;          /* allocated by the driver */
++      bool            map;            /* kernel mapped by the driver */
++};
++
++/* appended to fb_info */
++struct omapfb_info {
++      int id;
++      struct omapfb2_mem_region region;
++      atomic_t map_count;
++      int num_overlays;
++      struct omap_overlay *overlays[OMAPFB_MAX_OVL_PER_FB];
++      struct omapfb2_device *fbdev;
++      enum omap_dss_rotation_type rotation_type;
++      u8 rotation[OMAPFB_MAX_OVL_PER_FB];
++      bool mirror;
++};
++
++struct omapfb2_device {
++      struct device *dev;
++      struct mutex  mtx;
++
++      u32 pseudo_palette[17];
++
++      int state;
++
++      unsigned num_fbs;
++      struct fb_info *fbs[10];
++
++      unsigned num_displays;
++      struct omap_dss_device *displays[10];
++      unsigned num_overlays;
++      struct omap_overlay *overlays[10];
++      unsigned num_managers;
++      struct omap_overlay_manager *managers[10];
++};
++
++struct omapfb_colormode {
++      enum omap_color_mode dssmode;
++      u32 bits_per_pixel;
++      u32 nonstd;
++      struct fb_bitfield red;
++      struct fb_bitfield green;
++      struct fb_bitfield blue;
++      struct fb_bitfield transp;
++};
++
++void set_fb_fix(struct fb_info *fbi);
++int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var);
++int omapfb_realloc_fbmem(struct fb_info *fbi, unsigned long size, int type);
++int omapfb_apply_changes(struct fb_info *fbi, int init);
++
++int omapfb_create_sysfs(struct omapfb2_device *fbdev);
++void omapfb_remove_sysfs(struct omapfb2_device *fbdev);
++
++int omapfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg);
++
++int dss_mode_to_fb_mode(enum omap_color_mode dssmode,
++                      struct fb_var_screeninfo *var);
++
++/* find the display connected to this fb, if any */
++static inline struct omap_dss_device *fb2display(struct fb_info *fbi)
++{
++      struct omapfb_info *ofbi = FB2OFB(fbi);
++      int i;
++
++      /* XXX: returns the display connected to first attached overlay */
++      for (i = 0; i < ofbi->num_overlays; i++) {
++              if (ofbi->overlays[i]->manager)
++                      return ofbi->overlays[i]->manager->device;
++      }
++
++      return NULL;
++}
++
++static inline void omapfb_lock(struct omapfb2_device *fbdev)
++{
++      mutex_lock(&fbdev->mtx);
++}
++
++static inline void omapfb_unlock(struct omapfb2_device *fbdev)
++{
++      mutex_unlock(&fbdev->mtx);
++}
++
++static inline int omapfb_overlay_enable(struct omap_overlay *ovl,
++              int enable)
++{
++      struct omap_overlay_info info;
++
++      ovl->get_overlay_info(ovl, &info);
++      info.enabled = enable;
++      return ovl->set_overlay_info(ovl, &info);
++}
++
++#endif
+diff --git a/include/linux/omapfb.h b/include/linux/omapfb.h
+index a3611d3..52e0987 100644
+--- a/include/linux/omapfb.h
++++ b/include/linux/omapfb.h
+@@ -24,6 +24,7 @@
+ #ifndef __LINUX_OMAPFB_H__
+ #define __LINUX_OMAPFB_H__
+ 
++#include <linux/fb.h>
+ #include <linux/ioctl.h>
+ #include <linux/types.h>
+ 
+@@ -50,6 +51,11 @@
+ #define OMAPFB_UPDATE_WINDOW  OMAP_IOW(54, struct omapfb_update_window)
+ #define OMAPFB_SETUP_MEM      OMAP_IOW(55, struct omapfb_mem_info)
+ #define OMAPFB_QUERY_MEM      OMAP_IOW(56, struct omapfb_mem_info)
++#define OMAPFB_WAITFORVSYNC   OMAP_IO(57)
++#define OMAPFB_MEMORY_READ    OMAP_IOR(58, struct omapfb_memory_read)
++#define OMAPFB_GET_OVERLAY_COLORMODE OMAP_IOR(59, struct omapfb_ovl_colormode)
++#define OMAPFB_WAITFORGO      OMAP_IO(60)
++#define OMAPFB_GET_VRAM_INFO  OMAP_IOR(61, struct omapfb_vram_info)
+ 
+ #define OMAPFB_CAPS_GENERIC_MASK      0x00000fff
+ #define OMAPFB_CAPS_LCDC_MASK         0x00fff000
+@@ -87,6 +93,13 @@ enum omapfb_color_format {
+       OMAPFB_COLOR_CLUT_1BPP,
+       OMAPFB_COLOR_RGB444,
+       OMAPFB_COLOR_YUY422,
++
++      OMAPFB_COLOR_ARGB16,
++      OMAPFB_COLOR_RGB24U,    /* RGB24, 32-bit container */
++      OMAPFB_COLOR_RGB24P,    /* RGB24, 24-bit container */
++      OMAPFB_COLOR_ARGB32,
++      OMAPFB_COLOR_RGBA32,
++      OMAPFB_COLOR_RGBX32,
+ };
+ 
+ struct omapfb_update_window {
+@@ -158,6 +171,33 @@ enum omapfb_update_mode {
+       OMAPFB_MANUAL_UPDATE
+ };
+ 
++struct omapfb_memory_read {
++      __u16 x;
++      __u16 y;
++      __u16 w;
++      __u16 h;
++      size_t buffer_size;
++      void __user *buffer;
++};
++
++struct omapfb_ovl_colormode {
++      __u8 overlay_idx;
++      __u8 mode_idx;
++      __u32 bits_per_pixel;
++      __u32 nonstd;
++      struct fb_bitfield red;
++      struct fb_bitfield green;
++      struct fb_bitfield blue;
++      struct fb_bitfield transp;
++};
++
++struct omapfb_vram_info {
++      __u32 total;
++      __u32 free;
++      __u32 largest_free_block;
++      __u32 reserved[5];
++};
++
+ #ifdef __KERNEL__
+ 
+ #include <mach/board.h>
+@@ -173,6 +213,11 @@ struct omapfb_mem_region {
+       void __iomem    *vaddr;
+       unsigned long   size;
+       u8              type;           /* OMAPFB_PLANE_MEM_* */
++      enum omapfb_color_format format;/* OMAPFB_COLOR_* */
++      unsigned        format_used:1;  /* Must be set when format is set.
++                                       * Needed b/c of the badly chosen 0
++                                       * base for OMAPFB_COLOR_* values
++                                       */
+       unsigned        alloc:1;        /* allocated by the driver */
+       unsigned        map:1;          /* kernel mapped by the driver */
+ };
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-2.6.31/dss2/0016-OMAP-DSS2-Add-DPI-panel-drivers.patch b/recipes/linux/linux-omap-2.6.31/dss2/0016-OMAP-DSS2-Add-DPI-panel-drivers.patch
new file mode 100644 (file)
index 0000000..fd9db5a
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.31/dss2/0016-OMAP-DSS2-Add-DPI-panel-drivers.patch
@@ -0,0 +1,471 @@
+From e2ddc67b0d9a3450382110edfaca18ecd44804bc Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Tue, 4 Aug 2009 16:41:45 +0300
+Subject: [PATCH 16/18] OMAP: DSS2: Add DPI panel drivers
+
+- Generic panel
+- Samsung LTE430WQ-F0C LCD Panel
+- Sharp LS037V7DW01 LCD Panel
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ drivers/video/omap2/Kconfig                        |    1 +
+ drivers/video/omap2/Makefile                       |    1 +
+ drivers/video/omap2/displays/Kconfig               |   22 +++
+ drivers/video/omap2/displays/Makefile              |    3 +
+ drivers/video/omap2/displays/panel-generic.c       |  104 +++++++++++++
+ .../omap2/displays/panel-samsung-lte430wq-f0c.c    |  113 +++++++++++++++
+ .../video/omap2/displays/panel-sharp-ls037v7dw01.c |  153 ++++++++++++++++++++
+ 7 files changed, 397 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/video/omap2/displays/Kconfig
+ create mode 100644 drivers/video/omap2/displays/Makefile
+ create mode 100644 drivers/video/omap2/displays/panel-generic.c
+ create mode 100644 drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c
+ create mode 100644 drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
+
+diff --git a/drivers/video/omap2/Kconfig b/drivers/video/omap2/Kconfig
+index 3e60d7e..d877c36 100644
+--- a/drivers/video/omap2/Kconfig
++++ b/drivers/video/omap2/Kconfig
+@@ -6,3 +6,4 @@ config OMAP2_VRFB
+ 
+ source "drivers/video/omap2/dss/Kconfig"
+ source "drivers/video/omap2/omapfb/Kconfig"
++source "drivers/video/omap2/displays/Kconfig"
+diff --git a/drivers/video/omap2/Makefile b/drivers/video/omap2/Makefile
+index 3ba6ef5..d853d05 100644
+--- a/drivers/video/omap2/Makefile
++++ b/drivers/video/omap2/Makefile
+@@ -3,3 +3,4 @@ obj-$(CONFIG_OMAP2_VRFB) += vrfb.o
+ 
+ obj-y += dss/
+ obj-y += omapfb/
++obj-y += displays/
+diff --git a/drivers/video/omap2/displays/Kconfig b/drivers/video/omap2/displays/Kconfig
+new file mode 100644
+index 0000000..396905d
+--- /dev/null
++++ b/drivers/video/omap2/displays/Kconfig
+@@ -0,0 +1,22 @@
++menu "OMAP2/3 Display Device Drivers"
++        depends on OMAP2_DSS
++
++config PANEL_GENERIC
++        tristate "Generic Panel"
++        help
++        Generic panel driver.
++        Used for DVI output for Beagle and OMAP3 SDP.
++
++config PANEL_SAMSUNG_LTE430WQ_F0C
++        tristate "Samsung LTE430WQ-F0C LCD Panel"
++        depends on OMAP2_DSS
++        help
++          LCD Panel used on Overo Palo43
++
++config PANEL_SHARP_LS037V7DW01
++        tristate "Sharp LS037V7DW01 LCD Panel"
++        depends on OMAP2_DSS
++        help
++          LCD Panel used in TI's SDP3430 and EVM boards
++
++endmenu
+diff --git a/drivers/video/omap2/displays/Makefile b/drivers/video/omap2/displays/Makefile
+new file mode 100644
+index 0000000..a26bbd2
+--- /dev/null
++++ b/drivers/video/omap2/displays/Makefile
+@@ -0,0 +1,3 @@
++obj-$(CONFIG_PANEL_GENERIC) += panel-generic.o
++obj-$(CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C) += panel-samsung-lte430wq-f0c.o
++obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o
+diff --git a/drivers/video/omap2/displays/panel-generic.c b/drivers/video/omap2/displays/panel-generic.c
+new file mode 100644
+index 0000000..738147e
+--- /dev/null
++++ b/drivers/video/omap2/displays/panel-generic.c
+@@ -0,0 +1,104 @@
++/*
++ * Generic panel support
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++
++#include <mach/display.h>
++
++static struct omap_video_timings generic_panel_timings = {
++      /* 640 x 480 @ 60 Hz  Reduced blanking VESA CVT 0.31M3-R */
++      .x_res          = 640,
++      .y_res          = 480,
++      .pixel_clock    = 23500,
++      .hfp            = 48,
++      .hsw            = 32,
++      .hbp            = 80,
++      .vfp            = 3,
++      .vsw            = 4,
++      .vbp            = 7,
++};
++
++static int generic_panel_probe(struct omap_dss_device *dssdev)
++{
++      dssdev->panel.config = OMAP_DSS_LCD_TFT;
++      dssdev->panel.timings = generic_panel_timings;
++
++      return 0;
++}
++
++static void generic_panel_remove(struct omap_dss_device *dssdev)
++{
++}
++
++static int generic_panel_enable(struct omap_dss_device *dssdev)
++{
++      int r = 0;
++
++      if (dssdev->platform_enable)
++              r = dssdev->platform_enable(dssdev);
++
++      return r;
++}
++
++static void generic_panel_disable(struct omap_dss_device *dssdev)
++{
++      if (dssdev->platform_disable)
++              dssdev->platform_disable(dssdev);
++}
++
++static int generic_panel_suspend(struct omap_dss_device *dssdev)
++{
++      generic_panel_disable(dssdev);
++      return 0;
++}
++
++static int generic_panel_resume(struct omap_dss_device *dssdev)
++{
++      return generic_panel_enable(dssdev);
++}
++
++static struct omap_dss_driver generic_driver = {
++      .probe          = generic_panel_probe,
++      .remove         = generic_panel_remove,
++
++      .enable         = generic_panel_enable,
++      .disable        = generic_panel_disable,
++      .suspend        = generic_panel_suspend,
++      .resume         = generic_panel_resume,
++
++      .driver         = {
++              .name   = "generic_panel",
++              .owner  = THIS_MODULE,
++      },
++};
++
++static int __init generic_panel_drv_init(void)
++{
++      return omap_dss_register_driver(&generic_driver);
++}
++
++static void __exit generic_panel_drv_exit(void)
++{
++      omap_dss_unregister_driver(&generic_driver);
++}
++
++module_init(generic_panel_drv_init);
++module_exit(generic_panel_drv_exit);
++MODULE_LICENSE("GPL");
+diff --git a/drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c b/drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c
+new file mode 100644
+index 0000000..eafe581
+--- /dev/null
++++ b/drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c
+@@ -0,0 +1,113 @@
++/*
++ * LCD panel driver for Samsung LTE430WQ-F0C
++ *
++ * Author: Steve Sakoman <steve@sakoman.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++
++#include <mach/display.h>
++
++static struct omap_video_timings samsung_lte_timings = {
++      .x_res = 480,
++      .y_res = 272,
++
++      .pixel_clock    = 9200,
++
++      .hsw            = 41,
++      .hfp            = 8,
++      .hbp            = 45-41,
++
++      .vsw            = 10,
++      .vfp            = 4,
++      .vbp            = 12-10,
++};
++
++static int samsung_lte_panel_probe(struct omap_dss_device *dssdev)
++{
++      dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
++              OMAP_DSS_LCD_IHS;
++      dssdev->panel.timings = samsung_lte_timings;
++
++      return 0;
++}
++
++static void samsung_lte_panel_remove(struct omap_dss_device *dssdev)
++{
++}
++
++static int samsung_lte_panel_enable(struct omap_dss_device *dssdev)
++{
++      int r = 0;
++
++      /* wait couple of vsyncs until enabling the LCD */
++      msleep(50);
++
++      if (dssdev->platform_enable)
++              r = dssdev->platform_enable(dssdev);
++
++      return r;
++}
++
++static void samsung_lte_panel_disable(struct omap_dss_device *dssdev)
++{
++      if (dssdev->platform_disable)
++              dssdev->platform_disable(dssdev);
++
++      /* wait at least 5 vsyncs after disabling the LCD */
++
++      msleep(100);
++}
++
++static int samsung_lte_panel_suspend(struct omap_dss_device *dssdev)
++{
++      samsung_lte_panel_disable(dssdev);
++      return 0;
++}
++
++static int samsung_lte_panel_resume(struct omap_dss_device *dssdev)
++{
++      return samsung_lte_panel_enable(dssdev);
++}
++
++static struct omap_dss_driver samsung_lte_driver = {
++      .probe          = samsung_lte_panel_probe,
++      .remove         = samsung_lte_panel_remove,
++
++      .enable         = samsung_lte_panel_enable,
++      .disable        = samsung_lte_panel_disable,
++      .suspend        = samsung_lte_panel_suspend,
++      .resume         = samsung_lte_panel_resume,
++
++      .driver         = {
++              .name   = "samsung_lte_panel",
++              .owner  = THIS_MODULE,
++      },
++};
++
++static int __init samsung_lte_panel_drv_init(void)
++{
++      return omap_dss_register_driver(&samsung_lte_driver);
++}
++
++static void __exit samsung_lte_panel_drv_exit(void)
++{
++      omap_dss_unregister_driver(&samsung_lte_driver);
++}
++
++module_init(samsung_lte_panel_drv_init);
++module_exit(samsung_lte_panel_drv_exit);
++MODULE_LICENSE("GPL");
+diff --git a/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
+new file mode 100644
+index 0000000..2f8f0df
+--- /dev/null
++++ b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
+@@ -0,0 +1,153 @@
++/*
++ * LCD panel driver for Sharp LS037V7DW01
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/err.h>
++
++#include <mach/display.h>
++
++struct sharp_data {
++      /* XXX This regulator should actually be in SDP board file, not here,
++       * as it doesn't actually power the LCD, but something else that
++       * affects the output to LCD (I think. Somebody clarify). It doesn't do
++       * harm here, as SDP is the only board using this currently */
++      struct regulator *vdvi_reg;
++};
++
++static struct omap_video_timings sharp_ls_timings = {
++      .x_res = 480,
++      .y_res = 640,
++
++      .pixel_clock    = 19200,
++
++      .hsw            = 2,
++      .hfp            = 1,
++      .hbp            = 28,
++
++      .vsw            = 1,
++      .vfp            = 1,
++      .vbp            = 1,
++};
++
++static int sharp_ls_panel_probe(struct omap_dss_device *dssdev)
++{
++      struct sharp_data *sd;
++
++      dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
++              OMAP_DSS_LCD_IHS;
++      dssdev->panel.acb = 0x28;
++      dssdev->panel.timings = sharp_ls_timings;
++
++      sd = kzalloc(sizeof(*sd), GFP_KERNEL);
++      if (!sd)
++              return -ENOMEM;
++
++      dev_set_drvdata(&dssdev->dev, sd);
++
++      sd->vdvi_reg = regulator_get(&dssdev->dev, "vdvi");
++      if (IS_ERR(sd->vdvi_reg)) {
++              kfree(sd);
++              pr_err("failed to get VDVI regulator\n");
++              return PTR_ERR(sd->vdvi_reg);
++      }
++
++      return 0;
++}
++
++static void sharp_ls_panel_remove(struct omap_dss_device *dssdev)
++{
++      struct sharp_data *sd = dev_get_drvdata(&dssdev->dev);
++
++      regulator_put(sd->vdvi_reg);
++
++      kfree(sd);
++}
++
++static int sharp_ls_panel_enable(struct omap_dss_device *dssdev)
++{
++      struct sharp_data *sd = dev_get_drvdata(&dssdev->dev);
++      int r = 0;
++
++      /* wait couple of vsyncs until enabling the LCD */
++      msleep(50);
++
++      regulator_enable(sd->vdvi_reg);
++
++      if (dssdev->platform_enable)
++              r = dssdev->platform_enable(dssdev);
++
++      return r;
++}
++
++static void sharp_ls_panel_disable(struct omap_dss_device *dssdev)
++{
++      struct sharp_data *sd = dev_get_drvdata(&dssdev->dev);
++
++      if (dssdev->platform_disable)
++              dssdev->platform_disable(dssdev);
++
++      regulator_disable(sd->vdvi_reg);
++
++      /* wait at least 5 vsyncs after disabling the LCD */
++
++      msleep(100);
++}
++
++static int sharp_ls_panel_suspend(struct omap_dss_device *dssdev)
++{
++      sharp_ls_panel_disable(dssdev);
++      return 0;
++}
++
++static int sharp_ls_panel_resume(struct omap_dss_device *dssdev)
++{
++      return sharp_ls_panel_enable(dssdev);
++}
++
++static struct omap_dss_driver sharp_ls_driver = {
++      .probe          = sharp_ls_panel_probe,
++      .remove         = sharp_ls_panel_remove,
++
++      .enable         = sharp_ls_panel_enable,
++      .disable        = sharp_ls_panel_disable,
++      .suspend        = sharp_ls_panel_suspend,
++      .resume         = sharp_ls_panel_resume,
++
++      .driver         = {
++              .name   = "sharp_ls_panel",
++              .owner  = THIS_MODULE,
++      },
++};
++
++static int __init sharp_ls_panel_drv_init(void)
++{
++      return omap_dss_register_driver(&sharp_ls_driver);
++}
++
++static void __exit sharp_ls_panel_drv_exit(void)
++{
++      omap_dss_unregister_driver(&sharp_ls_driver);
++}
++
++module_init(sharp_ls_panel_drv_init);
++module_exit(sharp_ls_panel_drv_exit);
++MODULE_LICENSE("GPL");
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-2.6.31/dss2/0017-OMAP-DSS2-Taal-DSI-command-mode-panel-driver.patch b/recipes/linux/linux-omap-2.6.31/dss2/0017-OMAP-DSS2-Taal-DSI-command-mode-panel-driver.patch
new file mode 100644 (file)
index 0000000..c58ce9d
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.31/dss2/0017-OMAP-DSS2-Taal-DSI-command-mode-panel-driver.patch
@@ -0,0 +1,947 @@
+From fc8cd50c04b519f3839e9dc505532e725c7af080 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Fri, 7 Aug 2009 14:45:05 +0300
+Subject: [PATCH 17/18] OMAP: DSS2: Taal DSI command mode panel driver
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+---
+ drivers/video/omap2/displays/Kconfig      |    6 +
+ drivers/video/omap2/displays/Makefile     |    2 +
+ drivers/video/omap2/displays/panel-taal.c |  900 +++++++++++++++++++++++++++++
+ 3 files changed, 908 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/video/omap2/displays/panel-taal.c
+
+diff --git a/drivers/video/omap2/displays/Kconfig b/drivers/video/omap2/displays/Kconfig
+index 396905d..79d2861 100644
+--- a/drivers/video/omap2/displays/Kconfig
++++ b/drivers/video/omap2/displays/Kconfig
+@@ -19,4 +19,10 @@ config PANEL_SHARP_LS037V7DW01
+         help
+           LCD Panel used in TI's SDP3430 and EVM boards
+ 
++config PANEL_TAAL
++        tristate "Taal DSI Panel"
++        depends on OMAP2_DSS_DSI
++        help
++          Taal DSI command mode panel from TPO.
++
+ endmenu
+diff --git a/drivers/video/omap2/displays/Makefile b/drivers/video/omap2/displays/Makefile
+index a26bbd2..d44e765 100644
+--- a/drivers/video/omap2/displays/Makefile
++++ b/drivers/video/omap2/displays/Makefile
+@@ -1,3 +1,5 @@
+ obj-$(CONFIG_PANEL_GENERIC) += panel-generic.o
+ obj-$(CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C) += panel-samsung-lte430wq-f0c.o
+ obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o
++
++obj-$(CONFIG_PANEL_TAAL) += panel-taal.o
+diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c
+new file mode 100644
+index 0000000..84f0d47
+--- /dev/null
++++ b/drivers/video/omap2/displays/panel-taal.c
+@@ -0,0 +1,900 @@
++/*
++ * Taal DSI command mode panel
++ *
++ * Copyright (C) 2009 Nokia Corporation
++ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++/*#define DEBUG*/
++
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/jiffies.h>
++#include <linux/sched.h>
++#include <linux/backlight.h>
++#include <linux/fb.h>
++#include <linux/interrupt.h>
++#include <linux/gpio.h>
++#include <linux/completion.h>
++
++#include <mach/display.h>
++
++/* DSI Virtual channel. Hardcoded for now. */
++#define TCH 0
++
++#define DCS_READ_NUM_ERRORS   0x05
++#define DCS_READ_POWER_MODE   0x0a
++#define DCS_READ_MADCTL               0x0b
++#define DCS_READ_PIXEL_FORMAT 0x0c
++#define DCS_SLEEP_IN          0x10
++#define DCS_SLEEP_OUT         0x11
++#define DCS_DISPLAY_OFF               0x28
++#define DCS_DISPLAY_ON                0x29
++#define DCS_COLUMN_ADDR               0x2a
++#define DCS_PAGE_ADDR         0x2b
++#define DCS_MEMORY_WRITE      0x2c
++#define DCS_TEAR_OFF          0x34
++#define DCS_TEAR_ON           0x35
++#define DCS_MEM_ACC_CTRL      0x36
++#define DCS_PIXEL_FORMAT      0x3a
++#define DCS_BRIGHTNESS                0x51
++#define DCS_CTRL_DISPLAY      0x53
++#define DCS_WRITE_CABC                0x55
++#define DCS_READ_CABC         0x56
++#define DCS_GET_ID1           0xda
++#define DCS_GET_ID2           0xdb
++#define DCS_GET_ID3           0xdc
++
++struct taal_data {
++      struct backlight_device *bldev;
++
++      unsigned long   hw_guard_end;   /* next value of jiffies when we can
++                                       * issue the next sleep in/out command
++                                       */
++      unsigned long   hw_guard_wait;  /* max guard time in jiffies */
++
++      struct omap_dss_device *dssdev;
++
++      bool enabled;
++      u8 rotate;
++      bool mirror;
++
++      bool te_enabled;
++      bool use_ext_te;
++      struct completion te_completion;
++
++      bool use_dsi_bl;
++
++      bool cabc_broken;
++      unsigned cabc_mode;
++
++      bool intro_printed;
++};
++
++static void hw_guard_start(struct taal_data *td, int guard_msec)
++{
++      td->hw_guard_wait = msecs_to_jiffies(guard_msec);
++      td->hw_guard_end = jiffies + td->hw_guard_wait;
++}
++
++static void hw_guard_wait(struct taal_data *td)
++{
++      unsigned long wait = td->hw_guard_end - jiffies;
++
++      if ((long)wait > 0 && wait <= td->hw_guard_wait) {
++              set_current_state(TASK_UNINTERRUPTIBLE);
++              schedule_timeout(wait);
++      }
++}
++
++static int taal_dcs_read_1(u8 dcs_cmd, u8 *data)
++{
++      int r;
++      u8 buf[1];
++
++      r = dsi_vc_dcs_read(TCH, dcs_cmd, buf, 1);
++
++      if (r < 0)
++              return r;
++
++      *data = buf[0];
++
++      return 0;
++}
++
++static int taal_dcs_write_0(u8 dcs_cmd)
++{
++      return dsi_vc_dcs_write(TCH, &dcs_cmd, 1);
++}
++
++static int taal_dcs_write_1(u8 dcs_cmd, u8 param)
++{
++      u8 buf[2];
++      buf[0] = dcs_cmd;
++      buf[1] = param;
++      return dsi_vc_dcs_write(TCH, buf, 2);
++}
++
++static int taal_sleep_in(struct taal_data *td)
++
++{
++      u8 cmd;
++      int r;
++
++      hw_guard_wait(td);
++
++      cmd = DCS_SLEEP_IN;
++      r = dsi_vc_dcs_write_nosync(TCH, &cmd, 1);
++      if (r)
++              return r;
++
++      hw_guard_start(td, 120);
++
++      msleep(5);
++
++      return 0;
++}
++
++static int taal_sleep_out(struct taal_data *td)
++{
++      int r;
++
++      hw_guard_wait(td);
++
++      r = taal_dcs_write_0(DCS_SLEEP_OUT);
++      if (r)
++              return r;
++
++      hw_guard_start(td, 120);
++
++      msleep(5);
++
++      return 0;
++}
++
++static int taal_get_id(u8 *id1, u8 *id2, u8 *id3)
++{
++      int r;
++
++      r = taal_dcs_read_1(DCS_GET_ID1, id1);
++      if (r)
++              return r;
++      r = taal_dcs_read_1(DCS_GET_ID2, id2);
++      if (r)
++              return r;
++      r = taal_dcs_read_1(DCS_GET_ID3, id3);
++      if (r)
++              return r;
++
++      return 0;
++}
++
++static int taal_set_addr_mode(u8 rotate, bool mirror)
++{
++      int r;
++      u8 mode;
++      int b5, b6, b7;
++
++      r = taal_dcs_read_1(DCS_READ_MADCTL, &mode);
++      if (r)
++              return r;
++
++      switch (rotate) {
++      default:
++      case 0:
++              b7 = 0;
++              b6 = 0;
++              b5 = 0;
++              break;
++      case 1:
++              b7 = 0;
++              b6 = 1;
++              b5 = 1;
++              break;
++      case 2:
++              b7 = 1;
++              b6 = 1;
++              b5 = 0;
++              break;
++      case 3:
++              b7 = 1;
++              b6 = 0;
++              b5 = 1;
++              break;
++      }
++
++      if (mirror)
++              b6 = !b6;
++
++      mode &= ~((1<<7) | (1<<6) | (1<<5));
++      mode |= (b7 << 7) | (b6 << 6) | (b5 << 5);
++
++      return taal_dcs_write_1(DCS_MEM_ACC_CTRL, mode);
++}
++
++static int taal_set_update_window(u16 x, u16 y, u16 w, u16 h)
++{
++      int r;
++      u16 x1 = x;
++      u16 x2 = x + w - 1;
++      u16 y1 = y;
++      u16 y2 = y + h - 1;
++
++      u8 buf[5];
++      buf[0] = DCS_COLUMN_ADDR;
++      buf[1] = (x1 >> 8) & 0xff;
++      buf[2] = (x1 >> 0) & 0xff;
++      buf[3] = (x2 >> 8) & 0xff;
++      buf[4] = (x2 >> 0) & 0xff;
++
++      r = dsi_vc_dcs_write_nosync(TCH, buf, sizeof(buf));
++      if (r)
++              return r;
++
++      buf[0] = DCS_PAGE_ADDR;
++      buf[1] = (y1 >> 8) & 0xff;
++      buf[2] = (y1 >> 0) & 0xff;
++      buf[3] = (y2 >> 8) & 0xff;
++      buf[4] = (y2 >> 0) & 0xff;
++
++      r = dsi_vc_dcs_write_nosync(TCH, buf, sizeof(buf));
++      if (r)
++              return r;
++
++      dsi_vc_send_bta_sync(TCH);
++
++      return r;
++}
++
++static int taal_bl_update_status(struct backlight_device *dev)
++{
++      struct omap_dss_device *dssdev = dev_get_drvdata(&dev->dev);
++      struct taal_data *td = dev_get_drvdata(&dssdev->dev);
++      int r;
++      int level;
++
++      if (dev->props.fb_blank == FB_BLANK_UNBLANK &&
++                      dev->props.power == FB_BLANK_UNBLANK)
++              level = dev->props.brightness;
++      else
++              level = 0;
++
++      dev_dbg(&dssdev->dev, "update brightness to %d\n", level);
++
++      if (td->use_dsi_bl) {
++              if (td->enabled) {
++                      dsi_bus_lock();
++                      r = taal_dcs_write_1(DCS_BRIGHTNESS, level);
++                      dsi_bus_unlock();
++                      if (r)
++                              return r;
++              }
++      } else {
++              if (!dssdev->set_backlight)
++                      return -EINVAL;
++
++              r = dssdev->set_backlight(dssdev, level);
++              if (r)
++                      return r;
++      }
++
++      return 0;
++}
++
++static int taal_bl_get_intensity(struct backlight_device *dev)
++{
++      if (dev->props.fb_blank == FB_BLANK_UNBLANK &&
++                      dev->props.power == FB_BLANK_UNBLANK)
++              return dev->props.brightness;
++
++      return 0;
++}
++
++static struct backlight_ops taal_bl_ops = {
++      .get_brightness = taal_bl_get_intensity,
++      .update_status  = taal_bl_update_status,
++};
++
++static void taal_get_timings(struct omap_dss_device *dssdev,
++                      struct omap_video_timings *timings)
++{
++      *timings = dssdev->panel.timings;
++}
++
++static void taal_get_resolution(struct omap_dss_device *dssdev,
++              u16 *xres, u16 *yres)
++{
++      struct taal_data *td = dev_get_drvdata(&dssdev->dev);
++
++      if (td->rotate == 0 || td->rotate == 2) {
++              *xres = dssdev->panel.timings.x_res;
++              *yres = dssdev->panel.timings.y_res;
++      } else {
++              *yres = dssdev->panel.timings.x_res;
++              *xres = dssdev->panel.timings.y_res;
++      }
++}
++
++static irqreturn_t taal_te_isr(int irq, void *data)
++{
++      struct omap_dss_device *dssdev = data;
++      struct taal_data *td = dev_get_drvdata(&dssdev->dev);
++
++      complete_all(&td->te_completion);
++
++      return IRQ_HANDLED;
++}
++
++static ssize_t taal_num_errors_show(struct device *dev,
++              struct device_attribute *attr, char *buf)
++{
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++      struct taal_data *td = dev_get_drvdata(&dssdev->dev);
++      u8 errors;
++      int r;
++
++      if (td->enabled) {
++              dsi_bus_lock();
++              r = taal_dcs_read_1(DCS_READ_NUM_ERRORS, &errors);
++              dsi_bus_unlock();
++      } else {
++              r = -ENODEV;
++      }
++
++      if (r)
++              return r;
++
++      return snprintf(buf, PAGE_SIZE, "%d\n", errors);
++}
++
++static ssize_t taal_hw_revision_show(struct device *dev,
++              struct device_attribute *attr, char *buf)
++{
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++      struct taal_data *td = dev_get_drvdata(&dssdev->dev);
++      u8 id1, id2, id3;
++      int r;
++
++      if (td->enabled) {
++              dsi_bus_lock();
++              r = taal_get_id(&id1, &id2, &id3);
++              dsi_bus_unlock();
++      } else {
++              r = -ENODEV;
++      }
++
++      if (r)
++              return r;
++
++      return snprintf(buf, PAGE_SIZE, "%02x.%02x.%02x\n", id1, id2, id3);
++}
++
++static const char *cabc_modes[] = {
++      "off",          /* used also always when CABC is not supported */
++      "ui",
++      "still-image",
++      "moving-image",
++};
++
++static ssize_t show_cabc_mode(struct device *dev,
++              struct device_attribute *attr,
++              char *buf)
++{
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++      struct taal_data *td = dev_get_drvdata(&dssdev->dev);
++      const char *mode_str;
++      int mode;
++      int len;
++
++      mode = td->cabc_mode;
++
++      mode_str = "unknown";
++      if (mode >= 0 && mode < ARRAY_SIZE(cabc_modes))
++              mode_str = cabc_modes[mode];
++      len = snprintf(buf, PAGE_SIZE, "%s\n", mode_str);
++
++      return len < PAGE_SIZE - 1 ? len : PAGE_SIZE - 1;
++}
++
++static ssize_t store_cabc_mode(struct device *dev,
++              struct device_attribute *attr,
++              const char *buf, size_t count)
++{
++      struct omap_dss_device *dssdev = to_dss_device(dev);
++      struct taal_data *td = dev_get_drvdata(&dssdev->dev);
++      int i;
++
++      for (i = 0; i < ARRAY_SIZE(cabc_modes); i++) {
++              if (sysfs_streq(cabc_modes[i], buf))
++                      break;
++      }
++
++      if (i == ARRAY_SIZE(cabc_modes))
++              return -EINVAL;
++
++      if (td->enabled) {
++              dsi_bus_lock();
++              if (!td->cabc_broken)
++                      taal_dcs_write_1(DCS_WRITE_CABC, i);
++              dsi_bus_unlock();
++      }
++
++      td->cabc_mode = i;
++
++      return count;
++}
++
++static ssize_t show_cabc_available_modes(struct device *dev,
++              struct device_attribute *attr,
++              char *buf)
++{
++      int len;
++      int i;
++
++      for (i = 0, len = 0;
++           len < PAGE_SIZE && i < ARRAY_SIZE(cabc_modes); i++)
++              len += snprintf(&buf[len], PAGE_SIZE - len, "%s%s%s",
++                      i ? " " : "", cabc_modes[i],
++                      i == ARRAY_SIZE(cabc_modes) - 1 ? "\n" : "");
++
++      return len < PAGE_SIZE ? len : PAGE_SIZE - 1;
++}
++
++static DEVICE_ATTR(num_dsi_errors, S_IRUGO, taal_num_errors_show, NULL);
++static DEVICE_ATTR(hw_revision, S_IRUGO, taal_hw_revision_show, NULL);
++static DEVICE_ATTR(cabc_mode, S_IRUGO | S_IWUSR,
++              show_cabc_mode, store_cabc_mode);
++static DEVICE_ATTR(cabc_available_modes, S_IRUGO,
++              show_cabc_available_modes, NULL);
++
++static struct attribute *taal_attrs[] = {
++      &dev_attr_num_dsi_errors.attr,
++      &dev_attr_hw_revision.attr,
++      &dev_attr_cabc_mode.attr,
++      &dev_attr_cabc_available_modes.attr,
++      NULL,
++};
++
++static struct attribute_group taal_attr_group = {
++      .attrs = taal_attrs,
++};
++
++static int taal_probe(struct omap_dss_device *dssdev)
++{
++      struct taal_data *td;
++      struct backlight_device *bldev;
++      int r;
++
++      const struct omap_video_timings taal_panel_timings = {
++              .x_res          = 864,
++              .y_res          = 480,
++      };
++
++      dev_dbg(&dssdev->dev, "probe\n");
++
++      dssdev->panel.config = OMAP_DSS_LCD_TFT;
++      dssdev->panel.timings = taal_panel_timings;
++      dssdev->ctrl.pixel_size = 24;
++
++      td = kzalloc(sizeof(*td), GFP_KERNEL);
++      if (!td) {
++              r = -ENOMEM;
++              goto err0;
++      }
++
++      dev_set_drvdata(&dssdev->dev, td);
++
++      dssdev->get_timings = taal_get_timings;
++      dssdev->get_resolution = taal_get_resolution;
++
++      /* if no platform set_backlight() defined, presume DSI backlight
++       * control */
++      if (!dssdev->set_backlight)
++              td->use_dsi_bl = true;
++
++      bldev = backlight_device_register("taal", &dssdev->dev, dssdev,
++                      &taal_bl_ops);
++      if (IS_ERR(bldev)) {
++              r = PTR_ERR(bldev);
++              goto err1;
++      }
++
++      td->bldev = bldev;
++
++      bldev->props.fb_blank = FB_BLANK_UNBLANK;
++      bldev->props.power = FB_BLANK_UNBLANK;
++      if (td->use_dsi_bl) {
++              bldev->props.max_brightness = 255;
++              bldev->props.brightness = 255;
++      } else {
++              bldev->props.max_brightness = 127;
++              bldev->props.brightness = 127;
++      }
++
++      taal_bl_update_status(bldev);
++
++      if (dssdev->phy.dsi.ext_te) {
++              int gpio = dssdev->phy.dsi.ext_te_gpio;
++
++              r = gpio_request(gpio, "taal irq");
++              if (r) {
++                      dev_err(&dssdev->dev, "GPIO request failed\n");
++                      goto err2;
++              }
++
++              gpio_direction_input(gpio);
++
++              r = request_irq(gpio_to_irq(gpio), taal_te_isr,
++                              IRQF_DISABLED | IRQF_TRIGGER_RISING,
++                              "taal vsync", dssdev);
++
++              if (r) {
++                      dev_err(&dssdev->dev, "IRQ request failed\n");
++                      gpio_free(gpio);
++                      goto err2;
++              }
++
++              init_completion(&td->te_completion);
++
++              td->use_ext_te = true;
++      }
++
++      r = sysfs_create_group(&dssdev->dev.kobj, &taal_attr_group);
++      if (r) {
++              dev_err(&dssdev->dev, "failed to create sysfs files\n");
++              goto err3;
++      }
++
++      return 0;
++err3:
++      if (td->use_ext_te) {
++              int gpio = dssdev->phy.dsi.ext_te_gpio;
++              free_irq(gpio_to_irq(gpio), dssdev);
++              gpio_free(gpio);
++      }
++err2:
++      backlight_device_unregister(bldev);
++err1:
++      kfree(td);
++err0:
++      return r;
++}
++
++static void taal_remove(struct omap_dss_device *dssdev)
++{
++      struct taal_data *td = dev_get_drvdata(&dssdev->dev);
++      struct backlight_device *bldev;
++
++      dev_dbg(&dssdev->dev, "remove\n");
++
++      sysfs_remove_group(&dssdev->dev.kobj, &taal_attr_group);
++
++      if (td->use_ext_te) {
++              int gpio = dssdev->phy.dsi.ext_te_gpio;
++              free_irq(gpio_to_irq(gpio), dssdev);
++              gpio_free(gpio);
++      }
++
++      bldev = td->bldev;
++      bldev->props.power = FB_BLANK_POWERDOWN;
++      taal_bl_update_status(bldev);
++      backlight_device_unregister(bldev);
++
++      kfree(td);
++}
++
++static int taal_enable(struct omap_dss_device *dssdev)
++{
++      struct taal_data *td = dev_get_drvdata(&dssdev->dev);
++      u8 id1, id2, id3;
++      int r;
++
++      dev_dbg(&dssdev->dev, "enable\n");
++
++      if (dssdev->platform_enable) {
++              r = dssdev->platform_enable(dssdev);
++              if (r)
++                      return r;
++      }
++
++      /* it seems we have to wait a bit until taal is ready */
++      msleep(5);
++
++      r = taal_sleep_out(td);
++      if (r)
++              return r;
++
++      r = taal_get_id(&id1, &id2, &id3);
++      if (r)
++              return r;
++
++      /* on early revisions CABC is broken */
++      if (id2 == 0x00 || id2 == 0xff || id2 == 0x81)
++              td->cabc_broken = true;
++
++      taal_dcs_write_1(DCS_BRIGHTNESS, 0xff);
++      taal_dcs_write_1(DCS_CTRL_DISPLAY, (1<<2) | (1<<5)); /* BL | BCTRL */
++
++      taal_dcs_write_1(DCS_PIXEL_FORMAT, 0x7); /* 24bit/pixel */
++
++      taal_set_addr_mode(td->rotate, td->mirror);
++      if (!td->cabc_broken)
++              taal_dcs_write_1(DCS_WRITE_CABC, td->cabc_mode);
++
++      taal_dcs_write_0(DCS_DISPLAY_ON);
++
++      td->enabled = 1;
++
++      if (!td->intro_printed) {
++              dev_info(&dssdev->dev, "revision %02x.%02x.%02x\n",
++                              id1, id2, id3);
++              if (td->cabc_broken)
++                      dev_info(&dssdev->dev,
++                                      "old Taal version, CABC disabled\n");
++              td->intro_printed = true;
++      }
++
++      return 0;
++}
++
++static void taal_disable(struct omap_dss_device *dssdev)
++{
++      struct taal_data *td = dev_get_drvdata(&dssdev->dev);
++
++      dev_dbg(&dssdev->dev, "disable\n");
++
++      taal_dcs_write_0(DCS_DISPLAY_OFF);
++      taal_sleep_in(td);
++
++      /* wait a bit so that the message goes through */
++      msleep(10);
++
++      if (dssdev->platform_disable)
++              dssdev->platform_disable(dssdev);
++
++      td->enabled = 0;
++}
++
++static int taal_suspend(struct omap_dss_device *dssdev)
++{
++      struct taal_data *td = dev_get_drvdata(&dssdev->dev);
++      struct backlight_device *bldev = td->bldev;
++
++      bldev->props.power = FB_BLANK_POWERDOWN;
++      taal_bl_update_status(bldev);
++
++      return 0;
++}
++
++static int taal_resume(struct omap_dss_device *dssdev)
++{
++      struct taal_data *td = dev_get_drvdata(&dssdev->dev);
++      struct backlight_device *bldev = td->bldev;
++
++      bldev->props.power = FB_BLANK_UNBLANK;
++      taal_bl_update_status(bldev);
++
++      return 0;
++}
++
++static void taal_setup_update(struct omap_dss_device *dssdev,
++                                  u16 x, u16 y, u16 w, u16 h)
++{
++      taal_set_update_window(x, y, w, h);
++}
++
++static int taal_enable_te(struct omap_dss_device *dssdev, bool enable)
++{
++      struct taal_data *td = dev_get_drvdata(&dssdev->dev);
++      int r;
++
++      td->te_enabled = enable;
++
++      if (enable)
++              r = taal_dcs_write_1(DCS_TEAR_ON, 0);
++      else
++              r = taal_dcs_write_0(DCS_TEAR_OFF);
++
++      return r;
++}
++
++static int taal_wait_te(struct omap_dss_device *dssdev)
++{
++      struct taal_data *td = dev_get_drvdata(&dssdev->dev);
++      long wait = msecs_to_jiffies(500);
++
++      if (!td->use_ext_te || !td->te_enabled)
++              return 0;
++
++      INIT_COMPLETION(td->te_completion);
++      wait = wait_for_completion_timeout(&td->te_completion, wait);
++      if (wait == 0) {
++              dev_err(&dssdev->dev, "timeout waiting TE\n");
++              return -ETIME;
++      }
++
++      return 0;
++}
++
++static int taal_rotate(struct omap_dss_device *dssdev, u8 rotate)
++{
++      struct taal_data *td = dev_get_drvdata(&dssdev->dev);
++      int r;
++
++      dev_dbg(&dssdev->dev, "rotate %d\n", rotate);
++
++      if (td->enabled) {
++              r = taal_set_addr_mode(rotate, td->mirror);
++
++              if (r)
++                      return r;
++      }
++
++      td->rotate = rotate;
++
++      return 0;
++}
++
++static u8 taal_get_rotate(struct omap_dss_device *dssdev)
++{
++      struct taal_data *td = dev_get_drvdata(&dssdev->dev);
++      return td->rotate;
++}
++
++static int taal_mirror(struct omap_dss_device *dssdev, bool enable)
++{
++      struct taal_data *td = dev_get_drvdata(&dssdev->dev);
++      int r;
++
++      dev_dbg(&dssdev->dev, "mirror %d\n", enable);
++
++      if (td->enabled) {
++              r = taal_set_addr_mode(td->rotate, enable);
++
++              if (r)
++                      return r;
++      }
++
++      td->mirror = enable;
++
++      return 0;
++}
++
++static bool taal_get_mirror(struct omap_dss_device *dssdev)
++{
++      struct taal_data *td = dev_get_drvdata(&dssdev->dev);
++      return td->mirror;
++}
++
++static int taal_run_test(struct omap_dss_device *dssdev, int test_num)
++{
++      u8 id1, id2, id3;
++      int r;
++
++      r = taal_dcs_read_1(DCS_GET_ID1, &id1);
++      if (r)
++              return r;
++      r = taal_dcs_read_1(DCS_GET_ID2, &id2);
++      if (r)
++              return r;
++      r = taal_dcs_read_1(DCS_GET_ID3, &id3);
++      if (r)
++              return r;
++
++      return 0;
++}
++
++static int taal_memory_read(struct omap_dss_device *dssdev,
++              void *buf, size_t size,
++              u16 x, u16 y, u16 w, u16 h)
++{
++      int r;
++      int first = 1;
++      int plen;
++      unsigned buf_used = 0;
++
++      if (size < w * h * 3)
++              return -ENOMEM;
++
++      size = min(w * h * 3,
++                      dssdev->panel.timings.x_res *
++                      dssdev->panel.timings.y_res * 3);
++
++      /* plen 1 or 2 goes into short packet. until checksum error is fixed,
++       * use short packets. plen 32 works, but bigger packets seem to cause
++       * an error. */
++      if (size % 2)
++              plen = 1;
++      else
++              plen = 2;
++
++      taal_setup_update(dssdev, x, y, w, h);
++
++      r = dsi_vc_set_max_rx_packet_size(TCH, plen);
++      if (r)
++              return r;
++
++      while (buf_used < size) {
++              u8 dcs_cmd = first ? 0x2e : 0x3e;
++              first = 0;
++
++              r = dsi_vc_dcs_read(TCH, dcs_cmd,
++                              buf + buf_used, size - buf_used);
++
++              if (r < 0) {
++                      dev_err(&dssdev->dev, "read error\n");
++                      goto err;
++              }
++
++              buf_used += r;
++
++              if (r < plen) {
++                      dev_err(&dssdev->dev, "short read\n");
++                      break;
++              }
++      }
++
++      r = buf_used;
++
++err:
++      dsi_vc_set_max_rx_packet_size(TCH, 1);
++
++      return r;
++}
++
++static struct omap_dss_driver taal_driver = {
++      .probe          = taal_probe,
++      .remove         = taal_remove,
++
++      .enable         = taal_enable,
++      .disable        = taal_disable,
++      .suspend        = taal_suspend,
++      .resume         = taal_resume,
++
++      .setup_update   = taal_setup_update,
++      .enable_te      = taal_enable_te,
++      .wait_for_te    = taal_wait_te,
++      .set_rotate     = taal_rotate,
++      .get_rotate     = taal_get_rotate,
++      .set_mirror     = taal_mirror,
++      .get_mirror     = taal_get_mirror,
++      .run_test       = taal_run_test,
++      .memory_read    = taal_memory_read,
++
++      .driver         = {
++              .name   = "taal",
++              .owner  = THIS_MODULE,
++      },
++};
++
++static int __init taal_init(void)
++{
++      omap_dss_register_driver(&taal_driver);
++
++      return 0;
++}
++
++static void __exit taal_exit(void)
++{
++      omap_dss_unregister_driver(&taal_driver);
++}
++
++module_init(taal_init);
++module_exit(taal_exit);
++
++MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
++MODULE_DESCRIPTION("Taal Driver");
++MODULE_LICENSE("GPL");
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-2.6.31/dss2/0018-OMAP-SDP-Enable-DSS2-for-OMAP3-SDP-board.patch b/recipes/linux/linux-omap-2.6.31/dss2/0018-OMAP-SDP-Enable-DSS2-for-OMAP3-SDP-board.patch
new file mode 100644 (file)
index 0000000..98cd5ad
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.31/dss2/0018-OMAP-SDP-Enable-DSS2-for-OMAP3-SDP-board.patch
@@ -0,0 +1,327 @@
+From 8319bb7f267e0434e2d26f30b6f50ff2b0701bd1 Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Date: Wed, 5 Aug 2009 16:07:26 +0300
+Subject: [PATCH 18/18] OMAP: SDP: Enable DSS2 for OMAP3 SDP board
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+Acked-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/configs/omap_3430sdp_defconfig |   61 +++++++++++-
+ arch/arm/mach-omap2/board-3430sdp.c     |  172 +++++++++++++++++++++++++++---
+ 2 files changed, 214 insertions(+), 19 deletions(-)
+
+diff --git a/arch/arm/configs/omap_3430sdp_defconfig b/arch/arm/configs/omap_3430sdp_defconfig
+index 8fb918d..de063f9 100644
+--- a/arch/arm/configs/omap_3430sdp_defconfig
++++ b/arch/arm/configs/omap_3430sdp_defconfig
+@@ -1314,7 +1314,56 @@ CONFIG_DVB_ISL6421=m
+ #
+ # CONFIG_VGASTATE is not set
+ # CONFIG_VIDEO_OUTPUT_CONTROL is not set
+-# CONFIG_FB is not set
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++CONFIG_FB_CFB_FILLRECT=y
++CONFIG_FB_CFB_COPYAREA=y
++CONFIG_FB_CFB_IMAGEBLIT=y
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++# CONFIG_FB_SYS_FOPS is not set
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_MB862XX is not set
++# CONFIG_FB_BROADSHEET is not set
++# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
++CONFIG_OMAP2_VRAM=y
++CONFIG_OMAP2_VRFB=y
++CONFIG_OMAP2_DSS=y
++CONFIG_OMAP2_VRAM_SIZE=0
++CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
++# CONFIG_OMAP2_DSS_RFBI is not set
++CONFIG_OMAP2_DSS_VENC=y
++# CONFIG_OMAP2_DSS_SDI is not set
++# CONFIG_OMAP2_DSS_DSI is not set
++# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
++CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
++CONFIG_FB_OMAP2=y
++CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
++# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set
++CONFIG_FB_OMAP2_NUM_FBS=3
++
++#
++# OMAP2/3 Display Device Drivers
++#
++CONFIG_PANEL_GENERIC=y
++# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set
++CONFIG_PANEL_SHARP_LS037V7DW01=y
+ # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+ 
+ #
+@@ -1331,6 +1380,16 @@ CONFIG_DISPLAY_SUPPORT=y
+ #
+ # CONFIG_VGA_CONSOLE is not set
+ CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++CONFIG_LOGO_LINUX_MONO=y
++CONFIG_LOGO_LINUX_VGA16=y
++CONFIG_LOGO_LINUX_CLUT224=y
+ CONFIG_SOUND=y
+ CONFIG_SOUND_OSS_CORE=y
+ CONFIG_SND=y
+diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
+index ac262cd..a1ebc3f 100644
+--- a/arch/arm/mach-omap2/board-3430sdp.c
++++ b/arch/arm/mach-omap2/board-3430sdp.c
+@@ -36,6 +36,7 @@
+ #include <mach/common.h>
+ #include <mach/dma.h>
+ #include <mach/gpmc.h>
++#include <mach/display.h>
+ 
+ #include <mach/control.h>
+ #include <mach/keypad.h>
+@@ -148,23 +149,149 @@ static struct spi_board_info sdp3430_spi_board_info[] __initdata = {
+       },
+ };
+ 
+-static struct platform_device sdp3430_lcd_device = {
+-      .name           = "sdp2430_lcd",
+-      .id             = -1,
++
++#define SDP3430_LCD_PANEL_BACKLIGHT_GPIO      8
++#define SDP3430_LCD_PANEL_ENABLE_GPIO         5
++
++static unsigned backlight_gpio;
++static unsigned enable_gpio;
++static int lcd_enabled;
++static int dvi_enabled;
++
++static void __init sdp3430_display_init(void)
++{
++      int r;
++
++      enable_gpio    = SDP3430_LCD_PANEL_ENABLE_GPIO;
++      backlight_gpio = SDP3430_LCD_PANEL_BACKLIGHT_GPIO;
++
++      r = gpio_request(enable_gpio, "LCD reset");
++      if (r) {
++              printk(KERN_ERR "failed to get LCD reset GPIO\n");
++              goto err0;
++      }
++
++      r = gpio_request(backlight_gpio, "LCD Backlight");
++      if (r) {
++              printk(KERN_ERR "failed to get LCD backlight GPIO\n");
++              goto err1;
++      }
++
++      gpio_direction_output(enable_gpio, 0);
++      gpio_direction_output(backlight_gpio, 0);
++
++      return;
++err1:
++      gpio_free(enable_gpio);
++err0:
++      return;
++}
++
++static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev)
++{
++      if (dvi_enabled) {
++              printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
++              return -EINVAL;
++      }
++
++      gpio_direction_output(enable_gpio, 1);
++      gpio_direction_output(backlight_gpio, 1);
++
++      lcd_enabled = 1;
++
++      return 0;
++}
++
++static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev)
++{
++      lcd_enabled = 0;
++
++      gpio_direction_output(enable_gpio, 0);
++      gpio_direction_output(backlight_gpio, 0);
++}
++
++static int sdp3430_panel_enable_dvi(struct omap_dss_device *dssdev)
++{
++      if (lcd_enabled) {
++              printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
++              return -EINVAL;
++      }
++
++      dvi_enabled = 1;
++
++      return 0;
++}
++
++static void sdp3430_panel_disable_dvi(struct omap_dss_device *dssdev)
++{
++      dvi_enabled = 0;
++}
++
++static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev)
++{
++      return 0;
++}
++
++static void sdp3430_panel_disable_tv(struct omap_dss_device *dssdev)
++{
++}
++
++
++static struct omap_dss_device sdp3430_lcd_device = {
++      .name                   = "lcd",
++      .driver_name            = "sharp_ls_panel",
++      .type                   = OMAP_DISPLAY_TYPE_DPI,
++      .phy.dpi.data_lines     = 16,
++      .platform_enable        = sdp3430_panel_enable_lcd,
++      .platform_disable       = sdp3430_panel_disable_lcd,
+ };
+ 
+-static struct regulator_consumer_supply sdp3430_vdac_supply = {
+-      .supply         = "vdac",
+-      .dev            = &sdp3430_lcd_device.dev,
++static struct omap_dss_device sdp3430_dvi_device = {
++      .name                   = "dvi",
++      .driver_name            = "generic_panel",
++      .type                   = OMAP_DISPLAY_TYPE_DPI,
++      .phy.dpi.data_lines     = 24,
++      .platform_enable        = sdp3430_panel_enable_dvi,
++      .platform_disable       = sdp3430_panel_disable_dvi,
+ };
+ 
+-static struct regulator_consumer_supply sdp3430_vdvi_supply = {
+-      .supply         = "vdvi",
+-      .dev            = &sdp3430_lcd_device.dev,
++static struct omap_dss_device sdp3430_tv_device = {
++      .name                   = "tv",
++      .driver_name            = "venc",
++      .type                   = OMAP_DISPLAY_TYPE_VENC,
++      .phy.venc.type          = OMAP_DSS_VENC_TYPE_SVIDEO,
++      .platform_enable        = sdp3430_panel_enable_tv,
++      .platform_disable       = sdp3430_panel_disable_tv,
+ };
+ 
+-static struct platform_device *sdp3430_devices[] __initdata = {
++
++static struct omap_dss_device *sdp3430_dss_devices[] = {
+       &sdp3430_lcd_device,
++      &sdp3430_dvi_device,
++      &sdp3430_tv_device,
++};
++
++static struct omap_dss_board_info sdp3430_dss_data = {
++      .num_devices    = ARRAY_SIZE(sdp3430_dss_devices),
++      .devices        = sdp3430_dss_devices,
++      .default_device = &sdp3430_lcd_device,
++};
++
++static struct platform_device sdp3430_dss_device = {
++      .name           = "omapdss",
++      .id             = -1,
++      .dev            = {
++              .platform_data = &sdp3430_dss_data,
++      },
++};
++
++static struct regulator_consumer_supply sdp3430_vdda_dac_supply = {
++      .supply         = "vdda_dac",
++      .dev            = &sdp3430_dss_device.dev,
++};
++
++static struct platform_device *sdp3430_devices[] __initdata = {
++      &sdp3430_dss_device,
+ };
+ 
+ static void __init omap_3430sdp_init_irq(void)
+@@ -178,13 +305,8 @@ static struct omap_uart_config sdp3430_uart_config __initdata = {
+       .enabled_uarts  = ((1 << 0) | (1 << 1) | (1 << 2)),
+ };
+ 
+-static struct omap_lcd_config sdp3430_lcd_config __initdata = {
+-      .ctrl_name      = "internal",
+-};
+-
+ static struct omap_board_config_kernel sdp3430_config[] __initdata = {
+       { OMAP_TAG_UART,        &sdp3430_uart_config },
+-      { OMAP_TAG_LCD,         &sdp3430_lcd_config },
+ };
+ 
+ static int sdp3430_batt_table[] = {
+@@ -391,22 +513,34 @@ static struct regulator_init_data sdp3430_vdac = {
+                                       | REGULATOR_CHANGE_STATUS,
+       },
+       .num_consumer_supplies  = 1,
+-      .consumer_supplies      = &sdp3430_vdac_supply,
++      .consumer_supplies      = &sdp3430_vdda_dac_supply,
+ };
+ 
+ /* VPLL2 for digital video outputs */
++static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
++      {
++              .supply         = "vdvi",
++              .dev            = &sdp3430_lcd_device.dev,
++      },
++      {
++              .supply         = "vdds_dsi",
++              .dev            = &sdp3430_dss_device.dev,
++      }
++};
++
+ static struct regulator_init_data sdp3430_vpll2 = {
+       .constraints = {
+               .name                   = "VDVI",
+               .min_uV                 = 1800000,
+               .max_uV                 = 1800000,
++              .apply_uV               = true,
+               .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                       | REGULATOR_MODE_STANDBY,
+               .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                       | REGULATOR_CHANGE_STATUS,
+       },
+-      .num_consumer_supplies  = 1,
+-      .consumer_supplies      = &sdp3430_vdvi_supply,
++      .num_consumer_supplies  = ARRAY_SIZE(sdp3430_vpll2_supplies),
++      .consumer_supplies      = sdp3430_vpll2_supplies,
+ };
+ 
+ static struct twl4030_platform_data sdp3430_twldata = {
+@@ -495,6 +629,8 @@ static void __init omap_3430sdp_init(void)
+       omap_serial_init();
+       usb_musb_init();
+       board_smc91x_init();
++
++      sdp3430_display_init();
+ }
+ 
+ static void __init omap_3430sdp_map_io(void)
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap_git.bb b/recipes/linux/linux-omap_git.bb
index 2808455..215f88a 100644 (file)
--- a/recipes/linux/linux-omap_git.bb
+++ b/recipes/linux/linux-omap_git.bb
@@ -23,8 +23,29 @@ SRC_URI_append = " \
                   file://ehci-phy-reset.patch;patch=1 \
                   file://ehci.patch;patch=1 \
                   file://0001-implement-TIF_RESTORE_SIGMASK-support-and-enable-the.patch;patch=1 \
+                  file://cache/l1cache-shift.patch;patch=1 \
+                  file://cache/copy-page-tweak.patch;patch=1 \
+                  file://dss2/0001-OMAP2-Add-funcs-for-writing-SMS_ROT_-registers.patch;patch=1 \
+                  file://dss2/0002-OMAP-OMAPFB-split-omapfb.h.patch;patch=1 \
+                  file://dss2/0003-OMAP-OMAPFB-add-omapdss-device.patch;patch=1 \
+                  file://dss2/0004-OMAP-Add-VRAM-manager.patch;patch=1 \
+                  file://dss2/0005-OMAP-Add-support-for-VRFB-rotation-engine.patch;patch=1 \
+                  file://dss2/0006-OMAP-DSS2-Documentation-for-DSS2.patch;patch=1 \
+                  file://dss2/0007-OMAP-DSS2-Display-Subsystem-Driver-core.patch;patch=1 \
+                  file://dss2/0008-OMAP-DSS2-Add-more-core-files.patch;patch=1 \
+                  file://dss2/0009-OMAP-DSS2-DISPC.patch;patch=1 \
+                  file://dss2/0010-OMAP-DSS2-DPI-driver.patch;patch=1 \
+                  file://dss2/0011-OMAP-DSS2-Video-encoder-driver.patch;patch=1 \
+                  file://dss2/0012-OMAP-DSS2-RFBI-driver.patch;patch=1 \
+                  file://dss2/0013-OMAP-DSS2-SDI-driver.patch;patch=1 \
+                  file://dss2/0014-OMAP-DSS2-DSI-driver.patch;patch=1 \
+                  file://dss2/0015-OMAP-DSS2-omapfb-driver.patch;patch=1 \
+                  file://dss2/0016-OMAP-DSS2-Add-DPI-panel-drivers.patch;patch=1 \
+                  file://dss2/0017-OMAP-DSS2-Taal-DSI-command-mode-panel-driver.patch;patch=1 \
 "
 
+SRC_URI_append_beagleboard = " file://logo_linux_clut224.ppm \
+
 S = "${WORKDIR}/git"
 
 module_autoload_ohci-hcd_omap5912osk = "ohci-hcd"
Clone of mainline OpenEmbedded repository