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(parent: 64f5e3b) | patch
arm64: zynqmp: Add support for SC revC
authorMichal Simek <michal.simek@amd.com>
Wed, 27 Sep 2023 09:53:33 +0000 (11:53 +0200)
committerMichal Simek <michal.simek@amd.com>
Mon, 9 Oct 2023 10:12:30 +0000 (12:12 +0200)
commitfa822ad19e97af1176212f0f9f980f8061a39572
tree2677efc4bf6fa9adedc2cf685c903c0dc1a5e277tree | snapshot
parent64f5e3b4924781890c6913fd2537563df28b1cedcommit | diff
arm64: zynqmp: Add support for SC revC

System controller revC is using ADI ethernet phy instead of TI because of
supply chain issues.
Describe reset assert and de-assert times to 10us and 5ms respectively
according to the datasheet. Also setup RGMII RX and TX delay values to
2400ps as per board bring up observations.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2790f6cede7485556d581ab8270dda477fa21522.1695808407.git.michal.simek@amd.com
arch/arm/dts/Makefile diff | blob | history
arch/arm/dts/zynqmp-sc-revC.dts [new file with mode: 0644] blob
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