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(parent: b833de8) | patch
arm: dts: agilex5: Add HPS cache coherency unit configuration settings
authorTien Fong Chee <tien.fong.chee@intel.com>
Tue, 18 Feb 2025 08:34:54 +0000 (16:34 +0800)
committerTom Rini <trini@konsulko.com>
Tue, 25 Feb 2025 16:53:48 +0000 (10:53 -0600)
commite3097ca2bbdef182ac4e162387a4d1e92c625007
tree22fd31ba28e39ef170ff177d053413c876b6908btree | snapshot
parentb833de8d42663e157ce0039c5a7771f5d4aef11ecommit | diff
arm: dts: agilex5: Add HPS cache coherency unit configuration settings

These configuration settings are required to enable cache maintenance and
access between initiators and targets.

Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
arch/arm/dts/socfpga_agilex5-u-boot.dtsi diff | blob | history
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