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(parent: efdbd3a) | patch
usb: phy: mxs: add delay before set phyctrl.clkgate
authorPeter Chen <peter.chen@freescale.com>
Fri, 16 Jan 2015 10:29:01 +0000 (18:29 +0800)
committerFelipe Balbi <balbi@ti.com>
Tue, 27 Jan 2015 15:40:49 +0000 (09:40 -0600)
commite235f7b86f33beea7e096b46db1802dbf5d7d22e
treed7fb5e5b8949829c3b58a328ea0d4ebbf990647ctree | snapshot
parentefdbd3a5d6e6108f1565ab4dc4c53e77aba6fe0acommit | diff
usb: phy: mxs: add delay before set phyctrl.clkgate

There is a request from IC engineer that if we doesn't
set phypwd as 0xffffffff, we need to delay about five
32Khz cycles before set phy's pwd register, otherwise,
the wakeup signal may can't wake up controller.

Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
drivers/usb/phy/phy-mxs-usb.c diff | blob | history
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