ARM: tegra: clock: fix PLLD/PLLD2 related clock calculations
authorJonas Schwöbel <jonasschwoebel@yahoo.de>
Tue, 4 Mar 2025 07:02:11 +0000 (09:02 +0200)
committerSvyatoslav Ryhel <clamor95@gmail.com>
Tue, 11 Mar 2025 15:39:52 +0000 (17:39 +0200)
commitdbc27c2462871722fe9ee591a0e7cdba6d5f48b9
tree1ebe802fb2be793b4318badd06dfd157ad1125ad
parent8fb7ed59a8fa6d73a5d4ee9ec65c521de3ed1f21
ARM: tegra: clock: fix PLLD/PLLD2 related clock calculations

While PLLD/D2 is the nominal parent clock, all derived clocks are generated
from its single output, plld_out0, which is PLLD/D2 divided by two. Direct
use of PLLD/D2 is absent in peripheral clock configurations. Therefore,
clock derivation formulas must take in account this division.

Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
arch/arm/mach-tegra/clock.c