board: bsh: imx6ulz_smm_m2: Match SPL DDR settings to DCD table
authorMichael Trimarchi <michael@amarulasolutions.com>
Wed, 21 May 2025 09:47:29 +0000 (11:47 +0200)
committerFabio Estevam <festevam@gmail.com>
Wed, 21 May 2025 10:53:13 +0000 (07:53 -0300)
commitda6547acb8e645fe7000ea07d7ad0fcafc037b3a
treefc786eb316f80453060e35606fadf56e3ffb67e0
parentc1ccc4c0f3f96689cb71ec0ff30534af81627bf3
board: bsh: imx6ulz_smm_m2: Match SPL DDR settings to DCD table

When using SPL on i.mx6 we frequently notice some DDR initialization
mismatches between the SPL code and the non-SPL code.

As the non-SPL code have been tested for long time and proves to be
reliable, let's configure the DDR in the exact same way as the non-SPL
case.

The idea is simple: just use the DCD table and write directly to the DDR
registers.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
board/bsh/imx6ulz_smm_m2/spl.c