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(parent: ceec476) | patch
riscv: remove cache enablement in start.S
authorLeo Yu-Chi Liang <ycliang@andestech.com>
Tue, 28 May 2024 12:49:57 +0000 (20:49 +0800)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Thu, 30 May 2024 08:01:09 +0000 (16:01 +0800)
commitcea0ed2e3f37a36e6243bed8c3491d2281c30287
treed31d21ebf1adffbefec27966a1ea8a417515713etree | snapshot
parentceec4761141a920602c4a4c7b90039d144ec2e58commit | diff
riscv: remove cache enablement in start.S

Cache could be enabled in harts_early_init board-specific hook,
so remove cache enablement in start.S

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch/riscv/cpu/start.S diff | blob | history
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