ddr: altera: agilex5: LPDDRs in-line ECC support
authorTingting Meng <tingting.meng@altera.com>
Tue, 15 Apr 2025 06:50:51 +0000 (14:50 +0800)
committerTien Fong Chee <tien.fong.chee@intel.com>
Tue, 22 Apr 2025 03:47:40 +0000 (11:47 +0800)
commitc42ce8d8bd2ed0d20ae12517caccda6a04d7276d
tree9a30b1de1ded72677f4c90cddfd2524a263b1d54
parent52891fda68977e321043c2c4e04f6f3d55352726
ddr: altera: agilex5: LPDDRs in-line ECC support

In-line ECC support was added for LPDDR by reserving the last one-eighth
of the memory space for ECC data. Full memory initialization using the
BIST MEM INIT mailbox command, based on address and size, is required to
correctly generate ECC data and enable proper ECC logic verification.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
drivers/ddr/altera/iossm_mailbox.c
drivers/ddr/altera/iossm_mailbox.h
drivers/ddr/altera/sdram_agilex5.c
drivers/ddr/altera/sdram_soc64.c