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arm: socfpga: vining: Fix UDC controller phandle in DT
authorMarek Vasut <marex@denx.de>
Tue, 14 Sep 2021 03:25:34 +0000 (05:25 +0200)
committerMarek Vasut <marex@denx.de>
Wed, 22 Sep 2021 19:30:39 +0000 (21:30 +0200)
commitc3880e65975bd40ba025b9fafa5732a98ea9e736
tree485152d0af3262283b6c75f67652e40359644563tree | snapshot
parente21bbffa1d6d2634dabee393dd342764e2931441commit | diff
arm: socfpga: vining: Fix UDC controller phandle in DT

The USB peripheral controller is the DWC2 controller 1, not 0.
Update the phandle to fix UDC support on this board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi diff | blob | history
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