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(parent: 36b2a5d) | patch
drivers: mtd: nand: cadence: Flush & invalidate dma descriptor
authorDinesh Maniyam <dinesh.maniyam@intel.com>
Wed, 26 Feb 2025 16:18:23 +0000 (00:18 +0800)
committerMichael Trimarchi <michael@amarulasolutions.com>
Sat, 15 Mar 2025 09:35:01 +0000 (10:35 +0100)
commitb820fa95778493f20fedc8b2f2ab0c08f57e1f4b
tree79219d102ea7992d083fc22f085d2c69ae4e7e60tree | snapshot
parent36b2a5d676b4a13c8e66b30d8ff99a5e529fd6d2commit | diff
drivers: mtd: nand: cadence: Flush & invalidate dma descriptor

Ensure ddr memory is updated with the data from dcache.
This would help to ensure cdma always reading the latest dma descriptor
from ddr memory.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
drivers/mtd/nand/raw/cadence_nand.c diff | blob | history
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