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(parent: 2badc65) | patch
arm: renesas: Fix RZ/G2L GICR base address
authorPaul Barker <paul.barker.ct@bp.renesas.com>
Fri, 1 Nov 2024 14:20:16 +0000 (14:20 +0000)
committerMarek Vasut <marek.vasut+renesas@mailbox.org>
Sun, 10 Nov 2024 18:36:54 +0000 (19:36 +0100)
commit9d81a9ff990bae1bcf08ae5b888e0b6e12d1b58b
tree1abc104b692dd5cd950413cded949897c56ffc59tree | snapshot
parent2badc6529bb19aa35ddbb061c5bdb24f33d76d6fcommit | diff
arm: renesas: Fix RZ/G2L GICR base address

When support for the Renesas RZ/G2L SoC was added, the GICR base address
for CPU1 was accidentally used. We should instead supply the GICR base
address for CPU0 so that interrupts are correctly configured for the
CPU core that U-Boot is actually using.

Fixes: 387d4275ab0e ("arm: rmobile: Add basic RZ/G2L family support")
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
arch/arm/mach-renesas/include/mach/rzg2l.h diff | blob | history
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