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(parent: 7d2f288) | patch
arm: socfpga: agilex5: Enable cache flush for system memory cache in CCU
authorTien Fong Chee <tien.fong.chee@intel.com>
Thu, 8 Aug 2024 08:47:39 +0000 (16:47 +0800)
committerTom Rini <trini@konsulko.com>
Tue, 25 Feb 2025 16:53:56 +0000 (10:53 -0600)
commit9bb68bff4efaff541a6d19f11f14d269f5f89a19
tree907454c7d04a3835b451118755479b56c2661d75tree | snapshot
parent7d2f2883dcda6f2145e01ba7b5289ceb5d1e81e1commit | diff
arm: socfpga: agilex5: Enable cache flush for system memory cache in CCU

set/way instructions "dc cisw" which is used by the "dcache flush" command
only flushing CPU data caches from L1 -> L2 -> L3 to system memory cache in
cache coherency unit, hence this patch enables data flush from system
memory cache of CCU into DDR memory.

Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
arch/arm/mach-socfpga/Makefile diff | blob | history
arch/arm/mach-socfpga/ccu_ncore3.c [new file with mode: 0644] blob
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