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(parent: b8a902b) | patch
riscv: allow resume after exception
authorHeinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tue, 31 Oct 2023 12:55:51 +0000 (14:55 +0200)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Thu, 2 Nov 2023 08:22:06 +0000 (16:22 +0800)
commit9757cae991669f9a3d2b981b77231ee891d0597d
treeb87d518a0708339215a5770457d3a3a3e579dbdatree | snapshot
parentb8a902b81462a1fa6bd4fc8614cdc386fa7849d4commit | diff
riscv: allow resume after exception

If CSRs like seed are readable by S-mode, may not be determinable by
S-mode. For safe driver probing allow to resume via a longjmp after an
exception.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch/riscv/lib/interrupts.c diff | blob | history
doc/api/index.rst diff | blob | history
doc/api/interrupt.rst [new file with mode: 0644] blob
include/interrupt.h [new file with mode: 0644] blob
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