board: phytec: phycore-am62x: Add DDR size fixups if ECC is enabled

board: phytec: phycore-am62x: Add DDR size fixups if ECC is enabled

With commit 22ce56a3ebdb ("ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc()
to solve 'calculations restricted to 32 bits' issue") we need to provide the
detected RAM size in the device tree node prio to K3 DDRSS driver probe.
This is done by calling fdt_fixup_memory_banks() in do_board_detect().

After probing, call into k3-ddrss driver to fixup device tree and resize
the available amount of DDR if ECC is enabled.

A third fixup is required from A53 SPL to take the fixup
as done from R5 SPL and apply it to DT passed to A53 U-boot,
which in turn passes this to the OS.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>