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(parent: 0463545) | patch
riscv: cpu: th1520: Support cache enabling/disabling in M mode only
authorYao Zi <ziyao@disroot.org>
Fri, 30 May 2025 09:48:48 +0000 (09:48 +0000)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Mon, 9 Jun 2025 02:44:06 +0000 (10:44 +0800)
commit85cfabe895f4f32a5b65c114ebef7793321d5e01
tree89c18fa8563ab8076b047a1d81300dc812d613b5tree | snapshot
parent0463545678883b8d2b417eea08c76d47396104b7commit | diff
riscv: cpu: th1520: Support cache enabling/disabling in M mode only

These operations rely on a customized M-mode CSR, MHCR, which isn't
available when running in S mode.

Let's fallback to the generic weak stub when running in S mode to avoid
illegal accesses.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch/riscv/cpu/th1520/cache.c diff | blob | history
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