clk: mediatek: mt7629: fix parent clock of some top clock muxes
authorWeijie Gao <weijie.gao@mediatek.com>
Tue, 17 Dec 2024 08:39:16 +0000 (16:39 +0800)
committerTom Rini <trini@konsulko.com>
Tue, 31 Dec 2024 16:58:52 +0000 (10:58 -0600)
commit6e45549f4dac42748d66462e04f940ef6737289d
treeb26eba1216b3f46c633331048d27588a1739053c
parent25fb58e88aba0c4af0af554d7b141be3f2e5e0b5
clk: mediatek: mt7629: fix parent clock of some top clock muxes

According to the mt7629 programming guide, the CLK_TOP_F10M_REF_SEL
shares the same parent selection with CLK_TOP_IRRX_SEL, while the
present parent selection for CLK_TOP_F10M_REF_SEL is actually used
for CLK_TOP_SGMII_REF_1_SEL.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
drivers/clk/mediatek/clk-mt7629.c