rockchip: clk: rk3188: update dpll settings to make EMAC work
authorAlexander Kochetkov <al.kochet@gmail.com>
Mon, 26 Feb 2018 11:27:38 +0000 (14:27 +0300)
committerPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Wed, 28 Mar 2018 21:44:59 +0000 (23:44 +0200)
commit6b0c26fa05470b939be05ecf534566aef0f5a2b2
tree03a78ce3f3c9fefda75c81a3825e7b859d0de36c
parent6e60779156531f24c4585992615da7a14da2a836
rockchip: clk: rk3188: update dpll settings to make EMAC work

The patch set dpll settings for 300MHz to values used by binary
blob[1]. With new values dpll still generate 300MHz clock, but
EMAC work. Probably with new values dpll generate more stable clock.

dpll on rk3188 provide clocks to DDR and EMAC. With current
dpll settings EMAC doesn't work on radxa rock. EMAC sends packets
to network, but it doesn't receive anything. ifconfig shows a lot
of framing errors.

[1] https://github.com/linux-rockchip/u-boot-rockchip/blob/u-boot-rk3288/
    tools/rk_tools/3188_LPDDR2_300MHz_DDR3_300MHz_20130830.bin

Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
drivers/clk/rockchip/clk_rk3188.c