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(parent: bf12bb9) | patch
andes: cpu: Enable cache and TLB ECC support
authorLeo Yu-Chi Liang <ycliang@andestech.com>
Tue, 26 Dec 2023 06:17:35 +0000 (14:17 +0800)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Wed, 27 Dec 2023 09:29:07 +0000 (17:29 +0800)
commit61d5c543f330d660513e7d8c4d53c7db8a847bdc
tree37710debed41f1ad9386610ea67c4a199bb4b5cetree | snapshot
parentbf12bb99d870cccb666011c917cf3510f9b2d9a2commit | diff
andes: cpu: Enable cache and TLB ECC support

Andes CPU supports cache and TLB ECC.
Enable them by default.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
arch/riscv/cpu/andesv5/cpu.c diff | blob | history
arch/riscv/include/asm/arch-andes/csr.h diff | blob | history
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