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(parent: 981f040) | patch
arm: imx8ulp: Enable full L2 cache in SPL
authorYe Li <ye.li@nxp.com>
Sat, 7 Aug 2021 08:00:48 +0000 (16:00 +0800)
committerStefano Babic <sbabic@denx.de>
Mon, 9 Aug 2021 12:46:51 +0000 (14:46 +0200)
commit610083e547d19e87b567849b299187d66b643fb9
tree728844aae35918a91503e3395fad1e168bcc6533tree | snapshot
parent981f040a9a56ea4085308d4a6cf83561e02ed95fcommit | diff
arm: imx8ulp: Enable full L2 cache in SPL

SRAM2 is half L2 cache and default to SRAM after system boot.
To enable the full l2 cache (512KB), it needs to reset A35 to make
the change happen.

So re-implement the jump entry function in SPL:
1. configure the core0 reset vector to entry (ATF)
2. enable the L2 full cache
3. reset A35
So when core0 up, it runs into ATF. And we have 512KB L2 cache working.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
arch/arm/mach-imx/imx8ulp/soc.c diff | blob | history
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