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(parent: acf9384) | patch
riscv: cpu: Add TH1520 CPU support
authorYao Zi <ziyao@disroot.org>
Tue, 13 May 2025 09:04:56 +0000 (09:04 +0000)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Wed, 21 May 2025 08:49:52 +0000 (16:49 +0800)
commit5fe9ced3552ddeb40478b56507d3b48968be2939
tree8129de16948d4f1fd8b3b60457983b3c297f5c81tree | snapshot
parentacf9384d8cc372fc71a5857363cfe10c240c497acommit | diff
riscv: cpu: Add TH1520 CPU support

Introduce the SoC-specific code and corresponding Kconfig entries for
TH1520 SoC. Following features are implemented for TH1520,

- Cache enable/disable through customized CSR
- Invalidation of customized PMP entries
- DRAM driver probing for SPL

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch/riscv/Kconfig diff | blob | history
arch/riscv/cpu/th1520/Kconfig [new file with mode: 0644] blob
arch/riscv/cpu/th1520/Makefile [new file with mode: 0644] blob
arch/riscv/cpu/th1520/cache.c [new file with mode: 0644] blob
arch/riscv/cpu/th1520/cpu.c [new file with mode: 0644] blob
arch/riscv/cpu/th1520/dram.c [new file with mode: 0644] blob
arch/riscv/cpu/th1520/spl.c [new file with mode: 0644] blob
arch/riscv/include/asm/arch-th1520/cpu.h [new file with mode: 0644] blob
arch/riscv/include/asm/arch-th1520/spl.h [new file with mode: 0644] blob
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