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(parent: 4153ceb) | patch
riscv: cpu: th1520: Setup CPU feature CSRs in harts_early_init
authorYao Zi <ziyao@disroot.org>
Fri, 6 Jun 2025 04:28:01 +0000 (04:28 +0000)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Thu, 3 Jul 2025 08:14:13 +0000 (16:14 +0800)
commit5afad3d4a314464af34f9c312d3028b9053f1135
tree9413ed764b07060fba3fe138eb64bc6506cf3643tree | snapshot
parent4153ceb0fe4f8c866e45fbf149cebb05f0f8405fcommit | diff
riscv: cpu: th1520: Setup CPU feature CSRs in harts_early_init

C910 cores integrated in TH1520 SoC provide various customized CSRs for
configuring core behavior, including cache coherency and timing, branch
predication, and clock gating for internal components.

This patch sets them up for efficient operation and satisfying
requirements of an SMP system.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch/riscv/cpu/th1520/spl.c diff | blob | history
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