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(parent: d0bf7be) | patch
arm: dts: agilex5: Update CCU configuration
authorTingting Meng <tingting.meng@altera.com>
Tue, 15 Apr 2025 01:55:35 +0000 (09:55 +0800)
committerTien Fong Chee <tien.fong.chee@intel.com>
Tue, 22 Apr 2025 03:47:40 +0000 (11:47 +0800)
commit52891fda68977e321043c2c4e04f6f3d55352726
tree73659470422d8b508afa6d5db4fe3f24b9d06aadtree | snapshot
parentd0bf7bebfd5c045b96686e314177b2e01d0695e3commit | diff
arm: dts: agilex5: Update CCU configuration

Cache allocation for dirty writes in the CCU system cache was disabled
for performance optimization.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
arch/arm/dts/socfpga_agilex5-u-boot.dtsi diff | blob | history
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