arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0

arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0

The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the
function device_probe, the corresponding clocks are probed before calling
the device's probe. The PLL_CMNLC mux clock can only be created after the
device's probe. Therefore, move assigned-clocks and assigned-clock-parents
to the link nodes in U-Boot device tree file.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>