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(parent: 15d6518) | patch
dt: nand: add cadence nand dt-bindings
authorDinesh Maniyam <dinesh.maniyam@intel.com>
Wed, 26 Feb 2025 16:18:15 +0000 (00:18 +0800)
committerMichael Trimarchi <michael@amarulasolutions.com>
Sat, 15 Mar 2025 09:35:00 +0000 (10:35 +0100)
commit1ae1e9c55ec42d5176aa5f4a88efc62c63863e43
tree837d6be997c2da0a76b1c7d49cbebe5244b7168ftree | snapshot
parent15d6518c942f0da13f9a7ceeadbd925c3317ec8dcommit | diff
dt: nand: add cadence nand dt-bindings

The Cadence NAND is a configurable mtd raw block which
supports multiple options for chipsets, clocking and reset structure, and
feature list.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
doc/device-tree-bindings/mtd/cadence,nand.yaml [new file with mode: 0644] blob
Pandora U-Boot Repository